A manufacturing method of an asymmetric glass substrate based on double-sided ABF

Abstract

The application discloses a kind of based on the manufacturing method of asymmetric glass substrate of double-sided ABF, belong to semiconductor packaging technical field, the glass core with glass via hole is prepared first in the application, via hole fills the TGV metal conductor that penetrates upper and lower surfaces;Again, symmetrically stack ABF circuit layer on the upper and lower surfaces of glass core to form stress-balanced symmetric substrate;Then, only PI-RDL circuit layer is made on the ABF circuit layer of upper surface;Finally, chip flip-chip welding and subsequent packaging process are completed;The application fundamentally eliminates the risk of glass peeling by mutual offset of bilateral ABF internal stress, and single-layer PI-RDL significantly reduces stress mismatch to control warping, while retaining the advantages of low CTE of glass core and high wiring density of PI-RDL, suitable for SOC+HBM and other high-end chip packaging, significantly improving product reliability and yield.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, and specifically relates to a method for manufacturing an asymmetric glass substrate based on double-sided ABF. Background Technology

[0002] As semiconductor technology advances towards higher density and performance, traditional organic substrates have a high coefficient of thermal expansion (CTE), resulting in poor matching with the thermal expansion of chips and making it difficult to meet the packaging requirements of high-end chips. Glass substrates, due to their extremely low CTE, excellent flatness, and insulation properties, have become the core development direction for next-generation high-end packaging substrates.

[0003] Existing glass substrates are mainly divided into two categories: The first category is glass substrates with symmetrical ABF (Integrated Particulate Fiber) circuits stacked on top and bottom. This type changes the core of the substrate from organic glass fiber cloth to a glass core with a smaller CTE (Cost Efficiency), reducing the CTE of the substrate and making it more compatible with the chip. However, this structure has insufficient wiring density and cannot meet the high-density interconnection requirements of high-end chips such as HBM (Hardware-Based Microsystems). The second category is asymmetric glass substrates with RDL (Integrated Particulate Fiber) on the top layer and ABF (Integrated Particulate Fiber) on the bottom layer. This structure has high wiring density due to the fabrication of PI-RDL circuits. However, during the fabrication of ABF stacks, as the number of ABF layers increases, the stress mismatch between PI and ABF intensifies, leading to increased warping during production. At the same time, due to the layer-by-layer superposition of ABF stress, the ABF will eventually pull up the glass core, causing glass peeling, which seriously affects the reliability and yield of the product. Summary of the Invention

[0004] To address the problems mentioned in the background art, the present invention provides a method for manufacturing an asymmetric glass substrate based on double-sided ABF, thereby solving the problems of warpage and glass peeling in traditional asymmetric glass substrates.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A method for manufacturing an asymmetric glass substrate based on double-sided ABF includes the following steps: S1: Prepare a glass core with glass through holes, the glass through holes are filled with TGV metal conductors, and the TGV metal conductors are set through the upper and lower surfaces of the glass core. S2: ABF circuit layers are symmetrically stacked on the upper and lower surfaces of the glass core to form a symmetrical ABF glass substrate; the upper end of the TGV metal conductor in the glass through-hole is electrically connected to the ABF circuit layer on the upper surface of the glass core, and the lower end is electrically connected to the ABF circuit layer on the lower surface of the glass core. S3: Coat PI on the ABF circuit layer on the upper surface of the symmetrical ABF glass substrate to create a PI-RDL circuit layer, thus obtaining an asymmetrical glass substrate; the PI-RDL circuit layer is electrically connected to the ABF circuit layer on the upper surface. S4: Complete the chip flip-chip bonding and subsequent packaging process on the PI-RDL circuit layer to obtain the final packaged product; the chip is electrically connected to the PI-RDL circuit layer, and the BGA solder balls of the final packaged product are electrically connected to the ABF circuit layer on the lower surface.

[0006] Compared with the prior art, the beneficial effects of the present invention are: 1. Warpage is easy to control: The present invention fabricates a PI-RDL layer on the basis of a symmetrical ABF glass substrate. Compared with the traditional asymmetrical glass substrate with RDL on the top layer and ABF on the bottom layer, the present application has fewer RDL layers for the same thickness, which greatly reduces the stress mismatch problem between PI and ABF materials. The substrate warpage can be effectively controlled during the production process, which significantly improves the product yield.

[0007] 2. Eliminate the risk of glass peeling: Symmetrical ABF circuit layers are set on both the upper and lower surfaces of the glass core. The internal stress of the ABF layers on both sides is equal in magnitude and opposite in direction, which can cancel each other out. This fundamentally solves the problem of glass peeling caused by stress concentration on one side of the ABF in traditional asymmetrical structures pulling up the glass core, and greatly improves the reliability of the product.

[0008] 3. Retaining core technological advantages: This invention inherits the advantages of the two existing types of glass substrates. It retains the characteristics of the low thermal expansion coefficient of the glass core, which has good matching with the thermal expansion of the chip, and also retains the advantage of the high wiring density of the PI-RDL layer, which can meet the high-density interconnection requirements of high-end chips such as SOC+HBM. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the manufacturing process of this application. Detailed Implementation

[0010] To facilitate understanding of the technical content of this invention by those skilled in the art, the invention will be further described in detail below with reference to the accompanying drawings and specific examples. It should be understood that the specific examples described herein are merely illustrative and not intended to limit the scope of the invention.

[0011] like Figure 1 As shown, a method for manufacturing an asymmetric glass substrate based on double-sided ABF includes the following steps: S1: Prepare a glass core with through-hole glass (TGV); Substrate preparation: Borosilicate glass substrate was selected as the substrate material, with a coefficient of thermal expansion (CTE) of 3.2 ppm / ℃, which is highly matched with SOC chip (CTE≈2.8 ppm / ℃) and HBM chip (CTE≈3.0 ppm / ℃); the glass substrate was subjected to double-sided chemical mechanical polishing.

[0012] Laser drilling: forming a diameter array of glass through holes on a glass substrate.

[0013] Through-hole metallization: A titanium-copper seed layer is deposited on both sides of the glass substrate and the inner wall of the glass through-hole using a magnetron sputtering process; then, copper metal is filled into the glass through-hole using a DC electroplating process to form a continuous, void-free columnar TGV metal conductor.

[0014] Surface planarization: The electroplated glass substrate undergoes double-sided chemical mechanical polishing to remove excess copper metal and seed layer, ensuring that the upper and lower end faces of the TGV metal conductor are completely flush with the upper and lower surfaces of the glass core. This yields a glass core with TGV.

[0015] S2: Symmetrically stacking ABF circuit layers on the upper and lower surfaces of the glass core. ABF circuit layers are symmetrically fabricated on the upper and lower surfaces of the glass core using an alternating layer-addition process. In this embodiment, two layer-addition units (i.e., two ABF dielectric layers and two ABF metal circuit layers) are fabricated on each surface. The fabrication process for each layer-addition unit is exactly the same, and the specific steps are as follows: ABF dielectric layer lamination: An ABF dielectric layer is laminated onto the surface of the glass core or the surface of the previous ABF metal circuit layer using a vacuum hot pressing process.

[0016] Laser drilling: Creating vias in the ABF dielectric layer.

[0017] Metallization of vias: A thick copper seed layer is deposited on the inner wall of the ABF via using a chemical copper plating process, and then copper metal is filled using a DC electroplating process to form an ABF metallic conductor.

[0018] Fabrication of ABF metal circuit layer: The ABF metal circuit layer is fabricated on the surface of the ABF dielectric layer using a photolithography-etching process.

[0019] In the first layer addition unit on both sides of the glass core, the ABF via is precisely aligned with the center of the glass via. The lower end of the ABF metal conductor is in direct contact with the upper end of the TGV metal conductor and forms an ohmic connection. The upper end is electrically connected to the first ABF metal circuit layer. In the second layer addition unit, the ABF via is aligned with the pad of the first ABF metal circuit layer. The lower end of the ABF metal conductor is electrically connected to the first ABF metal circuit layer, and the upper end is electrically connected to the second ABF metal circuit layer.

[0020] The build-up process on the upper and lower surfaces is performed alternately: first, the first build-up unit on the upper surface is fabricated, then the first build-up unit on the lower surface is fabricated, followed by the second build-up unit on the upper surface, and finally the second build-up unit on the lower surface. This process ensures that the stress on both sides of the glass core accumulates synchronously and cancels each other out, avoiding substrate warping caused by unilateral build-up. This results in a symmetrical ABF glass substrate.

[0021] S3: Create the PI-RDL circuit layer; A single-layer PI-RDL circuit layer is fabricated on the surface of the second ABF metal circuit layer on the upper surface of a symmetrical ABF glass substrate. The specific steps are as follows: PI dielectric layer coating: A PI dielectric layer is coated on the surface of the ABF metal circuit layer using a spin coating process, and then cured in a stepwise manner under a nitrogen atmosphere.

[0022] RDL via fabrication: RDL vias are fabricated on the PI dielectric layer using a photolithography-dry etching process, with the bottom of the vias fully exposed to the underlying ABF metal circuit layer.

[0023] RDL metallization: A thick titanium-copper seed layer is deposited on the surface of the PI dielectric layer and the inner wall of the RDL via using magnetron sputtering. Then, the RDL metal conductor and RDL metal circuit are fabricated using pattern electroplating. The lower end of the RDL metal conductor is electrically connected to the second ABF metal circuit layer, and the upper end is electrically connected to the RDL metal circuit.

[0024] Because only a single PI-RDL circuit layer is fabricated, the stress mismatch between PI and ABF is minimal, resulting in an asymmetric glass substrate.

[0025] S4: Complete the subsequent packaging process; Chip flip-chip bonding: A thermo-press flip-chip bonding process is used to bond one SOC chip and two HBM chips onto corresponding pads on the PI-RDL circuit layer. After bonding, a reliable electrical connection is formed between the chip and the PI-RDL circuit layer.

[0026] Underfill: A capillary underfill process is used to fill the gap between the chip and the substrate with underfill adhesive, followed by curing. The underfill adhesive completely fills the gap between the chip and the substrate, without air bubbles or voids, which can effectively alleviate solder joint stress during thermal cycling.

[0027] Molding and Polishing: The chip is encapsulated using epoxy resin. After molding, the encapsulation layer is polished using a chemical mechanical polishing process.

[0028] Substrate cutting: A cutting machine is used to cut the entire board into individual packaging units; BGA solder balls: BGA solder balls are placed on the surface of the second ABF metal circuit layer under the glass core. The solder ball material is a tin-silver-copper alloy. After solder ball placement, reflow soldering is performed to form a reliable electrical connection between the solder balls and the ABF metal circuit layer.

[0029] The above embodiments illustrate and describe the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles and main features of the invention and are not intended to limit the scope of the invention in any way. Various changes and modifications can be made to the invention without departing from its scope, and all such changes and modifications fall within the scope of the claims.

Claims

1. A manufacturing method of a double-sided ABF-based asymmetric glass substrate, characterized by, Includes the following steps: S1: Prepare a glass core with glass through holes, the glass through holes are filled with TGV metal conductors, and the TGV metal conductors are set through the upper and lower surfaces of the glass core. S2: ABF circuit layers are symmetrically stacked on the upper and lower surfaces of the glass core to form a symmetrical ABF glass substrate; the upper end of the TGV metal conductor in the glass through-hole is electrically connected to the ABF circuit layer on the upper surface of the glass core, and the lower end is electrically connected to the ABF circuit layer on the lower surface of the glass core. S3: Coat PI on the ABF circuit layer on the upper surface of the symmetrical ABF glass substrate to create a PI-RDL circuit layer, thus obtaining an asymmetrical glass substrate; the PI-RDL circuit layer is electrically connected to the ABF circuit layer on the upper surface. S4: Complete the chip flip-chip bonding and subsequent packaging process on the PI-RDL circuit layer to obtain the final packaged product; the chip is electrically connected to the PI-RDL circuit layer, and the BGA solder balls of the final packaged product are electrically connected to the ABF circuit layer on the lower surface.

2. The method for manufacturing an asymmetric glass substrate based on double-sided ABF according to claim 1, characterized in that, In S1, the TGV metal conductor inside the glass via is a continuous columnar metal structure, with its upper and lower end faces flush with the upper and lower surfaces of the glass core, respectively, to achieve vertical electrical connection between the ABF circuit layers on the upper and lower surfaces of the glass core.

3. The method for manufacturing an asymmetric glass substrate based on double-sided ABF according to claim 1, characterized in that, In S2, ABF circuit layers are symmetrically stacked on the upper and lower surfaces of the glass core. Specifically, on the upper and lower surfaces of the glass core, each layer is stacked as an add-on unit, which is "first fabricating an ABF dielectric layer, and then fabricating an ABF metal circuit layer on the ABF dielectric layer". The number of add-on units and the total thickness of the ABF circuit layers on the upper and lower surfaces are symmetrical. The upper and lower surfaces of the glass core are in direct contact with the first ABF dielectric layer on the corresponding side.

4. The method for manufacturing an asymmetric glass substrate based on double-sided ABF according to claim 3, characterized in that, Each add-in unit is provided with an ABF via, which is filled with an ABF metal conductor. The ABF via penetrates the ABF dielectric layer of this add-in unit. The first end of the ABF metal conductor is electrically connected to the ABF metal circuit layer or the end face of the TGV metal conductor of another add-in unit adjacent to this ABF dielectric layer. The second end of the ABF metal conductor is electrically connected to the ABF metal circuit layer of this add-in unit.

5. The method for manufacturing an asymmetric glass substrate based on double-sided ABF according to claim 4, characterized in that, In S3, the PI-RDL circuit layer is fabricated as follows: a PI dielectric layer is coated on the surface of the topmost ABF metal circuit layer on the upper surface of the glass core. An RDL metal circuit is fabricated on the PI dielectric layer. The PI dielectric layer has RDL vias, and the RDL vias are filled with RDL metal conductors. The RDL vias penetrate the PI dielectric layer. The lower end of the RDL metal conductor is electrically connected to the adjacent ABF metal circuit layer, and the upper end is electrically connected to the RDL metal circuit.

6. The method for manufacturing an asymmetric glass substrate based on double-sided ABF according to claim 5, characterized in that, The wiring density of the PI-RDL circuit layer is higher than that of the ABF circuit layer.

7. A method for manufacturing an asymmetric glass substrate based on double-sided ABF according to claim 5, characterized in that, In S4, chip flip-chip bonding is completed on the PI-RDL circuit layer. Specifically, the solder balls of the SOC chip and HBM chip are soldered onto the RDL metal circuit of the PI-RDL circuit layer through the flip-chip bonding process, so as to realize the electrical connection between the SOC chip, HBM chip and PI-RDL circuit layer.

8. A method for manufacturing an asymmetric glass substrate based on double-sided ABF according to claim 5, characterized in that, In S4, the subsequent packaging processes include bottom filling, molding and polishing, substrate cutting, and BGA ball placement. Specifically, the BGA ball placement process involves placing BGA solder balls on the surface of the bottommost ABF metal circuit layer on the lower surface of the glass core to achieve electrical connection between the BGA solder balls and the back ABF circuit layer.

9. A method for manufacturing an asymmetric glass substrate based on double-sided ABF according to claim 7, characterized in that, The coefficient of thermal expansion of the glass core is matched with that of the SOC chip and HBM chip.

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