A method for fabricating a bridged BGA package structure for memory cascading

Abstract

This invention belongs to the field of semiconductor packaging technology, specifically a method for fabricating a bridged BGA package structure for memory cascading. The method includes: obtaining the physical property parameters of the organic packaging substrate to form a deviation vector; dividing the heterogeneous interface into partitions; performing failure boundary type-driven process window narrowing and differentiated solder paste printing on partitions with excessive thermal expansion coefficient mismatch; dividing the soldering process into sequential stages, unlocking for compliance and correcting for non-compliance; pre-configuring ball placement parameters; measuring the interconnect status of the memory dies; identifying outlier dies and performing position feature-driven orientation compensation; iterating until all dies are qualified before performing bottom filling and molding. This invention, by employing a technique of heterogeneous interface partitioning of the top pad array, achieves the effect that, under the objective condition of differences in thermal expansion coefficients at multi-layer heterogeneous interfaces, the reflow process execution parameters of each partition are always within the safe process window under the current batch physical property conditions.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically a method for fabricating a bridge BGA package structure for memory cascading. Background Technology

[0002] With the ever-increasing demand for storage bandwidth from high-performance computing, artificial intelligence accelerators, and server storage systems, single memory chips can no longer meet the dual requirements of capacity and speed. To address this, memory cascading technology has emerged. This technology involves vertically or horizontally stacking multiple memory dies within the same package using a bridged grid array (BGA) structure. High-density electrical interconnection between the chips is achieved through bridge chips embedded in the package substrate, significantly increasing storage capacity and access bandwidth within a limited package area. This technology, by embedding silicon bridge chips into an organic substrate, provides high-density, short-path, and low-power local interconnection within a small size, greatly promoting the performance improvement of heterogeneous integrated systems.

[0003] However, existing technologies are mainly limited by the core process bottleneck of controlling the coplanarity of solder joints and the mismatch of coefficient of thermal expansion (CTE) at multi-layer heterogeneous interfaces when realizing the integrated fabrication of bridged BGA packages for cascading multiple memory dies. This makes it difficult to balance the overall interconnect reliability of multi-layer solder joints and the signal transmission integrity of cascaded memory under high-speed operation in practical applications, thus affecting the overall performance. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a method for fabricating a bridged BGA package structure for memory cascading, thereby resolving issues such as solder joint coplanarity control and thermal expansion coefficient (CTE) mismatch in the prior art.

[0005] A method for fabricating a bridge BGA package structure for memory cascading includes the following steps: obtaining the current batch of organic packaging substrates, measuring the physical properties of the organic packaging substrates, constructing a physical property deviation vector from the deviation between the measured physical properties and the nominal design values, dividing the top surface pad array of the organic packaging substrate into multiple heterogeneous interface partitions based on the contour of the silicon bridge chip embedding region, calculating the thermal expansion coefficient mismatch index of each partition, performing process window boundary narrowing operation on partitions whose mismatch index exceeds the trigger threshold, triggering the corresponding process parameter directional narrowing strategy according to the failure boundary type, and configuring differentiated solder paste printing parameters for each partition based on the determined execution parameters of each partition.

[0006] The soldering process in the bridged BGA package structure is divided into multiple sequential soldering steps. After each soldering step is completed, an interface status evaluation report is generated and compared with preset compliance criteria. Based on the comparison results, it is determined whether the interface status of the current soldering step is compliant. If the current step is non-compliant, the defect information is transmitted back to the process parameter configuration sub-process of the current step to trigger targeted correction. The ball placement parameter configuration sub-process is pre-established before the BGA solder ball placement parameter configuration and overall reflow process are executed.

[0007] The solder joint interconnection status of all memory dies within the package is uniformly measured to obtain the interconnection status feature vector of each memory die. The overall deviation of the interconnection status feature vector of each memory die relative to the overall mean is calculated. Outlier dies are identified based on the calculation results. The cause of the outlier is identified based on the combination of the location characteristics and deviation index of the outlier die, and a targeted compensation operation is performed. The interconnection status feature vector after compensation is re-included in the horizontal comparison until the overall deviation of all memory dies falls within the outlier determination threshold. After configuring the bottom fill potting parameters, verifying the potting and interface integrity, the bridging BGA package structure is then encapsulated.

[0008] Preferably, the process window boundary narrowing operation performed on partitions where the mismatch index exceeds the trigger threshold is as follows:

[0009] Based on measured physical properties, and using the contour of the silicon bridge chip embedding region as a reference, the top surface pad array of the organic packaging substrate is divided into multiple heterogeneous interface partitions. The deviation of the measured value of the thermal expansion coefficient relative to the nominal design value for each heterogeneous interface partition is calculated. ;

[0010] Set thermal expansion coefficient deviation trigger threshold If each partition is individually assessed for boundary narrowing based on a set threshold, then:

[0011] If the result satisfies the formula Then it means the first The current batch's physical property deviation in each partition is within an acceptable range. The reflow process parameters for each partition remain unchanged from historical experience values.

[0012] If the result satisfies the formula Then it means the first The current batch property deviation in one partition exceeds the acceptable range, triggering the [missing information]. Each partition corresponds to the process window boundary narrowing operation.

[0013] Preferably, the step of triggering the corresponding process parameter narrowing strategy based on the failure boundary type is as follows:

[0014] If the current partition belongs to the solder overmelting collapse failure boundary type, then the peak temperature directional reduction strategy is triggered for the current partition, and the reflow peak temperature execution parameter of the current partition is shifted downward by a preset margin from the historical experience value.

[0015] If the current partition belongs to the insufficient wetting failure boundary type, the peak residence time directional extension strategy is triggered for the current partition, and the execution parameter of the reflux peak temperature residence time of the current partition is shifted upward by a preset margin from the historical experience value.

[0016] If the current partition belongs to the interface thermal shock failure boundary type, then trigger the heating slope directional reduction strategy for the current partition, and shift the reflow heating slope execution parameter of the current partition downward by a preset margin from the historical experience value.

[0017] If the current partition meets the criteria for two or more failure boundary types, then the current partition is determined to be a composite failure boundary type. In turn, a directional narrowing strategy is executed for each corresponding process parameter, that is, all applicable operations in peak temperature reduction, peak residence time extension and temperature rise slope reduction are executed simultaneously until the failure boundary type of all trigger boundary narrowing partitions is identified and the corresponding process parameters are determined.

[0018] Preferably, the step of configuring differentiated solder paste printing parameters for each partition based on the determined execution parameters for each partition is as follows:

[0019] For the area directly above the bridging chip, a standard reference solder paste printing thickness is used, and a low-activity flux formula is selected.

[0020] For the transition area around the bridging chip, the solder paste printing thickness is increased relative to the reference value to provide additional solder compensation for the current area during reflow. At the same time, the flux is selected with a modified formula containing elastic buffer components.

[0021] For the organic substrate body area, the solder paste printing thickness and flux formulation remain unchanged based on historical experience.

[0022] After configuring the differentiated solder paste printing parameters, the actual solder paste printing thickness of each zone is measured online. If the deviation of the actual printing thickness of any zone from the target value exceeds the preset tolerance range, the stencil opening parameter adjustment is automatically triggered. The stencil opening size corresponding to the zone with the excessive deviation is specifically corrected. After correction, the solder paste printing is re-executed and measured again until the solder paste printing thickness of all zones falls within their respective target tolerance range.

[0023] Preferably, the step of determining whether the interface state of the current welding process is compliant based on the comparison results is as follows:

[0024] For each sequential welding stage After the corresponding sequential welding step is completed, an interface status evaluation report for the current step is generated. The evaluation report is then compared with preset compliance criteria, resulting in:

[0025] If the first If the interface state evaluation result of the welding step meets the preset compliance criteria, then the welding step is considered to be in compliance. The interface status of each step is compliant, unlocking the first step. Execution permissions for each stage;

[0026] If the first If the interface state evaluation result of the welding step does not meet the compliance conditions compared with the preset compliance criteria, then it means that the first welding step... The interface status of each step is non-compliant. Each component must remain locked and cannot be started.

[0027] Preferably, the criteria for determining whether the interface state of the current welding stage is compliant vary depending on the welding stage, as follows:

[0028] Regarding the evaluation of the interface status and compliance criteria for the first stage, we have:

[0029] Obtain the void ratio of the bonded and cured layer and the continuous length of layered defects Set a compliance upper limit for the void ratio of the bonded curing layer. and the compliance limit for continuous length of layered defects The interface status of the first stage is judged according to the set compliance criteria.

[0030] Regarding the interface status evaluation and compliance criteria for the second stage, we have:

[0031] X-ray transmission electron microspinning (XRT) was used to obtain the internal void ratio of the microbump solder joints of each memory die after flip-chip bonding and reflow soldering. Solder joint height consistency deviation was obtained by laser confocal scanning. Simultaneously, optical inspection was performed on the wetting morphology of the weld joints to obtain the number of cold welding defects. Set a compliance upper limit for the void ratio of micro-bump solder joints. Upper limit of compliance for weld point height consistency deviation and the upper limit for the number of compliant cold welding defects. The interface status of the second stage is judged according to the established compliance criteria.

[0032] Regarding the evaluation of the interface status and compliance criteria for the third stage, we have:

[0033] After the bottom-side BGA solder ball placement and overall reflow soldering are completed, the overall coplanarity deviation of the BGA solder balls is obtained by automatic optical inspection. Number of bridging defects And the average contact resistance of the interface metallization layer was obtained by the four-probe method. Set an upper limit for the overall coplanarity deviation of BGA solder balls to meet compliance requirements. Maximum number of bridge defect compliance and the upper limit of compliance for contact resistance of the interface metallization layer. The interface status of the third stage is judged based on the established compliance criteria.

[0034] Preferably, the determination of the interface status in the first stage based on the set compliance criteria is as follows:

[0035] like If so, it means that the interface status of the first stage is compliant, and the execution permission of the second stage is unlocked;

[0036] like If the first stage interface state is non-compliant, the information about excessive void rate or delamination defects will be transmitted back to the embedded curing process parameter configuration sub-process. This will trigger targeted adjustments to the curing temperature or curing time based on the cause of the voids. After correction, curing will be re-executed and the test repeated until the formula is met. until.

[0037] Preferably, the identification of outlier wafers based on the calculation results is as follows:

[0038] The solder joint interconnect states of all memory dies within the package are uniformly measured to obtain the interconnect state feature vector for each die. A lateral comparison is then performed among the interconnect state feature vectors of all memory dies to calculate the deviation of each die's interconnect state feature vector from the overall mean. ;

[0039] Set outlier detection threshold If each memory die is determined to be an outlier based on a set threshold, then:

[0040] If the first The overall deviation of each memory die from the set threshold is compared with the formula. Then it means the first The interconnection status of the individual memory dies is consistent and no targeted compensation is required.

[0041] If the first The overall deviation of each memory die from the set threshold is compared with the formula. Then it means the first If a storage die is found to be an outlier, location feature analysis and targeted compensation for that die will be triggered.

[0042] Preferably, the step of identifying the cause of outliers and performing targeted compensation based on the combination of outlier wafer location characteristics and deviation indicators is as follows:

[0043] If the outlier die is located at the edge of the package, and its solder joint height averages Below the overall mean If the outlier is determined to be due to insufficient solder wetting caused by a low edge reflow thermal field, a local induction heating compensation operation is performed on the current location of the die.

[0044] If the outlier die is located in the central region of the package, and its average solder joint void ratio is... Higher than the overall mean If the out-of-group condition is determined to be due to the flux evaporation channel in the central area being blocked by the surrounding bare die, making it difficult for residual gas to escape, a vacuum-assisted exhaust operation is specifically performed on the current location of the bare die.

[0045] If the average contact resistance of the microbumps on the outlier die is Higher than the overall mean If the outlier is determined to be due to incomplete metallization of the microbump interface at the current location, a local controlled pressure bonding compensation operation will be performed on the current die.

[0046] Preferably, the step of re-incorporating the compensated interconnection state feature vectors into the lateral comparison is as follows:

[0047] After targeted compensation processing, the corrected interconnect state feature vectors of each outlier die are re-included in the lateral comparison, and the corrected overall deviation is recalculated. and outlier detection threshold Upon comparison, we have:

[0048] If the correction If the current die has passed the interconnection consistency test after directional compensation, then the current die will be included in the set of qualified dies.

[0049] If the correction If the current wafer still deviates after directional compensation, positional feature analysis is re-executed to identify any compound causes. For each compound cause, the corresponding directional compensation operation is performed sequentially. After compensation, the overall deviation is recalculated and compared again with the outlier threshold until the corrected overall deviation of the current wafer meets the threshold. until.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] 1. This invention achieves the following effect by adopting the technique of dividing the top surface pad array into heterogeneous interfaces based on the outline of the silicon bridge chip embedding area, independently calculating the degree of thermal expansion coefficient mismatch for each partition and performing process window boundary narrowing operation accordingly, and triggering a directional narrowing strategy for corresponding process parameters according to the failure boundary type. Under the condition that the difference in thermal expansion coefficient of multi-layer heterogeneous interfaces objectively exists, the reflow process execution parameters of each partition are always within the safe process window under the current batch physical properties. The solder joints of each partition are not triggered by overmelting collapse, insufficient wetting or interface thermal shock failure due to the execution of uniform parameters. The invention eliminates the root cause of solder joint coplanarity deviation caused by thermal expansion coefficient mismatch of multi-layer heterogeneous interfaces from the process parameter configuration stage.

[0052] 2. This invention achieves the following effects by adopting differentiated solder paste printing parameters for each partition, providing additional solder compensation by increasing the solder paste printing thickness for the transition area around the bridging chip, and measuring the actual solder paste thickness of each partition online after printing and triggering adaptive adjustment of the stencil opening parameters. These techniques match the amount of solder paste in each heterogeneous interface partition with the difference in solder volume requirements caused by the difference in thermal expansion coefficients during reflow, ensure that the solder joint height of each partition tends to be consistent after reflow, and guarantee the overall coplanarity of multi-level solder joints.

[0053] 3. This invention achieves the following effects by dividing the welding process into three sequential welding stages: embedded interface curing state confirmation, storage of bare die micro-bump welding, BGA solder ball placement and overall reflow. It also achieves the following effects: the interface state evaluation of the current stage is compliant before the next stage is unlocked; when the current stage is non-compliant, the defect information is transmitted back to the corresponding process parameter configuration sub-process to trigger targeted correction. These effects include blocking the interface defects of the preceding stage before they enter the subsequent interface processing stage; superimposing the solder joint interconnection status of each heterogeneous interface layer only after the interconnection status of each layer independently meets the standard; and ensuring that the overall interconnection reliability of multi-level solder joints does not decrease due to the cumulative propagation of interface defects from the preceding stage to the subsequent stage.

[0054] 4. This invention achieves the following effects: uniformly measuring the solder joint interconnection status of all memory dies within the package and obtaining interconnection status feature vectors; performing lateral consistency comparison among all memory dies to calculate the overall deviation of each die; and identifying the cause of outliers for dies exceeding the outlier determination threshold based on a combination of positional characteristics and deviation indicators, and performing local induction heating, vacuum-assisted degassing, or local controlled pressure bonding compensation operations. This ensures that the dispersion of solder joint interconnection status caused by positional differences among multiple memory dies within the package is controlled within the outlier determination threshold, and that the interconnection paths of each die maintain a high degree of consistency in three dimensions: solder joint height, interface void ratio, and micro-bump contact resistance. This ensures the consistency of the response characteristics of each interconnection path of the cascaded memory to high-speed signal transmission and avoids cross-chip signal timing deviations caused by interconnection status dispersion.

[0055] 5. This invention achieves the effect of no voids, no delamination, and no bubble encapsulation defects at the bottom filling interface of each interconnect area of ​​the bridging chip and the memory die by pre-configuring the potting parameters before the bottom filling is performed, dividing the bottom filling area into the bridging chip interconnect area and each memory die interconnect area and configuring the potting path and application amount respectively, and performing interface integrity verification after potting and feeding back the defect location information to the potting parameter configuration stage to trigger targeted correction. This ensures that the bottom filling material completely covers each interconnect interface, further reducing the thermal stress on the solder joints under thermal cycling conditions, maintaining the dielectric interface stability and signal transmission integrity of each interconnect path of the cascaded memory under high-speed operation, and taking into account the dual requirements of overall interconnect reliability of multi-level solder joints and high-speed signal transmission integrity. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of the overall method steps for fabricating a bridged BGA package structure for memory cascading according to the present invention. Detailed Implementation

[0057] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and should not be construed as limiting the scope of the invention.

[0058] Example 1

[0059] Reference Figure 1 As an embodiment of the present invention, a method for fabricating a bridge BGA package structure for memory cascading is provided, comprising the following steps:

[0060] S1: Perform heterogeneous interface partitioning identification and reflow process window boundary estimation on organic packaging substrates.

[0061] Specifically, the heterogeneous interface partitioning identification and reflow process window boundary estimation for organic packaging substrates is achieved by measuring the physical properties of the current batch of organic packaging substrates, identifying each heterogeneous interface region based on the measurement results, and then estimating the reflow process window boundary and determining the execution parameters. The specific implementation is as follows:

[0062] Obtain the current batch of organic packaging substrates. The organic packaging substrates have pre-formed bridging chip cavities inside, and silicon bridging chips have been embedded and fixed inside the bridging chip cavities.

[0063] The top surface of the organic packaging substrate is provided with a microbump pad array for supporting multiple memory dies, and the bottom surface is provided with a BGA solder ball pad array for interconnection with the printed circuit board.

[0064] The key physical properties of the current batch of organic packaging substrates are measured, including: the measured in-plane thermal expansion coefficient of the current batch of organic substrate materials, the initial warpage of the current batch of substrates in a free state, and the estimated value of the local stiffness difference between the silicon bridge chip embedding area and the substrate body area. The deviation between the measured values ​​and the nominal design values ​​constitutes the physical property deviation vector of the current batch.

[0065] Based on measured physical properties, and using the contour of the silicon bridging chip embedding region as a reference, the top surface pad array of the organic packaging substrate is divided into multiple heterogeneous interface partitions, as follows:

[0066] The top surface pad array of the organic packaging substrate is divided into... If there are heterogeneous interface partitions, then:

[0067] ;

[0068] in, Indicates the first A heterogeneous interface partition This indicates the total number of partitions. In this embodiment, the total number of partitions is 3, and the specific partitioning rules are as follows:

[0069] Using the outline of the silicon bridge chip embedding area as the central reference, the pad array is sequentially divided into the coverage area directly above the bridge chip. Transition area around bridging chip and the organic substrate body region .

[0070] For each of the divided heterogeneous interface partitions, the corresponding thermal expansion coefficient mismatch index is calculated for subsequent process window boundary prediction. Then:

[0071] ;

[0072] in, Indicates the first The measured coefficient of thermal expansion of each zone, Indicates the first The nominal design thermal expansion coefficient of each zone, Indicates the first The deviation of the measured value of the thermal expansion coefficient of each zone from the nominal design value is used to determine whether each zone needs to trigger process window boundary narrowing. Specifically:

[0073] Set thermal expansion coefficient deviation trigger threshold If each partition is individually assessed for boundary narrowing based on a set threshold, then:

[0074] If the result satisfies the formula Then it means the first The current batch's physical property deviation in each partition is within an acceptable range. The reflow process parameters for each partition remain unchanged from historical experience values.

[0075] If the result satisfies the formula Then it means the first The current batch property deviation in one partition exceeds the acceptable range, triggering the [missing information]. Each partition corresponds to the process window boundary narrowing operation.

[0076] Furthermore, before performing the boundary narrowing operation, the failure boundary type of the current partition is identified. Based on the different failure boundary types, the corresponding process parameter targeted narrowing strategy is triggered, as specifically implemented as follows:

[0077] For partitions with narrowing trigger boundaries, based on failure boundary characteristics, the failure boundary type of the current partition is determined as follows:

[0078] The solder joint morphology records of the current partition under historical conditions of similar physical property deviations are examined to determine whether solder overmelting and collapse failure characteristics exist. The criteria for determining solder overmelting and collapse failure characteristics are as follows:

[0079] The amount of sinking of the weld joint height relative to the standard value exceeds the preset collapse judgment threshold, and the amount of expansion of the weld joint diameter relative to the standard value exceeds the preset expansion judgment threshold;

[0080] If the current partition belongs to the solder overmelting collapse failure boundary type, then a peak temperature directional reduction strategy is triggered for the current partition. The reflow peak temperature execution parameter of the current partition is shifted downward by a preset margin from the historical empirical value, resulting in:

[0081] ;

[0082] in, This indicates the peak temperature execution parameter after targeted reduction. This indicates the historical peak temperature. This represents the peak temperature margin offset for solder overmelting collapse failure boundary type, which is set by the implementer based on the magnitude of the current batch property deviation vector.

[0083] If the current partition does not belong to the solder overmelting collapse failure boundary type, then continue to check whether it belongs to the insufficient wetting failure boundary type. The criteria for determining the insufficient wetting failure boundary type are:

[0084] Under historical conditions of similar physical property deviations, the incidence of cold welding defects at weld joints exceeded the preset cold welding rate threshold, and the wetting angle of the weld joints was relatively large compared to the standard value.

[0085] If the current partition belongs to the insufficient wetting failure boundary type, then a peak residence time extension strategy is triggered for the current partition. The residence time parameter of the reflux peak temperature of the current partition is shifted upward by a preset margin from the historical empirical value. Then:

[0086] ;

[0087] in, This indicates the peak dwell time execution parameter after targeted extension. This indicates the peak dwell time based on historical experience. This indicates the dwell time margin offset for the insufficient wetting failure boundary type, which is set by the implementer based on the magnitude of the current batch property deviation vector.

[0088] If the current partition does not belong to the insufficient wetting failure boundary type, then continue to check whether it belongs to the interface thermal shock failure boundary type. The criteria for determining the interface thermal shock failure boundary type are:

[0089] There are records of microcrack defects in the metallization layer at the solder joint interface under similar physical property deviation conditions in the past, and the warpage of the substrate exceeds the preset dynamic warpage judgment threshold during the heating stage.

[0090] If the current partition belongs to the interface thermal shock failure boundary type, then a strategy to reduce the heating slope is triggered for the current partition. The reflow heating slope parameter of the current partition is shifted downward by a preset margin from the historical empirical value, resulting in:

[0091] ;

[0092] in, This indicates the execution parameter representing the temperature rise slope after directional reduction. This indicates the slope of the warming trend based on historical experience. This represents the temperature rise slope margin offset for the interface thermal shock failure boundary type, which is set by the implementer based on the magnitude of the current batch property deviation vector.

[0093] It should be noted that if the current partition meets the judgment criteria for two or more failure boundary types at the same time, the current partition is determined to be a composite failure boundary type. The directional narrowing strategy is then executed for each corresponding process parameter in sequence, that is, all applicable operations in peak temperature reduction, peak residence time extension and temperature rise slope reduction are executed simultaneously until the failure boundary type of all trigger boundary narrowing partitions is identified and the corresponding process parameters are determined.

[0094] After completing the process window boundary prediction and execution parameter determination for each zone, record the physical property deviation vector of this batch, the failure boundary type identification results of each zone, and the corresponding boundary narrowing amount, and include them in the historical database for boundary prediction accuracy correction of subsequent batches, so that the boundary prediction error gradually narrows with the accumulation of batches until the execution parameters of all zones are determined.

[0095] Furthermore, based on the determined execution parameters for each partition, differentiated solder paste printing parameters are configured for each partition, specifically as follows:

[0096] For the area directly above the bridging chip, since this area is constrained by the dual rigidity of silicon material and organic substrate material and has the smallest thermal deformation, a conventional reference solder paste printing thickness is adopted and a low-activity flux formula is selected.

[0097] For the transition area around the bridging chip, since there is a risk of out-of-plane warping in this area during reflow, the solder paste printing thickness is appropriately increased relative to the reference value to provide additional solder compensation for this area during reflow. At the same time, the flux is selected with a modified formula containing elastic buffer components.

[0098] For the organic substrate body area, since this area has the lowest stiffness and the largest thermal deformation, the solder paste printing thickness and flux formulation remain unchanged based on historical experience.

[0099] After configuring the differentiated solder paste printing parameters, the actual solder paste printing thickness of each zone is measured online. If the deviation of the actual printing thickness of any zone from the target value exceeds the preset tolerance range, the stencil opening parameter adjustment is automatically triggered. The stencil opening size corresponding to the zone with the excessive deviation is specifically corrected. After correction, the solder paste printing is re-executed and measured again until the solder paste printing thickness of all zones falls within their respective target tolerance range.

[0100] S2: Welding of multi-layer heterogeneous interfaces based on prior compliance certification mechanism.

[0101] Specifically, the welding of multi-layered heterogeneous interfaces based on a pre-compliance certification mechanism is based on the determined execution parameters of each partition. This pre-compliance certification mechanism designs the welding process for multi-layered heterogeneous interfaces such that subsequent sequential structures can only be unlocked after pre-compliance is achieved. Welding and status evaluation are performed sequentially on each interface layer, and the evaluation results drive parameter correction or unlocking of subsequent steps. The specific implementation is as follows:

[0102] The soldering process involving heterogeneous interface interconnection in the bridged BGA package structure is divided into: If there are sequential welding steps, then:

[0103] ;

[0104] in, Indicates the first A sequential welding process. This indicates the total number of welding stages. In this embodiment, the total number of welding stages is 3, and the specific division rules are as follows:

[0105] The sequential welding process is divided into the first stage (confirmation of the curing status of the embedding interface between the silicon bridge chip and the organic substrate). The second stage (micro-bump soldering of the storage die) And the third stage (bottom BGA solder ball placement and overall reflow process) .

[0106] Furthermore, for each sequential welding stage... After the corresponding sequential welding step is completed, an interface state evaluation report for the current step is generated. This report is then compared with preset compliance criteria. Based on the comparison results, it is determined whether the interface state of the current welding step is compliant, thereby determining the execution status of the next step. Specifically:

[0107] If the first If the interface state evaluation result of the welding step meets the preset compliance criteria, then the welding step is considered to be in compliance. The interface status of each step is compliant, unlocking the first step. Execution permissions for each stage;

[0108] If the first If the interface state evaluation result of the welding step does not meet the compliance conditions compared with the preset compliance criteria, then it means that the first welding step... The interface status of each step is non-compliant. Each component must remain locked and cannot be started.

[0109] When the When the interface status of a certain step is non-compliant, the non-compliance information of the current step is passed back to the process parameter configuration sub-process of the current step, triggering targeted parameter correction. After the correction is completed, the current step is re-executed, the interface status evaluation report is generated again and compliance comparison is performed, and the next step is unlocked only after the interface status of the current step is compliant.

[0110] It should be noted that the criteria for determining whether the interface state of the current welding process is compliant vary depending on the specific welding stage, as follows:

[0111] The evaluation of the interface status and compliance criteria in the first stage involves using ultrasonic scanning to inspect the adhesive curing layer embedded in the silicon bridge chip cavity. The specific implementation is as follows:

[0112] Obtain the void ratio of the bonded and cured layer and the continuous length of layered defects ;

[0113] Set a compliance limit for the void ratio of the bonded curing layer. and the compliance limit for continuous length of layered defects Based on the established compliance criteria, the interface status of the first stage is judged, and the following is obtained:

[0114] like If so, it means that the interface status of the first stage is compliant, and the execution permission of the second stage is unlocked;

[0115] like If the first stage interface state is non-compliant, the information about excessive void rate or delamination defects will be transmitted back to the embedded curing process parameter configuration sub-process. This will trigger targeted adjustments to the curing temperature or curing time based on the cause of the voids. After correction, curing will be re-executed and the test repeated until the formula is met. until.

[0116] The specific implementation of the interface status evaluation and compliance criteria for the second stage is as follows:

[0117] X-ray transmission electron microspinning (XRT) was used to obtain the internal void ratio of the microbump solder joints of each memory die after flip-chip bonding and reflow soldering. Solder joint height consistency deviation was obtained by laser confocal scanning. Simultaneously, optical inspection was performed on the wetting morphology of the weld joints to obtain the number of cold welding defects. ;

[0118] Set a compliance limit for the void ratio of micro-bump solder joints. Upper limit of compliance for weld point height consistency deviation and the upper limit for the number of compliant cold welding defects. Based on the established compliance criteria, the interface status of the second stage is judged, and the following is obtained:

[0119] like If so, it means that the interface status of the second stage is compliant, and the execution permission of the third stage is unlocked;

[0120] If any compliance condition is not met, it indicates that the interface status of the second stage is non-compliant. The corresponding defect type information is then passed back to the reflow temperature profile configuration subprocess. If it is a cold solder joint defect, the reflow peak dwell time is extended accordingly. If it is a void ratio exceeding the standard, the heating rate is adjusted accordingly. If it is a high consistency deviation exceeding the standard, the cooling rate of each zone is adjusted accordingly. After correction, the non-compliant area is re-executed for local rework reflow, and an evaluation report is generated and compared again until all three compliance conditions are met.

[0121] In addition, before evaluating the interface status and compliance criteria for the third stage, a BGA ball-planting parameter configuration sub-process is pre-established. This sub-process receives defect information from the interface when the third stage interface status is non-compliant and triggers corresponding parameter corrections based on the defect type. The specific implementation is as follows:

[0122] Based on the established execution parameters for each partition and the actual warpage state of the substrate after the second stage of compliance verification, the ball-mounting stencil parameters for the bottom BGA solder pad array are configured as follows:

[0123] Using the overall coplanarity measurement value of the bottom BGA solder ball pad array as input, the bottom pad array is divided into regions with larger coplanarity deviation and regions with smaller coplanarity deviation according to the coplanarity deviation distribution;

[0124] For areas with large coplanarity deviations, the corresponding stencil opening size is appropriately increased relative to the reference value to compensate for the insufficient weld ball height caused by the coplanarity deviation in this area by increasing the volume of the weld balls;

[0125] For areas with small coplanarity deviations, the opening size of the steel mesh remains unchanged from the baseline value;

[0126] Based on the failure boundary type identification results for each zone, the overall reflow temperature profile of the bottom surface is pre-configured, specifically as follows:

[0127] If the area directly above the bridging chip is identified as an interface thermal shock failure boundary type, the heating slope of the overall bottom reflow will be reduced relative to the reference value to reduce the thermal shock to the completed top surface welding structure during the bottom reflow process.

[0128] If none of the partitions are identified as interface thermal shock failure boundary types, the overall reflow temperature profile of the bottom surface will remain unchanged as the historical experience baseline profile.

[0129] After the ball-mounting parameter configuration sub-process is completed, the bottom BGA solder balls are reflow soldered according to the pre-configured reflow temperature profile.

[0130] Furthermore, the specific implementation of the interface status evaluation and compliance criteria for the third stage is as follows:

[0131] After the bottom-side BGA solder ball placement and overall reflow soldering are completed, the overall coplanarity deviation of the BGA solder balls is obtained by automatic optical inspection. Number of bridging defects And the average contact resistance of the interface metallization layer was obtained by the four-probe method. ;

[0132] Set the upper limit for overall coplanarity deviation of BGA solder balls. Maximum number of bridge defect compliance and the upper limit of compliance for contact resistance of the interface metallization layer. Based on the established compliance criteria, the status of the third-stage interface is judged, and the following is obtained:

[0133] like If the interface status of the third stage is compliant, the sequential welding process will terminate normally.

[0134] If any compliance condition is not met, it indicates that the interface status of the third stage is non-compliant. The corresponding defect information will be passed back to the ball-planting parameter configuration sub-process. Targeted corrections will be triggered for steel mesh parameters or reflow curves due to coplanarity deviation or bridging reasons. After correction, ball-planting and reflow will be re-executed, and an evaluation report will be generated and compared again until all three compliance conditions are met.

[0135] It should be noted that when the interface status evaluation in the third stage finds that the bridging defect exceeds the standard and transmits the defect information back to the ball-planting parameter configuration sub-process, the opening size of the steel mesh corresponding to the location where the bridging defect occurs is appropriately reduced relative to the current configuration value, so as to eliminate the bridging risk by reducing the amount of solder at the corresponding location.

[0136] In the ball planting parameter configuration sub-process, the two types of correction actions—the increase in steel mesh opening corresponding to excessive coplanarity deviation and the reduction in steel mesh opening corresponding to excessive bridging—are triggered independently based on the type of returned defect and do not interfere with each other.

[0137] S3: Detection and directional compensation based on solder joint interconnection status.

[0138] Specifically, the detection and directional compensation based on solder joint interconnection status involves uniformly measuring and laterally comparing the solder joint interconnection status of all memory dies within the package after completing multi-level sequential soldering compliance verification. This identifies outlier dies introduced by positional differences and performs directional compensation based on the positional characteristics of each outlier die. The specific implementation is as follows:

[0139] By uniformly measuring the solder joint interconnection state of all memory dies within the package and obtaining the interconnection state feature vector corresponding to each memory die, we have:

[0140] ;

[0141] in, Indicates the first The interconnect state feature vector of each storage die. This indicates the serial number of the stored die. Indicates the first Average solder joint height corresponding to each memory die Indicates the first The average void ratio of solder joints corresponding to each bare memory die. Indicates the first The average contact resistance of the microbumps corresponding to each storage die.

[0142] Perform a lateral comparison among the interconnect state feature vectors of all memory dies, and calculate the deviation of each memory die's interconnect state feature vector from the overall mean. Then:

[0143] ;

[0144] in, , , These represent the average values ​​of the solder joint height, void ratio, and contact resistance of all memory dies, respectively. , , These represent the weighting coefficients of the three indicators, which are set by the implementers based on the actual application scenario. Indicates the first The overall deviation of each storage die is used to identify outlier dies, specifically:

[0145] Set outlier detection threshold If each memory die is determined to be an outlier based on a set threshold, then:

[0146] If the first The overall deviation of each memory die from the set threshold is compared with the formula. Then it means the first The interconnection status of the individual memory dies is consistent and no targeted compensation is required.

[0147] If the first The overall deviation of each memory die from the set threshold is compared with the formula. Then it means the first If a storage die is found to be an outlier, location feature analysis and targeted compensation for that die will be triggered.

[0148] Furthermore, for each outlier die, the positional characteristics and deviation direction within the package are analyzed to identify the positional causes leading to the deviation in the interconnect state of the die, and corresponding directional compensation operations are performed. The specific implementation is as follows:

[0149] The location coordinates and main deviation indicators of each outlier wafer are obtained sequentially. Based on the combination of location characteristics and deviation indicators, cause identification and targeted compensation are performed. Then:

[0150] If the outlier die is located at the edge of the package, and its solder joint height averages Below the overall mean The outlier is determined to be due to insufficient solder wetting caused by a low edge reflow thermal field. A local induction heating compensation operation is then performed on the current die location. Specifically:

[0151] Position the induction heating coil directly above the location of the outlier die. The coverage area of ​​the induction heating coil extends outward by a predetermined distance from the chip outline of the outlier die to ensure that the heating range covers the entire solder joint area of ​​the die without affecting adjacent dies.

[0152] Induction heating is activated to apply a localized induction heat field to the location of the bare die at a controlled heating rate, so that the temperature of the solder in the area is raised to above the minimum temperature required for secondary wetting of the solder, but below the temperature at which the solder completely over-melts and collapses.

[0153] During the induction heating process, the real-time temperature of the wafer location is monitored using a non-contact infrared thermometer. The monitored temperature is then compared in real-time with the upper and lower boundaries of the preset secondary wetting temperature window. Therefore:

[0154] If the monitored temperature exceeds the upper boundary of the temperature window, the induction heating power will be reduced.

[0155] If the monitored temperature is below the lower boundary of the temperature window, increase the induction heating power;

[0156] After maintaining a preset dwell time within the target temperature window, the induction heating is turned off and the temperature is restored to room temperature at a controlled cooling rate.

[0157] After the local induction heating compensation operation is completed, the average height of the corresponding solder joints on the bare die is remeasured to confirm whether its deviation from the overall mean has converged to within the outlier determination threshold.

[0158] If the outlier die is located in the central region of the package, and its average solder joint void ratio is... Higher than the overall mean If the outlier is determined to be due to the flux evaporation channel in the central area being blocked by surrounding bare wafers, making it difficult for residual gas to escape, a vacuum-assisted venting operation will be performed specifically on the current location of the bare wafer, as follows:

[0159] Transfer the package into the vacuum chamber and perform a pumping operation on the vacuum chamber at a preset pumping rate to reduce the air pressure in the vacuum chamber from atmospheric pressure to a preset negative pressure value.

[0160] Under negative pressure, the residual gas in the solder joint area inside the package expands outward due to the decrease in external air pressure and escapes outward along the gap at the edge of the solder joint;

[0161] Maintain the preset pressure holding time under the preset negative pressure value to allow the residual gas to escape completely;

[0162] After the pressure holding is completed, inert gas is slowly introduced into the vacuum chamber at a controlled back pressure rate to restore the chamber pressure from the preset negative pressure value to atmospheric pressure. Inert gas is introduced instead of directly opening the valve to let the atmosphere through, so as to avoid the pressure rise suddenly and forcing the residual gas that has escaped the path back into the weld joint.

[0163] After the vacuum-assisted venting operation is completed, the package is subjected to supplementary heat treatment in an inert gas protective atmosphere, so that the solder at the voids left by the escape of residual gas can be refilled under the action of capillary force.

[0164] After the supplementary heat treatment is completed, the average void ratio of the solder joints corresponding to the bare die is remeasured to confirm whether its deviation from the overall mean has converged to within the outlier determination threshold.

[0165] If the average contact resistance of the microbumps on the outlier die is Higher than the overall mean If the outlier is determined to be due to incomplete metallization of the microbump interface at the current location, a localized controlled pressure bonding compensation operation is performed on the die. Specifically:

[0166] Position the bonding head directly above the outlier die, with the contact area of ​​the bonding head matching the chip area of ​​the current outlier die, to ensure that the applied pressure is evenly distributed across the entire microbump solder joint array of the die.

[0167] Controlled pressure is applied to the die at a preset pressure rate, which increases the contact area between the micro-bump solder joints and the corresponding pads under pressure, promoting the full diffusion of the interface metallization layer on the contact surface.

[0168] While applying pressure, an auxiliary thermal field is applied to the bare die through the heating element built into the bonding head, so that the temperature of the micro-bump solder joint is raised to above the diffusion activation temperature of the interface metallization layer and below the solder remelting temperature, so as to accelerate the diffusion continuity of the interface metallization layer without destroying the existing bonding morphology of the solder joint.

[0169] Maintain a preset bonding residence time under preset pressure and temperature conditions;

[0170] After the dwell time ends, the pressure is gradually removed at a controlled depressurization rate and the room temperature is restored at a controlled cooling rate.

[0171] After the localized controlled pressure bonding compensation operation is completed, the average contact resistance of the corresponding microbumps on the die is measured again using the four-probe method to confirm whether its deviation from the overall mean has converged to within the outlier determination threshold.

[0172] Furthermore, after the targeted compensation process is completed, the corrected interconnection state feature vectors of each outlier die are re-included in the horizontal comparison, and the corrected overall deviation is recalculated. and outlier detection threshold Upon comparison, we have:

[0173] If the correction If the above indicates that the interconnection state consistency of the die has been qualified after orientation compensation, the die will be included in the qualified die set.

[0174] If the correction If the deviation is not found after directional compensation, it indicates that the wafer still has a deviation. Position feature analysis is then performed again to identify any compound causes, and corresponding directional compensation operations are performed sequentially for each compound cause. After compensation, the overall deviation is recalculated and compared again with the outlier detection threshold until the corrected overall deviation of the wafer meets the threshold. until.

[0175] In addition, after all the memory dies pass the lateral consistency comparison and outlier orientation compensation verification, the bridged BGA package structure is subjected to bottom filling and molding protection processes to complete the final fabrication of the bridged BGA package structure for memory cascading.

[0176] It should be noted that before performing the bottom filling and grouting process, a bottom filling and grouting parameter configuration step is pre-established. This step is used to receive defect location information fed back during the bottom filling interface integrity verification and to trigger grouting parameter correction based on the defect type. The specific implementation is as follows:

[0177] Based on the interconnect state feature vector measurement results of each memory die and the positional distribution of each die within the package, the bottom filler path and adhesive application amount are configured in zones, specifically as follows:

[0178] Based on the spacing boundaries between each memory die and the outline of the bridge chip embedding area, the bottom filling and potting area is divided into the bridge chip interconnect area and the interconnect area of ​​each memory die.

[0179] For the interconnect area of ​​the bridging chip, because the interconnect spacing in this area is fine and the capillary flow path is short, a low viscosity and high wettability bottom filler material is selected. An enclosed potting path is adopted to apply the adhesive along the four sides of the bridging chip. The amount of adhesive applied is determined based on the volume estimate of the gap between the bridging chip embedding cavity and the surrounding area.

[0180] For each memory die interconnect area, since multiple memory dies are cascaded and there is a filling front interface between adjacent memory dies, a symmetrical potting path is adopted to advance synchronously from the outer edge of each memory die towards the interface between adjacent dies. The amount of adhesive applied to each memory die interconnect area is determined based on the volume estimate of the corresponding gap of each die. For interconnect areas of dies identified as having high void ratios, the amount of adhesive applied is appropriately increased based on the baseline amount to ensure that the gaps in this area are fully filled.

[0181] After configuring the injection parameters, perform bottom filling injection according to the configured injection path and application amount.

[0182] Furthermore, after the bottom filling and infusion process is completed, the integrity of the bottom filling interface also needs to be verified, specifically:

[0183] Ultrasonic scanning was performed on the interconnect area of ​​the bridging chip to confirm the absence of voids and delamination defects; X-ray tomography was performed on the interface between adjacent dies in the interconnect area of ​​the memory die to confirm the absence of bubble encapsulation defects.

[0184] If any interface defect exists in any area, the defect location information will be fed back to the bottom filling and infusion parameter configuration stage. For different defect types, corresponding infusion parameter correction actions will be triggered, specifically:

[0185] If there is a void defect in the interconnect area of ​​the bridging chip, increase the amount of adhesive applied to the corresponding position in the area and adjust the enclosed adhesive application sequence so that the adhesive application starts from the side where the void is detected, so as to improve the capillary filling driving force on that side, until the void defect at the corresponding position is eliminated.

[0186] If there is a bubble encapsulation defect at the interface between adjacent dies in the storage die interconnect area, the symmetrical filling rate on both sides of the interface is adjusted. The side that reaches the interface more slowly is identified and the glue application rate on that side is increased so that the timing of the filling fronts on both sides reaching the interface is consistent, thereby eliminating the risk of bubble encapsulation at the interface, until the bubble encapsulation defect at the corresponding interface is eliminated.

[0187] After local rework, the curing and interface integrity verification are repeated until the bottom fill interface of all areas meets the integrity requirements, thus finally completing the fabrication of the bridged BGA package structure for memory cascading.

[0188] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of protection claimed by the present invention.

Claims

1. A method for fabricating a bridged BGA package structure for memory cascading, characterized in that: Includes the following steps: Obtain the current batch of organic packaging substrates, measure the physical properties of the organic packaging substrates, and construct a physical property deviation vector by comparing the deviation between the measured physical properties and the nominal design values. Based on the contour of the silicon bridge chip embedding area, divide the top surface pad array of the organic packaging substrate into multiple heterogeneous interface partitions, calculate the thermal expansion coefficient mismatch index of each partition, perform process window boundary narrowing operation on partitions whose mismatch index exceeds the trigger threshold, and trigger the corresponding process parameter directional narrowing strategy according to the failure boundary type. Configure differentiated solder paste printing parameters for each partition based on the determined execution parameters of each partition. The soldering process in the bridged BGA package structure is divided into multiple sequential soldering steps. After each soldering step is completed, an interface status evaluation report is generated and compared with preset compliance criteria. Based on the comparison results, it is determined whether the interface status of the current soldering step is compliant. If the current step is non-compliant, the defect information is transmitted back to the process parameter configuration sub-process of the current step to trigger targeted correction. The ball placement parameter configuration sub-process is pre-established before the BGA solder ball placement parameter configuration and overall reflow process are executed. The solder joint interconnection status of all memory dies within the package is uniformly measured to obtain the interconnection status feature vector of each memory die. The overall deviation of the interconnection status feature vector of each memory die relative to the overall mean is calculated. Outlier dies are identified based on the calculation results. The cause of the outlier is identified based on the combination of the location characteristics and deviation index of the outlier die, and a targeted compensation operation is performed. The interconnection status feature vector after compensation is re-included in the horizontal comparison until the overall deviation of all memory dies falls within the outlier determination threshold. After configuring the bottom fill potting parameters, verifying the potting and interface integrity, the bridging BGA package structure is then encapsulated.

2. The method for fabricating a bridged BGA package structure for memory cascading as described in claim 1, characterized in that: The process window boundary narrowing operation for partitions where the mismatch index exceeds the trigger threshold is performed as follows: Based on measured physical properties, and using the contour of the silicon bridge chip embedding region as a reference, the top surface pad array of the organic packaging substrate is divided into multiple heterogeneous interface partitions. The deviation of the measured value of the thermal expansion coefficient relative to the nominal design value for each heterogeneous interface partition is calculated. Set the threshold for triggering thermal expansion coefficient deviation. If each partition is individually assessed for boundary narrowing based on a set threshold, then: If the result satisfies the formula Then it means the first The current batch's physical property deviation in each partition is within an acceptable range. The reflow process parameters for each partition remain unchanged from historical experience values. If the result satisfies the formula Then it means the first The current batch property deviation in one partition exceeds the acceptable range, triggering the [missing information]. Each partition corresponds to the process window boundary narrowing operation.

3. The method for fabricating a bridged BGA package structure for memory cascading as described in claim 1, characterized in that: The specific details of triggering the corresponding process parameter narrowing strategy based on the failure boundary type are as follows: If the current partition belongs to the solder overmelting collapse failure boundary type, then the peak temperature directional reduction strategy is triggered for the current partition, and the reflow peak temperature execution parameter of the current partition is shifted downward by a preset margin from the historical experience value. If the current partition belongs to the insufficient wetting failure boundary type, the peak residence time directional extension strategy is triggered for the current partition, and the execution parameter of the reflux peak temperature residence time of the current partition is shifted upward by a preset margin from the historical experience value. If the current partition belongs to the interface thermal shock failure boundary type, then trigger the heating slope directional reduction strategy for the current partition, and shift the reflow heating slope execution parameter of the current partition downward by a preset margin from the historical experience value. If the current partition meets the criteria for two or more failure boundary types, then the current partition is determined to be a composite failure boundary type. In turn, a directional narrowing strategy is executed for each corresponding process parameter, that is, all applicable operations in peak temperature reduction, peak residence time extension and temperature rise slope reduction are executed simultaneously until the failure boundary type of all trigger boundary narrowing partitions is identified and the corresponding process parameters are determined.

4. The method for fabricating a bridged BGA package structure for memory cascading as described in claim 1, characterized in that: The specific configuration of differentiated solder paste printing parameters for each partition based on the determined execution parameters for each partition is as follows: For the area directly above the bridging chip, a standard reference solder paste printing thickness is used, and a low-activity flux formula is selected. For the transition area around the bridging chip, the solder paste printing thickness is increased relative to the reference value to provide additional solder compensation for the current area during reflow. At the same time, the flux is selected with a modified formula containing elastic buffer components. For the organic substrate body area, the solder paste printing thickness and flux formulation remain unchanged based on historical experience. After configuring the differentiated solder paste printing parameters, the actual solder paste printing thickness of each zone is measured online. If the deviation of the actual printing thickness of any zone from the target value exceeds the preset tolerance range, the stencil opening parameter adjustment is automatically triggered. The stencil opening size corresponding to the zone with the excessive deviation is specifically corrected. After correction, the solder paste printing is re-executed and measured again until the solder paste printing thickness of all zones falls within their respective target tolerance range.

5. The method for fabricating a bridged BGA package structure for memory cascading as described in claim 1, characterized in that: The process of determining whether the interface state of the current welding stage is compliant based on the comparison results is as follows: For each sequential welding stage After the corresponding sequential welding step is completed, an interface status evaluation report for the current step is generated. The evaluation report is then compared with preset compliance criteria, resulting in: If the first If the interface state evaluation result of the welding step meets the preset compliance criteria, then the welding step is considered to be in compliance. The interface status of each step is compliant, unlocking the first step. Execution permissions for each stage; If the first If the interface state evaluation result of the welding step does not meet the compliance conditions compared with the preset compliance criteria, then it means that the first welding step... The interface status of each step is non-compliant. Each component must remain locked and cannot be started.

6. The method for fabricating a bridged BGA package structure for memory cascading as described in claim 5, characterized in that: The criteria for determining whether the interface state in the current welding process is compliant vary depending on the specific welding stage, as follows: Regarding the evaluation of the interface status and compliance criteria for the first stage, we have: Obtain the void ratio of the bonded and cured layer and the continuous length of layered defects Set a compliance upper limit for the void ratio of the bonded curing layer. and the compliance limit for continuous length of layered defects The interface status of the first stage is judged according to the set compliance criteria. Regarding the interface status evaluation and compliance criteria for the second stage, we have: X-ray transmission electron microspinning (XRT) was used to obtain the internal void ratio of the microbump solder joints of each memory die after flip-chip bonding and reflow soldering. Solder joint height consistency deviation was obtained by laser confocal scanning. Simultaneously, optical inspection was performed on the wetting morphology of the weld joints to obtain the number of cold welding defects. Set a compliance upper limit for the void ratio of micro-bump solder joints. Upper limit of compliance for weld point height consistency deviation and the upper limit for the number of compliant cold welding defects. The interface status of the second stage is judged according to the established compliance criteria. Regarding the evaluation of the interface status and compliance criteria for the third stage, we have: After the bottom-side BGA solder ball placement and overall reflow soldering are completed, the overall coplanarity deviation of the BGA solder balls is obtained by automatic optical inspection. Number of bridging defects And the average contact resistance of the interface metallization layer was obtained by the four-probe method. Set an upper limit for the overall coplanarity deviation of BGA solder balls to meet compliance requirements. Maximum number of bridge defect compliance and the upper limit of compliance for contact resistance of the interface metallization layer. The interface status of the third stage is judged based on the established compliance criteria.

7. The method for fabricating a bridged BGA package structure for memory cascading as described in claim 6, characterized in that: The determination of the interface status in the first stage based on the set compliance criteria is as follows: like If so, it means that the interface status of the first stage is compliant, and the execution permission of the second stage is unlocked; like If the first stage interface state is non-compliant, the information about excessive void rate or delamination defects will be transmitted back to the embedded curing process parameter configuration sub-process. This will trigger targeted adjustments to the curing temperature or curing time based on the cause of the voids. After correction, curing will be re-executed and the test repeated until the formula is met. until.

8. The method for fabricating a bridged BGA package structure for memory cascading as described in claim 1, characterized in that: The identification of outlier wafers based on the calculation results is as follows: The solder joint interconnect states of all memory dies within the package are uniformly measured to obtain the interconnect state feature vector for each die. A lateral comparison is then performed among the interconnect state feature vectors of all memory dies to calculate the deviation of each die's interconnect state feature vector from the overall mean. Set an outlier detection threshold If each memory die is determined to be an outlier based on a set threshold, then: If the first The overall deviation of each memory die from the set threshold is compared with the formula. Then it means the first The interconnection status of the individual memory dies is consistent and no targeted compensation is required. If the first The overall deviation of each memory die from the set threshold is compared with the formula. Then it means the first If a storage die is found to be an outlier, location feature analysis and targeted compensation for that die will be triggered.

9. The method for fabricating a bridged BGA package structure for memory cascading as described in claim 8, characterized in that: The process of identifying the cause of outliers and performing targeted compensation based on a combination of outlier wafer location characteristics and deviation indices is as follows: If the outlier die is located at the edge of the package, and its solder joint height averages Below the overall mean If the outlier is determined to be due to insufficient solder wetting caused by a low edge reflow thermal field, a local induction heating compensation operation is performed on the current location of the die. If the outlier die is located in the central region of the package, and its average solder joint void ratio is... Higher than the overall mean If the out-of-group condition is determined to be due to the flux evaporation channel in the central area being blocked by the surrounding bare die, making it difficult for residual gas to escape, a vacuum-assisted exhaust operation is specifically performed on the current location of the bare die. If the average contact resistance of the microbumps on the outlier die is Higher than the overall mean If the outlier is determined to be due to incomplete metallization of the microbump interface at the current location, a local controlled pressure bonding compensation operation will be performed on the current die.

10. The method for fabricating a bridged BGA package structure for memory cascading as described in claim 1, characterized in that: The process of re-incorporating the compensated interconnection state feature vectors into the lateral comparison is as follows: After targeted compensation processing, the corrected interconnect state feature vectors of each outlier die are re-included in the lateral comparison, and the corrected overall deviation is recalculated. and outlier detection threshold Upon comparison, we have: If the correction If the current die has passed the interconnection consistency test after directional compensation, then the current die will be included in the set of qualified dies. If the correction If the current wafer still deviates after directional compensation, positional feature analysis is re-executed to identify any compound causes. For each compound cause, the corresponding directional compensation operation is performed sequentially. After compensation, the overall deviation is recalculated and compared again with the outlier threshold until the corrected overall deviation of the current wafer meets the threshold. until.

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