Dual-layer wiring vertical interconnection wafer level package structure and method of manufacturing the same

Abstract

This invention provides a wafer-level packaging structure and fabrication method for a dual-layer vertical interconnect (RDL) package, relating to the field of chip packaging technology. The packaging structure includes at least one power device chip, a dielectric layer, a first redistribution layer, a molding compound, a vertical interconnect structure, a second redistribution layer, and power electrode pads. It employs a dual-layer redistribution layer (RDL) structure, with the source metal layer and gate metal layer fabricated separately and spaced apart, effectively reducing parasitic parameters. Simultaneously, the source lead layer and gate lead layer can respectively cover the source metal layer and gate metal layer, significantly expanding the range and thickness of the metal layers and greatly improving the thermal conductivity and heat dissipation capabilities of the power device chip's front side. Furthermore, utilizing the vertical interconnect structure to achieve front and back metal interconnection results in a smaller volume compared to traditional packaging structures, facilitating miniaturization of packaged products, shortening the transmission path, and significantly improving the overall performance of the power device.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a wafer-level packaging structure with dual-layer wiring vertical interconnection and its fabrication method. Background Technology

[0002] Traditional power devices mostly use conventional discrete packaging forms such as PDFN, TO, and DFN. Mainstream packaging processes employ single-chip packaging, metal strip bonding, or gold / copper wire bonding to interconnect the front electrodes, while the back of the chip uses solder paste to attach a lead frame island for electrode exposure and heat dissipation. This type of traditional packaging structure has many inherent drawbacks, including large parasitic parameters, large footprint, difficulty in balancing conduction losses and switching performance, and poor heat dissipation. Furthermore, in existing improvement solutions, wafer-level fan-out packaging and TMV (Through Mold Via) molding vertical interconnect technology are gradually being applied to the power device packaging field. Existing technologies typically require the use of RDL (Redistribution Layer) for circuit connections; however, their wiring structure is simplistic, often employing a single-layer RDL, which cannot achieve differentiated wiring designs for electrodes with varying currents in power devices. This makes it difficult to balance high current carrying capacity with low parasitic parameter requirements, and fails to substantially address the core pain points of low parasitics and high heat dissipation in power devices. Summary of the Invention

[0003] The purpose of this invention is to provide a wafer-level packaging structure with dual-layer wiring vertical interconnection and its fabrication method, which can overcome the problems of traditional packaging wiring being single, having large parasitic parameters, large size, and poor heat dissipation performance, and significantly improve the overall performance of power devices.

[0004] The embodiments of the present invention are implemented through the following scheme: In a first aspect, embodiments of the present invention provide a wafer-level packaging structure with dual-layer wiring vertical interconnect, comprising: At least one power device chip; A dielectric layer is disposed on the front side of the power device chip and has source windows and gate windows spaced apart. The first redistribution layer includes a source metal layer and a gate metal layer, which are respectively disposed in the source window and the gate window and separated by the dielectric layer. A molding compound surrounds the power device chip, wherein the source metal layer and the gate metal layer are exposed outside the molding compound. A vertical interconnect structure includes a source conductive pillar and a gate conductive pillar, both of which are disposed through the molding compound and exposed outside the molding compound. The second wiring layer includes a source pin layer and a gate pin layer, wherein the source pin layer covers the source metal layer and the source conductive pillar, and the gate pin layer covers the gate metal layer and the gate conductive pillar; The power electrode pads include a drain pad, a source pad, and a gate pad that are spaced apart from each other. The drain pad is disposed on the back side of the power device chip. The source pad covers the end of the source conductive post away from the source pin layer. The gate pad covers the gate conductive post.

[0005] In an optional implementation, the area of ​​the source metal layer is larger than the area of ​​the gate metal layer.

[0006] In an optional implementation, the area of ​​the source metal layer is greater than or equal to 50% of the front area of ​​the power device chip.

[0007] In an optional embodiment, the width of the gate metal layer is between 5 and 20 μm.

[0008] In an optional embodiment, an insulating layer is further provided on the side surface of the molding layer near the front of the power device chip. A source slot and a gate slot are formed on the insulating layer. The source slot exposes the source metal layer and the source conductive pillar, and the gate slot exposes the gate metal layer and the gate conductive pillar. The source pin layer and the gate pin layer are respectively disposed in the source slot and the gate slot.

[0009] In an optional embodiment, a protective adhesive layer is further provided on the surface of the second redistribution layer away from the power device chip, the protective adhesive layer covering the source pin layer and the gate pin layer.

[0010] In an optional embodiment, a protective silicon wafer is also attached to the surface of the protective adhesive layer away from the power device chip.

[0011] In an optional embodiment, a bonding via is formed on the source metal layer and the source pin layer, the bonding via penetrating the source metal layer and the source pin layer.

[0012] In an optional embodiment, the side of the source pad away from the source conductive pillar, the side of the drain pad away from the power device chip, and the side of the gate pad away from the gate conductive pillar are all covered with a tin plating layer.

[0013] In another aspect, embodiments of the present invention also provide a method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnection, for use in the aforementioned wafer-level packaging structure with dual-layer wiring vertical interconnection, the fabrication method comprising: A wafer is provided, wherein the wafer includes a plurality of power device chips; A dielectric layer and a first redistribution layer are formed on the front side of the wafer, wherein the dielectric layer covers the front side of the power device chip and has spaced-apart source windows and gate windows. The first redistribution layer includes a source metal layer and a gate metal layer, which are respectively disposed in the source window and the gate window and separated by the dielectric layer. The wafer is diced to form a single power device chip; The back side of the power device chip is attached to the first carrier; A molding compound is formed on the first carrier, wherein the molding compound covers the power device chip and the source metal layer and the gate metal layer are exposed outside the molding compound; A vertical interconnect structure is formed in the molding compound, wherein the vertical interconnect structure includes a source conductive pillar and a gate conductive pillar, both of which are disposed through the molding compound and exposed outside the molding compound; A second wiring layer is formed on the first wiring layer, wherein the second wiring layer includes a source pin layer and a gate pin layer, the source pin layer covers the source metal layer and the source conductive pillar, and the gate pin layer covers the gate metal layer and the gate conductive pillar; The first carrier is stripped off, and power electrode pads are formed on the back side of the power device chip. The power electrode pads include drain pads, source pads and gate pads that are spaced apart from each other. The drain pads are disposed on the back side of the power device chip. The source pads cover the end of the source conductive pillar away from the source pin layer. The gate pads cover the gate conductive pillar.

[0014] In an optional embodiment, the step of forming a dielectric layer and a first redistribution layer on the front side of the wafer includes: A dielectric layer is formed on the front side of the wafer; The dielectric layer is patterned to form spaced-apart source windows and gate windows on the dielectric layer; A source metal layer and a gate metal layer are formed in the source window and the gate window, respectively.

[0015] In an optional implementation, the step of forming a second overlay layer on the first overlay layer includes: An insulating layer is formed on the molding layer; The insulating layer is patterned to form source slots and gate slots on the insulating layer, wherein the source slots expose the source metal layer and the source conductive pillars, and the gate slots expose the gate metal layer and the gate conductive pillars. A source pin layer and a gate pin layer are formed in the source slot and the gate slot, respectively.

[0016] In an optional implementation, after the step of forming the second overriding layer on the first overriding layer, the method further includes: A protective adhesive layer is formed on the second rewiring layer; A protective silicon wafer is attached to the protective adhesive layer.

[0017] In an optional implementation, the step of stripping the first carrier and forming power electrode pads on the back side of the power device chip includes: The first carrier is thermally peeled off to expose the back side of the power device chip; The protective silicon wafer is attached to the second carrier; A metal seed layer is sputtered onto the back side of the power device chip and then electroplated to thicken it to form power electrode pads.

[0018] In a third aspect, embodiments of the present invention provide a method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnect, for use in the aforementioned wafer-level packaging structure with dual-layer wiring vertical interconnect, the fabrication method comprising: A wafer is provided, wherein the wafer includes a plurality of power device chips; A dielectric layer and a first redistribution layer are formed on the front side of the wafer, wherein the dielectric layer covers the front side of the power device chip and has spaced-apart source windows and gate windows. The first redistribution layer includes a source metal layer and a gate metal layer, which are respectively disposed in the source window and the gate window and separated by the dielectric layer. The wafer is diced to form a single power device chip; A vertical interconnect structure is formed on a first carrier, wherein the vertical interconnect structure includes spaced source conductive pillars and gate conductive pillars; The back side of the power device chip is attached to the first carrier; A molding compound is formed on the first carrier, wherein the molding compound covers the power device chip, the source metal layer and the gate metal layer are exposed in the molding compound, and the source conductive pillar and the gate conductive pillar are both disposed through the molding compound and exposed in the molding compound. A second wiring layer is formed on the first wiring layer, wherein the second wiring layer includes a source pin layer and a gate pin layer, the source pin layer covers the source metal layer and the source conductive pillar, and the gate pin layer covers the gate metal layer and the gate conductive pillar; The first carrier is stripped off, and power electrode pads are formed on the back side of the power device chip. The power electrode pads include drain pads, source pads and gate pads that are spaced apart from each other. The drain pads are disposed on the back side of the power device chip. The source pads cover the end of the source conductive pillar away from the source pin layer. The gate pads cover the gate conductive pillar.

[0019] In an optional implementation, the step of forming a vertical interconnect structure on the first vehicle includes: A photoresist layer is formed on the surface of the first carrier; The photoresist layer is patterned to form source trenches and gate trenches by spaced grooves on the photoresist layer. Source conductive pillars and gate conductive pillars are respectively electroplated in the source groove and the gate groove; Remove the photoresist layer.

[0020] The beneficial effects of the embodiments of the present invention include: This invention provides a wafer-level packaging structure with dual-layer vertical interconnect and its fabrication method. A dielectric layer is disposed on the front side of the power device chip, on which spaced-apart source windows and gate windows are formed. Source metal layers and gate metal layers are respectively disposed within the source and gate windows, forming a first wiring layer. A molding compound surrounds the power device chip, with the source and gate metal layers exposed. Source conductive pillars and gate conductive pillars are also disposed through the molding compound, forming a vertical interconnect structure. A source lead layer covers the source metal layer and source conductive pillars, and a gate lead layer covers the gate metal layer and gate conductive pillars, forming a second wiring layer. Power electrode pads are distributed on the back side of the power device chip. The source pads cover the end of the source conductive pillars furthest from the source lead layer, achieving vertical interconnection with the source lead layer on the front side through the source conductive pillars. Gate pads cover the gate conductive pillars, achieving vertical interconnection with the gate lead layer on the front side through the gate conductive pillars.

[0021] Compared to existing technologies, the wafer-level packaging structure and its fabrication method with dual-layer vertical interconnect provided in this invention employs a dual-layer redistribution layer (RDL) structure. The source metal layer and gate metal layer are fabricated separately and spaced apart, effectively reducing parasitic parameters. Simultaneously, the source lead layer and gate lead layer can respectively cover the source metal layer and gate metal layer, significantly expanding the range and thickness of the metal layers and greatly improving the thermal conductivity and heat dissipation capabilities of the power device chip's front side. Furthermore, utilizing the vertical interconnect structure to achieve front and back metal interconnection results in a smaller package size compared to traditional packaging structures, facilitating miniaturization of packaged products, shortening the transmission path, and significantly improving the overall performance of the power device. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A schematic diagram of a wafer-level packaging structure with dual-layer wiring vertical interconnect provided in an embodiment of the present invention; Figure 2 for Figure 1 Top view at point AA; Figure 3 for Figure 1 Top view at point BB; Figure 4a for Figure 1 A bottom view at point C; Figure 4b A schematic diagram of another wafer-level packaging structure with dual-layer wiring vertical interconnection provided in an embodiment of the present invention; Figure 4c for Figure 4b Top view at point DD; Figure 5 This is a schematic diagram of the structure corresponding to step S2 in the method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnection provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of the structure corresponding to step S3 in the method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnection provided in an embodiment of the present invention. Figure 7 This is a schematic diagram of step S4 in the fabrication method of the wafer-level packaging structure with dual-layer wiring vertical interconnection provided in the embodiment of the present invention. Figure 8This is a schematic diagram of step S5 in the method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnection provided in an embodiment of the present invention. Figure 9 This is a schematic diagram of step S6 in the method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnection provided in an embodiment of the present invention. Figure 10 This is a top view of the structure corresponding to step S6 in the method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnection provided in an embodiment of the present invention. Figure 11 This is a schematic diagram of the structure corresponding to step S7 in the method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnection provided in an embodiment of the present invention. Figure 12 This is a top view of the structure corresponding to step S7 in the method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnection provided in an embodiment of the present invention. Figure 13 This is a schematic diagram of the protection step in the fabrication method of the wafer-level packaging structure with dual-layer wiring vertical interconnection provided in the embodiment of the present invention. Figure 14a This is a schematic diagram of the structure corresponding to step S8 in the method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnection provided in an embodiment of the present invention. Figure 14b This is a schematic diagram of another structure corresponding to step S8 in the method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnection provided in an embodiment of the present invention. Figure 15 A schematic diagram of step S4 in a method for fabricating another wafer-level packaging structure with vertical interconnection of double-layer wiring provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of step S5 in a method for fabricating another wafer-level packaging structure with vertical interconnection of double-layer wiring provided in an embodiment of the present invention.

[0024] Icons: 100 - Wafer-level package structure with dual-layer vertical interconnect; 110 - Power device chip; 120 - Dielectric layer; 130 - First rewiring layer; 131 - Source metal layer; 132 - Gate metal layer; 140 - Molding layer; 150 - Vertical interconnect structure; 151 - Source conductive pillar; 152 - Gate conductive pillar; 160 - Second rewiring layer; 161 - Source pin layer; 162 - Gate pin layer; 170 - Power electrode pad; 171 - Drain pad; 172 - Source pad; 173 - Gate pad; 174 - Tin plating layer; 175 - Side creep trench; 180 - Insulating layer; 190 - Protective adhesive layer; 191 - Protective silicon wafer; 192 - Bonding via; 200 - First carrier; 300 - Second carrier. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0027] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0028] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0029] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0030] As disclosed in the background section, existing conventional power devices mostly adopt traditional discrete packaging forms such as PDFN, TO, and DFN. Mainstream packaging processes use single-chip packaging, metal strip bonding, or gold / copper wire bonding to achieve front electrode interconnection, while the back of the chip uses solder paste to attach lead frames and base islands for electrode extraction and heat dissipation. This type of traditional packaging structure has many inherent defects: First, traditional wire bonding and metal strip bonding interconnection methods have large parasitic resistance and parasitic inductance, resulting in high switching losses and poor signal stability under high-frequency operating conditions, which cannot meet the application requirements of high-frequency and high-efficiency power devices. Second, the lead frame structure occupies a large package volume, which limits the miniaturization of the package. Furthermore, the single-chip packaging process is cumbersome, with many process redundancies, resulting in high mass production costs and low production efficiency. Third, the large and small current electrodes on the front of the chip use a uniform bonding method, which cannot be specifically adapted to the differentiated needs of large current carrying capacity and small current low parasitics, making it difficult to balance device conduction loss and switching performance. Fourth, the back of the chip relies on a solder paste layer to connect with the base island, resulting in a long heat dissipation path and high thermal resistance. Under high-power operation, it is prone to excessive temperature rise, which restricts the current carrying capacity and lifespan of power devices.

[0031] In existing improvement solutions, wafer-level fan-out packaging and TMV molding vertical interconnect technology are gradually being applied to the power device packaging field. Conventional TMV packaging often uses a process of laser drilling and copper filling after molding; however, the drilling process easily damages the chip itself, resulting in poor via consistency and low yield. Furthermore, traditional wafer-level packaging often uses whole-wafer bonding processes, which are limited by the inherent yield of the wafer, preventing improvements in overall packaging yield and incurring high equipment costs. Simultaneously, existing RDL wiring structures are simple, often using single-layer RDL wiring, which cannot achieve differentiated wiring designs for electrodes with varying currents in power devices. It is difficult to balance high current carrying capacity with low parasitic parameters, and there is a lack of combination processes that combine double-layer RDL with pre-formed TMV vertical interconnect and D2W precise mounting. This fails to simultaneously address the core pain points of low parasitic parameters, high heat dissipation, high yield, and low-cost mass production of power devices, resulting in poor packaging versatility and device compatibility, making it difficult to meet the large-scale mass production needs of various power devices. In addition, the stacked structure of conventional power devices is prone to delamination, leading to warping and affecting chip performance.

[0032] In summary, there is an urgent need for a wafer-level power device packaging solution based on dual-layer differentiated RDL wiring and TMV vertical interconnect, which can balance electrical performance, heat dissipation performance and mass production performance, and solve many of the shortcomings of existing technologies.

[0033] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0034] See Figure 1 , Figure 2 , Figure 3 and Figure 4a This invention provides a wafer-level packaging structure 100 with dual-layer wiring vertical interconnection, which can overcome the problems of traditional packaging wiring being single, having large parasitic parameters, large size, and poor heat dissipation performance, and significantly improve the overall performance of power devices.

[0035] The wafer-level package structure 100 with dual-layer vertical interconnect provided in this embodiment of the invention includes at least one power device chip 110, a dielectric layer 120, a first rewiring layer 130, a molding compound layer 140, a vertical interconnect structure 150, a second rewiring layer 160, and power electrode pads 170. The dielectric layer 120 is disposed on the front side of the power device chip 110 and has spaced-apart source windows and gate windows. The first rewiring layer 130 includes a source metal layer 131 and a gate metal layer 132, which are respectively disposed in the source window and the gate window and separated by the dielectric layer 120. The molding compound layer 140 covers the power device chip 110, wherein the source metal layer 131 and the gate metal layer 132 are exposed outside the molding compound layer 140. The vertical interconnect structure 150 includes a source conductive pillar 151 and a gate conductive pillar 152, both of which are disposed through the molding compound 140 and exposed outside the molding compound 140. The second redistribution layer 160 includes a source pin layer 161 and a gate pin layer 162. The source pin layer 161 covers the source metal layer 131 and the source conductive pillar 151, and the gate pin layer 162 covers the gate metal layer 132 and the gate conductive pillar 152. The power electrode pad 170 includes a drain pad 171, a source pad 172, and a gate pad 173 spaced apart from each other. The drain pad 171 is disposed on the back side of the power device chip 110, the source pad 172 covers the end of the source conductive pillar 151 away from the source pin layer 161, and the gate pad 173 covers the gate conductive pillar 152.

[0036] It should be noted that the wafer-level packaging structure 100 with dual-layer vertical interconnect and its fabrication method provided in this embodiment of the invention adopts a dual-layer redistribution layer (RDL) structure. The first redistribution layer 130 and the second redistribution layer 160 can form a dual-layer vertical interconnect wiring system. The source metal layer 131 and the gate metal layer 132 are fabricated separately and spaced apart, effectively reducing parasitic parameters. Simultaneously, the source pin layer 161 and the gate pin layer 162 can respectively cover the source metal layer 131 and the gate metal layer 132, significantly expanding the range and thickness of the metal layers and greatly improving the heat conduction and dissipation capabilities of the power device chip 110. Furthermore, the vertical interconnect structure 150 achieves front and back metal interconnection, resulting in a smaller volume compared to traditional packaging structures, which is beneficial for miniaturization of packaged products and shortens the transmission path, significantly improving the overall performance of the power device.

[0037] In some embodiments, there may be multiple power device chips 110 arranged in an array. This embodiment of the invention uses one of them as an example for structural description. The power device chips 110 are precisely mounted using a D2W (Die-to-Wafer) chip bonding process, and all power device chips 110 are in a fixed orientation with the front side facing up and the back side facing down. The front side of the power device chip 110 may have a source pin layer 161 and a gate pin layer 162, serving as high-current electrode pads and low-current control electrode pads, respectively, while the back side has power electrode pads 170. For information on the electrical connection characteristics and principles of the power device chip 110, please refer to existing packaging structures.

[0038] It should be noted that in this embodiment of the invention, the molding compound 140 is formed by wafer-level molding, covering all power devices and the first rewiring layer 130. The molding compound 140 integrates several pre-formed vertical interconnect structures 150, wherein the source conductive pillars 151 and gate conductive pillars 152 constitute the vertical interconnect structure 150, and both the source conductive pillars 151 and gate conductive pillars 152 are TMV copper pillars. The bottom end of the vertical interconnect structure 150 (source conductive pillar 151 / gate conductive pillar 152) can be vertically connected to each electrode wiring of the first rewiring layer 130, and the top end can extend to the surface of the molding compound 140, realizing the vertical interconnect transition between the upper and lower layers. The second rewiring layer 160 is formed on the surface of the molding compound 140 and connects the tops of each pre-formed TMV copper pillar through a patterned wiring structure, realizing multi-channel parallel lead-out of high-current electrodes and independent and precise lead-out of low-current control electrodes, thereby forming standardized external pins on the front side of the package.

[0039] In some embodiments, the area of ​​the source metal layer 131 is larger than the area of ​​the gate metal layer 132. Further, the area of ​​the source metal layer 131 is greater than or equal to 50% of the front area of ​​the power device chip 110, and the width of the gate metal layer 132 is between 5 and 20 μm. Specifically, the source metal layer 131, gate metal layer 132, source lead layer 161, and gate lead layer 162 are all copper layers, and the dielectric layer 120 can be made of polyimide (PI) material. The source metal layer 131 and gate metal layer 132 can employ differentiated thick copper wiring. The source metal layer 131 can employ large-area thick copper wiring to correspond to the high-current electrode region, adapting to the high-current conduction requirements and maximizing the device's high-current carrying and conduction capabilities. The gate metal layer 132 can employ narrow-line thick copper wiring to correspond to the low-current electrode region, reducing parasitic parameters.

[0040] In some embodiments, an insulating layer 180 is further disposed on the side surface of the molding compound 140 near the front of the power device chip 110. A source slot and a gate slot are formed on the insulating layer 180. The source slot exposes the source metal layer 131 and the source conductive pillar 151, and the gate slot exposes the gate metal layer 132 and the gate conductive pillar 152. A source lead layer 161 and a gate lead layer 162 are respectively disposed in the source slot and the gate slot. Specifically, the insulating layer 180 can be made of an insulating dielectric material, such as polyimide (PI), and the area of ​​the source slot is larger than the area of ​​the source metal layer 131, and the area of ​​the gate slot is larger than the area of ​​the gate metal layer 132, making the areas of the source lead layer 161 and the gate lead layer 162 relatively larger. This ensures current carrying capacity and improves heat dissipation.

[0041] It is worth noting that the gate metal layer 132 and source metal layer 131 of the first wiring layer 130 can be formed together. The wiring thickness of the first wiring layer 130 is controlled between 20-50μm. The high-current electrode region (source metal layer 131) adopts full-coverage thick copper wiring to reduce conduction losses. The wiring width of the low-current control electrode region can be controlled within 10μm, which can effectively reduce high-frequency parasitic inductance and achieve performance adaptation between high and low current electrodes. The thickness of the second wiring layer 160 is 10-20μm. It adopts high-precision patterned wiring, which can realize the parallel interconnection of multiple high-current TMV copper pillars (source conductive pillars 151), improve the overall current carrying capacity and wiring uniformity, and at the same time ensure the precise and independent wiring of the low-current control electrode to avoid signal interference.

[0042] Furthermore, the molding layer 140 can be molded using a high thermal conductivity epoxy molding compound with a thickness of 150-200μm, completely encapsulating the power device chip 110 and the first redistribution layer 130 (bottom RDL), thus providing structural protection, insulation, and auxiliary heat dissipation.

[0043] In some embodiments, a protective adhesive layer 190 is further disposed on the surface of the second redistribution layer 160 away from the power device chip 110, the protective adhesive layer 190 covering the source pin layer 161 and the gate pin layer 162. The protective adhesive layer 190 may be polyimide (PI) and serves to provide protection and electrical isolation.

[0044] Furthermore, a protective silicon wafer 191 is also attached to the surface of the protective adhesive layer 190 away from the power device chip 110. By setting the silicon wafer, it can provide further protection and structural support.

[0045] See also Figure 4b and Figure 4cIn other preferred embodiments of the present invention, bonding vias are formed on the source metal layer 131 and the source lead layer 161, and the bonding vias penetrate the source metal layer 131 and the source lead layer 161. Specifically, since the protective adhesive layer 190 and the source lead layer 161 are in surface-to-surface contact, and the metal layer is formed on the surface of the power device chip 110, a stacked structure is formed. This stacked structure is prone to delamination, which can lead to warping and affect chip performance. To improve the packaging delamination and overall structural stress, some holes can be formed in the source metal layer 131 and the source lead layer 161, that is, after molding the source metal layer 131 and the source lead layer 161, slots are made to form bonding vias 192. When forming the protective adhesive layer 190, the protective adhesive layer 190 can fill the bonding vias 192, so that the protective adhesive layer 190 and the metal layer can be staggered, increasing the bonding force and reducing warping.

[0046] Furthermore, several through-holes can be distributed in the middle region and around the perimeter of the source metal layer 131. These through-holes are preferably circular or hexagonal to avoid stress concentration at sharp corners, ensuring that the protective adhesive layer 190 can be fully filled. The overall perforated area accounts for 5-15% of the total area of ​​the source metal layer 131, achieving interface strengthening without sacrificing current carrying capacity. When forming the protective adhesive layer 190, adhesive can be injected under molding conditions. The adhesive layer penetrates and fills all the through-holes and cures, forming an array of adhesive pillars anchoring the source metal layer 131. This constructs a mechanically interlocking structure between the copper layer and the adhesive layer, blocking the path of interface delamination and expansion; it also cuts off the continuous residual stress path within the thick copper layer, preventing stress concentration.

[0047] In some embodiments, the side of the source pad 172 away from the source conductive pillar 151, the side of the drain pad 171 away from the power device chip 110, and the side of the gate pad 173 away from the gate conductive pillar 152 are all covered with a tin plating layer 174. Specifically, the side of the source pad 172 away from the source conductive pillar 151 is also covered with a source tin layer; the side of the drain pad 171 away from the power device chip 110 is also covered with a drain tin layer; and the side of the gate pad 173 away from the gate conductive pillar 152 is also covered with a gate tin layer. In particular, the power electrode pads 170 on the back side of the power device chip 110 are all thickened electroplated copper layers with a thickness of 15-25 μm, and are tin-plated on the surface, giving the power electrode pads 170 on the back side excellent conductivity and heat dissipation performance, suitable for high-power applications.

[0048] This invention also provides a method for fabricating a first type of wafer-level package structure 100 with dual-layer wiring vertical interconnect, for use in the aforementioned wafer-level package structure 100 with dual-layer wiring vertical interconnect. The fabrication method includes the following steps: S1: Provide a wafer, wherein the wafer includes a plurality of power device chips 110.

[0049] Specifically, the wafer is first pre-processed to provide a whole wafer (containing multiple power device chips 110 dies), then the back side of the wafer is ground and thinned to control the wafer thickness to 100-150μm, and the front and back sides of the wafer are plasma cleaned to remove the surface oxide layer and impurities.

[0050] S2: A dielectric layer 120 and a first redistribution layer 130 are formed on the front side of the wafer.

[0051] See also Figure 5 The dielectric layer 120 covers the front side of the power device chip 110 and forms a source window and a gate window spaced apart. The first redistribution layer 130 includes a source metal layer 131 and a gate metal layer 132, which are respectively disposed in the source window and the gate window and are separated by the dielectric layer 120.

[0052] Specifically, a dielectric layer 120 can be formed on the front side of the wafer first, and a PI / silicon dioxide insulating layer 180 can be deposited on the front side of the wafer. Then, the dielectric layer 120 is patterned to form spaced-apart source windows and gate windows. Specifically, the high-current electrode and low-current control electrode pads on the front side of the chip can be exposed by an exposure and development process. Finally, a source metal layer 131 and a gate metal layer 132 are formed in the source window and gate window, respectively. Specifically, the first copper RDL (first redistribution layer 130) can be fabricated by an electroplating process. A 20-50 μm thick copper layer is electroplated in the high-current electrode area (source window) to form a large area of ​​wiring, and a 20-50 μm thick copper layer is electroplated simultaneously in the low-current control electrode area (gate window) with the line diameter controlled to be within 10 μm, completing the differentiated bottom layer wiring.

[0053] In actual fabrication, fabricating the first interconnect layer 130 involves completing the thick copper interconnects of the source metal layer 131 and the gate metal layer 132. The first interconnect layer 130 is mainly used to construct the first interconnect structure of the high-current source and low-current gate on the front side of the chip, thereby replacing the traditional gold and copper wire bonding interconnection method. The specific process is as follows: 8–12 μm polyimide (PI) insulating dielectric material is spin-coated on the front side of the cleaned wafer, and then cured at high temperature to form a flat insulating substrate dielectric layer 120. Then, through photolithography exposure and development processes, windows are precisely opened on the dielectric layer 120 to form source windows and gate windows, exposing the source (S) and gate (G) aluminum pad areas on the front side of the chip. Subsequently, a patterned thick copper electroplating process was used to complete the differentiated wiring. A 30–50 μm thick copper layer was plated in the S-region (source window), forming a large copper layer covering 50% or more of the chip's front surface area, maximizing the device's high current carrying capacity and conduction capability. Similarly, a 30–50 μm thick copper layer was plated in the G-region (gate window), with the line width strictly controlled at 6–10 μm. This fine line structure effectively reduced high-frequency parasitic inductance. After wiring, residual photoresist was removed, and the first wiring layer 130 underwent plasma cleaning and surface roughening treatment to improve the bonding stability between the subsequent molding compound and the wiring layer.

[0054] S3: Divide the wafer to form a single power device chip 110.

[0055] See also Figure 6 Specifically, the entire wafer that has completed the fabrication of the first wiring layer 130 is cut into individual power device chips 110, and the electrical performance of each chip is pre-tested to select qualified chips for use.

[0056] In actual fabrication, UV cutting tape can be attached to the back of the wafer (i.e. the back of the power device chip 110) for fixation. Then, a cutting process (mechanical cutting or laser cutting) is used to cut the entire wafer into individual MOS chips (DIEs) along the cutting path. Then, the individual power device chip 110 is subjected to full parameter pre-testing with a probe card to screen out chips with qualified electrical performance.

[0057] S4: Attach the back side of the power device chip 110 to the first carrier 200.

[0058] See also Figure 7Specifically, a temporary carrier with a peelable adhesive layer can be prepared. Using a D2W chip-to-wafer mounting process, qualified single power device chips 110 are precisely mounted onto the surface of the temporary carrier with their front side facing up and back side facing down, and then cured. In actual preparation, a first carrier 200 can be used as a temporary support. A peelable pyrolytic adhesive layer is uniformly coated on the surface of the first carrier 200 and cured by heating to form a detachable temporary bonding layer. Then, a D2W mounting device picks up qualified power device chips 110, uniformly aligning them with their front side facing up and their back power electrodes facing down, and precisely mounts them onto the preset mounting points of the first carrier 200. After the entire chip mounting is completed, it is cured at a constant temperature in a vacuum oven to achieve a stable temporary bond between the power device chips 110 and the first carrier 200.

[0059] It should be noted that here, a single power device chip 110 is formed by dicing a wafer, and after passing the test and screening, it is re-mounted onto the first carrier 200 using the D2W high-precision pre-screening and mounting process. The first carrier 200 is then used to reconstruct the wafer. Therefore, by sorting qualified chips through pre-testing of chip electrical properties before whole-wafer packaging, the limitations of the original wafer yield are effectively avoided, and mass production losses are reduced. S5: Form a plastic sealant layer 140 on the first vehicle 200.

[0060] See Figure 8 The molding compound 140 surrounds the power device chip 110, with the source metal layer 131 and the gate metal layer 132 exposed outside the molding compound 140. Specifically, whole-wafer-level molding can be used, employing epoxy molding compound to mold the reconstructed wafer on which the power device chip 110 is mounted. The molding compound thickness is controlled at 150–200 μm, completely covering all power device chips 110 and the first redistribution layer 130. After molding and curing, the surface of the molding compound 140 is ground smooth to ensure the overall flatness of the molding compound 140.

[0061] In actual fabrication, a high thermal conductivity epoxy molding compound can be used to integrally encapsulate the entire chip on the substrate through a vacuum molding process. The molding compound completely covers all power device chips 110, the first redistribution layer 130, and the sidewalls of the power device chips 110. After the molding compound has completely cured, the top surface of the molding layer 140 is mechanically ground and chemically mechanically polished to flatten the surface of the molding layer 140 and ensure the overall structural flatness, thus providing a foundation for the subsequent TMV fabrication process.

[0062] S6: Form a vertical interconnect structure 150 in the molding layer 140.

[0063] See Figure 9 and Figure 10The vertical interconnect structure 150 includes a source conductive pillar 151 and a gate conductive pillar 152, both of which are disposed through the molding compound 140 and exposed outside the molding compound 140. Specifically, vertical vias can first be fabricated at the corresponding electrode positions in the flattened molding compound 140, and then pre-formed TMV copper pillars can be formed through an electroplating copper filling process, thus forming the source conductive pillar 151 and the gate conductive pillar 152. The bottom end of the TMV copper pillar is precisely connected to the electrode wiring of the first redistribution layer 130, and the top end is exposed on the surface of the molding compound 140, thus constructing a vertical interconnect channel.

[0064] In actual fabrication, photolithography can be performed on the surface of the flattened molding layer 140 to form TMV via molds corresponding to the source metal layer 131 and the gate metal layer 132, respectively. Then, vertical vias are fabricated using etching or laser drilling processes. Next, metal seed layers are sputtered onto the inner wall and bottom of the vias, and the vias are filled by electroplating copper to form pre-formed TMV vertical copper pillars with uniform conductivity and excellent verticality, thus forming the source conductive pillar 151 and the gate conductive pillar 152. Finally, the surface of the molding layer 140 is polished to remove excess copper material, so that the top of the TMV copper pillars is flat and exposed on the molding layer 140.

[0065] S7: A second routing layer 160 is formed on the first routing layer 130.

[0066] See Figure 11 and Figure 12 The second wiring layer 160 includes a source pin layer 161 and a gate pin layer 162. The source pin layer 161 covers the source metal layer 131 and the source conductive pillar 151, and the gate pin layer 162 covers the gate metal layer 132 and the gate conductive pillar 152. Specifically, an insulating layer 180 can be deposited on the molding layer 140 first, and then the insulating layer 180 can be patterned to form source trenches and gate trenches by photolithography. The source trenches expose the source metal layer 131 and the source conductive pillar 151, and the gate trenches expose the gate metal layer 132 and the gate conductive pillar 152. Finally, source pin layers 161 and gate pin layers 162 are formed in the source trenches and gate trenches, respectively. That is, the second wiring layer 160 is fabricated by patterned electroplating. The parallel interconnection of the high-current electrode TMV copper pillars (source conductive pillars 151) and the independent interconnection of the low-current control electrode TMV copper pillars (gate conductive pillars 152) are realized through the second wiring layer 160, thus completing the fabrication of the double-layer RDL vertical interconnection structure 150.

[0067] In actual fabrication, an insulating layer 180 can be spin-coated onto the surface of the molding layer 140 and the exposed TMV copper pillars and cured. Photolithography is used to open windows to expose the top electrodes of all TMV copper pillars. After sputtering a metal seed layer, a second wiring layer 160 is fabricated using a patterned electroplating process. All high-current TMV copper pillars (source conductive pillars 151) of the same power device chip 110 are connected in parallel and turned on, while low-current TMV copper pillars (gate conductive pillars 152) are led out independently to form a regular external pin on the front of the device. See Figure 13 In some embodiments, after the fabrication of the second redistribution layer 160 is completed, a protection step can be performed to form a protective adhesive layer 190 on the second redistribution layer 160, and then a protective silicon wafer 191 can be mounted on the protective adhesive layer 190.

[0068] S8: Strip the first carrier 200 and form power electrode pads 170 on the back side of the power device chip 110.

[0069] See Figure 14a The power electrode pads 170 include drain pads 171, source pads 172, and gate pads 173 spaced apart from each other. The drain pad 171 is disposed on the back side of the power device chip 110, the source pad 172 covers the end of the source conductive post 151 away from the source lead layer 161, and the gate pad 173 covers the gate conductive post 152. Specifically, the first carrier 200 can be thermally peeled off first to expose the back side of the power device chip 110. Then, the protective silicon wafer 191 is attached to the second carrier 300, a metal seed layer is sputtered on the back side of the power device chip 110, and a 10–20 μm thick back power electrode pad 170 is formed by electroplating and tin plating for anti-oxidation treatment.

[0070] In actual fabrication, the entire package of the first carrier 200 can be heated first to cause the pyrolytic adhesive on the surface of the first carrier 200 to fail and disintegrate. Then, the first carrier 200 is removed, and the entire wafer to be processed is flipped and re-attached to a new carrier (i.e., mounted to the second carrier 300), exposing the power electrode surface on the back of the chip. Then, the back of the package is plasma cleaned to thoroughly remove residual adhesive and impurities. Finally, a metal seed layer is sputtered on the back of the power device chip 110, and electroplating is used to thicken it to form a full-coverage large-area back power electrode pad 170, which forms the drain pad 171, the source pad 172 and the gate pad 173, and then tin plating is performed.

[0071] See Figure 14bIn other preferred embodiments of the present invention, before forming the power electrode pad 170, a side creep trench 175 can be formed on the molding layer 140. The side creep trench 175 is adjacent to and connected to the source conductive pillar 151 and / or the gate conductive pillar 152. After the electrode pad is reflowed, a quantifiable solder creep angle can be formed on the side of the conductive pillar. Subsequently, the solder creep height can be directly detected by 2D AOI, and the solder yield can be directly determined by visual inspection. Furthermore, a PDFN package structure (Wettable Flank PDFN) with wettable sides and detectable solder creep height can be realized.

[0072] Finally, please continue to see Figure 1 It can perform product cutting and testing sorting, cutting the entire 140mm plastic encapsulation layer into individual MOS transistors, and completing the final testing and packaging. For qualified products, it performs laser marking, tape and reel packaging, completing the entire encapsulation process.

[0073] This invention also provides a second method for fabricating a wafer-level package structure 100 with dual-layer wiring vertical interconnect, used to fabricate the aforementioned wafer-level package structure 100 with dual-layer wiring vertical interconnect. Its basic steps, principles, and resulting technical effects are the same as the aforementioned fabrication method. For brevity, any aspects not mentioned in this fabrication method can be referred to the corresponding content in the aforementioned fabrication method. The second fabrication method includes the following steps: S1: Provide a wafer.

[0074] First, a wafer is provided and preprocessed, wherein the wafer includes multiple power device chips 110.

[0075] S2: A dielectric layer 120 and a first redistribution layer 130 are formed on the front side of the wafer.

[0076] The dielectric layer 120 covers the front side of the power device chip 110 and has a source window and a gate window spaced apart. The first redistribution layer 130 includes a source metal layer 131 and a gate metal layer 132, which are respectively disposed in the source window and the gate window and are separated by the dielectric layer 120.

[0077] S3: Divide the wafer to form a single power device chip 110.

[0078] Steps S1 to S3 are the same as those in the first preparation method.

[0079] S4: A vertical interconnection structure 150 is formed on the first vehicle 200.

[0080] See Figure 15The vertical interconnect structure 150 includes spaced-apart source conductive pillars 151 and gate conductive pillars 152. The vertical copper pillar structure can be pre-fabricated on the first carrier 200 to reserve positions for subsequent precise chip D2W mounting and vertical interconnection. Specifically, the first carrier 200, made of glass or silicon, can be used as a temporary support substrate. A peelable pyrolytic adhesive is coated onto the surface of the first carrier 200 and cured. A metal seed layer is sputtered onto the pyrolytic adhesive surface to construct an electroplated conductive base. Subsequently, a copper pillar forming mold corresponding to the positions of the source and gate electrodes on the front side of the chip is prepared using photolithography. Copper is then electroplated into the mold to prepare pre-embedded integrated TMV vertical copper pillars, i.e., pre-forming the source conductive pillars 151 and gate conductive pillars 152. Finally, the entire wafer is subjected to CMP planarization to expose the tops of the copper pillars, completing the pre-embedded copper pillar array preparation. The mold is then removed, and the overall copper pillar structure is pre-fabricated on the wafer surface, ready for direct use in subsequent chip bonding.

[0081] In other preferred embodiments of the present invention, prefabricated copper pillars can also be used, that is, prefabricated copper pillars can be directly bonded to the first carrier 200. The height and dimensions of the prefabricated copper pillars are predetermined.

[0082] It should be noted that the use of pre-prepared copper pillars here avoids the laser drilling process after molding in traditional processes. The pre-fabrication of the vertical copper pillar array avoids chip damage and improves the verticality and conductivity consistency of the copper pillars.

[0083] S5: Attach the back side of the power device chip 110 to the first carrier 200.

[0084] See Figure 16 The D2W mounting equipment picks up qualified chips and mounts them precisely to the preset mounting points on the first carrier 200 with the front side facing up and the back side facing down. After the power device chips 110 on the whole board are mounted, they are cured at a constant temperature in a vacuum oven to achieve a stable temporary bond between the power device chips 110 and the first carrier 200.

[0085] It should be noted that during actual mounting, the pre-fabricated TMV copper pillars (i.e., source conductive pillar 151 and gate conductive pillar 152) can be used as positioning markers to facilitate more precise mounting of the power device chip 110.

[0086] S6: Form a plastic sealant layer 140 on the first vehicle 200.

[0087] Please continue reading Figure 9 and Figure 10The molding compound 140 surrounds the power device chip 110, with the source metal layer 131 and gate metal layer 132 exposed outside the molding compound 140. The source conductive pillars 151 and gate conductive pillars 152 are both disposed through the molding compound 140 and exposed outside it. Specifically, a high thermal conductivity epoxy molding compound is used to integrally mold the entire board of power device chips 110 on the first carrier 200 using a vacuum molding process. The molding compound completely covers all power device chips 110, the first redistribution layer 130, the chip sidewalls, and the embedded copper pillars. After the molding compound has completely cured, the top surface of the molding compound 140 is mechanically ground and chemically mechanically polished, and the molding compound 140 is thinned to expose the top surface of the copper pillars and the first redistribution layer 130, thus smoothing the surface of the molding compound 140.

[0088] It should be noted that, since the power device chip 110 and the prefabricated copper pillars are completed in advance, the molding compound can flow smoothly to the area around the chip and the copper pillars during the molding process. With the help of capillary action, the molding compound can be successfully filled, avoiding the occurrence of molding voids. S7: A second routing layer 160 is formed on the first routing layer 130.

[0089] Please continue reading Figure 11 and Figure 12 The second wiring layer 160 includes a source pin layer 161 and a gate pin layer 162. The source pin layer 161 covers the source metal layer 131 and the source conductive pillar 151, and the gate pin layer 162 covers the gate metal layer 132 and the gate conductive pillar 152.

[0090] S8: Strip the first carrier 200 and form power electrode pads 170 on the back side of the power device chip 110.

[0091] Please see Figure 14a The power electrode pad 170 includes a drain pad 171, a source pad 172 and a gate pad 173 that are spaced apart from each other. The drain pad 171 is disposed on the back side of the power device chip 110. The source pad 172 covers the end of the source conductive post 151 away from the source pin layer 161. The gate pad 173 covers the gate conductive post 152.

[0092] Steps S7 and S8 can be referenced from the first preparation method.

[0093] In summary, this invention provides a wafer-level package structure 100 with dual-layer vertical interconnect and its fabrication method. A dielectric layer 120 is disposed on the front side of a power device chip 110, and source windows and gate windows are formed on the dielectric layer 120 at intervals. A source metal layer 131 and a gate metal layer 132 are respectively disposed in the source windows and the gate windows, forming a first interconnect layer 130. A molding compound 140 covers the power device chip 110, and the source metal layer 131 and the gate metal layer 132 are exposed outside the molding compound 140. A source conductive pillar 151 and a gate conductive pillar 152 are also disposed through the molding compound 140, forming a vertical interconnect structure 150. A source lead layer 161 covers the source metal layer 131 and the source conductive pillar 151, and a gate lead layer 162 covers the gate metal layer 132 and the gate conductive pillar 152, forming a second interconnect layer 160. The power electrode pads 170 are distributed on the back of the power device chip 110. The source pad 172 covers the end of the source conductive pillar 151 away from the source pin layer 161 and is vertically interconnected with the source pin layer 161 on the front side through the source conductive pillar 151. The gate pad 173 covers the gate conductive pillar 152 and is vertically interconnected with the gate pin layer 162 on the front side through the gate conductive pillar 152.

[0094] Compared to existing technologies, the wafer-level packaging structure 100 with dual-layer vertical interconnect and its fabrication method provided in this embodiment of the invention adopts a core structure of dual-layer differentiated RDL+TMV vertical interconnect. The bottom first wiring layer 130 realizes differentiated wiring for electrodes with large and small currents. The source metal layer 131 and the gate metal layer 132 are fabricated separately and spaced apart from each other, which can effectively reduce parasitic parameters and meet the requirements of low conduction loss for large currents and low parasitic inductance for small currents. The upper second wiring layer 160, together with TMV copper pillars, realizes vertical interconnect and pin alignment, replacing the traditional wire bonding and metal strip bonding structure, significantly reducing packaging parasitic parameters, significantly reducing high-frequency switching losses, and greatly improving the electrical performance of the device. Moreover, the source pin layer 161 and the gate pin layer 162 can respectively cover the source metal layer 131 and the gate metal layer 132, greatly expanding the range and thickness of the metal layers, and greatly improving the heat conduction and heat dissipation capabilities of the front side of the power device chip 110. Furthermore, the vertical interconnect structure 150 enables front and back metal interconnection, resulting in a smaller size compared to traditional packaging structures. This facilitates the miniaturization of packaged products, shortens the transmission path, and significantly improves the overall performance of power devices.

[0095] Furthermore, the embodiments of the present invention employ a D2W chip-to-wafer mounting process, which can pre-screen qualified chips, avoid the yield shortcomings of whole-wafer bonding, and significantly improve the packaging yield. At the same time, the equipment has strong adaptability, low mass production cost, and is compatible with various power device chips 110, making the packaging extremely versatile.

[0096] Furthermore, this embodiment of the invention employs a pre-formed TMV vertical copper pillar structure, which offers high conductivity consistency and structural stability, avoiding the negative impact of laser drilling on the power device chip 110 in traditional processes. Combined with dual-layer RDL vertical interconnects, the wiring hierarchy is clear and the conduction path is short, further reducing conduction resistance and thermal resistance.

[0097] Meanwhile, the power device chip 110 has a large area of ​​power electrode pads 170 directly formed on the back, without intermediate redundant structures such as lead frames and solder paste layers. The heat dissipation path is greatly shortened and the heat dissipation efficiency is significantly improved, which can support the long-term stable operation of the power device under high current and high load.

[0098] Finally, the embodiments of the present invention adopt a wafer-level whole-wafer molding process, which results in a smaller package size and higher integration, realizing miniaturized device packaging, while simplifying the packaging process, reducing process redundancy, and effectively reducing the cost of mass production.

[0099] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A wafer-level packaging structure with dual-layer wiring vertical interconnect, characterized in that, include: At least one power device chip; A dielectric layer is disposed on the front side of the power device chip and has source windows and gate windows spaced apart. The first redistribution layer includes a source metal layer and a gate metal layer, which are respectively disposed in the source window and the gate window and separated by the dielectric layer. A molding compound surrounds the power device chip, wherein the source metal layer and the gate metal layer are exposed outside the molding compound. A vertical interconnect structure includes a source conductive pillar and a gate conductive pillar, both of which are disposed through the molding compound and exposed outside the molding compound. The second wiring layer includes a source pin layer and a gate pin layer, wherein the source pin layer covers the source metal layer and the source conductive pillar, and the gate pin layer covers the gate metal layer and the gate conductive pillar; The power electrode pads include a drain pad, a source pad, and a gate pad that are spaced apart from each other. The drain pad is disposed on the back side of the power device chip. The source pad covers the end of the source conductive post away from the source pin layer. The gate pad covers the gate conductive post.

2. The wafer-level packaging structure with dual-layer wiring vertical interconnection according to claim 1, characterized in that, The area of ​​the source metal layer is larger than the area of ​​the gate metal layer.

3. The wafer-level packaging structure with dual-layer wiring vertical interconnection according to claim 2, characterized in that, The area of ​​the source metal layer is greater than or equal to 50% of the front area of ​​the power device chip.

4. The wafer-level packaging structure with dual-layer wiring vertical interconnection according to claim 2, characterized in that, The width of the gate metal layer is between 5 and 20 μm.

5. The wafer-level packaging structure with dual-layer wiring vertical interconnection according to claim 1, characterized in that, An insulating layer is also provided on the side surface of the molding compound near the front of the power device chip. A source slot and a gate slot are formed on the insulating layer. The source slot exposes the source metal layer and the source conductive pillar. The gate slot exposes the gate metal layer and the gate conductive pillar. The source pin layer and the gate pin layer are respectively disposed in the source slot and the gate slot.

6. The wafer-level packaging structure with dual-layer wiring vertical interconnection according to claim 1, characterized in that, The second redistribution layer has a protective adhesive layer on the side of its surface away from the power device chip, and the protective adhesive layer covers the source pin layer and the gate pin layer.

7. The wafer-level packaging structure with dual-layer wiring vertical interconnection according to claim 6, characterized in that, A protective silicon wafer is also attached to the side of the protective adhesive layer away from the power device chip.

8. The wafer-level packaging structure with dual-layer wiring vertical interconnect according to claim 1 or 6, characterized in that, A bonding via is formed on the source metal layer and the source pin layer, and the bonding via penetrates the source metal layer and the source pin layer.

9. The wafer-level packaging structure with dual-layer wiring vertical interconnect according to claim 1, characterized in that, The side of the source pad away from the source conductive pillar, the side of the drain pad away from the power device chip, and the side of the gate pad away from the gate conductive pillar are all covered with a tin plating layer.

10. A method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnect, used to fabricate the wafer-level packaging structure with dual-layer wiring vertical interconnect as described in claim 1, characterized in that, The preparation method includes: A wafer is provided, wherein the wafer includes a plurality of power device chips; A dielectric layer and a first redistribution layer are formed on the front side of the wafer, wherein the dielectric layer covers the front side of the power device chip and has spaced-apart source windows and gate windows. The first redistribution layer includes a source metal layer and a gate metal layer, which are respectively disposed in the source window and the gate window and separated by the dielectric layer. The wafer is diced to form a single power device chip; The back side of the power device chip is attached to the first carrier; A molding compound is formed on the first carrier, wherein the molding compound covers the power device chip and the source metal layer and the gate metal layer are exposed outside the molding compound; A vertical interconnect structure is formed in the molding compound, wherein the vertical interconnect structure includes a source conductive pillar and a gate conductive pillar, both of which are disposed through the molding compound and exposed outside the molding compound; A second wiring layer is formed on the first wiring layer, wherein the second wiring layer includes a source pin layer and a gate pin layer, the source pin layer covers the source metal layer and the source conductive pillar, and the gate pin layer covers the gate metal layer and the gate conductive pillar; The first carrier is stripped off, and power electrode pads are formed on the back side of the power device chip. The power electrode pads include drain pads, source pads and gate pads that are spaced apart from each other. The drain pads are disposed on the back side of the power device chip. The source pads cover the end of the source conductive pillar away from the source pin layer. The gate pads cover the gate conductive pillar.

11. The method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnect according to claim 10, characterized in that, The steps of forming a dielectric layer and a first redistribution layer on the front side of the wafer include: A dielectric layer is formed on the front side of the wafer; The dielectric layer is patterned to form spaced-apart source windows and gate windows on the dielectric layer; A source metal layer and a gate metal layer are formed in the source window and the gate window, respectively.

12. The method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnect according to claim 10, characterized in that, The step of forming a second overlay layer on the first overlay layer includes: An insulating layer is formed on the molding layer; The insulating layer is patterned to form source slots and gate slots on the insulating layer, wherein the source slots expose the source metal layer and the source conductive pillars, and the gate slots expose the gate metal layer and the gate conductive pillars. A source pin layer and a gate pin layer are formed in the source slot and the gate slot, respectively.

13. The method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnect according to claim 10, characterized in that, After the step of forming the second overlay layer on the first overlay layer, the method further includes: A protective adhesive layer is formed on the second rewiring layer; A protective silicon wafer is attached to the protective adhesive layer.

14. The method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnect according to claim 13, characterized in that, The step of stripping the first carrier and forming power electrode pads on the back side of the power device chip includes: The first carrier is thermally peeled off to expose the back side of the power device chip; The protective silicon wafer is attached to the second carrier; A metal seed layer is sputtered onto the back side of the power device chip and then electroplated to thicken it to form power electrode pads.

15. A method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnect, used to fabricate the wafer-level packaging structure with dual-layer wiring vertical interconnect as described in claim 1, characterized in that, The preparation method includes: A wafer is provided, wherein the wafer includes a plurality of power device chips; A dielectric layer and a first redistribution layer are formed on the front side of the wafer, wherein the dielectric layer covers the front side of the power device chip and has spaced-apart source windows and gate windows. The first redistribution layer includes a source metal layer and a gate metal layer, which are respectively disposed in the source window and the gate window and separated by the dielectric layer. The wafer is diced to form a single power device chip; A vertical interconnect structure is formed on a first carrier, wherein the vertical interconnect structure includes spaced source conductive pillars and gate conductive pillars; The back side of the power device chip is attached to the first carrier; A molding compound is formed on the first carrier, wherein the molding compound covers the power device chip, the source metal layer and the gate metal layer are exposed in the molding compound, and the source conductive pillar and the gate conductive pillar are both disposed through the molding compound and exposed in the molding compound. A second wiring layer is formed on the first wiring layer, wherein the second wiring layer includes a source pin layer and a gate pin layer, the source pin layer covers the source metal layer and the source conductive pillar, and the gate pin layer covers the gate metal layer and the gate conductive pillar; The first carrier is stripped off, and power electrode pads are formed on the back side of the power device chip. The power electrode pads include drain pads, source pads and gate pads that are spaced apart from each other. The drain pads are disposed on the back side of the power device chip. The source pads cover the end of the source conductive pillar away from the source pin layer. The gate pads cover the gate conductive pillar.

16. The method for fabricating a wafer-level packaging structure with dual-layer wiring vertical interconnect according to claim 15, characterized in that, The steps of forming a vertical interconnection structure on the first vehicle include: A photoresist layer is formed on the surface of the first carrier; The photoresist layer is patterned to form source trenches and gate trenches by spaced grooves on the photoresist layer. Source conductive pillars and gate conductive pillars are respectively electroplated in the source groove and the gate groove; Remove the photoresist layer.

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