Semiconductor packaging structure and its fabrication method

Abstract

This invention provides a semiconductor packaging structure and its fabrication method, comprising forming glass vias and glass trenches on an ultrathin glass substrate using a laser-induced deep etching process. The size of the glass trenches is larger than the planar size of the chip. The chip is housed within the glass trenches, and ABF material is used to fill the gaps. Chamfering and beveling are used to improve stress distribution at the edges and corners of the glass trenches, preventing cracking and warping of the hard glass. Subsequently, conductive metal is formed within the glass vias, and copper is filled using an electroplating process to form conductive vias. Electrical connections are formed with copper pillars through redistribution circuit layers and inner circuit layers, forming a high-density vertical interconnect structure. Finally, external connections are achieved through solder balls. This invention solves problems such as thermal expansion mismatch, warping, insufficient surface flatness, and limited vertical interconnect density in traditional packaging, improving packaging reliability and signal transmission performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and its fabrication method. Background Technology

[0002] As semiconductor packaging technology evolves towards high-density, high-performance, and multi-chip heterogeneous integration, Integrated Fan-Out Packaging (InFO-PoP) has become an important packaging method for achieving vertical integration of system-on-a-chip (SoC), memory chips, and other functional components. Traditional InFO-PoP processes typically place core components such as SoCs on a temporary substrate and encapsulate them using epoxy molding compound (EMC). Subsequently, a redistribution layer (RDL) is fabricated on the surface of the encapsulation to achieve fan-out chip I / O and high-density interconnection.

[0003] However, with the continuous increase in the number of chip I / Os, the shrinking interconnect pitch, and the trend towards thinner and lighter packages, the limitations of traditional EMC molding structures in terms of thermomechanical reliability, process precision, and manufacturing efficiency are becoming increasingly prominent. Specifically, the coefficient of thermal expansion of EMC materials differs significantly from that of silicon chips, easily generating large interfacial stresses during temperature cycling, thermosetting, and reflow soldering processes. This can lead to package warpage, interface delamination, and even cracking failure. Furthermore, EMC molding and subsequent polishing processes struggle to achieve good thickness uniformity and surface flatness in large-size board-level packages, thus affecting the fabrication precision of subsequent fine circuitry and high-frequency signal transmission performance. In addition, when forming conductive vias in EMC, the via diameter is difficult to further reduce due to limitations imposed by filler particle size, laser ablation heat-affected zone, and material processing characteristics, thus restricting vertical interconnect density. Moreover, EMC also suffers from insufficient mechanical support and thermal shock resistance in thinner and lighter package structures. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor packaging structure and its preparation method, which solves the problems in the prior art where the EMC molding structure and the chip thermal expansion coefficient mismatch leads to package warping, interface delamination or crack failure, and the EMC molding surface flatness is insufficient, the conductive via diameter is difficult to reduce, the vertical interconnect density is limited, and the reliability of thin and light packaging is insufficient.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor packaging structure, the method comprising:

[0006] S1, a glass substrate is provided, the glass substrate having a first side and a second side opposite to each other, and the thickness of the glass substrate is greater than the thickness of the chip to be embedded.

[0007] S2, using laser-induced deep etching process to form glass through-holes and glass through-grooves that penetrate the glass substrate;

[0008] S3, a fixture is provided, the fixture having a clearance groove and a plurality of vacuum adsorption holes penetrating along the thickness direction, the planar dimension of the clearance groove being larger than the planar dimension of the glass through groove, the glass substrate being fixed to the side of the fixture where the clearance groove is formed through the vacuum adsorption holes, so that the clearance groove corresponds to the position of the glass through groove, and on a projection plane parallel to the surface of the glass substrate, the clearance groove surrounds the outer periphery of the glass through groove, and there is a single-sided compensation gap between the sidewall of the clearance groove and the sidewall of the glass through groove;

[0009] S4, a grinding rod is provided, the outer peripheral surface of which has a trapezoidal groove grinding profile extending circumferentially. The trapezoidal groove grinding profile includes a groove bottom surface and groove side surfaces connected to both sides of the groove bottom surface. The grinding rod is used to perform moving grinding on the inner wall of the glass channel. The inner wall edge of the glass channel is chamfered by the groove side surfaces to form a chamfered structure. The grinding rod is controlled to move along a preset arc travel trajectory at the corner of the glass channel to perform arc chamfering on the corner of the glass channel to form a chamfered structure.

[0010] S5, fill the glass through hole with conductive metal to form a conductive through hole that penetrates the glass substrate;

[0011] S6, a temporary adhesive film is attached to the second side of the glass substrate, and the chip with copper pillars is placed in the glass channel with the copper pillars facing the temporary adhesive film, and the chip is temporarily fixed in the glass channel by the temporary adhesive film, wherein the copper pillars are embedded in the chip, and adjacent copper pillars are isolated by an insulating medium.

[0012] S7, using a vacuum pressing process, press ABF onto the side of the obtained structure away from the temporary adhesive film, so that the ABF fills the space between the chip and the inner wall of the glass channel and covers the glass substrate and the chip;

[0013] S8, the ABF is cured and the cured ABF is planarized to expose the end face of the conductive via away from the temporary adhesive film;

[0014] S9, Remove the temporary adhesive film;

[0015] S10, an inner circuit layer is formed on the exposed surface of the copper pillar and on the end face of the conductive via located on the second surface;

[0016] S11, a redistributed circuit layer is formed on the second surface of the glass substrate on which the inner circuit layer is formed, and the redistributed circuit layer is electrically connected to the copper pillar and the conductive via through the inner circuit layer;

[0017] S12, a solder resist layer is formed on the surface of the redistribution circuit layer away from the glass substrate and a window is opened, and a solder ball is formed at the window to contact and connect with the redistribution circuit layer;

[0018] S13, provide an upper package and align and bond the upper package to the first surface of the glass substrate so that the upper package is vertically electrically interconnected with the redistribution circuit layer through the conductive via.

[0019] Optionally, the thickness of the glass substrate is 200μm to 500μm; the diameter of the glass through-hole is 20μm to 40μm.

[0020] Optionally, when forming the glass channel using laser-induced deep etching in step S2, the sidewall taper of the glass channel is controlled between 0° and 5° by adjusting at least one of the parameters of the incident light spot spacing, energy, and pulse width induced by the laser.

[0021] Optionally, the single-sided compensation distance between the sidewall of the clearance groove and the sidewall of the glass passage is 0.2mm~0.3mm.

[0022] Optionally, in step S4, the inner wall edge of the glass channel is chamfered by the side of the channel, and a chamfered surface is formed at the opening edge of the first and second surfaces of the glass channel near the glass substrate. The angle between the chamfered surface and its adjacent first or second surface is 30° to 60°.

[0023] Optionally, in step S4, the chamfer radius of the chamfer structure formed by rounding the corner of the glass channel is 0.5mm to 10mm.

[0024] Optionally, in step S4, the method of moving the grinding rod to grind the inner wall of the glass channel includes controlling the grinding rod to rotate at a speed of 1000 rpm to 3000 rpm and controlling the grinding rod to move along the inner wall of the glass channel at a feed speed of 100 mm / min to 300 mm / min.

[0025] Optionally, in step S4, during the grinding process of the grinding rod moving to grind the inner wall of the glass channel, high-pressure coolant is sprayed onto the grinding area to remove the heat generated during the grinding process.

[0026] The present invention also provides a semiconductor packaging structure, the semiconductor packaging structure comprising:

[0027] A glass substrate and a chip with copper pillars, wherein the glass substrate has opposing first and second surfaces, and the thickness of the glass substrate is greater than the thickness of the chip; the copper pillars are embedded in the chip, and adjacent copper pillars are isolated by an insulating medium.

[0028] The conductive via penetrating the glass substrate includes a glass via penetrating the glass substrate and a conductive metal filling the glass via;

[0029] A glass channel penetrating the glass substrate, wherein the chip is housed in the glass channel with the end face of the copper pillar flush with the second surface, the glass channel having a chamfered structure at the inner wall edge of the glass channel and a chamfered structure at the corner of the glass channel;

[0030] ABF is filled between the sidewall of the chip and the inner wall of the glass channel;

[0031] An inner circuit layer is disposed on the second side of the glass substrate, and the inner circuit layer is electrically connected to the end face of the copper pillar and the conductive via located on the second side.

[0032] A redistribution circuit layer is disposed on the side of the inner circuit layer away from the glass substrate, and the redistribution circuit layer is electrically connected to the copper pillar and the conductive via through the inner circuit layer;

[0033] A solder resist layer is disposed on the surface of the redistribution circuit layer away from the glass substrate, and the solder resist layer has openings;

[0034] Solder balls are disposed at the opening and are in contact with the redistribution circuit layer; and...

[0035] An upper package is disposed on the first side of the glass substrate, and the upper package is vertically electrically interconnected with the redistribution circuit layer through the conductive via.

[0036] Optionally, the thickness of the glass substrate is 200μm to 500μm; the diameter of the glass through-hole is 20μm to 40μm.

[0037] Optionally, the taper of the sidewall of the glass channel is 0° to 5°.

[0038] Optionally, the chamfered structure includes a chamfered surface located at the opening edge of the first and second surfaces of the glass channel near the glass substrate, and the included angle between the chamfered surface and its adjacent first or second surface is 30° to 60°.

[0039] Optionally, the chamfer radius of the chamfer structure is 0.5mm to 10mm.

[0040] As described above, the semiconductor packaging structure and its fabrication method of the present invention have the following beneficial effects:

[0041] By using a glass substrate instead of the traditional EMC molding compound as the packaging carrier structure, and forming a through glass channel in the glass substrate to embed the chip with copper pillars, while reserving a filling gap between the glass channel and the chip and using ABF for vacuum pressing and curing, the problems of material thermal expansion mismatch, poor thickness uniformity and insufficient surface flatness caused by traditional large-area EMC molding can be reduced, thereby improving the chip embedding accuracy and packaging structure stability.

[0042] By chamfering the inner edge of the glass channel and rounding the corners, the stress concentration at the edge and corner of the glass channel can be mitigated. This allows the stress generated by ABF during curing shrinkage and subsequent thermal cycling to be more evenly distributed between the chip, glass substrate and filler material, thereby reducing the risk of interface delamination, cracks and glass edge chipping, and effectively suppressing package warping.

[0043] By forming glass vias in a glass substrate and filling them with conductive metal to form conductive vias that penetrate the glass substrate, and combining them with an inner circuit layer, a redistribution circuit layer, a solder mask layer and solder balls disposed on the second side, and an upper package disposed on the first side and aligned and bonded to the conductive vias, high-density vertical electrical interconnects between the chip, the redistribution circuit layer and the upper package can be achieved, shortening the signal transmission path and improving interconnect density and electrical performance.

[0044] By adopting the InFO-PoP packaging structure with vertical stacking, the chip is embedded in the glass substrate and the upper package is stacked on one side of the glass substrate. This can reduce the package thickness while maintaining high-density interconnection, so that the overall package height can be reduced to about 0.8 mm, thereby reducing the package volume and meeting the requirements of thinner and smaller packaging.

[0045] Meanwhile, the SoC and the top package are vertically connected via TGV. Compared with the interconnection method that relies on peripheral solder joints, transition lines or long fan-out lines in the FC-PoP structure, it can reduce intermediate transition links, reduce parasitic inductance and parasitic capacitance in the interconnect structure, reduce signal delay and improve power integrity. Therefore, it is more suitable for high-speed, high-bandwidth and high-integration packaging applications.

[0046] In addition, the coefficient of thermal expansion of the glass substrate is adjustable, and it can be matched with the material properties of the chip, upper package and circuit structure. This makes the warping and expansion deformation of the overall package structure during thermal cycling, reflow soldering and operating temperature changes more controllable, thereby further improving the thermomechanical reliability and dimensional stability of the package structure.

[0047] Meanwhile, glass substrates possess excellent surface flatness, dimensional stability, low water absorption, and suitability for microfabrication, which facilitates the subsequent formation of fine circuitry and small-diameter conductive vias. Therefore, this invention addresses the problems of existing InFO-PoP packaging, where EMC molding structures are prone to warping, delamination, or cracking due to thermal expansion coefficient mismatch, as well as insufficient surface flatness, difficulty in reducing conductive via diameter, limited vertical interconnect density, and insufficient reliability in thinner packaging. It achieves a semiconductor packaging structure with low warpage, high interconnect density, high circuit fabrication precision, miniaturization, and high reliability. Attached Figure Description

[0048] Figure 1 The diagram shows a flow chart of the method for fabricating the semiconductor packaging structure of the present invention.

[0049] Figures 2 to 11 The diagram shows a cross-sectional structure of each step in the fabrication method of the semiconductor packaging structure of the present invention.

[0050] Figure 12 The diagram shown is a top view of the glass channel with chamfered and beveled structures according to the present invention.

[0051] Figure 13 The diagram shows the simulated stress and warping distribution of the glass channel.

[0052] Component labeling explanation: 1 Glass substrate, 11 First side, 12 Second side, 13 Conductive via, 131 Glass via, 132 Conductive metal, 14 Glass channel, 141 Chamfered structure, 142 Chamfered structure, 143 Chamfered surface, 15 Fixture, 151 Vacuum adsorption hole, 152 Clearance groove, 16 Grinding rod, 161 Trapezoidal groove grinding profile, 162 Groove bottom, 163 Groove side, 2 Chip, 21 Copper pillar, 22 Fill gap, 3 ABF, 4 Inner circuit layer, 5 Redistribution circuit layer, 51 Dielectric layer, 52 Metal circuit layer, 6 Solder mask, 7 Solder ball, 8 Upper package, 9 Conductive bump, Steps S1~S13. Detailed Implementation

[0053] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] Please see Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0055] This embodiment provides a method for fabricating a semiconductor packaging structure, such as... Figure 1 As shown, the preparation method includes:

[0056] S1, a glass substrate is provided, the glass substrate having a first side and a second side opposite to each other, and the thickness of the glass substrate is greater than the thickness of the chip to be embedded.

[0057] S2, using laser-induced deep etching process to form glass through-holes and glass through-grooves that penetrate the glass substrate;

[0058] S3, a fixture is provided, the fixture having a clearance groove and a plurality of vacuum adsorption holes penetrating along the thickness direction, the planar dimension of the clearance groove being larger than the planar dimension of the glass through groove, the glass substrate being fixed to the side of the fixture where the clearance groove is formed through the vacuum adsorption holes, so that the clearance groove corresponds to the position of the glass through groove, and on a projection plane parallel to the surface of the glass substrate, the clearance groove surrounds the outer periphery of the glass through groove, and there is a single-sided compensation gap between the sidewall of the clearance groove and the sidewall of the glass through groove;

[0059] S4, a grinding rod is provided, the outer peripheral surface of which has a trapezoidal groove grinding profile extending circumferentially. The trapezoidal groove grinding profile includes a groove bottom surface and groove side surfaces connected to both sides of the groove bottom surface. The grinding rod is used to perform moving grinding on the inner wall of the glass channel. The inner wall edge of the glass channel is chamfered by the groove side surfaces to form a chamfered structure. The grinding rod is controlled to move along a preset arc travel trajectory at the corner of the glass channel to perform arc chamfering on the corner of the glass channel to form a chamfered structure.

[0060] S5, fill the glass through hole with conductive metal to form a conductive through hole that penetrates the glass substrate;

[0061] S6, a temporary adhesive film is attached to the second side of the glass substrate, and the chip with copper pillars is placed in the glass channel with the copper pillars facing the temporary adhesive film, and the chip is temporarily fixed in the glass channel by the temporary adhesive film, wherein the copper pillars are embedded in the chip, and adjacent copper pillars are isolated by an insulating medium.

[0062] S7, using a vacuum pressing process, press ABF onto the side of the obtained structure away from the temporary adhesive film, so that the ABF fills the space between the chip and the inner wall of the glass channel and covers the glass substrate and the chip;

[0063] S8, the ABF is cured and the cured ABF is planarized to expose the end face of the conductive via away from the temporary adhesive film;

[0064] S9, Remove the temporary adhesive film;

[0065] S10, an inner circuit layer is formed on the exposed surface of the copper pillar and on the end face of the conductive via located on the second surface;

[0066] S11, a redistributed circuit layer is formed on the second surface of the glass substrate on which the inner circuit layer is formed, and the redistributed circuit layer is electrically connected to the copper pillar and the conductive via through the inner circuit layer;

[0067] S12, a solder resist layer is formed on the surface of the redistribution circuit layer away from the glass substrate and a window is opened, and a solder ball is formed at the window to contact and connect with the redistribution circuit layer;

[0068] S13, provide an upper package and align and bond the upper package to the first surface of the glass substrate so that the upper package is vertically electrically interconnected with the redistribution circuit layer through the conductive via.

[0069] The semiconductor packaging structure fabrication method of this embodiment uses a glass substrate instead of the traditional EMC molding compound as the packaging carrier structure. A through-hole glass channel is formed in the glass substrate to embed a chip with copper pillars. A filling gap is reserved between the glass channel and the chip, and vacuum bonding and curing are performed using ABF (Alternating Aperture Forming). This reduces the problems of material thermal expansion mismatch, poor thickness uniformity, and insufficient surface flatness caused by traditional large-area EMC molding, improving chip embedding accuracy and packaging structure stability. By chamfering the inner edge of the glass channel and rounding the corners, stress concentration at the edges and corners of the glass channel is mitigated. This allows the stress generated during ABF curing shrinkage and subsequent thermal cycling to be more evenly distributed among the chip, glass substrate, and filling material, thereby reducing the risk of interface delamination, cracking, and glass edge chipping, and effectively suppressing package warpage. By forming glass vias in the glass substrate and filling them with conductive gold... This invention forms conductive vias penetrating a glass substrate. Combined with an inner circuit layer, a redistribution circuit layer, a solder mask layer, and solder balls disposed on the second side, and an upper package disposed on the first side and aligned and bonded to the conductive vias, it enables high-density vertical electrical interconnection between the chip, the redistribution circuit layer, and the upper package. This shortens the signal transmission path and improves interconnection density and electrical performance. Simultaneously, the glass substrate possesses good surface flatness, dimensional stability, low water absorption, and suitability for microfabrication, which is beneficial for the subsequent formation of fine circuits and small-diameter conductive vias. Therefore, this embodiment can solve the problems of warping, delamination, or cracking failure of existing InFO-PoP packaging EMC molding structures due to thermal expansion coefficient mismatch, as well as insufficient surface flatness, difficulty in reducing the diameter of conductive vias, limited vertical interconnection density, and insufficient reliability of thinner packaging. It achieves a semiconductor packaging structure with low warpage, high interconnection density, high circuit fabrication precision, and high reliability.

[0070] The method for fabricating the semiconductor packaging structure of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0071] like Figure 2 As shown, step S1 is performed first, in which a glass substrate 1 is provided, the glass substrate 1 having a first surface 11 and a second surface 12 facing each other.

[0072] like Figure 3 As shown, step S2 is then performed, in which a glass through-hole 131 and a glass through-groove 14 penetrating the glass substrate 1 are formed using a laser-induced deep etching process.

[0073] Specifically, the planar dimensions of the glass channel 14 are larger than the planar dimensions of the chip 2 to be embedded, so that after the chip 2 is embedded in the glass channel 14, a filling gap 22 is formed between the sidewall of the chip 2 and the inner wall of the glass channel 14 (see reference). Figure 6).

[0074] Specifically, the thickness of the glass substrate 1 is greater than the thickness of the chip 2. As an example, the glass substrate 1 is ultra-thin glass, and its thickness can be selected according to the thickness of the chip 2 and the overall packaging thickness requirements, preferably 200μm to 500μm. By making the thickness of the glass substrate 1 greater than the thickness of the chip 2 to be embedded, it is possible to ensure that the chip 2 is completely housed within the glass substrate 1 after being embedded in the glass channel 14. This facilitates subsequent filling and curing of insulating material between the chip 2 and the glass channel 14, and also helps to reduce the overall packaging thickness, achieving a thinner and lighter package. The use of ultra-thin glass material in the glass substrate 1 also utilizes the excellent surface flatness, dimensional stability, low dielectric loss, and low water absorption characteristics of glass material to improve the accuracy of subsequent fine circuit fabrication and packaging reliability.

[0075] Furthermore, the aperture of the glass via 131 is preferably 20μm to 40μm. Since glass material is suitable for micro-hole fabrication using laser-induced deep etching, it is possible to form the glass via 131 with a small aperture, controllable morphology, and penetrating the glass substrate 1. Compared to conductive vias formed in conventional EMC materials, the aperture of the glass via 131 can be further reduced, and high-density conductive vias can be formed after subsequent filling with conductive metal, thereby increasing the vertical interconnect density of the package structure, shortening the electrical connection path, and improving high-frequency signal transmission performance.

[0076] As a preferred example, when forming the glass channel 14 using a laser-induced deep etching process, the sidewall taper of the glass channel 14 is controlled within 0° to 5° by adjusting at least one parameter among the laser-induced incident spot spacing, energy, and pulse width. The sidewall taper refers to the degree of inclination of the sidewall of the glass channel 14 relative to the vertical direction; the smaller the sidewall taper, the closer the inner wall of the glass channel 14 is to a vertical state. By controlling the sidewall taper of the glass channel 14 within the range of 0° to 5°, the dimensional accuracy of the glass channel 14 and the stability of the chip 2 embedding position can be improved. This results in a more uniform filling gap 22 between the chip 2 to be embedded and the glass channel 14, which is beneficial for the subsequent full filling and uniform curing of the ABF 3 within the filling gap 22. This improves the interface bonding quality between the sidewall of the chip 2, the ABF 3, and the glass substrate 1, reduces the risk of delamination, cracking, and warping caused by uneven filling or local stress concentration, and further enhances the reliability of the semiconductor packaging structure.

[0077] like Figure 4As shown, step S3 is then performed, providing a fixture 15. The fixture 15 has a clearance groove 152 and a plurality of vacuum adsorption holes 151 extending along the thickness direction. The planar dimension of the clearance groove 152 is larger than the planar dimension of the glass channel 14. The glass substrate 1 is fixed to the side of the fixture 15 where the clearance groove 152 is formed through the vacuum adsorption holes 151, so that the clearance groove 152 corresponds to the position of the glass channel 14. On the projection plane parallel to the surface of the glass substrate 1, the clearance groove 152 surrounds the outer periphery of the glass channel 14, and there is a single-sided compensation distance d between the side wall of the clearance groove 152 and the side wall of the glass channel 14.

[0078] As an example, the fixture 15 is preferably an aerospace aluminum fixture, which has high rigidity, good dimensional stability and light weight, and can provide stable support for the glass substrate 1 when the glass channel 14 is subsequently ground.

[0079] Specifically, in step S3, during the process of fixing the glass substrate 1 to the side of the fixture 15 where the clearance groove 152 is formed through the vacuum adsorption hole 151, the glass substrate 1 and the fixture 15 can first be aligned by using the CCD identification positioning hole, so that the glass substrate 1 is placed in the designated position of the fixture 15 and the glass through groove 14 is located above the clearance groove 152. Then, a negative pressure adsorption force is applied to the glass substrate 1 through the vacuum adsorption hole 151, so that the glass substrate 1 is reliably fixed on the fixture 15. Since the fixture 15 is provided with multiple vacuum adsorption holes 151, a strong and uniform vacuum adsorption effect can be formed between the glass substrate 1 and the fixture 15, preventing the glass substrate 1 from shifting or lifting relative to the fixture 15 during subsequent grinding processes.

[0080] Specifically, when the single-sided compensation distance d is too small, the clearance groove 152 may not be able to adequately avoid the grinding area of ​​the glass channel 14, affecting the entry of the grinding rod 16 into the glass channel 14 and the stable processing of the glass channel 14; when the single-sided compensation distance d is too large, the suspended area of ​​the glass substrate 1 around the glass channel 14 increases, and vibration is easily generated during the grinding process due to insufficient support, which in turn leads to chipping or cracks at the edge of the glass channel 14. As a preferred example, the single-sided compensation distance d between the sidewall of the clearance groove 152 and the sidewall of the glass channel 14 is 0.2mm~0.3mm.

[0081] like Figure 4As shown, step S4 is then performed, providing a grinding rod 16. The outer circumferential surface of the grinding rod 16 has a trapezoidal groove grinding profile 161 extending circumferentially. The trapezoidal groove grinding profile 161 includes a groove bottom surface 162 and groove side surfaces 163 connecting the two sides of the groove bottom surface 162. The grinding rod 16 is used to perform moving grinding on the inner wall of the glass through groove 14. (Refer to...) Figure 5 Structural cross-section diagram and Figure 12 The top view of the glass channel 14 shows that the inner wall edge of the glass channel 14 is chamfered by the side 163 of the channel to form a chamfered structure 141, and the grinding rod 16 is controlled to move along a preset arc trajectory at the corner of the glass channel 14 to form a chamfered structure 142.

[0082] As an example, the grinding rod 16 includes, but is not limited to, diamond grinding rods.

[0083] Specifically, the grinding rod 16 rotates around its own axis during the processing. The rotation direction of the grinding rod 16 can be selected according to the spindle setting of the processing equipment, the feed direction of the grinding rod 16, and the processing path of the glass through groove 14. For example, it can be clockwise or counterclockwise. This embodiment does not make any special limitation on this, as long as the trapezoidal groove grinding profile 161 can stably grind the inner wall edge of the glass through groove 14.

[0084] As an example, the length of the groove bottom surface 162 can be designed according to the size of the glass through groove 14, the width of the chamfer structure 141 and the machining allowance of the grinding rod 16. In this embodiment, the length of the groove bottom surface 162 is 0.15mm.

[0085] As an example, the angle β between the groove side surface 163 and the horizontal plane is equal to or substantially equal to the angle α between the chamfered surface 143 and its adjacent first surface 11 or second surface 12. Thus, when the grinding rod 16 moves along the inner wall of the glass channel 14 for grinding, the opening edge of the glass channel 14 contacts the groove side surface 163, and the groove side surface 163 is ground to form the chamfered surface 143 corresponding to its contour, thereby matching the shape of the formed chamfered structure 141 with the trapezoidal groove grinding contour 161. The grinding rod 16 can be customized according to the size of the glass channel 14, the target angle of the chamfered structure 141, the width H of the chamfered surface 143, and the thickness of the glass substrate 1. Specifically, the trapezoidal groove grinding profile 161 on the outer peripheral surface of the grinding rod 16 can be customized according to actual processing requirements, so that the length of the groove bottom surface 162, the included angle β between the groove side surface 163 and the horizontal plane, and the extension length of the groove side surface 163 match the chamfering requirements of the glass through groove 14.

[0086] refer to Figure 12 As an example, in step S4, the inner wall edge of the glass channel 14 is chamfered by the side surface 163 of the channel, forming a chamfered surface 143 at the opening edge of the glass channel 14 near the first surface 11 and the second surface 12 of the glass substrate 1. The angle α between the chamfered surface 143 and its adjacent first surface 11 or second surface 12 is 30° to 60°. The smaller the angle α between the chamfered surface 143 and its adjacent first surface 11 or second surface 12, the wider the chamfer width H formed by the chamfered structure 141 at the opening edge of the glass channel 14. This further increases the transition area at the opening edge of the glass channel 14, allowing the local stress generated during the chip 2 embedding and subsequent ABF filling and curing process to be gradually released along the chamfered surface 143, avoiding sharp stress concentration at the edge of the hard glass, thereby reducing the risk of glass chipping, interface delamination and cracking.

[0087] Further, as an example, in step S4, the chamfer radius of the chamfer structure 142 formed by rounding the corners of the glass channel 14 is 0.5mm to 10mm, preferably 2mm in this embodiment. By transforming the corners of the glass channel 14 from sharp corners to rounded transitions, the sharp-point effect at the corners can be eliminated or reduced, resulting in a more uniform stress distribution of the ABF 3 subsequently filled between the sidewall of the chip 2 and the inner wall of the glass channel 14 during curing shrinkage and thermal cycling. This improves the reliability of the interface bonding between the ABF 3 and the glass substrate 1 and the chip 2. Thus, the chamfer structure 141 and the chamfer structure 142 work together to effectively improve the stress concentration problem at the edges and corners of the glass channel 14, enhancing the warping resistance, crack resistance, and overall thermomechanical reliability of the embedded glass substrate packaging structure of the chip 2. This effectively prevents edge chipping or delamination of the glass substrate 1 due to excessive local stress.

[0088] As an example, in step S4, the method of using a grinding rod 16 to perform moving grinding on the inner wall of the glass channel 14 includes controlling the grinding rod 16 to rotate at a speed of 1000 rpm to 3000 rpm and controlling the grinding rod 16 to move along the inner wall of the glass channel 14 at a feed speed of 100 mm / min to 300 mm / min.

[0089] As an example, in step S4, during the grinding process of the grinding rod 16 moving and grinding the inner wall of the glass channel 14, high-pressure coolant is sprayed onto the grinding area to remove the heat generated during the grinding process, thereby reducing the risk of the glass substrate 1 burning, chipping, or microcracks on the inner wall of the glass channel 14 due to excessive local temperature rise.

[0090] like Figure 5 As shown, step S5 is then performed, in which conductive metal 132 is filled into the glass through hole 131 to form a conductive through hole 13 penetrating the glass substrate 1.

[0091] Specifically, a thin metal layer is first deposited as a conductive seed layer on the inner wall of the glass via 131 and the surface of the glass substrate 1 using physical vapor deposition (PVD) or chemical deposition processes. This conductive seed layer can be a titanium / copper composite metal layer or other metal layers suitable for subsequent electroplating. The titanium layer can improve the adhesion between the metal layer and the glass substrate 1, while the copper layer serves as the conductive base for subsequent copper electroplating. Next, a bottom-up copper electroplating process is used to fill the glass via 131 with conductive metal 132. During this electroplating process, the concentrations of inhibitors and accelerators in the electroplating solution can be adjusted to ensure that the deposition rate of copper at the bottom of the glass via 131 is higher than that at the opening. This allows the conductive metal 132 to grow gradually from the bottom to the opening and fill the glass via 131, achieving a high-quality metal filling without voids or gaps, forming the conductive via 13 that penetrates the glass substrate 1. After electroplating, the surface of the glass substrate 1 can be planarized using a chemical mechanical polishing (CMP) process to remove excess copper and metal residue on the surface of the glass substrate 1. This makes the end face of the conductive via 13 on the first surface 11 and / or the second surface 12 of the glass substrate 1 substantially flush with the corresponding surface of the glass substrate 1. This provides a flat and reliable process reference surface for subsequent processes on the surface of the glass substrate 1 and improves the electrical connection reliability between the conductive via 13 and the subsequent circuit structure.

[0092] like Figure 6 As shown, step S6 is then performed, where a temporary adhesive film 9 is attached to the second surface 12 of the glass substrate 1, and the chip 2 with copper pillars 21 is placed in the glass channel 14 with the copper pillars 21 facing the temporary adhesive film 9, and the chip 2 is temporarily fixed in the glass channel 14 by the temporary adhesive film 9, wherein the copper pillars 21 are embedded in the chip 2, and adjacent copper pillars 21 are isolated by an insulating medium.

[0093] Compared to the copper pillar structure protruding from the surface of the chip 2, the embedded copper pillars 21 exhibit better continuity of the insulating medium, improving the insulation reliability between adjacent copper pillars 21 and reducing the risk of short circuits or leakage between them. Furthermore, since the copper pillars 21 are embedded within the chip 2, the surface undulations of the chip 2 are smaller. Therefore, when using a vacuum lamination process to laminate the ABF 3, there is no need to form deep, narrow gaps between adjacent protruding copper pillars. This reduces the difficulty of flow filling of the ABF 3, minimizing voids, incomplete filling, and interface defects, and improving the process feasibility and packaging reliability of the ABF 3 lamination filling.

[0094] like Figure 7As shown, step S7 is then performed, in which ABF 3 is pressed onto the side of the obtained structure away from the temporary adhesive film 9 using a vacuum pressing process, so that the ABF 3 fills the space between the chip 2 and the inner wall of the glass channel 14 and covers the glass substrate 1 and the chip 2.

[0095] like Figure 7 As shown, step S8 is then performed to cure the ABF 3 and planarize the cured ABF 3 to expose the end face of the conductive via 13 away from the temporary adhesive film 9.

[0096] Specifically, the ABF 3 possesses excellent insulation, low water absorption, and good adhesion to glass and silicon wafers. It can form a reliable insulating filling and mechanical support structure between the chip 2 and the glass substrate 1, and improve the stability of the chip 2 within the glass channel 14. After filling, the ABF 3 undergoes thermosetting to form a stable hardened structure, thereby achieving complete encapsulation of the embedded chip 2 and forming an integrated package structure of the chip 2, the ABF 3, and the glass substrate 1. By using ABF 3 as a filling material, not only can the reliability of the interface bonding between the chip 2 and the glass substrate 1 be improved, reducing the risk of delamination, cracking, and warping due to material mismatch during subsequent thermal cycling, but it also provides a relatively flat dielectric plane after curing, providing a good process foundation for subsequent fine wiring, formation of inner circuit layers, and redistribution circuit layers on the second surface 12 of the glass substrate 1.

[0097] like Figure 7 As shown, step S9 is then performed to remove the temporary adhesive film 9.

[0098] Specifically, the temporary adhesive film 9 attached to the second surface 12 of the glass substrate 1 can be removed by means of heating, ultraviolet irradiation, laser irradiation, or mechanical peeling to expose the surface of the chip 2 near the second surface 12 and the copper pillars 21 disposed on the chip 2. After removing the temporary adhesive film 9, some adhesive residue, oxides, or organic contaminants may remain on the surface of the chip 2 and the copper pillars 21. For example, a plasma cleaning process can be further used to treat the exposed surface of the chip 2 and the copper pillars 21 to remove adhesive residue, oxide layer, and contaminants, and improve the cleanliness and activation level of the copper pillars 21 surface, thereby improving the bonding reliability and electrical connection stability between the subsequent metal circuits and the copper pillars 21.

[0099] like Figure 8As shown, step S10 is then performed to form an inner circuit layer 4 on the exposed surface of the copper pillar 21 and on the end face of the conductive via 13 located on the second surface 12.

[0100] As an example, the inner circuit layer 4 can be formed through processes such as whole-board metallization, copper electroplating, dry film lamination, exposure, development, and etching; or a semi-additive method or a modified semi-additive method can be used to form a fine circuit pattern. The inner circuit layer 4 is used to realize the initial electrical lead-out and circuit redistribution between the copper pillars 21 and the conductive vias 13 of the chip 2, so that the I / O terminals of the chip 2 can be connected to the subsequently formed redistributed circuit layer 5 and the conductive vias 13 through the inner circuit layer 4, thereby shortening the signal transmission path and improving the wiring integration and electrical connection reliability of the package structure.

[0101] like Figure 9 As shown, step S11 is then performed, in which a redistribution circuit layer 5 is formed on the second surface 12 of the glass substrate 1 on which the inner circuit layer 4 is formed. The redistribution circuit layer 5 is electrically connected to the copper pillar 21 and the conductive via 13 through the inner circuit layer 4.

[0102] Specifically, the redistributed circuit layer 5 includes at least one dielectric layer 51, a metal circuit layer 52, and vias located between adjacent metal circuit layers 52. As an example, the redistributed circuit layer 5 can be fabricated using a modified semi-additive process (mSAP), whereby a dielectric layer 51 is formed on the inner circuit layer 4, laser-drilled vias are applied to the dielectric layer 51 to expose the underlying pads or circuit areas, followed by seed layer deposition, pattern plating, film removal, and etching processes to form the required fine redistributed circuitry. Depending on the number of I / Os, circuit density, and packaging design requirements of the chip 2, the redistributed circuit layer 5 can be a single-layer structure or a multi-layer stacked structure. By setting the redistributed circuit layer 5, the high-density I / O terminals of the chip 2 can be redistributed to a larger-pitch soldering area, and electrically connected to the copper pillars 21 and the conductive vias 13 through the inner circuit layer 4, thereby improving the fan-out capability, wiring flexibility, and vertical interconnect performance of the packaging structure. The material of the dielectric layer 51 includes, but is not limited to, ABF or polyimide (PI).

[0103] like Figure 10 As shown, step S12 is then performed, where a solder resist layer 6 is formed on the surface of the redistribution circuit layer 5 away from the glass substrate 1 and a window is opened, and a solder ball 7 is formed at the window to contact and connect with the redistribution circuit layer 5.

[0104] Specifically, the solder mask layer 6 can be formed on the side of the redistribution layer 5 away from the glass substrate 1 through methods such as screen printing, coating, or dry film lamination. Then, the opening is formed at a predetermined position on the solder mask layer 6 through processes such as exposure and development to expose the solder pad areas in the redistribution layer 5. Afterwards, surface treatment and ball-forming processes can be performed at the opening to form solder balls 7 that contact and connect with the redistribution layer 5. The solder mask layer 6 provides insulation protection, prevents solder bridging, and improves surface reliability for the redistribution layer 5. The solder balls 7 form the ball grid array (BGA) interface of the package structure for electrical connection with the external motherboard (PCB). By forming the solder mask layer 6 and the solder balls 7, the external connection reliability of the package structure can be improved, and subsequent reflow soldering and board-level assembly can be facilitated.

[0105] like Figure 11 As shown, step S13 is then performed, providing an upper package 8 and aligning and bonding the upper package 8 with the first surface 11 of the glass substrate 1, so that the upper package 8 is vertically electrically interconnected with the redistribution circuit layer 5 through the conductive via 13.

[0106] Specifically, the upper package 8 can be a memory chip package, a functional chip package, or other pre-packaged device structures. The upper package 8 may have solder balls, metal bumps 81, or other connection terminals. The upper package 8 is aligned with the first surface 11 of the glass substrate 1, so that the connection terminals of the upper package 8 (such as...) Figure 10 The metal bumps 81 in the upper package correspond to the end face of the conductive via 13 on the first surface 11 side or the pad area connected to it. Mechanical and electrical connections are then achieved through reflow soldering, thermoforming, or other suitable bonding processes. Thus, the upper package 8 can achieve vertical electrical interconnection with the inner circuit layer 4 and the redistribution circuit layer 5 on the second surface 12 side through the conductive via 13 penetrating the glass substrate 1, thereby forming a stacked semiconductor package structure. This structure shortens the signal transmission path between the upper package 8 and the chip 2 and the redistribution circuit layer 5, improves vertical interconnect density and system integration, and facilitates the realization of high-performance, thinner InFO-PoP packaging.

[0107] The preparation method provided in this application does not impose any restrictions on the order of steps and can be reasonably adjusted as needed.

[0108] This embodiment also provides a semiconductor packaging structure, see reference. Figures 2 to 12 The semiconductor packaging structure includes:

[0109] A glass substrate 1 and a chip 2 having copper pillars 21, wherein the glass substrate 1 has opposing first surfaces 11 and second surfaces 12, and the thickness of the glass substrate 1 is greater than the thickness of the chip 2; the copper pillars 21 are embedded in the chip 2, and adjacent copper pillars 21 are isolated by an insulating medium.

[0110] The conductive via 13 penetrating the glass substrate 1 includes a glass via 131 penetrating the glass substrate 1 and a conductive metal 132 filling the glass via 131.

[0111] The chip 2 is housed in the glass through groove 14 that penetrates the glass substrate 1, with the end face of the copper pillar 21 flush with the second surface 12. The glass through groove 14 has a chamfered structure 141 at the inner wall edge of the glass through groove 14 and a chamfered structure 142 at the corner of the glass through groove 14.

[0112] ABF 3 is filled between the sidewall of the chip 2 and the inner wall of the glass channel 14;

[0113] The inner circuit layer 4 is disposed on the second surface 12 side of the glass substrate 1, and the inner circuit layer 4 is electrically connected to the exposed surface of the copper pillar 21 and the end face of the conductive via 13 located on the second surface 12.

[0114] A redistribution circuit layer 5 is disposed on the side of the inner circuit layer 4 away from the glass substrate 1. The redistribution circuit layer 5 is electrically connected to the copper pillar 21 and the conductive via 13 through the inner circuit layer 4.

[0115] A solder resist layer 6 is disposed on the surface of the redistribution circuit layer 5 away from the glass substrate 1, and the solder resist layer 6 has a window.

[0116] Solder ball 7 is disposed at the opening and is in contact with the redistribution circuit layer 5; and,

[0117] The upper package 8 is disposed on the first surface 11 side of the glass substrate 1, and the upper package 8 is vertically electrically interconnected with the redistribution line layer 5 through the conductive via 13.

[0118] The semiconductor packaging structure can be prepared using the semiconductor packaging structure preparation method described above, but it is not limited to this method. Other suitable preparation methods are also possible, and the beneficial effects they can achieve can be found in the specific description of the preparation method, which will not be repeated here.

[0119] As an example, the glass substrate 1 is made of ultra-thin glass, and its thickness can be selected according to the thickness of the chip 2 to be embedded and the overall packaging thickness requirements, preferably 200μm to 500μm. By making the thickness of the glass substrate 1 greater than the thickness of the chip 2 to be embedded, it can be ensured that the chip 2 is completely housed within the glass substrate 1 after being embedded in the glass channel 14. This facilitates the subsequent filling and curing of insulating material between the chip and the glass channel, and also helps to reduce the overall packaging thickness, achieving a thinner and lighter package. The use of ultra-thin glass material in the glass substrate 1 also utilizes the excellent surface flatness, dimensional stability, low dielectric loss, and low water absorption characteristics of glass material to improve the accuracy of subsequent fine circuit fabrication and packaging reliability.

[0120] Furthermore, the aperture of the glass via 131 is 20μm to 40μm. Since glass material is suitable for micro-hole fabrication using laser-induced deep etching, it is possible to form the glass via 131 with a small aperture, controllable morphology, and penetrating the glass substrate 1. Compared to conductive vias formed in conventional EMC materials, the aperture of the glass via 131 can be further reduced, and high-density conductive vias can be formed after subsequent filling with conductive metal. This increases the vertical interconnect density of the package structure, shortens the electrical connection path, and improves high-frequency signal transmission performance.

[0121] As an example, the sidewall taper of the glass channel 14 is 0° to 5°. The sidewall taper refers to the degree of inclination of the sidewall of the glass channel 14 relative to the vertical direction. The smaller the sidewall taper, the closer the inner wall of the glass channel 14 is to a vertical state. By controlling the sidewall taper of the glass channel 14 within the range of 0° to 5°, the dimensional accuracy of the glass channel 14 and the stability of the chip 2's embedding position can be improved.

[0122] As an example, the chamfered structure 141 includes a chamfered surface 143 located at the opening edge of the glass channel 14 near the first surface 11 and the second surface 12 of the glass substrate 1, and the included angle α between the chamfered surface 143 and its adjacent first surface 11 or second surface 12 is 30° to 60°.

[0123] As an example, the chamfer radius of the chamfer structure 142 is 0.5mm to 10mm. In this embodiment, it is preferably 2mm. By changing the corner of the glass channel 14 from a sharp corner structure to a rounded transition structure, the sharp point effect at the corner position can be eliminated or reduced.

[0124] This embodiment also includes simulations of the effects of the glass channel chamfering structure and filling material on encapsulation stress and warpage. For example... Figure 13 As shown, the stress distribution and warping under three different schemes were simulated, and the results are summarized in Table 1. Figure 13 As shown in Table 1, the chamfered structure + ABF filling scheme of this embodiment exhibits the lowest stress values ​​on both the glass substrate and the chip surface, while also minimizing chip warpage. This result demonstrates that by chamfering the inner wall of the glass via and using ABF filling, localized stress concentration at the glass substrate-chip interface can be significantly reduced, minimizing the risk of delamination, cracking, or warpage caused by excessive stress, thereby improving the overall reliability of the package.

[0125] Table 1: Summary of Simulation Stress and Warpage Parameters of Glass Grooves in Embodiments of the Present Invention and Prior Art

[0126]

[0127] In summary, the semiconductor packaging structure and its fabrication method of the present invention, by using a glass substrate instead of the traditional EMC molding compound as the packaging carrier structure, and forming a through-hole glass channel in the glass substrate to embed a chip with copper pillars, while reserving a filling gap between the glass channel and the chip and using ABF for vacuum pressing and curing, can reduce the problems of material thermal expansion mismatch, poor thickness uniformity, and insufficient surface flatness caused by traditional large-area EMC molding, and improve the chip embedding accuracy and packaging structure stability. By chamfering the inner wall edge of the glass channel and rounding the corners, stress concentration at the edges and corners of the glass channel can be mitigated, so that the stress generated by ABF during curing shrinkage and subsequent thermal cycling is more evenly distributed between the chip, glass substrate, and filling material, thereby reducing the risk of interface delamination, cracking, and glass edge chipping, and effectively suppressing package warpage. By forming and filling glass vias in the glass substrate, Conductive metal forms conductive vias penetrating the glass substrate. Combined with an inner circuit layer, redistribution circuit layer, solder mask layer, and solder balls disposed on the second side, and an upper package disposed on the first side and aligned and bonded to the conductive vias, high-density vertical electrical interconnects between the chip, redistribution circuit layer, and upper package can be achieved, shortening the signal transmission path and improving interconnect density and electrical performance. Simultaneously, the glass substrate possesses good surface flatness, dimensional stability, low water absorption, and suitability for microfabrication, which is beneficial for the subsequent formation of fine circuits and small-diameter conductive vias. Therefore, this invention can solve the problems of warping, delamination, or cracking failure caused by thermal expansion coefficient mismatch in existing InFO-PoP packaging EMC molding structures, as well as insufficient surface flatness, difficulty in reducing the diameter of conductive vias, limited vertical interconnect density, and insufficient reliability in thinner packaging. This invention achieves a semiconductor packaging structure with low warpage, high interconnect density, high circuit fabrication precision, and high reliability. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0128] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor packaging structure, characterized in that, The preparation method includes: S1, a glass substrate is provided, the glass substrate having a first side and a second side opposite to each other, and the thickness of the glass substrate is greater than the thickness of the chip to be embedded. S2, using laser-induced deep etching process to form glass through-holes and glass through-grooves that penetrate the glass substrate; S3, a fixture is provided, the fixture having a clearance groove and a plurality of vacuum adsorption holes penetrating along the thickness direction, the planar dimension of the clearance groove being larger than the planar dimension of the glass through groove, the glass substrate being fixed to the side of the fixture where the clearance groove is formed through the vacuum adsorption holes, so that the clearance groove corresponds to the position of the glass through groove, and on a projection plane parallel to the surface of the glass substrate, the clearance groove surrounds the outer periphery of the glass through groove, and there is a single-sided compensation gap between the sidewall of the clearance groove and the sidewall of the glass through groove; S4, a grinding rod is provided, the outer peripheral surface of which has a trapezoidal groove grinding profile extending circumferentially. The trapezoidal groove grinding profile includes a groove bottom surface and groove side surfaces connected to both sides of the groove bottom surface. The grinding rod is used to perform moving grinding on the inner wall of the glass channel. The inner wall edge of the glass channel is chamfered by the groove side surfaces to form a chamfered structure. The grinding rod is controlled to move along a preset arc travel trajectory at the corner of the glass channel to perform arc chamfering on the corner of the glass channel to form a chamfered structure. S5, fill the glass through hole with conductive metal to form a conductive through hole that penetrates the glass substrate; S6, a temporary adhesive film is attached to the second side of the glass substrate, and the chip with copper pillars is placed in the glass channel with the copper pillars facing the temporary adhesive film, and the chip is temporarily fixed in the glass channel by the temporary adhesive film, wherein the copper pillars are embedded in the chip, and adjacent copper pillars are isolated by an insulating medium. S7, using a vacuum pressing process, press ABF onto the side of the obtained structure away from the temporary adhesive film, so that the ABF fills the space between the chip and the inner wall of the glass channel and covers the glass substrate and the chip; S8, the ABF is cured and the cured ABF is planarized to expose the end face of the conductive via away from the temporary adhesive film; S9, Remove the temporary adhesive film; S10, an inner circuit layer is formed on the exposed surface of the copper pillar and on the end face of the conductive via located on the second surface; S11, a redistributed circuit layer is formed on the second surface of the glass substrate on which the inner circuit layer is formed, and the redistributed circuit layer is electrically connected to the copper pillar and the conductive via through the inner circuit layer; S12, a solder resist layer is formed on the surface of the redistribution circuit layer away from the glass substrate and a window is opened, and a solder ball is formed at the window to contact and connect with the redistribution circuit layer; S13, provide an upper package and align and bond the upper package to the first surface of the glass substrate so that the upper package is vertically electrically interconnected with the redistribution circuit layer through the conductive via.

2. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that: The thickness of the glass substrate is 200μm to 500μm; the diameter of the glass through-hole is 20μm to 40μm.

3. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that: In step S2, when the glass channel is formed using laser-induced deep etching, the taper of the sidewall of the glass channel is controlled between 0° and 5° by adjusting at least one of the parameters of the incident light spot spacing, energy, and pulse width induced by the laser.

4. The method for preparing a semiconductor packaging structure according to claim 1, characterized in that: The single-sided compensation distance between the sidewall of the clearance groove and the sidewall of the glass passage is 0.2mm~0.3mm.

5. The method for preparing a semiconductor packaging structure according to claim 1, characterized in that: In step S4, the inner wall edge of the glass channel is chamfered by the side of the channel, and a chamfered surface is formed at the opening edge of the first and second surfaces of the glass channel near the glass substrate. The angle between the chamfered surface and its adjacent first or second surface is 30° to 60°.

6. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that: In step S4, the chamfer radius of the chamfer structure formed by rounding the corner of the glass channel is 0.5mm to 10mm.

7. The method for fabricating a semiconductor packaging structure according to claim 1, characterized in that: In step S4, the method of moving the grinding rod to grind the inner wall of the glass channel includes controlling the grinding rod to rotate at a speed of 1000 rpm to 3000 rpm and controlling the grinding rod to move along the inner wall of the glass channel at a feed speed of 100 mm / min to 300 mm / min.

8. The method for preparing a semiconductor packaging structure according to claim 1, characterized in that: In step S4, during the grinding process of the grinding rod moving to grind the inner wall of the glass channel, high-pressure coolant is sprayed onto the grinding area to remove the heat generated during the grinding process.

9. A semiconductor packaging structure, characterized in that, The semiconductor packaging structure includes: A glass substrate and a chip with copper pillars, wherein the glass substrate has opposing first and second surfaces, and the thickness of the glass substrate is greater than the thickness of the chip; the copper pillars are embedded in the chip, and adjacent copper pillars are isolated by an insulating medium. The conductive via penetrating the glass substrate includes a glass via penetrating the glass substrate and a conductive metal filling the glass via; A glass channel penetrating the glass substrate, wherein the chip is housed in the glass channel with the end face of the copper pillar flush with the second surface, the glass channel having a chamfered structure at the inner wall edge of the glass channel and a chamfered structure at the corner of the glass channel; ABF is filled between the sidewall of the chip and the inner wall of the glass channel; An inner circuit layer is disposed on the second side of the glass substrate, and the inner circuit layer is electrically connected to the end face of the copper pillar and the conductive via located on the second side. A redistribution circuit layer is disposed on the side of the inner circuit layer away from the glass substrate, and the redistribution circuit layer is electrically connected to the copper pillar and the conductive via through the inner circuit layer; A solder resist layer is disposed on the surface of the redistribution circuit layer away from the glass substrate, and the solder resist layer has openings; Solder balls are disposed at the opening and are in contact with the redistribution circuit layer; and... An upper package is disposed on the first side of the glass substrate, and the upper package is vertically electrically interconnected with the redistribution circuit layer through the conductive via.

10. The semiconductor packaging structure according to claim 9, characterized in that: The thickness of the glass substrate is 200μm to 500μm; the diameter of the glass through-hole is 20μm to 40μm.

11. The semiconductor packaging structure according to claim 9, characterized in that: The taper of the sidewall of the glass channel is 0° to 5°.

12. The semiconductor packaging structure according to claim 9, characterized in that: The chamfered structure includes a chamfered surface located at the opening edge of the first and second surfaces of the glass through groove near the glass substrate, and the included angle between the chamfered surface and its adjacent first or second surface is 30° to 60°.

13. The semiconductor packaging structure according to claim 9, characterized in that: The chamfer radius of the chamfer structure is 0.5mm to 10mm.

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