High-voltage power chip packaging structure and packaging method

Abstract

This invention discloses a high-voltage power chip packaging structure and method, comprising: a substrate having a first surface; a high-voltage power chip disposed on the first surface of the substrate, the high-voltage power chip including a surface electrode, the edge of the high-voltage power chip having a high-potential region surrounding the surface electrode; a locally reinforcing insulating layer covering at least a portion of the surface of the high-potential region of the chip edge, the surface of the locally reinforcing insulating layer being non-planar; and an insulating package covering at least the high-voltage power chip and the locally reinforcing insulating layer. The high-voltage power chip packaging structure and method of this invention overcome the defects in existing high-voltage power chip packaging where the edge region is prone to surface discharge, localized arcing, and increased leakage current under high-temperature conditions, effectively suppressing high-temperature surface discharge, improving packaging withstand voltage, and enhancing long-term reliability.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device packaging and insulation protection technology, specifically relating to a high-voltage power chip packaging structure and a high-voltage power chip packaging method, which is suitable for insulation protection of high-voltage power chips under high temperature and high electric field conditions. Background Technology

[0002] With the development of power semiconductor devices, high-voltage power chips of 10 kV and above have broad application prospects in power transmission and distribution, power grid equipment, new energy power generation, rail transit, and pulse power devices. The emergence of wide-bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) enables power chips to withstand higher breakdown field strengths, have lower conduction losses, and higher operating temperature capabilities. However, along with this, the insulation reliability problem of high-voltage power chips during the packaging process is becoming increasingly prominent.

[0003] For vertical power chips, the scribe lines, termination areas, or edge passivation areas around the chip are typically at high potentials during operation, and have complex electric field coupling relationships with the surface electrodes, encapsulation insulating materials, and the external environment. After the chip is soldered and fixed to the substrate, existing packaging methods typically use potting silicone or similar soft insulating materials to comprehensively encapsulate and protect the chip surface, relying mainly on the insulating capacity of the potting material itself to withstand the high voltage on the chip surface.

[0004] However, in practical applications, it has been found that when the geometric distance between the high potential region at the edge of the chip and the surface metal electrode or the external environment is small, the potting material may still meet the short-term insulation requirements at room temperature. However, under high temperature conditions, due to factors such as the decrease in dielectric properties of the potting material, the deterioration of the interface state, the increase in micro-voids caused by local thermal stress, and the enhancement of the local electric field along the surface path, it is easy to induce surface discharge, local arcing, increased gate leakage current, increased drain leakage current, or even permanent device failure.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a high-voltage power chip packaging structure and a high-voltage power chip packaging method, which can overcome the defects in the edge area of ​​the high-voltage power chip packaging in the prior art that are prone to surface discharge, local arcing and increased leakage current under high temperature conditions, effectively suppress high-temperature surface discharge, improve the packaging withstand voltage and long-term reliability.

[0007] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0008] A high-voltage power chip packaging structure, comprising:

[0009] The substrate has a first surface;

[0010] A high-voltage power chip is disposed on a first surface of the substrate. The high-voltage power chip includes a surface electrode, and the edge of the high-voltage power chip has a chip edge high-potential region surrounding the surface electrode.

[0011] A locally reinforced insulating layer, at least covering a portion of the surface of a high-potential region at the edge of the chip, wherein the surface of the locally reinforced insulating layer is non-planar; and

[0012] An insulating package that at least covers the high-voltage power chip and the locally reinforced insulating layer;

[0013] The locally reinforced insulating layer has at least one of the following properties that are superior to the insulating package: dielectric strength, volume resistivity, surface resistivity, heat resistance, interface adhesion with the high-potential region at the chip edge, and interface stability after high-temperature aging. The locally reinforced insulating layer and the insulating package form a composite insulating interface, which is configured to extend the effective surface discharge path from the high-potential region at the chip edge to the external environment and / or adjacent electrodes and / or substrate conductors.

[0014] In one or more embodiments of the present invention, the high-potential region at the chip edge includes at least a portion of the scribe line region of the high-voltage power chip and / or at least a portion of the front terminal region of the high-voltage power chip and / or at least a portion of the edge passivation region of the high-voltage power chip and / or at least a portion of the first surface of the substrate.

[0015] In one or more embodiments of the present invention, the locally reinforced insulating layer is distributed continuously or intermittently in a ring shape along the edge of the high-voltage power chip; and / or,

[0016] The locally reinforced insulating layer extends from the edge of the high-voltage power chip towards the inner and / or outer side of the chip, covering a predetermined width, wherein the predetermined width ranges from 50 μm to 50 mm; and / or,

[0017] The locally reinforced insulating layer covers at least a portion of the edge region or non-electrically connected region of the surface electrodes of the high-voltage power chip; and / or,

[0018] The high-voltage power chip is electrically connected to the substrate via bonding wires, and the locally reinforced insulating layer covers at least a portion of the surface surface of the surface electrode of the high-voltage power chip and / or at least a portion of the surface of the bonding wires; and / or,

[0019] The total thickness of the locally reinforced insulating layer ranges from 10 nm to 1000 μm; and / or,

[0020] The width of the locally reinforced insulating layer is greater than the width of the passivation layer within the edge passivation region of the high-voltage power chip; and / or,

[0021] The locally reinforced insulation layer has a three-dimensional morphology selected from a group consisting of protruding structures, dam structures, slope structures, stepped structures, and combinations thereof; and / or,

[0022] The locally reinforced insulating layer has a gradually decreasing thickness, which decreases from the high-potential region at the edge of the chip along the direction away from the high-voltage power chip.

[0023] In one or more embodiments of the present invention, the material of the locally reinforced insulating layer is different from the material of the insulating package; and / or,

[0024] The material of the locally reinforced insulation layer is selected from one or more of the following: polyimide, epoxy insulation material, silicone-modified insulation material, composite insulation material containing inorganic filler, and ceramic particle-filled insulation material.

[0025] In one or more embodiments of the present invention, the locally reinforced insulation layer is a single-layer insulation structure or a multi-layer composite insulation structure.

[0026] In one or more embodiments of the present invention, the locally reinforced insulating layer is a multilayer composite insulating structure, including an inner insulating layer and an outer insulating layer. The inner insulating layer is at least attached to the surface of the high-voltage power chip, and the outer insulating layer covers the inner insulating layer. The flexibility or adhesion of the inner insulating layer is greater than that of the outer insulating layer, and the dielectric strength of the outer insulating layer is greater than that of the inner insulating layer. Alternatively...

[0027] The locally reinforced insulation layer is a multi-layer composite insulation structure, including an inner insulation layer, a transition layer, and an outer insulation layer. The inner insulation layer is attached to at least the surface of the high-voltage power chip. The transition layer covers the inner insulation layer, and the outer insulation layer covers the transition layer. The dielectric constant, elastic modulus, coefficient of thermal expansion, or filler content of different layers vary in gradient from the direction away from the high-voltage power chip.

[0028] In one or more embodiments of the present invention, the material of the inner insulating layer is selected from polyimide, silicone-modified insulating material, or epoxy insulating material; the outer insulating layer is an inorganic dense insulating layer and / or a composite insulating layer containing inorganic fillers; wherein, the material of the inorganic dense insulating layer includes Al2O3, SiO2, and SiN. xOne or more of Al2O3, AlN, BN, diamond, or diamond-like carbon film; the composite insulating layer containing inorganic fillers comprises a polymer matrix and Al2O3, AlN, BN, SiO2, and SiN dispersed in the polymer matrix. x One or more of diamond or diamond-like carbon particles.

[0029] A high-voltage power chip packaging method, comprising:

[0030] A substrate is provided, the substrate having a first surface;

[0031] A high-voltage power chip is provided, wherein the high-voltage power chip is disposed on a first surface of the substrate, the high-voltage power chip includes a surface electrode, and the edge of the high-voltage power chip has a chip edge high-potential region surrounding the surface electrode;

[0032] A locally reinforced insulating layer is formed and cured on at least a portion of the surface of the high-potential region at the edge of the high-voltage power chip, wherein the surface of the locally reinforced insulating layer is non-planar; and

[0033] An insulating package is formed that at least covers the high-voltage power chip and the localized reinforced insulating layer;

[0034] The locally reinforced insulating layer has at least one of the following properties that are superior to the insulating package: dielectric strength, volume resistivity, surface resistivity, heat resistance, interface adhesion with the high-potential region at the chip edge, and interface stability after high-temperature aging. The locally reinforced insulating layer and the insulating package form a composite insulating interface, which is configured to extend the effective surface discharge path from the high-potential region at the chip edge to the external environment and / or adjacent electrodes and / or substrate conductors.

[0035] In one or more embodiments of the present invention, forming the locally reinforced insulating layer includes:

[0036] An insulating material is applied to the surface of the high-potential region at the edge of the chip using at least one of the following methods: deposition, coating, printing, dispensing, molding, or attachment; and / or,

[0037] Multiple applications of insulating material and / or contour shaping are performed to form a locally reinforced insulating layer with a three-dimensional morphology;

[0038] The localized reinforcing insulation layer is distributed continuously in a ring along the edge of the high-voltage power chip, or the localized reinforcing insulation layer is distributed discontinuously in a ring along the edge of the high-voltage power chip, forming multiple discontinuously arranged localized reinforcing insulation regions.

[0039] In one or more embodiments of the present invention, prior to forming the locally reinforced insulating layer, the surface of the high-potential region at the edge of the chip is further subjected to cleaning, dehumidification, or surface activation pretreatment.

[0040] Compared with the prior art, the high-voltage power chip packaging structure and method of the present invention construct a locally reinforced insulating layer in the high-potential region at the chip edge. This layer has at least one superior performance in terms of dielectric strength, volume resistivity, surface resistivity, heat resistance, interfacial adhesion with the high-potential region at the chip edge, and interfacial stability after high-temperature aging. The layer is non-planar and can specifically enhance the insulation capability of the area most prone to surface discharge. The locally reinforced insulating layer and the insulating package form a composite insulation system. The composite insulation interface between the two makes the effective surface discharge path from the high-potential region at the chip edge to the external environment, adjacent electrodes and / or substrate conductors longer than the shortest planar path when no locally reinforced insulating layer is provided. This extends the effective surface discharge path, improves the local electric field distribution at the edge, isolates the high-potential region from direct contact with the insulating package, and improves the insulation reliability under high-temperature conditions.

[0041] The high-voltage power chip packaging structure and method of the present invention can use materials with higher temperature resistance, higher dielectric strength and stronger adhesion than the insulating package body for the locally enhanced insulating layer, which effectively reduces the discharge risk caused by softening of the insulating package body, changes in dielectric properties and increase of interface microvoids at high temperatures.

[0042] The high-voltage power chip packaging structure and method of the present invention suppress arcing by constructing a three-dimensional morphology for a locally enhanced insulating layer, thereby transforming the potential discharge path into a longer and more tortuous effective surface path.

[0043] The high-voltage power chip packaging structure and method of the present invention can, to a certain extent, mitigate the electric field concentration near the high-potential region at the edge of the chip and reduce the probability of partial discharge initiation by locally thickening and contour optimizing the locally reinforced insulating layer.

[0044] The high-voltage power chip packaging structure and method of the present invention do not require simply increasing the planar spacing between the chip surface electrodes and the edge to improve the withstand voltage capability, which is beneficial to maintaining the chip area and package size; it can be introduced after the chip is fixed, adapting to the existing power device packaging process, and facilitating industrial implementation. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic cross-sectional view of the existing high-voltage power chip packaging structure (the thick black line represents the high-potential area at the chip edge).

[0047] Figure 2 This is a top view of the existing high-voltage power chip packaging structure (the black area is the high-potential area at the edge of the chip).

[0048] Figure 3 This is a schematic cross-sectional view of the high-voltage power chip packaging structure in Embodiment 1 of the present invention (the colored area is a local reinforced insulating layer).

[0049] Figure 4 This is a top view of the high-voltage power chip packaging structure in Embodiment 1 of the present invention (the colored area is a local reinforced insulating layer).

[0050] Figure 5 The diagram shows the HVIDSS (leakage current under high voltage drain (or high potential region) performance of the high voltage power chip packaging structure of the prior art and the high voltage power chip packaging structure of Embodiment 1 of the present invention at 25°C and 10KV.

[0051] Figure 6 The diagram shows the HVIDSS (leakage current under high voltage drain (or high potential region) performance of the high voltage power chip packaging structure of the prior art and the high voltage power chip packaging structure of Embodiment 1 of the present invention at 175°C and 10KV.

[0052] Figure 7 This is a schematic cross-sectional view of the high-voltage power chip packaging structure in Embodiment 3 of the present invention (the colored area is a local reinforced insulating layer). Detailed Implementation

[0053] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0054] Terminology Explanation:

[0055] "High-voltage power chips" refer to semiconductor chips used in the field of power electronics, including but not limited to MOSFETs, IGBTs, diodes, etc., and their materials can be silicon (Si), silicon carbide (SiC), gallium nitride (GaN) or other semiconductor materials.

[0056] "High-potential areas at the chip edge" refers to areas located around the chip and with a potential higher than that of the external environment or adjacent electrodes when the high-voltage power chip is in operation, including but not limited to scribe lines, terminal areas, and edge passivation areas.

[0057] Figure 1 and Figure 2 This is a schematic diagram of the packaging structure of a high-voltage power chip in the prior art.

[0058] like Figure 1 As shown, the high-voltage power chip package structure includes: a substrate 10, a high-voltage power chip 20, a surface electrode 30, a high-potential region 40 at the chip edge, an insulating package 50, and bonding wires 60. The high-voltage power chip 20 is soldered and fixed to the substrate 10. For example, the high-voltage power chip 20 and the substrate 10 can be soldered and fixed using a copper-clad ceramic sheet A. The surface electrode 30 is disposed on the surface of the high-voltage power chip 20, and the surface electrode 30 serves as the source, gate, or anode lead-out terminal of the high-voltage power chip 20. The high-potential region 40 at the chip edge is located around the periphery of the high-voltage power chip 20. Figure 1 The high-potential area at the edge of the chip is marked with a thick black line. It is at a high potential during operation and is a high-risk area for surface discharge and local arcing. The insulating package 50 covers at least a portion of the high-voltage power chip 20 and the substrate 10.

[0059] like Figure 2 As shown, viewed from above the package structure, a ring-shaped high-potential region 40 is formed around the high-voltage power chip 20. Figure 2 (The location of the high-potential area at the edge of the chip is marked by a black area). This ring-shaped high-potential area 40 at the edge of the chip is continuously distributed around the high-voltage power chip 20 and even extends to the equipotential copper layer on the surface of the substrate 10.

[0060] Combination Figure 1 and Figure 2As is known from the background technology, existing high-voltage power chip packaging methods generally rely on the insulation capacity of the overall potting material itself (insulating package) to withstand the high voltage on the chip surface. However, in practical applications, it has been found that when the geometric distance between the high-potential area at the chip edge and the surface electrode or external environment is small, the potting material may still meet the short-term insulation requirements at room temperature. However, under high temperature conditions, due to factors such as the decrease in dielectric properties of the potting material, the deterioration of the interface state, the increase in micro-voids caused by local thermal stress, and the enhancement of the local electric field along the surface path, it is easy to induce surface discharge, local arcing, increased gate leakage current, increased drain leakage current, or even permanent device failure.

[0061] To address the aforementioned issues, one existing solution is to improve insulation reliability by increasing the planar distance between the high-voltage region on the chip surface and the surface electrodes. However, this solution significantly increases the chip area and package size, which is detrimental to the miniaturization and high-power density design of high-voltage devices. Another solution is to simply replace the overall potting material. While this can improve insulation to some extent, it lacks targeted suppression methods for surface discharge channels formed in local high-field edge regions at high temperatures, making it difficult to simultaneously achieve local withstand voltage enhancement, interface stability, and process feasibility.

[0062] Based on this, the present invention provides a high-voltage power chip packaging structure and a high-voltage power chip packaging method. By locally constructing a highly insulating, high-temperature resistant, and controllably covered locally enhanced insulating layer in the high-potential region at the chip edge, a composite insulating system is formed with the external insulating package. This improves the local insulation strength of the high-potential region at the chip edge, extends the effective surface discharge path of the high-potential region at the chip edge to the outside, and suppresses the electric field concentration near the chip edge scribe line, terminal area, or surface electrode edge. It also reduces the discharge risk caused by the degradation of the interface between the external insulating package and the chip surface under high-temperature conditions, and improves the packaging withstand voltage and long-term reliability without significantly increasing the chip planar size.

[0063] The present invention provides a high-voltage power chip packaging structure, comprising:

[0064] The substrate has a first surface;

[0065] A high-voltage power chip is disposed on a first surface of a substrate. The high-voltage power chip includes a surface electrode, and the edge of the high-voltage power chip has a chip edge high-potential region surrounding the surface electrode.

[0066] A locally reinforced insulating layer, at least covering a portion of the surface of a high-potential region at the edge of the chip, wherein the surface of the locally reinforced insulating layer is non-planar; and

[0067] An insulating package that at least covers the high-voltage power chip and a locally reinforced insulating layer;

[0068] Among them, the dielectric strength, volume resistivity, surface resistivity, heat resistance, interface adhesion between the localized reinforced insulating layer and the high-potential region at the chip edge, and interface stability after high-temperature aging are all superior to those of the insulating package. The localized reinforced insulating layer and the insulating package form a composite insulating interface. The composite insulating interface is configured to extend the effective surface discharge path from the high-potential region at the chip edge to the external environment and / or adjacent electrodes and / or substrate conductors.

[0069] In the above technical solution, the composite insulating interface enables the effective surface discharge path from the high potential area at the edge of the chip to the external environment, adjacent electrodes and / or substrate conductors to be greater than the shortest planar path when no local reinforcing insulating layer is provided. This specifically enhances the insulation capability of the area most prone to surface discharge, effectively suppresses high-temperature surface discharge, improves the package withstand voltage capability and long-term reliability.

[0070] The present invention provides a high-voltage power chip packaging method, comprising:

[0071] A substrate is provided, the substrate having a first surface;

[0072] A high-voltage power chip is provided, wherein the high-voltage power chip is disposed on a first surface of the substrate, the high-voltage power chip includes a surface electrode, and the edge of the high-voltage power chip has a chip edge high-potential region surrounding the surface electrode;

[0073] A locally reinforced insulating layer is formed and cured on at least a portion of the surface of the high-potential region at the edge of the high-voltage power chip, wherein the surface of the locally reinforced insulating layer is non-planar; and

[0074] An insulating package is formed that at least covers the high-voltage power chip and the localized reinforced insulating layer;

[0075] The locally reinforced insulating layer has at least one of the following properties that are superior to the insulating package: dielectric strength, volume resistivity, surface resistivity, heat resistance, interface adhesion with the high-potential region at the chip edge, and interface stability after high-temperature aging. The locally reinforced insulating layer and the insulating package form a composite insulating interface, which is configured to extend the effective surface discharge path from the high-potential region at the chip edge to the external environment and / or adjacent electrodes and / or substrate conductors.

[0076] The high-voltage power chip packaging structure and method of the present invention include a locally reinforced insulating layer disposed on at least a portion of the surface of the high-potential region at the chip edge. This layer is continuously or intermittently distributed along the chip edge, and its thickness, width, material heat resistance, volume resistivity, surface resistivity, dielectric strength, and / or interface adhesion and interface stability are higher than those of the corresponding area of ​​the insulating package. This provides local insulation reinforcement and discharge path detour to the high-potential region at the chip edge. The locally reinforced insulating layer and the insulating package together constitute a composite insulation system, used to extend the effective surface path between the high-potential region at the chip edge and the external environment and / or adjacent electrodes and / or substrate conductors, suppressing surface discharge and localized arcing under high-temperature conditions.

[0077] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described in this specification are merely illustrative of the invention and are not intended to limit the invention.

[0078] Example 1:

[0079] like Figure 3 and Figure 4 As shown, the high-voltage power chip packaging structure in this embodiment includes a substrate 100, a high-voltage power chip 200, a surface electrode 300, a high-potential region at the chip edge 400, a locally reinforced insulating layer 500, and a package body 600.

[0080] A high-voltage power chip 200 is disposed on the substrate 100. In this embodiment, the high-voltage power chip 200 is a vertical high-voltage power chip, such as a silicon carbide MOSFET or a silicon carbide diode, with an operating voltage of up to 600V, or even 10kV. The high-voltage power chip 200 can be fixed to the substrate 100 by welding, sintering, or bonding to achieve electrical and thermal connections. In this embodiment, the high-voltage power chip 200 is fixed to the first surface of the substrate 100 by welding a double-sided copper-clad ceramic sheet B.

[0081] A surface electrode 300 is disposed on the surface of the high-voltage power chip 200. The surface electrode 300 serves as the source, gate, or anode lead-out terminal of the high-voltage power chip 200, and withstands a high potential during operation. In this embodiment, the surface electrode 300 may be formed of aluminum, copper, or other conductive metal materials.

[0082] The edge region of the high-voltage power chip 200 has a high-potential region 400 at the chip edge, which can be referenced. Figure 2The existing packaging structure is shown. The high-potential region 400 at the chip edge is a ring-shaped region formed around the chip edge, and its extension may include the chip's scribe line region, termination region, or edge passivation region, or a combination of the above regions. In the operating state, the potential of this region is higher than that of the external environment or adjacent electrodes.

[0083] The locally reinforced insulating layer 500 at least covers at least a portion of the surface of the high-potential region 400 at the chip edge. For example... Figure 3 As shown, a locally reinforced insulating layer 500 is disposed on the side surface (diced area) of the high-voltage power chip 200 and extends from the chip edge to the inside and / or outside of the chip, covering a predetermined width. This width can be designed according to the chip's withstand voltage level and package size, for example, from tens of micrometers to several millimeters.

[0084] In this embodiment, it is continuously distributed in a ring shape along the edge of the high-voltage power chip 200. In other embodiments, the locally reinforced insulating layer 500 may also be distributed intermittently in a concentric ring shape along the edge of the high-voltage power chip 200.

[0085] In this embodiment, the locally reinforced insulating layer 500 is a single-layer structure. The dielectric strength of the locally reinforced insulating layer 500 is higher than that of the insulating package 600. For example, the locally reinforced insulating layer 500 can be made of polyimide (dielectric strength approximately 200 kV / mm-300 kV / mm), while the insulating package 600 can be made of silicone (dielectric strength approximately 20 kV / mm-40 kV / mm). The locally reinforced insulating layer 500 has stronger high-temperature resistance than the insulating package 600. The locally reinforced insulating layer 500 has stronger interface stability than the insulating package 600. The adhesion of the locally reinforced insulating layer 500 is higher than that of the insulating package 600. The above configuration can further improve the local insulation stability of the chip surface edge area at high temperatures.

[0086] In other embodiments, the material of the locally reinforced insulating layer 500 may also be selected from one or more of epoxy insulating materials, organosilicon modified insulating materials, composite insulating materials containing inorganic fillers (such as diamond, diamond-like carbon film, aluminum nitride, boron nitride, alumina, silicon oxide, and silicon nitride), and ceramic particle-filled insulating materials. The locally reinforced insulating layer 500 uses an insulating material with both high dielectric strength and high thermal conductivity, enabling the high-potential region 400 at the chip edge to simultaneously achieve local insulation enhancement and heat dissipation effects under high-temperature blocking conditions, reducing the risk of edge hotspots, interface degradation, and partial discharge initiation.

[0087] Furthermore, the width of the locally reinforced insulating layer 500 may be greater than the width of the passivation layer in the passivation region at the surface edge of the high-voltage power chip 200. That is, the locally reinforced insulating layer 500 completely covers the passivation layer in the passivation region at the surface edge of the high-voltage power chip 200 and extends to at least a portion of the edge region or non-electrical connection region of the surface electrode 300.

[0088] In this embodiment, the surface of the locally reinforced insulating layer 500 is non-planar and may have a three-dimensional morphology. For example, a portion of the surface of the locally reinforced insulating layer 500 protrudes upward, forming a freely protruding tooth-like structure, which requires the surface discharge path to traverse the tooth-like structure, thereby extending the effective discharge path.

[0089] In other embodiments, the three-dimensional morphology of the locally reinforced insulating layer 500 may also include dam structures, slope structures, stepped structures, combinations thereof, or other irregular structures. For example, the locally reinforced insulating layer 500 may be constructed as a slope structure, meaning that the locally reinforced insulating layer 500 has a greater thickness in the high-potential region 400 near the chip edge and gradually thins away from the chip edge, forming a slope-shaped or arc-shaped transition structure to reduce the electric field abrupt change at the boundary of the locally reinforced insulating layer 500.

[0090] The insulating package 600 covers at least a portion of the high-voltage power chip 200, the locally reinforced insulating layer 500, and the substrate 100. The insulating package 600 is typically formed using a potting process, and the material can be silicone, epoxy resin, or other insulating potting materials, used for overall environmental protection and insulation of the chip.

[0091] The locally reinforced insulation layer 500 and the insulating encapsulation 600 together form a composite insulation interface. For example... Figure 1 As shown, in a conventional packaging structure, the surface discharge path extends directly along the chip surface to the surface electrode, resulting in a shorter path; however, in the packaging structure of this embodiment, as... Figure 3 As shown, the surface discharge path needs to pass through the composite insulating interface between the locally reinforced insulating layer 500 and the insulating package 600, significantly extending the path. Therefore, this composite insulating interface is configured to extend the surface discharge path from the high-potential region 400 at the chip edge to the external environment or adjacent electrodes, thereby suppressing surface discharge and localized arcing under high-temperature conditions.

[0092] Figure 5 The diagram shows the HVIDSS (leakage current under high voltage drain (or high potential region) performance of the existing high voltage power chip packaging structure and the high voltage power chip packaging structure of the present invention at 25°C and 10KV. Figure 6The diagram shows the HVIDSS (leakage current under high-voltage drain (or high-potential region) bias) performance of the existing high-voltage power chip packaging structure and the high-voltage power chip packaging structure of the present invention at 175°C and 10KV. NEW PI represents the packaging form with a locally reinforced insulating layer formed after wire bonding of the high-voltage power chip, and OLD PI represents the packaging form without a locally reinforced insulating layer formed after wire bonding of the high-voltage power chip.

[0093] refer to Figure 5 and Figure 6 As shown, experimental data obtained from testing the packaging structures in the prior art and the packaging structure in this embodiment at room temperature and high temperature revealed the following: At room temperature (25°C), the packaging structure with wire bonding followed by a localized reinforcing insulation layer has a VDS of 10kV and an HVIDSS of 10nA~20nA; the packaging structure without wire bonding has a VDS of 10kV and an HVIDSS of 50nA~100nA. At high temperature (175°C), the packaging structure with wire bonding followed by a localized reinforcing insulation layer has a VDS of 10kV and an HVIDSS of 260nA; the packaging structure without wire bonding has a VDS of 10kV and an HVIDSS of 700nA. Data shows that, under the same chip size, the same distance between the surface electrode and the edge, and the same potting material, the packaging structure of the present invention significantly reduces leakage current and arcing probability compared to the packaging structure of the prior art, regardless of whether it is under normal temperature and 10 kV conditions or high temperature and 10 kV conditions.

[0094] Example 2:

[0095] The high-voltage power chip packaging structure in this embodiment is largely the same as that in Embodiment 1, except that in this embodiment, the locally reinforced insulating layer is a multi-layer composite insulating structure. Specifically, the multi-layer composite insulating structure includes: an inner insulating layer attached to the surface of the high-voltage power chip; and an outer insulating layer covering the inner insulating layer.

[0096] The inner insulating layer is made of a highly adhesive flexible insulating material, such as polyimide, silicone-modified resin, or epoxy resin, to buffer thermal stress between the high-voltage power chip, passivation layer, surface electrode, and insulating package, thereby improving interfacial adhesion stability. The outer insulating layer is an inorganic dense insulating layer and / or a composite insulating layer containing inorganic fillers. The inorganic dense insulating layer may contain materials such as Al2O3, SiO2, or SiN. x One or more of Al2O3, AlN, BN, diamond or diamond-like carbon films; the composite insulating layer containing inorganic fillers includes a polymer matrix and Al2O3, AlN, BN, SiO2, SiN dispersed in the polymer matrix. xOne or more of diamond or diamond-like carbon particles are used to form a dense barrier layer and a high-voltage barrier. The adhesion of the inner insulating layer is higher than that of the outer insulating layer, while the dielectric strength of the outer insulating layer is higher than that of the inner insulating layer. This composite structure with functional allocation between the inner and outer layers balances interfacial bonding performance and insulation protection performance.

[0097] In other embodiments, the multilayer composite insulation structure may further include: an inner insulating layer attached to the surface of the high-voltage power chip; an intermediate transition layer covering the inner insulating layer; and an outer insulating layer covering the intermediate transition layer. The inner insulating layer is preferably made of a low-modulus, high-adhesion material, and the outer insulating layer is preferably made of a high-dielectric-strength material. The dielectric constant, elastic modulus, coefficient of thermal expansion, or filler content of the different layers varies gradiently away from the high-voltage power chip, for example, increasing gradient. This gradient structure can effectively reduce interlayer interface stress and decrease the risk of delamination or cracking caused by mismatch in coefficients of thermal expansion.

[0098] Example 3:

[0099] like Figure 7 As shown, the high-voltage power chip packaging structure of this embodiment is largely the same as that in Embodiment 1, except that in this embodiment, the localized reinforcing insulating layer 500 not only covers part of the surface of the high-potential region 400 at the chip edge, but also further covers the entire surface of the surface electrode 300 and / or the entire surface of the bonding wire 700 of the high-voltage power chip. Specifically, the localized reinforcing insulating layer 500 can cover the surface electrode region, the edge passivation region, and the bonding wire 700 connecting the chip to the external circuit on the chip surface to further reduce the possibility of surface discharge.

[0100] This implementation method is suitable for applications with higher insulation requirements, such as power modules with voltage levels of 10kV and above.

[0101] In other embodiments, the locally reinforced insulating layer 500 may also cover part of the surface electrode 300 and / or part of the bonding wire 700 of the high-potential region 400 at the edge of the chip, while also covering part of the surface of the high-voltage power chip.

[0102] Example 4:

[0103] This embodiment provides a packaging method for a high-voltage power chip packaging structure, which specifically includes the following steps:

[0104] Step S1: Chip assembly.

[0105] A substrate 100 is provided, and a high-voltage power chip 200 is fixed on the first surface of the substrate 100. Specifically, the high-voltage power chip 200 can be fixed on the substrate 100 by means of welding, sintering or bonding through a double-sided copper-clad ceramic sheet B, so as to realize the electrical connection and thermal connection between the chip and the substrate.

[0106] In this step, the high-voltage power chip 200 is a vertical power chip with an operating voltage of over 600V. The chip can be mounted using conventional die attach processes, such as soldering with silver paste or solder.

[0107] Step S2: Surface pretreatment.

[0108] Before forming the localized reinforcing insulating layer 500, the chip surface, chip edge region, and / or the region where the localized reinforcing insulating layer 500 is to be formed (the high-potential region 400 at the chip edge) may be pretreated. This pretreatment includes cleaning, decontamination, baking and dehumidification, and / or surface activation to improve the adhesion and interface stability of the subsequent localized reinforcing insulating layer 500 material.

[0109] For example, surface contaminants can be removed by plasma cleaning or chemical cleaning, followed by baking at an appropriate temperature (such as 150-200°C) to remove moisture.

[0110] Step S3: Form a locally reinforced insulation layer.

[0111] A locally reinforced insulating layer 500 is formed on at least a portion of the surface of a high-potential region 400 at the chip edge of the high-voltage power chip 200. This high-potential region 400 is located around the periphery of the high-voltage power chip 200 and has a non-planar surface. Specifically, the insulating material can be applied to the surface of the high-potential region 400 at the chip edge by at least one of the following methods: deposition, coating (spraying, spin coating, blade coating), printing, dispensing, molding, attachment, or transfer.

[0112] Specifically, different formation processes can be used for locally reinforced insulating layers 500 with different materials and properties. For example, sputtering / PVD (Physical Vapor Deposition) processes are suitable for Al2O3, AlN, SiO2, and SiN. xDLC-type thin films; ALD (Atomic Layer Deposition) technology is suitable for forming dense, uniform, and well-covered ultrathin inner layers such as Al2O3, HfO2, and SiO2; PECVD (Plasma Enhanced Chemical Vapor Deposition) / CVD (Chemical Vapor Deposition) can be used for SiN... x Suitable for thicker layers of PI (Polyimide), epoxy resin, silicone resin, ceramic-filled resin, etc., including SiO2, DLC, diamond-like carbon film, etc.; dispensing / spraying / printing / scraping are suitable for thicker layers of PI (Polyimide), epoxy resin, silicone resin, ceramic-filled resin, etc.

[0113] The locally reinforced insulating layer 500 can be formed in a continuous ring shape along the edge of the high-voltage power chip 200, or it can form multiple discontinuous locally reinforced insulating regions. The locally reinforced insulating layer 500 extends from the chip edge to the inner and / or outer side of the chip with a predetermined width, for example, 50 μm-50 mm.

[0114] This step also includes a sub-step of locally thickening and contouring the locally reinforced insulation layer 500. Depending on the insulation requirements, the locally reinforced insulation layer 500 may be repeatedly coated, locally stacked, contoured, or shaped before curing to form a locally reinforced insulation layer 500 with a three-dimensional morphology, such as a dam-like, stepped, sloping, arc-shaped transition, or labyrinthine spacing-increasing structure.

[0115] Step S4: Curing treatment.

[0116] The locally reinforced insulation layer 500 is then cured. Specifically, heat curing, step curing, UV curing, or a combination of curing methods can be used to improve its mechanical stability, heat resistance, and insulation performance.

[0117] The curing conditions are determined based on the material type. For example, for polyimide materials, a stepped temperature increase curing method can be used (e.g., 80℃ / 1h → 150℃ / 1h → 250℃ / 2h); for UV-curable materials, post-baking can be performed after UV irradiation.

[0118] Step S5: Form an insulating encapsulation.

[0119] After the locally reinforced insulating layer 500 is completed, an insulating package 600 is formed, covering at least a portion of the high-voltage power chip 200, the locally reinforced insulating layer 500, and the substrate 100. Specifically, the insulating package 600 can be formed using a potting process. The material of the insulating package 600 is preferably silicone or epoxy-based potting insulating material. The locally reinforced insulating layer 500, as a locally high insulating barrier, together with the insulating package 600, forms a composite insulating system.

[0120] During the potting process, vacuum degassing can be performed to eliminate air bubbles, ensuring the compactness and insulation performance of the insulating package 600.

[0121] Step S6: Post-processing and detection.

[0122] Optionally, the packaging structure can be post-processed and tested, including: degassing, post-curing, withstand voltage testing, partial discharge testing, high temperature aging testing, thermal cycling testing, or reliability screening, to verify the effect of the packaging structure on improving high temperature anti-sparking performance.

[0123] In the above method, the dielectric strength, volume resistivity, surface resistivity, heat resistance, interface adhesion between the localized reinforcing insulating layer 500 and the high-potential region at the chip edge, and interface stability after high-temperature aging are all higher than those of the insulating package 600. The localized reinforcing insulating layer 500 and the insulating package 600 form a composite insulating interface. The composite insulating interface is configured such that the effective surface discharge path from the high-potential region at the chip edge to the external environment, adjacent electrodes and / or substrate conductors is greater than the shortest planar path when the localized reinforcing insulating layer is not provided.

[0124] Compared with the prior art, the high-voltage power chip packaging structure and method of the present invention construct a locally reinforced insulating layer in the high-potential region at the chip edge. This layer has at least one superior performance in terms of dielectric strength, volume resistivity, surface resistivity, heat resistance, interfacial adhesion with the high-potential region at the chip edge, and interfacial stability after high-temperature aging. The layer is non-planar and can specifically enhance the insulation capability of the area most prone to surface discharge. The locally reinforced insulating layer and the insulating package form a composite insulation system. The composite insulation interface between the two makes the effective surface discharge path from the high-potential region at the chip edge to the external environment, adjacent electrodes and / or substrate conductors longer than the shortest planar path when no locally reinforced insulating layer is provided. This extends the effective surface discharge path, improves the local electric field distribution at the edge, isolates the high-potential region from direct contact with the insulating package, and improves the insulation reliability under high-temperature conditions.

[0125] The high-voltage power chip packaging structure and method of the present invention can use materials with higher temperature resistance, higher dielectric strength and stronger adhesion than the insulating package body for the locally enhanced insulating layer, which effectively reduces the discharge risk caused by softening of the insulating package body, changes in dielectric properties and increase of interface microvoids at high temperatures.

[0126] The high-voltage power chip packaging structure and method of the present invention suppress arcing by constructing a three-dimensional morphology for a locally enhanced insulating layer, thereby transforming the potential discharge path into a longer and more tortuous effective surface path.

[0127] The high-voltage power chip packaging structure and method of the present invention can, to a certain extent, mitigate the electric field concentration near the high-potential region at the edge of the chip and reduce the probability of partial discharge initiation by locally thickening and contour optimizing the locally reinforced insulating layer.

[0128] The high-voltage power chip packaging structure and method of the present invention do not require simply increasing the planar spacing between the chip surface electrodes and the edge to improve the withstand voltage capability, which is beneficial to maintaining the chip area and package size; it can be introduced after the chip is fixed, adapting to the existing power device packaging process, and facilitating industrial implementation.

[0129] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0130] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A high-voltage power chip packaging structure, characterized in that, include: The substrate has a first surface; A high-voltage power chip is disposed on a first surface of the substrate. The high-voltage power chip includes a surface electrode, and the edge of the high-voltage power chip has a chip edge high-potential region surrounding the surface electrode. A locally reinforced insulating layer, at least covering a portion of the surface of a high-potential region at the edge of the chip, wherein the surface of the locally reinforced insulating layer is non-planar; and An insulating package that at least covers the high-voltage power chip and the locally reinforced insulating layer; The locally reinforced insulating layer has at least one of the following properties that are superior to the insulating package: dielectric strength, volume resistivity, surface resistivity, heat resistance, interface adhesion with the high-potential region at the chip edge, and interface stability after high-temperature aging. The locally reinforced insulating layer and the insulating package form a composite insulating interface, which is configured to extend the effective surface discharge path from the high-potential region at the chip edge to the external environment and / or adjacent electrodes and / or substrate conductors.

2. The high-voltage power chip packaging structure according to claim 1, characterized in that, The high-potential region at the edge of the chip includes at least a portion of the dicing region of the high-voltage power chip and / or at least a portion of the front terminal region of the high-voltage power chip and / or at least a portion of the edge passivation region of the high-voltage power chip and / or at least a portion of the first surface of the substrate.

3. The high-voltage power chip packaging structure according to claim 1, characterized in that, The locally reinforced insulating layer is distributed in a continuous or discontinuous ring along the edge of the high-voltage power chip; and / or, The locally reinforced insulating layer extends from the edge of the high-voltage power chip towards the inner and / or outer side of the chip, covering a predetermined width, wherein the predetermined width ranges from 50 μm to 50 mm; and / or, The locally reinforced insulating layer covers at least a portion of the edge region or non-electrically connected region of the surface electrodes of the high-voltage power chip; and / or, The high-voltage power chip is electrically connected to the substrate via bonding wires, and the locally reinforced insulating layer covers at least a portion of the surface surface of the surface electrode of the high-voltage power chip and / or at least a portion of the surface of the bonding wires; and / or, The total thickness of the locally reinforced insulating layer ranges from 10 nm to 1000 μm; and / or, The width of the locally reinforced insulating layer is greater than the width of the passivation layer within the edge passivation region of the high-voltage power chip; and / or, The locally reinforced insulation layer has a three-dimensional morphology selected from a group consisting of protruding structures, dam structures, slope structures, stepped structures, and combinations thereof; and / or, The locally reinforced insulating layer has a gradually decreasing thickness, which decreases from the high-potential region at the edge of the chip along the direction away from the high-voltage power chip.

4. The high-voltage power chip packaging structure according to claim 1, characterized in that, The material of the locally reinforced insulating layer is different from the material of the insulating encapsulation; and / or The material of the locally reinforced insulation layer is selected from one or more of the following: polyimide, epoxy insulation material, silicone-modified insulation material, composite insulation material containing inorganic filler, and ceramic particle-filled insulation material.

5. The high-voltage power chip packaging structure according to claim 1, characterized in that, The locally reinforced insulation layer is a single-layer insulation structure or a multi-layer composite insulation structure.

6. The high-voltage power chip packaging structure according to claim 5, characterized in that, The locally reinforced insulating layer is a multi-layer composite insulating structure, including an inner insulating layer and an outer insulating layer. The inner insulating layer is at least attached to the surface of the high-voltage power chip, and the outer insulating layer covers the inner insulating layer. The inner insulating layer has higher flexibility or adhesion than the outer insulating layer, and the outer insulating layer has higher dielectric strength than the inner insulating layer. Alternatively... The locally reinforced insulation layer is a multi-layer composite insulation structure, including an inner insulation layer, a transition layer, and an outer insulation layer. The inner insulation layer is attached to at least the surface of the high-voltage power chip. The transition layer covers the inner insulation layer, and the outer insulation layer covers the transition layer. The dielectric constant, elastic modulus, coefficient of thermal expansion, or filler content of different layers vary in gradient from the direction away from the high-voltage power chip.

7. The high-voltage power chip packaging structure according to claim 6, characterized in that, The inner insulating layer is made of polyimide, silicone-modified insulating material, or epoxy insulating material; the outer insulating layer is an inorganic dense insulating layer and / or a composite insulating layer containing inorganic fillers; wherein, the inorganic dense insulating layer is made of Al2O3, SiO2, or SiN. x One or more of Al2O3, AlN, BN, diamond, or diamond-like carbon film; the composite insulating layer containing inorganic fillers comprises a polymer matrix and Al2O3, AlN, BN, SiO2, and SiN dispersed in the polymer matrix. x One or more of diamond or diamond-like carbon particles.

8. A method for packaging a high-voltage power chip, characterized in that, include: A substrate is provided, the substrate having a first surface; A high-voltage power chip is provided, wherein the high-voltage power chip is disposed on a first surface of the substrate, the high-voltage power chip includes a surface electrode, and the edge of the high-voltage power chip has a chip edge high-potential region surrounding the surface electrode; A locally reinforced insulating layer is formed and cured on at least a portion of the surface of the high-potential region at the edge of the high-voltage power chip, wherein the surface of the locally reinforced insulating layer is non-planar; and An insulating package is formed that at least covers the high-voltage power chip and the localized reinforced insulating layer; The locally reinforced insulating layer has at least one of the following properties that are superior to the insulating package: dielectric strength, volume resistivity, surface resistivity, heat resistance, interface adhesion with the high-potential region at the chip edge, and interface stability after high-temperature aging. The locally reinforced insulating layer and the insulating package form a composite insulating interface, which is configured to extend the effective surface discharge path from the high-potential region at the chip edge to the external environment and / or adjacent electrodes and / or substrate conductors.

9. The high-voltage power chip packaging method according to claim 8, characterized in that, Forming the locally reinforced insulating layer includes: An insulating material is applied to the surface of the high-potential region at the edge of the chip using at least one of the following methods: deposition, coating, printing, dispensing, molding, or attachment; and / or, Multiple applications of insulating material and / or contour shaping are performed to form a locally reinforced insulating layer with a three-dimensional morphology; The localized reinforcing insulation layer is distributed continuously in a ring along the edge of the high-voltage power chip, or the localized reinforcing insulation layer is distributed discontinuously in a ring along the edge of the high-voltage power chip, forming multiple discontinuously arranged localized reinforcing insulation regions.

10. The high-voltage power chip packaging method according to claim 8, characterized in that, Before forming the localized reinforced insulating layer, the surface of the high-potential region at the edge of the chip is pretreated by cleaning, dehumidifying, or surface activation.

Images