Stacked passivation structure for oxide semiconductor transistor, transistor and method of manufacture
Patent Information
- Application Number
- CN202610765355.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-29
- Publication Date
- 2026-09-01
AI Technical Summary
氢在IGZO材料中扮演着双重角色：适量的氢可以填补氧空位，起到修复缺陷的作用；但过量的氢，尤其是以原子形态存在的氢，很容易作为浅施主（Shallow Donor）进入IGZO的禁带中，提供大量自由电子，导致IGZO材料的导电性异常增加，使其呈现出类金属特性，并引发严重的负向阈值电压漂移
[0017]根据本公开实施例，第一钝化层的沉积工艺采用原子层沉积工艺、低功率等离子体增强化学气相沉积工艺或低氢高绝缘工艺；第二钝化层的沉积工艺采用物理气相沉积、原子层沉积或金属蒸发工艺；第三钝化层的沉积工艺采用等离子体增强化学气相沉积工艺或原子层沉积工艺。
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Abstract
Description
Technical Field
[0001] This disclosure relates to the fields of integrated circuits and semiconductor technology, and in particular to a stacked passivation structure for oxide semiconductor transistors, the transistor, and a method for fabrication thereof. Background Technology
[0002] In recent years, metal oxide semiconductor materials, represented by amorphous IGZO (indium gallium zinc oxide), have become the core driving technology in the flat panel display field, especially in large-size OLED TVs with high resolution and high refresh rate, and mobile terminal displays that require low power consumption, thanks to their outstanding advantages such as high electron mobility (more than 10 times higher than amorphous silicon), low off-state leakage current, excellent uniformity, and low-temperature process compatibility.
[0003] Typical IGZO thin-film transistors typically employ back channel etching (BCE) or etch stop layer (ESL) structures. Regardless of the structure, the top IGZO active layer (i.e., the back channel) is directly or indirectly exposed to the external environment. The electrical properties of oxide semiconductor materials like IGZO are extremely sensitive to the chemical state and physical environment of their surface. During device manufacturing and long-term use, if the back channel lacks effective protection, it is highly susceptible to chemical etching damage and physical bombardment during subsequent processes (such as metal wiring and planarization layer deposition), or reactions with reactive substances such as water and oxygen in the air. This can lead to the generation or exposure of a large number of defect states (such as oxygen vacancies) within the device, causing problems such as threshold voltage (Vth) drift, increased subthreshold swing (SS), and decreased on / off ratio, severely affecting the stability and reliability of the device.
[0004] To address the aforementioned issues, depositing one or more passivation layers on the IGZO active layer is currently the mainstream technical solution. The main functions of the passivation layer are: 1) physical isolation, protecting the IGZO back channel from damage during subsequent processes; and 2) chemical inertization, preventing water, oxygen, and other substances from the environment from penetrating the active layer. Currently, the industry commonly uses plasma-enhanced chemical vapor deposition (PECVD) technology to deposit silicon dioxide (SiO2) or silicon nitride (SiN). x ) as a passivation layer.
[0005] However, traditional PECVD processes deposit SiO2 or SiN xIn thin film deposition, reaction precursors containing a large amount of hydrogen (H) are typically used (such as silane SiH4 and ammonia NH3). This inevitably results in a high concentration of hydrogen atoms or hydrogen-containing groups remaining in the deposited film. Hydrogen plays a dual role in IGZO materials: an appropriate amount of hydrogen can fill oxygen vacancies and repair defects; however, excessive hydrogen, especially hydrogen in atomic form, can easily enter the band gap of IGZO as a shallow donor, providing a large number of free electrons. This leads to an abnormal increase in the conductivity of IGZO materials, giving them metal-like properties and causing a severe negative threshold voltage drift.
[0006] Under subsequent heat treatment or long-term electrical stress, hydrogen in the passivation layer will further diffuse into the IGZO active layer, continuously deteriorating the transistor's electrical performance and becoming a key bottleneck restricting the long-term reliability of the device. Although some studies have proposed using dense atomic layer deposition (ALD) alumina (Al2O3) as a passivation layer, its excellent density can effectively block water and oxygen, but a single ALD film cannot meet all requirements in terms of thickness, stress control, and production cost, and it does not fundamentally solve the problem of the upper layer (such as the subsequent thick SiN layer). x The problem of hydrogen diffusion downwards in the process.
[0007] Therefore, developing a passivation technology that can provide excellent interface quality and physicochemical protection for the IGZO back channel while effectively preventing hydrogen generated in subsequent processes from penetrating into the IGZO active layer has become an urgent need to improve the stability and reliability of high-performance oxide semiconductor transistors. Summary of the Invention
[0008] In view of the above, in order to at least partially solve at least one of the aforementioned technical problems, this disclosure provides a stacked passivation structure for oxide semiconductor transistors, a transistor, and a fabrication method, aiming to improve the electrical stability and environmental reliability of the device. The first passivation layer ensures an excellent interface with the semiconductor layer, the second passivation layer precisely addresses the critical issue of hydrogen permeation, and the third passivation layer meets the process integration requirements in actual production. The transistor employing the stacked passivation structure of this invention can significantly suppress threshold voltage drift caused by hydrogen diffusion and enhance stability under combined pressures such as bias voltage, temperature, humidity, and light exposure, thereby greatly improving the overall performance, reliability, and lifespan of the device. The technical solution is as follows:
[0009] According to one aspect of the present disclosure, a stacked passivation structure for an oxide semiconductor transistor is provided, disposed on the active layer of the transistor. The stacked passivation structure comprises, from bottom to top: a first passivation layer, covering the active layer, which is a low-hydrogen and highly insulating thin film material; a second passivation layer, disposed on the first passivation layer, for blocking hydrogen atom penetration; and a third passivation layer, disposed on the second passivation layer, for overall electrical insulation.
[0010] According to embodiments of this disclosure, the first passivation layer comprises a single-layer film structure or a multi-layer film structure; the material used to prepare the film structure of the first passivation layer is selected from at least one of silicon oxide, aluminum oxide, hafnium oxide, and silicon oxynitride; the hydrogen content of the first passivation layer is less than 10%. 19 cm -3 .
[0011] According to embodiments of this disclosure, the second passivation layer is a single-layer or multi-layer film structure; the material used to prepare the film structure of the second passivation layer is selected from at least one of titanium, aluminum, tantalum, molybdenum, tungsten, titanium nitride, aluminum oxide, and tantalum nitride; the material used to prepare the film structure of the second passivation layer can block or absorb hydrogen, serving as a hydrogen barrier layer to effectively prevent hydrogen atoms from diffusing downwards and entering the active layer.
[0012] According to embodiments of this disclosure, the third passivation layer is a single-layer film structure or a multi-layer film structure; the material used to prepare the film structure of the third passivation layer is selected from at least one of silicon oxide and silicon nitride.
[0013] According to embodiments of this disclosure, the active layer is an amorphous or crystalline oxide semiconductor.
[0014] According to embodiments of this disclosure, the active layer is indium gallium zinc oxide (IGZO) or indium tin zinc oxide (IZO).
[0015] According to another embodiment of this disclosure, an oxide semiconductor thin film transistor is provided, comprising: a substrate; a gate layer disposed on the substrate; a gate insulating layer disposed on the gate layer; an active layer disposed on the gate insulating layer, wherein an active electrode and a drain electrode are respectively disposed on both sides of the surface of the active layer; and the aforementioned stacked passivation structure disposed on the active layer, wherein the lower part of the first passivation layer is in contact with the upper surface of the active layer.
[0016] According to another aspect of this disclosure, a method for fabricating the aforementioned oxide semiconductor thin-film transistor is also provided, comprising: depositing a low-hydrogen and high-insulation material on the active layer of the transistor to form a first passivation layer; depositing a hydrogen-blocking or hydrogen-absorbing material on the first passivation layer to form a second passivation layer; and depositing an insulating material on the second passivation layer to form a third passivation layer.
[0017] According to embodiments of this disclosure, the deposition process of the first passivation layer is atomic layer deposition, low-power plasma-enhanced chemical vapor deposition, or low-hydrogen high-insulation process; the deposition process of the second passivation layer is physical vapor deposition, atomic layer deposition, or metal evaporation process; and the deposition process of the third passivation layer is plasma-enhanced chemical vapor deposition or atomic layer deposition. Attached Figure Description
[0018] The objects, features, and advantages of this disclosure will become clearer from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:
[0019] Figure 1 This is a schematic diagram of an oxide semiconductor transistor and its stacked passivation structure according to an embodiment of the present disclosure.
[0020] Figure 2 This is a schematic diagram comparing the performance of a transistor with a stacked passivation structure and a transistor with a conventional passivation structure according to an embodiment of this disclosure.
[0021] Figure 3 This is a schematic diagram comparing the SIMS characterization of a transistor with a stacked passivation structure and a transistor with a conventional passivation structure according to an embodiment of this disclosure. Detailed Implementation
[0022] This disclosure provides a stacked passivation structure for oxide semiconductor transistors, a transistor, and a fabrication method, primarily aimed at overcoming the defects of existing thin-film transistor passivation structures. Specifically, conventional passivation layer structures (such as those deposited using a single PECVD process with SiO2 or SiN) x During deposition, a large amount of hydrogen (H) is introduced. In subsequent thermal processes or under electrical stress, these hydrogen atoms diffuse into the active layer, acting as shallow donors. This causes a severe negative drift in the transistor threshold voltage and reduces the overall stability of the device. Therefore, the technical problem to be solved by this invention is to provide a novel layered passivation structure for oxide semiconductor transistors and its manufacturing method. This passivation structure is sequentially stacked on the active layer of the transistor, effectively blocking the diffusion of hydrogen atoms from the upper film layer or subsequent processes into the active layer, while ensuring excellent interface quality between the passivation layer and the back channel of the active layer, thereby significantly improving the electrical stability and environmental reliability of the transistor.
[0023] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.
[0024] In this disclosure, a stacked passivation structure for oxide semiconductor transistors is provided, such as... Figure 1As shown, the stacked passivation structure is disposed on the active layer 3 of the transistor, and the stacked passivation structure includes, from bottom to top:
[0025] The first passivation layer 5 is coated on the active layer and is a thin film material with low hydrogen content and high insulation.
[0026] The second passivation layer 6 is disposed on top of the first passivation layer to block the penetration of hydrogen atoms;
[0027] The third passivation layer 7 is disposed on top of the second passivation layer and is used for electrical insulation of the main body.
[0028] According to embodiments of this disclosure, the first passivation layer comprises a single-layer film structure or a multilayer film structure formed by alternating stacks; the material for preparing the film structure of the first passivation layer 5 is selected from silicon oxide (SiO2). x The first passivation layer contains at least one of aluminum oxide (Al2O3), hafnium oxide (HfO2), and silicon oxynitride (SiON); the hydrogen content of the first passivation layer is less than 10%. 19 cm -3 Regarding insulation, the breakdown field strength is above 5kV / mm. The first passivation layer 5, also known as the interface stabilization layer, is directly deposited and contacts the back channel surface of the active layer. Its main function is to provide a chemically inert interface with low defect state density for the active layer (e.g., an IGZO active layer), repair and protect the back channel surface of the active layer from plasma damage during subsequent processes, and prevent the passivation layer structure itself from introducing hydrogen impurities into the active layer. The first passivation layer 5, the second passivation layer 6, and the second passivation layer 7 together constitute a sandwich stacked passivation structure.
[0029] According to embodiments of this disclosure, the second passivation layer 6 is a single-layer or multi-layer film structure. The material used to prepare the film structure of the second passivation layer is selected from at least one of titanium (Ti), aluminum (Al), tantalum (Ta), molybdenum (Mo), tungsten (W), titanium nitride (TiN), aluminum oxide (Al2O3), and tantalum nitride (TaN), for example, a single-layer or alternatingly stacked multi-layer film structure. The material used to prepare the film structure of the second passivation layer can block or absorb hydrogen, acting as a hydrogen barrier layer to effectively prevent hydrogen atoms from diffusing downwards and entering the active layer. The function of the second passivation layer 6 is to act as a core barrier, actively intercepting hydrogen atoms generated and diffusing downwards from the third passivation layer 7 above it or subsequent processes (such as metal wiring, planarization layer deposition), preventing them from penetrating and reaching the first passivation layer 5 and the active layer below.
[0030] According to embodiments of this disclosure, the third passivation layer is a single-layer film structure or a multilayer film structure formed by alternating stacks; the material used to prepare the film structure of the third passivation layer is selected from silicon oxide (SiO2). x ) and silicon nitride (SiN) xAt least one of the following. The third passivation layer 7, as the main insulating layer, is deposited on top of the second passivation layer 6. Its main functions are to provide the main electrical insulation performance, excellent step coverage, mechanical protection and planarization function required by transistor devices, so as to facilitate subsequent complex integration processes such as multilayer metal wiring.
[0031] According to embodiments of this disclosure, the active layer is an amorphous or crystalline oxide semiconductor; for example, the active layer is indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO) or other oxide semiconductors.
[0032] Another embodiment of this disclosure provides an oxide semiconductor thin-film transistor, such as Figure 1 As shown, the oxide semiconductor thin-film transistor includes:
[0033] Substrate (not shown in the figure);
[0034] Gate layer 1 is disposed on the substrate and serves as the bottom gate;
[0035] Gate insulating layer 2 is disposed on the gate layer;
[0036] An active layer 3 is disposed on the gate insulating layer 2, and an active electrode 4-1 and a drain electrode 4-2 are respectively disposed on both sides of the surface of the active layer 2;
[0037] A stacked passivation structure is disposed on the active layer 3, wherein the lower part of the first passivation layer 6 is in contact with the upper surface of the active layer 3.
[0038] According to another embodiment of this disclosure, a method for fabricating the above-mentioned oxide semiconductor thin-film transistor is also provided, comprising:
[0039] S1: A first passivation layer is formed by depositing a low-hydrogen and high-insulation material on the active layer of the transistor.
[0040] S2: Deposit a hydrogen blocking or hydrogen absorbing material on the first passivation layer to form a second passivation layer; and
[0041] S3: Deposit insulating material on the second passivation layer to form the third passivation layer 7.
[0042] Specifically, the deposition process of the first passivation layer adopts atomic layer deposition, low-power plasma-enhanced chemical vapor deposition, or low-hydrogen high-insulation process; the deposition process of the second passivation layer adopts physical vapor deposition, atomic layer deposition, or metal evaporation process; and the deposition process of the third passivation layer adopts plasma-enhanced chemical vapor deposition or atomic layer deposition.
[0043] Preferably, the first passivation layer 5 can be silicon oxide (SiO2) prepared by atomic layer deposition (ALD) or low-power PECVD process. xThe first passivation layer 6 is composed of aluminum oxide (Al2O3), hafnium oxide (HfO2), or silicon oxynitride (SiON), and is relatively thin, for example, 5 to 50 nanometers. The second passivation layer 6 can be composed of metallic materials prepared by physical vapor deposition (PVD) or ALD processes, such as titanium (Ti), aluminum (Al), tantalum (Ta), molybdenum (Mo), tungsten (W), or their compounds, such as aluminum oxide (Al2O3), titanium nitride (TiN), tantalum nitride (TaN), etc. This layer has high density or high hydrogen adsorption capacity. The third passivation layer 7 can be composed of silicon oxide (SiO2) prepared by conventional PECVD processes. x Silicon nitride (SiN) x It consists of alternating stacked film layers, or films with a thickness of 100 to 500 nanometers.
[0044] More specifically, including:
[0045] Provide the substrate and gate layer: On a clean glass substrate, a 100-nanometer (nm) thick molybdenum (Mo) metal layer is deposited by physical vapor deposition (PVD, such as sputtering), and then patterned by photolithography and etching processes to form the gate electrode.
[0046] Deposition of the gate insulator and active layer: A plasma-enhanced chemical vapor deposition (PECVD) method is used to continuously deposit a gate insulator and an active layer on the substrate and gate electrode. Preferably, the gate insulator is a 150 nm thick silicon nitride (SiN) layer. x The stacked structure consists of a 50 nm thick silicon oxide (SiO2) layer and a 50 nm thick silicon oxide (SiO2) layer. Subsequently, a 40 nm thick indium gallium zinc oxide (IGZO) semiconductor layer is deposited on the gate insulating layer by sputtering.
[0047] Formation of the Etch Barrier Layer (ESL) and Source / Drain Electrodes: A 100 nm thick silicon oxide (SiO2) layer is deposited on the IGZO semiconductor layer via PECVD as the etch barrier layer (ESL). The ESL is then patterned using photolithography and etching processes to cover the channel region of the IGZO. Next, a 40 nm thick ITO source / drain layer is deposited by sputtering and patterned to form the source and drain electrodes. During this etching step, the underlying ESL protects the IGZO channel region from damage by the etchant.
[0048] Annealing: Place the above semi-finished device in an oven or annealing furnace and perform heat treatment (Annealing) at a temperature of 250°C to 350°C for 2 hours. This step aims to repair the damage to the IGZO active layer caused during sputtering and etching, stabilize the electrical properties of the IGZO material, and improve the ohmic contact between the source / drain metal and the active layer.
[0049] Deposited stacked passivation structure: Sequentially deposited layers on an annealed device:
[0050] The first passivation layer 5, consisting of 20 nm thick aluminum oxide (Al2O3), is deposited over the entire device structure (including the source / drain electrodes and ESL) at a low temperature of 200°C using atomic layer deposition (ALD) technology. ALD technology offers excellent conformality and compactness with extremely low plasma damage. This Al2O3 layer, serving as the first passivation layer 5, has an extremely low hydrogen content and directly covers the back channel (ESL) of the IGZO and both sides of the source / drain metals, providing excellent interface passivation and initial protection for the IGZO.
[0051] Second Passivation Layer 6: A 10 nm thick layer of metallic titanium (Ti) is deposited on top of the first passivation layer 5 (Al2O3) using PVD (sputtering). Metallic Ti is a recognized hydrogen absorber (H-getter) and diffusion barrier layer. The core function of this layer (2. Second Passivation Layer (H-Blocking Layer)) is to capture and block hydrogen atoms from above, preventing them from penetrating downwards.
[0052] Third passivation layer 7: On top of the second passivation layer 6 (Ti), a 300 nm thick silicon nitride (SiN) layer is deposited at 300°C using a conventional PECVD process. x The PECVD process for SiN x The first layer (thick film, high dielectric constant insulator) has a high hydrogen content, releasing a large number of hydrogen atoms (H) during deposition. However, due to the presence of the second passivation layer 6 (Ti), these hydrogen atoms are effectively blocked or absorbed as they diffuse downwards, unable to penetrate the Ti and Al2O3 layers, and thus unable to reach the bottom IGZO semiconductor layer. Subsequent processes: The third, second, and first passivation layers 5 are sequentially etched through using photolithography and dry etching to open the contact vias, exposing the pads for the source and drain electrodes. Finally, a layer of transparent conductive oxide (such as ITO) is sputtered and patterned, connecting it to the source / drain electrodes through the contact vias to form pixel electrodes or test electrodes.
[0053] This disclosure also verifies the beneficial effects of the present invention through comparative tests, demonstrating the fabrication of transistor devices with conventional passivation structures, i.e., directly depositing a 300 nm thick PECVD SiN layer on the device after annealing. x The layer serves as the sole passivation layer. Stability testing and results were performed on the TFT devices of Example 1 and the comparative example using positive bias stress (PBS) and negative bias stress (PBS) tests, as follows: Figure 2 As shown, at room temperature, a threshold voltage V is applied to the gate of two transistor devices with different passivation structures. th A constant voltage of 4V was applied, with the source and drain grounded, for 2000 seconds. The test results showed that during the PBS test, the offset ΔV... th Optimized from 0.31V to 0.002V, during NBS testing, the offset ΔV th Optimized from -0.04V to -0.001V; it can be seen that transistor devices with ordinary passivation structures, due to PECVD SiN x A large number of hydrogen atoms diffuse into the active layer channel of IGZO under the influence of electric field and heat, acting as shallow donors, leading to a higher threshold voltage V. th This resulted in a significant positive drift. However, in the transistor device with the stacked passivation structure disclosed herein, the second passivation layer 6 (Ti layer) effectively blocks hydrogen diffusion, and the first passivation layer 5 (ALD Al2O3) provides a stable interface, resulting in a threshold voltage V. th The drift was successfully suppressed to within 2mV. Experimental results demonstrate that the stacked passivation structure of this invention, by introducing a low-hydrogen interface layer and a hydrogen barrier layer, successfully solves the hydrogen-induced stability problem caused by traditional passivation layers, significantly improving the reliability of IGZO transistors. This disclosure also performs SIMS characterization on transistor devices with ordinary passivation structures and transistor devices with the stacked passivation structure of this disclosure at room temperature, such as... Figure 3 As shown, the left part presents the SIMS characterization results of the transistor device using the sandwich stacked passivation structure of this disclosure, while the right part presents the SIMS characterization results of the transistor device using a conventional passivation structure. Experimental results demonstrate that, compared to transistor devices with conventional passivation structures, the stacked passivation structure transistor device of this disclosure reduces the hydrogen (H) concentration in the IGZO active layer by two orders of magnitude, effectively reducing the impact of hydrogen (H) on the reliability of the active layer. Simultaneously, indium (In) does not exhibit significant diffusion due to the stacked passivation structure.
[0054] This disclosure also provides an application of the above-described oxide semiconductor thin-film transistor in a storage logic driving circuit or a display panel circuit unit.
[0055] Compared with the prior art, the beneficial effects of the stacked passivation structure for oxide semiconductor transistors, the transistor, and the fabrication method of the present invention include at least the following:
[0056] Excellent hydrogen barrier capability: By introducing a dedicated second passivation layer 6 (hydrogen barrier layer), this invention can effectively block subsequent high hydrogen content processes (such as PECVD SiN). x This addresses the downward diffusion path of hydrogen atoms generated in the IGZO channel. This fundamentally solves the problem of hydrogen impurities acting as shallow donors invading the IGZO channel, significantly suppressing the resulting negative threshold voltage drift.
[0057] High-quality interface characteristics: The first passivation layer 5 uses a thin film, low-hydrogen, high-quality insulating material (such as ALDAl2O3) to ensure the formation of an excellent interface with low defect density between it and the IGZO back channel, avoiding damage to the channel surface by high-energy plasma, which is beneficial to improving the subthreshold swing (SS) and mobility of the device.
[0058] High reliability and stability: Since hydrogen-induced defects and interface defects are effectively controlled, the IGZO transistor with the passivation structure of this invention exhibits extremely high stability when subjected to long-term combined stress tests such as bias voltage-temperature-light illumination, and the reliability and service life of the device are greatly improved.
[0059] Excellent process compatibility: The structure of this invention is ingeniously designed. The second layer (hydrogen barrier layer) protects the first layer and the active layer, allowing the third layer (main insulating layer) to continue using the standard PECVD process, which is low-cost, has a fast deposition rate, and is highly compatible with subsequent processes, without worrying about the negative impact of its high hydrogen content. This balances the production requirements of high performance and low cost.
[0060] In summary, this disclosure breaks through the conventional IGZO transistor passivation structure, optimizes the interface, reduces defects, and the first low-hydrogen insulating layer protects the IGZO channel, reduces interface defect states, and improves the device's switching characteristics. The second hydrogen-blocking layer efficiently blocks hydrogen, suppresses drift, and significantly suppresses the threshold voltage Vth caused by hydrogen diffusion during subsequent processes and testing. th Drift ensures electrical stability; process compatibility improves reliability, allows the use of standard PECVD thick films on the upper layer, and significantly enhances the overall stability of the device under bias, temperature, and light.
[0061] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. It should be noted that implementations not illustrated or described in the drawings or the main text of the specification are forms known to those skilled in the art and have not been described in detail. It should be understood that the above are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
Claims
1. A stacked passivation structure for an oxide semiconductor transistor, disposed on the active layer of the transistor, the stacked passivation structure comprising, from bottom to top: The first passivation layer, covering the active layer, is a thin film material with low hydrogen content and high insulation. The second passivation layer is disposed on top of the first passivation layer to block the penetration of hydrogen atoms; A third passivation layer is disposed on top of the second passivation layer and is used for electrical insulation of the main body.
2. The stacked passivation structure according to claim 1, wherein the first passivation layer comprises a single-layer film structure or a multi-layer film structure; the material for preparing the film structure of the first passivation layer is selected from at least one of silicon oxide, aluminum oxide, hafnium oxide, and silicon oxynitride; and the hydrogen content of the first passivation layer is less than 10%. 19 cm -3 .
3. The stacked passivation structure according to claim 1, wherein the second passivation layer is a single-layer film structure or a multi-layer film structure; the material for preparing the film structure of the second passivation layer is selected from at least one of titanium, aluminum, tantalum, molybdenum, tungsten, titanium nitride, aluminum oxide and tantalum nitride; the material for preparing the film structure of the second passivation layer can block or absorb hydrogen, and serve as a hydrogen blocking layer to effectively prevent hydrogen atoms from diffusing downward and entering the active layer.
4. The stacked passivation structure according to claim 1, wherein the third passivation layer is a single-layer film structure or a multi-layer film structure; the material for preparing the film structure of the third passivation layer is selected from at least one of silicon oxide and silicon nitride.
5. The stacked passivation structure according to claim 1, wherein the active layer is an amorphous or crystalline oxide semiconductor.
6. The stacked passivation structure according to claim 1, wherein the active layer is indium gallium zinc oxide (IGZO) or indium tin zinc oxide (IZO).
7. An oxide semiconductor thin-film transistor, comprising: Base; A gate layer is disposed on the substrate; A gate insulating layer is disposed on the gate layer; An active layer is disposed on the gate insulating layer, and an active electrode and a drain electrode are respectively disposed on both sides of the surface of the active layer; The stacked passivation structure according to any one of claims 1-6 is disposed on the active layer, wherein the lower part of the first passivation layer is in contact with the upper surface of the active layer.
8. A method for fabricating an oxide semiconductor thin-film transistor according to claim 7, comprising: A low-hydrogen, high-insulation material is deposited on the active layer of the transistor to form the first passivation layer; A second passivation layer is formed by depositing a hydrogen blocking or hydrogen absorbing material on the first passivation layer; as well as An insulating material is deposited on the second passivation layer to form a third passivation layer 7.
9. The preparation method according to claim 8, wherein: The deposition process of the first passivation layer is atomic layer deposition, low-power plasma-enhanced chemical vapor deposition, or low-hydrogen high-insulation process. The deposition process for the second passivation layer employs physical vapor deposition, atomic layer deposition, or metal evaporation. The deposition process of the third passivation layer adopts either plasma-enhanced chemical vapor deposition or atomic layer deposition.
10. The application of the oxide semiconductor thin-film transistor of claim 7 in a storage logic driving circuit or a display panel circuit unit.