Method for manufacturing semiconductor structure, semiconductor structure and micro-bump

Abstract

The present disclosure relates to a semiconductor structure manufacturing method, a semiconductor structure and a micro bump, and belongs to the technical field of semiconductor technology. The manufacturing method comprises: a high-temperature solder layer and a low-temperature solder layer are arranged between a first pad and a second pad, the high-temperature solder layer is in contact with the first pad and / or the second pad, and the melting point of the low-temperature solder layer is lower than that of the high-temperature solder layer; a first bonding process is performed at a bonding temperature between the melting points of the low-temperature solder layer and the high-temperature solder layer, the low-temperature solder layer is converted into a first connecting part, the first pad and the second pad are connected, and the melting point of the first connecting part is higher than that of the high-temperature solder layer; and a second bonding process is performed at a bonding temperature between the melting points of the high-temperature solder layer and the first connecting part, the high-temperature solder layer is converted into a second connecting part and forms a connecting structure with the first connecting part, and the connecting structure connects the first pad and the second pad. In the two bonding processes, there are spacing control structures to prevent bridging caused by too small spacing.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure, a semiconductor structure, and microbumps. Background Technology

[0002] In the field of semiconductor packaging technology, hot-press bonding of solder balls is commonly used for chip stacking. However, due to uneven solder ball height and chip warping, if the pressing distance is too small during hot-press bonding, some solder balls may not be able to connect with their corresponding pads. If the pressing distance is sufficient to connect all solder balls with their corresponding pads, some molten solder balls may be over-pressed, causing solder to overflow laterally and resulting in short circuits between adjacent solder balls. This also leads to excessively small local spacing between the two chips, affecting the uniformity of the filler and severely restricting the reliability and yield of the stacked structure. Summary of the Invention

[0003] To overcome the problems existing in the related technologies, this disclosure provides a method for fabricating a semiconductor structure, a semiconductor structure, and microbumps.

[0004] According to a first aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, the method comprising: A first semiconductor device and a second semiconductor device to be bonded are provided, and the first semiconductor device and the second semiconductor device are stacked with their bonding surfaces facing each other. The bonding surface of the first semiconductor device is provided with a first pad, and the bonding surface of the second semiconductor device is provided with a second pad opposite to the first pad. At least one high-temperature solder layer and at least one low-temperature solder layer are included between the first pad and the second pad, and the high-temperature solder layer is in contact with the first pad and / or the second pad. The melting point of the low-temperature solder layer is lower than the melting point of the high-temperature solder layer. The first semiconductor device and the second semiconductor device are subjected to a first bonding process. The bonding temperature of the first bonding process is between the melting points of the low-temperature solder layer and the high-temperature solder layer. The low-temperature solder layer is transformed into a first connection part. The first pad and the second pad are connected. The melting point of the first connection part is greater than the melting point of the high-temperature solder layer. The first connection part is an alloy. Under conditions where no bonding pressure is applied, the first semiconductor device and the second semiconductor device are subjected to a second bonding process. The bonding temperature of the second bonding process is between the melting point of the high-temperature solder layer and the melting point of the first connection portion. The high-temperature solder layer is transformed into a second connection portion and together with the first connection portion forms a connection structure. The connection structure connects the first pad and the second pad.

[0005] In some embodiments of this disclosure, the material of the low-temperature solder layer includes a physically composite first metal material and a second metal material, wherein the melting point of the second metal material is lower than the melting point of the high-temperature solder layer, and the melting point of the first metal material is higher than the melting point of the first connection portion.

[0006] In some embodiments of this disclosure, the low-temperature solder layer includes a first metal material layer and a second metal material layer alternately disposed in the stacking direction of the first semiconductor device and the second semiconductor device.

[0007] In some embodiments of this disclosure, the heights of adjacent first metal material layers and second metal material layers are equal in the stacking direction of the first semiconductor device and the second semiconductor device.

[0008] In some embodiments of this disclosure, the low-temperature solder layer comprises a mixed powder layer formed by physically mixing the powder of the first metal material and the powder of the second metal material.

[0009] In some embodiments of this disclosure, the first metal material includes at least one of copper, tungsten, or gold, the second metal material includes at least one of tin or indium, and the material of the high-temperature solder layer includes at least one of tin-lead alloy, tin-antimony alloy, indium-lead alloy, or indium-antimony alloy.

[0010] In some embodiments of this disclosure, when the high-temperature solder layer is provided on one of the first pads and the second pads, the outer contours of the projections of the first pads and the second pads on the first plane surround the outer side of the projection of the high-temperature solder layer on the first plane. In the first bonding process step, the high-temperature solder layer contacts the first pads and the second pads, the first connecting portion surrounds the outer side of the high-temperature solder layer, and the first connecting portion contacts and connects with the first pads and the second pads. or, When the first pad and the second pad are respectively provided with the high-temperature solder layer, the outer contour of the projection of the first pad and the second pad on the first plane surrounds the outside of the projection of the high-temperature solder layer on the first plane. Then, in the first bonding process step: the high-temperature solder layer on the first pad and the high-temperature solder layer on the second pad are in contact, the first connecting part surrounds the outside of the two high-temperature solder layers, and the first connecting part is in contact with and connected to the first pad and the second pad. The first plane is parallel to the first pad.

[0011] In some embodiments of this disclosure, in the projection parallel to the first plane of the first pad, the outer contours of the projections of the first pad and the second pad are both surrounding the outside of the projection of the high-temperature solder layer, the outer contours of the projections of the first pad are surrounding the outside of the projection of the low-temperature solder layer, or the projection of the first pad coincides with the projection of the low-temperature solder layer, the outer contours of the projections of the second pad are surrounding the outside of the projection of the low-temperature solder layer, or the projection of the second pad coincides with the projection of the low-temperature solder layer, and in the first bonding process step: the two ends of the first connecting portion are in contact with the first pad and the second pad respectively; or, In the projection of the first plane parallel to the first pad, the projection of the first pad and the projection of the second pad are both equal to the projection of the high-temperature solder layer. The outer contour of the projection of the first pad surrounds the outside of the projection of the low-temperature solder layer, or the projection of the first pad coincides with the projection of the low-temperature solder layer. The outer contour of the projection of the second pad surrounds the outside of the projection of the low-temperature solder layer, or the projection of the second pad coincides with the projection of the low-temperature solder layer. In the first bonding process step: at most one end of the first connection portion contacts one of the first pad and the second pad.

[0012] In some embodiments of this disclosure, both the first pad and the second pad are provided with the high-temperature solder layer, and at least one of the first pad and the second pad is provided with the low-temperature solder layer on the high-temperature solder layer; or, The high-temperature solder layer is provided on one of the first pad and the second pad, and the low-temperature solder layer is provided on the other of the first pad and the second pad and / or on the high-temperature solder layer.

[0013] In some embodiments of this disclosure, after forming the connection structure, the method for fabricating the semiconductor structure further includes: An adhesive layer is filled between the first semiconductor device and the second semiconductor device.

[0014] In some embodiments of this disclosure, after forming the first connection portion and before performing the second bonding process, the method for fabricating the semiconductor structure further includes: An adhesive layer is filled between the first semiconductor device and the second semiconductor device.

[0015] According to a second aspect of the present disclosure, a semiconductor structure is provided, the semiconductor structure being fabricated using the semiconductor structure fabrication method of the first aspect, the semiconductor structure comprising: A first semiconductor device, wherein a first pad is provided on the bonding surface of the first semiconductor device; The second semiconductor device is stacked with the first semiconductor device with their bonding surfaces facing each other, and the bonding surface of the second semiconductor device is provided with a second pad that is opposite to the first pad. A connection structure is provided between the first pad and the second pad. The connection structure includes a first connection part and a second connection part connected together, wherein the melting point of the first connection part is greater than the melting point of the second connection part.

[0016] In some embodiments of this disclosure, the first connecting part is an alloy, the alloy including a first metal material and a second metal material; the first metal material includes at least one of copper, tungsten or gold, the second metal material includes at least one of tin or indium, and the material of the second connecting part includes at least one of tin-lead alloy, tin-antimony alloy, indium-lead alloy or indium-antimony alloy.

[0017] In some embodiments of this disclosure, the first connecting portion surrounds the outside of the second connecting portion, and the two ends of the first connecting portion are respectively in contact with the first pad and the second pad; The two ends of the second connection portion are respectively in contact with the first pad and the second pad; or, the second connection portion has at least one, one end of each second connection portion is in contact with the first connection portion, and the other end of each second connection portion is connected to the first pad or the second pad.

[0018] In some embodiments of this disclosure, the first connecting portion and the second connecting portion are sequentially connected in the stacking direction of the first semiconductor device and the second semiconductor device; Alternatively, along the stacking direction of the first semiconductor device and the second semiconductor device, the first connection portion is connected between two second connection portions, and the two second connection portions are respectively in contact with the first pad and the second pad.

[0019] According to a third aspect of the present disclosure, a microbump is provided, the microbump being formed on a semiconductor device, the microbump comprising: A high-temperature solder layer is disposed on the pads of the semiconductor device; A low-temperature solder layer is disposed on the high-temperature solder layer and is located on the side of the high-temperature solder layer away from the solder pad. The melting point of the low-temperature solder layer is lower than that of the high-temperature solder layer. The low-temperature solder layer is used to melt and solidify to form an alloy. The melting point of the alloy is higher than that of the high-temperature solder layer.

[0020] In some embodiments of this disclosure, the material of the low-temperature solder layer includes a physically composite first metal material and a second metal material, wherein the melting point of the second metal material is lower than the melting point of the high-temperature solder layer, and the melting point of the first metal material is higher than the melting point of the alloy. The first metal material includes at least one of copper, tungsten, or gold; the second metal material includes at least one of tin or indium; and the material of the high-temperature solder layer includes at least one of tin-lead alloy, tin-antimony alloy, indium-lead alloy, or indium-antimony alloy.

[0021] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: By setting a high-temperature solder layer and a low-temperature solder layer between relatively opposite first and second pads, with the high-temperature solder layer in contact with the first and / or second pads, and the low-temperature solder layer having a lower melting point than the high-temperature solder layer; in the first bonding process, the low-temperature solder layer melts to achieve a preliminary connection between the first and second pads, and the molten low-temperature solder layer solidifies to form a first connection portion, while the high-melting-point high-temperature solder layer does not melt and plays a role in spacing control, ensuring that there is at least a spacing between the first semiconductor device and the second semiconductor device corresponding to the thickness of the high-temperature solder layer; and in the second bonding process, the high-temperature solder layer melts and connects with the first connection portion. Since the melting point of the first connection portion is higher than that of the high-temperature solder layer, the first connection portion does not melt and plays a role in spacing control, ensuring that there is at least a spacing between the first semiconductor device and the second semiconductor device corresponding to the thickness of the first connection portion. Spacing; Thus, a spacing control structure exists in both bonding processes to ensure a certain spacing between the first and second semiconductor components. This effectively avoids the problem of insufficient spacing between the first and second semiconductor components caused by the height difference between the high-temperature solder layer and the low-temperature solder layer or by warping of the first and second semiconductor components. This prevents bridging caused by excessive solder compression due to insufficient spacing and connection failure caused by uneven glue filling, significantly improving connection quality. Furthermore, in the second bonding process, no bonding pressure is applied to the first and second semiconductor components. This prevents the molten high-temperature solder layer from being excessively squeezed and overflowing laterally under bonding pressure, preventing bridging and short circuits at adjacent connection positions. It also allows the assembly stress between the first and second semiconductor components to be released, preventing warping of the stacked structure after bonding.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0024] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment; Figure 2 This is a schematic diagram of the structure after a high-temperature solder layer and a low-temperature solder layer are formed on a first semiconductor device according to an exemplary embodiment; Figure 3 This is a schematic diagram of the structure after a low-temperature solder layer is formed on a second semiconductor device according to an exemplary embodiment; Figure 4 This is a schematic diagram of the structure after a high-temperature solder layer is formed on a first semiconductor device according to an exemplary embodiment; Figure 5 This is a schematic diagram of a structure in which a first semiconductor device and a second semiconductor device are stacked according to an exemplary embodiment; Figure 6 This is a schematic diagram of the structure of a first semiconductor device and a second semiconductor device after a first bonding process according to an exemplary embodiment; Figure 7 This is a schematic diagram of the structure of a first semiconductor device and a second semiconductor device after a second bonding process, according to an exemplary embodiment. Figure 8 This is a schematic diagram of the structure after the second bonding process and the filling of the adhesive layer, according to an exemplary embodiment. Figure 9 This is a schematic diagram of the structure after the semiconductor structure has been connected according to an exemplary embodiment; Figure 10 This is another schematic diagram illustrating the second bonding process of the first and second semiconductor devices according to an exemplary embodiment; Figure 11 This is a schematic diagram of the structure after the connection structure has been formed and the adhesive layer has been filled, according to an exemplary embodiment. Figure 12 This is another structural schematic diagram showing the formation of a high-temperature solder layer and a low-temperature solder layer on a first semiconductor device according to an exemplary embodiment; Figure 13 This is another schematic diagram illustrating the stacked arrangement of a first semiconductor device and a second semiconductor device according to an exemplary embodiment; Figure 14 This is yet another schematic diagram illustrating a first semiconductor device and a second semiconductor device stacked according to an exemplary embodiment; Figure 15 This is a schematic diagram of the structure after the first connection portion is formed in a semiconductor structure according to an exemplary embodiment; Figure 16This is a schematic diagram of the structure after a third bonding process is performed on a first semiconductor device and a second semiconductor device according to an exemplary embodiment; Figure 17 This is a schematic diagram of the structure after the semiconductor structure has formed a connection structure according to another exemplary embodiment; Figure 18 This is another schematic diagram of a semiconductor structure after a connection structure has been formed and a filler layer has been applied, according to an exemplary embodiment. Figure 19 This is another structural schematic diagram showing the third bonding process performed on the first and second semiconductor devices according to an exemplary embodiment; Figure 20 This is a schematic diagram of the structure after the semiconductor structure has been formed into a connection structure according to yet another exemplary embodiment; Figure 21 This is a schematic diagram of the structure after a semiconductor structure has been formed into a connection structure and filled with an adhesive layer, according to an exemplary embodiment. Figure 22 This is another flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment; Figure 23 This is another flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment; Figure 24 This is a schematic diagram of the structure of a microbump according to an exemplary embodiment.

[0025] In the picture: 1. First semiconductor device; 11. First pad; 11a. Pad; 2. Second semiconductor device; 21. Second solder pad; 3. High-temperature solder layer; 4. Low-temperature solder layer; 41. First metal material layer; 42. Second metal material layer; 43. Mixed powder layer; 5. Connection structure; 51. First connecting part; 52. Second connecting part; 6. Adhesive layer. Detailed Implementation

[0026] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0027] In the field of semiconductor packaging technology, during chip stacking, solder balls are typically placed on the surface of one chip, and then thermocompression bonding is used to bond the solder balls to the pads of another chip. However, due to uneven solder ball height caused by molding processes and warping deformation of the chip caused by local stress, if the pressing distance is too small during thermocompression bonding, some solder balls will not be able to connect to their corresponding pads. If the pressing distance is sufficient to connect all solder balls to their corresponding pads, some molten solder balls will be over-pressed, causing solder to overflow laterally, resulting in bridging and short circuits between adjacent solder balls. This also leads to excessively small local spacing between the two chips, affecting the uniformity of the filler and severely restricting the reliability and yield of the stacked structure.

[0028] Based on this, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure. This method involves setting a high-temperature solder layer and a low-temperature solder layer between opposing first and second pads, with the high-temperature solder layer in contact with the first and / or second pads, and the low-temperature solder layer having a melting point lower than that of the high-temperature solder layer. In a first bonding process, the low-temperature solder layer melts to achieve a preliminary connection between the first and second pads. The molten low-temperature solder layer solidifies to form a first connection portion, while the high-melting-point high-temperature solder layer does not melt and serves as a spacing control, ensuring that there is at least a spacing between the first and second semiconductor devices corresponding to the thickness of the high-temperature solder layer. Furthermore, in a second bonding process, the high-temperature solder layer melts and connects to the first connection portion. Since the melting point of the first connection portion is higher than that of the high-temperature solder layer, the first connection portion does not melt and also serves as a spacing control, ensuring that there is at least a spacing between the first and second semiconductor devices corresponding to the thickness of the high-temperature solder layer. The spacing is less than the thickness of the first connection portion; therefore, a spacing control structure exists in both bonding processes to ensure a certain spacing between the first semiconductor and the second semiconductor, effectively avoiding the problem of too small a spacing between the first and second semiconductors caused by the height difference between the high-temperature solder layer and the low-temperature solder layer or by warping of the first and second semiconductors. This prevents bridging caused by excessive solder extrusion due to too small a spacing, as well as connection failure caused by uneven glue filling in the subsequent process, significantly improving the connection quality. Furthermore, in the second bonding process, no bonding pressure is applied to the first and second semiconductors, which can prevent the molten high-temperature solder layer from being excessively extruded to the side under the action of bonding pressure, preventing bridging and short circuits at adjacent connection positions, and allowing the assembly stress between the first and second semiconductors to be released, preventing warping of the stacked structure after bonding.

[0029] In an exemplary embodiment of this disclosure, a method for fabricating a semiconductor structure is provided, with reference to... Figure 1 Methods for fabricating semiconductor structures include: S100. A first semiconductor device and a second semiconductor device to be bonded are provided, and the first semiconductor device and the second semiconductor device are stacked with their bonding surfaces facing each other. The bonding surface of the first semiconductor device is provided with a first pad, and the bonding surface of the second semiconductor device is provided with a second pad opposite to the first pad. At least one high-temperature solder layer and at least one low-temperature solder layer are included between the first pad and the second pad. The high-temperature solder layer is in contact with the first pad and / or the second pad, and the melting point of the low-temperature solder layer is lower than the melting point of the high-temperature solder layer.

[0030] In step S100, refer to Figure 5 The first semiconductor device 1 and the second semiconductor device 2 can both be chips. The first semiconductor device 1 and the second semiconductor device 2 can be the same chip or different chips, and the bonding between the chips can adopt the embodiments of this solution. One of the first semiconductor device 1 and the second semiconductor device 2 can be a chip, and the other of the first semiconductor device 1 and the second semiconductor device 2 can be a substrate. The first semiconductor device 1 and the second semiconductor device 2 can also be wafers, and the bonding between the wafers can also adopt the embodiments of this solution. One of the first semiconductor device 1 and the second semiconductor device 2 can be a wafer, and the other is a substrate. Exemplarily, the chip can be a memory chip, which can be a Dynamic Random Access Memory (DRAM), or the chip can be a logic chip. Exemplarily, the substrate can be an adapter board or a circuit board.

[0031] For example, refer to Figure 2 The first pad 11 may protrude from the bonding surface of the first semiconductor device 1, or it may be partially embedded within the first semiconductor device 1 and partially protrude from the bonding surface of the first semiconductor device 1. Alternatively, the first pad 11 may be embedded within the first semiconductor device 1, with the bonding surface of the first semiconductor device 1 exposing the surface of the first pad 11. The material of the first pad 11 may be a metallic material or an alloy material. For example, the material of the first pad 11 may include at least one of copper, tungsten, aluminum, chromium, and nickel, or at least one of an alloy of copper, tungsten, aluminum, chromium, and nickel. The first pad 11 may be formed using processes such as electroplating, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), or combinations thereof.

[0032] For example, refer to Figure 3The second pad 21 may protrude from the bonding surface of the second semiconductor device 2. Alternatively, the second pad 21 may be partially embedded within the second semiconductor device 2 and partially protrude from the bonding surface of the second semiconductor device 2; or the second pad 21 may be embedded within the second semiconductor device 2, with the bonding surface of the second semiconductor device 2 exposing the surface of the second pad 21. The material of the second pad 21 may be a metallic material or an alloy material. For example, the material of the second pad 21 may include at least one of copper, tungsten, aluminum, chromium, and nickel, or at least one alloy of copper, tungsten, aluminum, chromium, and nickel. The second pad 21 may be formed using processes such as electroplating, physical vapor deposition, atomic layer deposition, chemical vapor deposition, or combinations thereof.

[0033] For example, refer to Figure 2 and Figure 5 The first pad 11 and the second pad 21 may include two high-temperature solder layers 3 and two low-temperature solder layers 4. The two high-temperature solder layers 3 are respectively disposed on the first pad 11 and the second pad 21 and are in contact with the first pad 11 and the second pad 21 respectively. The two low-temperature solder layers 4 are located between the two high-temperature solder layers 3 and are in contact with the two high-temperature solder layers 3 respectively. (Reference) Figure 3 and Figure 4 The first pad 11 and the second pad 21 may further include a high-temperature solder layer 3 and a low-temperature solder layer 4. The high-temperature solder layer 3 is in contact with one of the first pad 11 and the second pad 21, and the low-temperature solder layer 4 is located between the other of the first pad 11 and the second pad 21 and the high-temperature solder layer 3, and the low-temperature solder layer 4 is in contact with either the other of the first pad 11 and the second pad 21 or the high-temperature solder layer 3. Alternatively, the first pad 11 and the second pad 21 may further include two high-temperature solder layers 3 and one low-temperature solder layer 4. The two high-temperature solder layers 3 are in contact with the first pad 11 and the second pad 21 respectively, and the low-temperature solder layer 4 is located between the two high-temperature solder layers 3 and is in contact with one of the high-temperature solder layers 3. A high-temperature solder layer 3 and two low-temperature solder layers 4 may also be included between the first pad 11 and the second pad 21. The high-temperature solder layer 3 contacts one of the first pad 11 and the second pad 21, and the two low-temperature solder layers 4 are located between the other of the first pad 11 and the second pad 21 and the high-temperature solder layer 3, respectively contacting the other of the first pad 11 and the second pad 21 and the high-temperature solder layer 3. This design can provide multiple forms to meet different bonding requirements.

[0034] For example, the high-temperature solder layer 3 and the low-temperature solder layer 4 can be pillars. For example, the melting point of the high-temperature solder layer 3 can be 290°C-400°C, the melting point of the low-temperature solder layer 4 can be 230°C-300°C, and the melting point of the low-temperature solder layer 4 is lower than that of the high-temperature solder layer 3.

[0035] For example, a high-temperature solder layer 3 can be formed by processes such as electroplating, physical vapor deposition, atomic layer deposition, chemical vapor deposition, or a combination thereof, and a low-temperature solder layer 4 can be formed by processes such as electroplating, physical vapor deposition, atomic layer deposition, chemical vapor deposition, or a combination thereof.

[0036] When the first semiconductor component 1 and the second semiconductor component 2 are stacked, the first semiconductor component 1 can be located above the second semiconductor component 2, and the second semiconductor component 2 can also be located above the first semiconductor component 1. The first semiconductor component 1 and the second semiconductor component 2 can be fixed on a thermosetting bonding device. Of the two semiconductor components 1 and 2, the lower component is fixed in the height direction, while the upper component moves in the height direction with the structure of the thermosetting bonding device.

[0037] S200, A first bonding process is performed on the first semiconductor device and the second semiconductor device. The bonding temperature of the first bonding process is between the melting points of the low-temperature solder layer and the high-temperature solder layer. The low-temperature solder layer is transformed into a first connection part, and the first pad and the second pad are connected. The melting point of the first connection part is greater than the melting point of the high-temperature solder layer.

[0038] In step S200, the first pad 11 and the second pad 21 are connected, as shown in the reference. Figure 6 and Figure 7 The first connecting portion 51 can be in contact with the first pad 11 and the second pad 21, or the first connecting portion 51 can be in contact with the first pad 11 and the high-temperature solder layer 3, thus connecting the first pad 11 and the second pad 21. Alternatively, the first connecting portion 51 can be in contact with the second pad 21 and the high-temperature solder layer 3, thus connecting the first pad 11 and the second pad 21. (Refer to...) Figure 10 Alternatively, the first connecting part 51 can be in contact with the high-temperature solder layer 3, so that the first pad 11 and the second pad 21 are connected.

[0039] A thermocompression bonding apparatus can be used to apply bonding pressure to the upper semiconductor device 1 and the second semiconductor device 2, moving it downwards a certain distance. The apparatus also heats the low-temperature solder layer 4, causing it to melt. The molten low-temperature solder layer 4 connects the first pad 11 and the second pad 21. After solidification, the molten low-temperature solder layer 4 forms the first connection portion 51. While the low-temperature solder layer 4 is melting, the high-temperature solder layer 3 does not melt. For example, the material of the first connection portion 51 can be an alloy, and the melting point of the first connection portion 51 can be 400℃-800℃.

[0040] S300. Under conditions where no bonding pressure is applied, a second bonding process is performed on the first semiconductor device and the second semiconductor device. The bonding temperature of the second bonding process is between the melting point of the high-temperature solder layer and the melting point of the first connection portion. The high-temperature solder layer is transformed into the second connection portion and together with the first connection portion, they form a connection structure. The connection structure connects the first pad and the second pad.

[0041] In step S300, refer to Figure 8 and Figure 9 as well as Figure 11 In the second bonding process, the high-temperature solder layer 3 melts and solidifies into the second connection portion 52, which together with the first connection portion 51 constitutes the connection structure 5. In the second bonding process, no bonding pressure is applied to the first semiconductor device 1 and the second semiconductor device 2.

[0042] In this embodiment, a high-temperature solder layer 3 and a low-temperature solder layer 4 are provided between the opposing first pad 11 and second pad 21. The high-temperature solder layer 3 is in contact with the first pad 11 and / or the second pad 21, and the melting point of the low-temperature solder layer 4 is lower than that of the high-temperature solder layer 3. In the first bonding process, the low-temperature solder layer 4 melts to achieve a preliminary connection between the first pad 11 and the second pad 21. The molten low-temperature solder layer 4 solidifies to form a first connection portion 51. At the same time, the high-melting-point high-temperature solder layer 3 does not melt and plays a role in spacing control, ensuring that there is at least a spacing between the first semiconductor device 1 and the second semiconductor device 2 corresponding to the thickness of the high-temperature solder layer 3. In the second bonding process, the high-temperature solder layer 3 melts and connects with the first connection portion 51. Since the melting point of the first connection portion 51 is higher than that of the high-temperature solder layer 3, the first connection portion 51 does not melt and plays a role in spacing control, ensuring that there is at least a spacing between the first semiconductor device 1 and the second semiconductor device 2. The spacing is less than the thickness of the first connection portion 51; therefore, a spacing control structure exists in both bonding processes to ensure that there is a certain spacing between the first semiconductor 1 and the second semiconductor 2, effectively avoiding the problem of too small a spacing between the first semiconductor 1 and the second semiconductor 2 caused by the height difference between the high-temperature solder layer 3 and the low-temperature solder layer 4 or by the warping of the first semiconductor 1 and the second semiconductor 2. This prevents bridging caused by excessive solder extrusion due to too small a spacing, as well as connection failure caused by uneven glue filling in the subsequent process, and significantly improves the connection quality. Furthermore, in the second bonding process, no bonding pressure is applied to the first semiconductor 1 and the second semiconductor 2, which can prevent the molten high-temperature solder layer 3 from being excessively extruded to the side under the action of bonding pressure, prevent bridging and short circuits at adjacent connection positions, and allow the assembly stress between the first semiconductor 1 and the second semiconductor 2 to be released, preventing warping of the stacked structure after bonding.

[0043] In one embodiment, the material of the low-temperature solder layer 4 includes a physically composite first metal material and a second metal material, that is, the material of the low-temperature solder layer 4 is a physically composite material. The melting point of the second metal material is lower than that of the high-temperature solder layer 3, and the melting point of the first metal material is higher than that of the first connection portion 51. With this design, during the first bonding process, the connection between the first pad 11 and the second pad 21 can be achieved using the low-melting-point second metal material, and a high-melting-point alloy can be formed, so that the first connection portion 51 plays a role in spacing control during the second bonding process, ensuring that there is at least a spacing between the first semiconductor device 1 and the second semiconductor device 2 corresponding to the thickness of the first connection portion 51.

[0044] In one embodiment, reference Figure 12 The low-temperature solder layer 4 includes a first metal material layer 41 and a second metal material layer 42 alternately disposed in the stacking direction of the first semiconductor device 1 and the second semiconductor device 2. This ensures that the first metal material and the second metal material are relatively evenly distributed, which is beneficial for forming a uniform alloy with a stable melting point. It avoids excessive melting point differences due to uneven material distribution, prevents the strength of the first connection portion 51 from decreasing or voids from forming, improves the quality of the first connection portion 51, and thus avoids cracks in subsequent thinning processes, thereby improving the packaging quality. For example, the material of the first metal material layer 41 is the first metal material, and the material of the second metal material layer 42 is the second metal material.

[0045] For example, the first metal material layer 41 can be formed by processes such as electroplating, physical vapor deposition, atomic layer deposition, chemical vapor deposition, or a combination thereof, and the second metal material layer 42 can be formed by processes such as electroplating, physical vapor deposition, atomic layer deposition, chemical vapor deposition, or a combination thereof.

[0046] In one embodiment, the adjacent first metal material layer 41 and second metal material layer 42 have equal heights in the stacking direction of the first semiconductor device 1 and the second semiconductor device 2, further improving the uniformity of the distribution of the first and second metal materials, thereby forming a more uniform alloy, reducing voids, and improving the quality of the first connection portion 51. Exemplarily, the height of the first metal material layer 41 and the second metal material layer 42 in the stacking direction of the first semiconductor device 1 and the second semiconductor device 2 is the maximum dimension of the first metal material layer 41 and the second metal material layer 42 in the stacking direction of the first semiconductor device 1 and the second semiconductor device 2.

[0047] In one embodiment, reference Figure 13The low-temperature solder layer 4 comprises a mixed powder layer 43 formed by mixing powders of a first metal material and powders of a second metal material. This prevents local aggregation of the first and second metal materials, ensuring uniform distribution of the first and second metal materials and guaranteeing the formation of a uniform alloy. This effectively suppresses void formation, improves the quality of the first connection portion 51, and further prevents cracks from forming during subsequent thinning processes, thereby improving the packaging quality. Exemplarily, the material of the mixed powder layer 43 includes a material formed by mixing the first and second metal materials, and the mixed powder layer 43 can be formed using processes such as electroplating, physical vapor deposition, atomic layer deposition, chemical vapor deposition, or a combination thereof.

[0048] In one embodiment, the first metallic material includes at least one of copper, tungsten, or gold; the second metallic material includes at least one of tin or indium; and the material of the high-temperature solder layer 3 includes at least one of a tin-lead alloy, a tin-antimony alloy, an indium-lead alloy, or an indium-antimony alloy. This design allows for various combinations to be formed to suit different bonding needs.

[0049] For example, among the three materials copper, tungsten, and gold, the first metallic material can include any one material, any two materials, or even three materials. For example, the second metallic material can include only tin, or only indium, or both tin and indium. For example, among the four materials tin-lead alloy, tin-antimony alloy, indium-lead alloy, and indium-antimony alloy, the material of the high-temperature solder layer 3 can include any one material, any two materials, any three materials, or even four materials.

[0050] In one embodiment, reference Figure 6 and Figure 7 The first bonding process includes a first bonding process and a second bonding process. The bonding pressure in the first bonding process is lower than that in the second bonding process. By setting the first bonding process with a relatively low bonding pressure, the molten low-temperature solder layer 4 is less likely to be squeezed out, effectively preventing bridging short circuits between adjacent connection sites. Subsequently, the second bonding process further reduces the spacing between the first semiconductor device 1 and the second semiconductor device 2 and increases the bonding pressure, enabling the first pad 11 and the second pad 21 in areas with significant warping to also be connected. This ensures effective connection at all connection sites. This step-by-step bonding method, starting with low pressure and then increasing it, avoids the problem of solder overflow and bridging short circuits between adjacent connection sites caused by a sudden increase in bonding pressure, while also ensuring effective connection of each first pad 11 and second pad 21, thus improving bonding quality.

[0051] refer to Figure 6 and Figure 7 The spacing between the first semiconductor device 1 and the second semiconductor device 2 is a first spacing. During the second bonding process, the spacing between the first semiconductor device 1 and the second semiconductor device 2 is reduced to a second spacing, which is smaller than the first spacing. The bonding temperature of the first bonding process is equal to the bonding temperature of the second bonding process. For example, after the first semiconductor device 1 and the second semiconductor device 2 are stacked, the spacing between the first semiconductor device 1 and the second semiconductor device 2 refers to the spacing between the first pad 11 and the second pad 21.

[0052] After the first bonding process, the gap between the first semiconductor device 1 and the second semiconductor device 2 decreases, and the low-temperature solder layer 4 transforms into a molten state, connecting the first semiconductor device 1 and the second semiconductor device 2. (Reference) Figure 6 and Figure 7 After the second bonding process, the distance between the first semiconductor 1 and the second semiconductor 2 continues to decrease, and the low-temperature solder layers 4 in the molten state connect the first pad 11 and the second pad 21 that are arranged opposite to each other.

[0053] For example, in the first bonding process, at least partially opposite first pads 11 and second pads 21 are connected. In the second bonding process, each molten low-temperature solder layer 4 connects the corresponding opposite first pads 11 and second pads 21. Before the second bonding process, the molten low-temperature solder layer 4 solidifies to form the first connection portion 51.

[0054] For example, the bonding pressure in the first bonding process is a first bonding pressure, which can be 0.1N-10N. During the first bonding process, the pressure between the first semiconductor device 1 and the second semiconductor device 2 rises from zero to the first bonding pressure and remains at the first bonding pressure. For example, the bonding pressure in the second bonding process is a second bonding pressure, which can be 0.1N-100N. During the second bonding process, the pressure between the first semiconductor device 1 and the second semiconductor device 2 rises from the first bonding pressure to the second bonding pressure and remains at the second bonding pressure.

[0055] In this embodiment, setting the second spacing to be smaller than the first spacing can further reduce the spacing between the first semiconductor device 1 and the second semiconductor device 2, and further enable the first pad 11 and the second pad 21 in the area with larger local warping to be connected, ensuring that each connection position can be effectively connected and improving the bonding quality.

[0056] In one embodiment, during the first bonding process, the distance between the first semiconductor device 1 and the second semiconductor device 2 is reduced by a first distance. During the second bonding process, the distance between the first semiconductor device 1 and the second semiconductor device 2 is reduced by a second distance, and the second distance is smaller than the first distance. By setting the second distance to be smaller than the first distance, it is possible to ensure that the air between the first semiconductor device 1 and the second semiconductor device 2 is fully discharged, and to avoid excessive compression of the solder during the second bonding process, thus preventing solder overflow and bridging short circuits between adjacent connection sites. For example, the second distance can be 1µm-100µm.

[0057] For example, when the bonding pressure applied to the first semiconductor device 1 and the second semiconductor device 2 increases from the first bonding pressure to the second bonding pressure, the low-temperature solder layer 4 can be pressed to completely surround the outside of the high-temperature solder layer 3; the low-temperature solder layer 4 can also be pressed to partially surround the outside of the high-temperature solder layer 3 and partially located between the two high-temperature solder layers 3, or partially located between the high-temperature solder layer 3 and the first pad 11 or the second pad 21; the low-temperature solder layer 4 can also be entirely located between the two high-temperature solder layers 3, or entirely located between the high-temperature solder layer 3 and the first pad 11 or the second pad 21.

[0058] In one embodiment, the height of the low-temperature solder layer 4 in the stacking direction of the first semiconductor device 1 and the second semiconductor device 2 is 1µm-100µm, which can ensure that the low-temperature solder layer 4 is sufficient to achieve a reliable connection between the first pad 11 and the second pad 21, while avoiding lateral overflow and bridging caused by excessively thick low-temperature solder layer 4, thereby improving the connection quality and the yield of the semiconductor structure.

[0059] In one embodiment, the radial dimension of the low-temperature solder layer 4 is 2µm-200µm. This ensures sufficient low-temperature solder layer 4 for reliable connection of the first pad 11 and the second pad 21, while avoiding lateral overflow and bridging caused by excessive low-temperature solder layer 4, thus improving connection quality and semiconductor structure yield. For example, the central axis of the low-temperature solder layer 4 is parallel to the stacking direction of the first semiconductor device 1 and the second semiconductor device 2. The distance between the two points where a straight line perpendicularly intersects the central axis of the low-temperature solder layer 4 and the outer surface of the low-temperature solder layer 4 intersects is the radial dimension of the low-temperature solder layer 4. (Refer to...) Figure 3 The radial dimension of the low-temperature solder layer 4 is L4. Any radial dimension of the low-temperature solder layer 4 is between 2µm and 200µm. The low-temperature solder layer 4 is, for example, cylindrical, and the diameter of the low-temperature solder layer 4 is between 2µm and 200µm.

[0060] When the height of the low-temperature solder layer 4 in the stacking direction of the first semiconductor device 1 and the second semiconductor device 2 is 1µm-100µm, and the radial dimension of the low-temperature solder layer 4 is 2µm-200µm, the low-temperature solder layer 4 can be provided on both the first pad 11 and the second pad 21 to ensure that the low-temperature solder layer 4 is sufficient to achieve a reliable connection between the first pad 11 and the second pad 21. Of course, the low-temperature solder layer 4 can also be provided on one of the first pad 11 and the second pad 21.

[0061] In one embodiment, the height of the high-temperature solder layer 3 in the stacking direction of the first semiconductor device 1 and the second semiconductor device 2 is 1µm-100µm. During the pressing and melting of the low-temperature solder layer 4, the high-temperature solder layer 3 provides a spacing control function between the first semiconductor device 1 and the second semiconductor device 2, ensuring that there is at least a spacing between the first semiconductor device 1 and the second semiconductor device 2 corresponding to the height of the high-temperature solder layer 3. This prevents bridging caused by excessively small spacing between the first semiconductor device 1 and the second semiconductor device 2, while also avoiding excessive thickness of the high-temperature solder layer 3 from affecting the melting efficiency, thus balancing connection quality and connection efficiency. For example, the height of the high-temperature solder layer 3 in the stacking direction of the first semiconductor device 1 and the second semiconductor device 2 is the maximum dimension of the high-temperature solder layer 3 in the stacking direction of the first semiconductor device 1 and the second semiconductor device 2.

[0062] In one embodiment, the radial dimension of the high-temperature solder layer 3 is 2µm-200µm, enabling it to provide sufficient support for the low-temperature solder layer 4 and to create a stable spacing control between the first semiconductor device 1 and the second semiconductor device 2. Simultaneously, it avoids excessively large radial dimensions of the high-temperature solder layer 3 from affecting melting efficiency, thereby improving the connection efficiency of the first semiconductor device 1 and the second semiconductor device 2. Exemplarily, the central axis of the high-temperature solder layer 3 is parallel to the stacking direction of the first semiconductor device 1 and the second semiconductor device 2. The distance between the two points where a straight line perpendicularly intersects the central axis of the high-temperature solder layer 3 and the outer surface of the high-temperature solder layer 3 intersects is the radial dimension of the high-temperature solder layer 3. The high-temperature solder layer 3 is, for example, cylindrical, with a diameter of 2µm-200µm. (Reference) Figure 2 The radial dimension of the high-temperature solder layer 3 is L3.

[0063] In one embodiment, reference Figure 13In the projection of the first plane parallel to the first pad 11, the projection of the high-temperature solder layer 3 coincides with the projection of the first pad 11 and also with the projection of the second pad 21. The outer contour of the projection of the first pad 11 surrounds the outer side of the projection of the low-temperature solder layer 4, or the projection of the first pad 11 coincides with the projection of the low-temperature solder layer 4, and the outer contour of the projection of the second pad 21 surrounds the outer side of the projection of the low-temperature solder layer 4, or the projection of the second pad 21 coincides with the projection of the low-temperature solder layer 4. In the first bonding process step: at most one end of the first connecting portion 51 contacts one of the first pad 11 and the second pad 21. This design ensures sufficient gap between the first semiconductor component 1 and the second semiconductor component 2, and ensures uniformity of the filler between the first semiconductor component 1 and the second semiconductor component 2.

[0064] For example, in the first bonding process step, the first connecting portion 51 is configured to contact at most one end with one of the first pad 11 and the second pad 21. This can be described as follows: both ends of the first connecting portion 51 do not contact the first pad 11 and the second pad 21, and both ends of the first connecting portion 51 are in contact with a high-temperature solder layer 3. Alternatively, one end of the first connecting portion 51 is in contact with the first pad 11, and the other end of the first connecting portion 51 is in contact with the high-temperature solder layer 3. Or, one end of the first connecting portion 51 is in contact with the second pad 21, and the other end of the first connecting portion 51 is in contact with the high-temperature solder layer 3.

[0065] In one embodiment, reference Figure 12 and Figure 14 In the projection parallel to the first plane of the first pad 11, the outer contours of the projections of the first pad 11 and the second pad 21 both surround the outer side of the projection of the high-temperature solder layer 3, and the outer contour of the projection of the first pad 11 surrounds the outer side of the projection of the low-temperature solder layer 4, or the projection of the first pad 11 coincides with the projection of the low-temperature solder layer 4, and the outer contour of the projection of the second pad 21 surrounds the outer side of the projection of the low-temperature solder layer 4, or the projection of the second pad 21 coincides with the projection of the low-temperature solder layer 4. In the first bonding process step: the two ends of the first connecting portion 51 contact the first pad 11 and the second pad 21 respectively. Exemplarily, the projection direction is perpendicular to the first plane, and the first plane is perpendicular to the stacking direction of the first semiconductor device 1 and the second semiconductor device 2.

[0066] In this embodiment, by setting the outer contour of the projection of the first pad 11 and the outer contour of the projection of the second pad 21 to surround the outer side of the projection of the high-temperature solder layer 3, the molten solder is effectively confined within the area of ​​the first pad 11 and the second pad 21 when the first connection portion 51 is formed, avoiding lateral overflow of solder and bridging defects at adjacent connection positions, thereby significantly reducing the risk of short circuits between adjacent connection positions. Furthermore, without the need for a complex anti-overflow structure, the process flow of the semiconductor structure is simplified, which is beneficial to reducing production costs and enhancing the reliability of the stacked structure.

[0067] In one embodiment, the ratio of the radial dimension of the high-temperature solder layer 3 to the radial dimension of the first pad 11 is 1 / 100-1 / 2, and the ratio of the radial dimension of the high-temperature solder layer 3 to the radial dimension of the second pad 21 is 1 / 100-1 / 2. This ensures that both the first pad 11 and the second pad 21 have space to connect with the molten solder of the low-temperature solder layer 4. The molten solder is effectively confined within the areas of the first pad 11 and the second pad 21, avoiding bridging defects caused by lateral solder overflow, thereby significantly reducing the risk of short circuits between adjacent connection locations.

[0068] For example, the central axis of the first pad 11 is parallel to the stacking direction of the first semiconductor device 1 and the second semiconductor device 2. The distance between the two intersection points of a straight line perpendicularly intersecting the central axis of the first pad 11 and the outer surface of the first pad 11 is the radial dimension of the first pad 11. The ratio of any radial dimension of the high-temperature solder layer 3 to any radial dimension of the first pad 11 satisfies 1 / 100-1 / 2. The central axis of the second pad 21 is parallel to the stacking direction of the first semiconductor device 1 and the second semiconductor device 2. The distance between the two intersection points of a straight line perpendicularly intersecting the central axis of the second pad 21 and the outer surface of the second pad 21 is the radial dimension of the second pad 21. The ratio of any radial dimension of the high-temperature solder layer 3 to any radial dimension of the second pad 21 satisfies 1 / 100-1 / 2. (Reference) Figure 2 and Figure 3 The diameter of the first pad 11 is L1, and the radial dimension of the second pad 21 is L2.

[0069] In one embodiment, the ratio of the radial dimension of the low-temperature solder layer 4 to the radial dimension of the first pad 11 is 1 / 100-1 / 2, and the ratio of the radial dimension of the low-temperature solder layer 4 to the radial dimension of the second pad 21 is 1 / 100-1 / 2. This ensures sufficient solder in the low-temperature solder layer 4, achieving a stable connection between the first pad 11 and the second pad 21, while preventing excessive solder in the low-temperature solder layer 4 from causing lateral overflow of solder, avoiding bridging and short circuits between adjacent connection locations, and ensuring a stable connection between the first semiconductor device 1 and the second semiconductor device 2. Exemplarily, the ratio of any radial dimension of the low-temperature solder layer 4 to any radial dimension of the first pad 11 satisfies 1 / 100-1 / 2, and the ratio of any radial dimension of the low-temperature solder layer 4 to any radial dimension of the second pad 21 satisfies 1 / 100-1 / 2.

[0070] When the ratio of the radial dimension of the low-temperature solder layer 4 to the radial dimension of the first pad 11 is 1 / 100-1 / 2, and the ratio of the radial dimension of the low-temperature solder layer 4 to the radial dimension of the second pad 21 is 1 / 100-1 / 2, both the first semiconductor device 1 and the second semiconductor device 2 are provided with low-temperature solder layer 4. This ensures that there is enough solder in the low-temperature solder layer 4 to achieve a stable connection between the first pad 11 and the second pad 21, and avoids excessive solder in the low-temperature solder layer 4, which would cause lateral overflow of solder and prevent bridging and short circuits at adjacent connection positions.

[0071] In one embodiment, reference Figure 14 When a high-temperature solder layer 3 is provided on one of the first pad 11 and the second pad 21, the outer contours of the projections of the first pad 11 and the second pad 21 onto the first plane surround the outer side of the projection of the high-temperature solder layer 3 onto the first plane, as shown in the reference. Figure 15 In the first bonding process step: the high-temperature solder layer 3 contacts the first pad 11 and the second pad 21, the first connecting part 51 surrounds the outside of the high-temperature solder layer 3, and the first connecting part 51 contacts and connects with the first pad 11 and the second pad 21, so that the high-temperature solder layer 3 is supported between the first pad 11 and the second pad 21, avoiding the gap between the first semiconductor 1 and the second semiconductor 2 being too small.

[0072] In one embodiment, reference Figure 5 When high-temperature solder layers 3 are respectively provided on the first pad 11 and the second pad 21, the outer contours of the projections of the first pad 11 and the second pad 21 on the first plane surround the outer side of the projection of the high-temperature solder layer 3 on the first plane, for reference. Figure 7In the first bonding process, the high-temperature solder layer 3 on the first pad 11 and the high-temperature solder layer 3 on the second pad 21 come into contact. The first connecting part 51 surrounds the outside of the two high-temperature solder layers 3 and is in contact with the first pad 11 and the second pad 21, so that the high-temperature solder layer 3 is supported between the first pad 11 and the second pad 21, thus avoiding the gap between the first semiconductor 1 and the second semiconductor 2 being too small.

[0073] In one embodiment, reference Figure 7 , Figure 16 and Figure 17 as well as Figure 10 , Figure 19 and Figure 20 Following the second bonding process, the first bonding process also includes a third bonding process. The bonding pressure in the third bonding process is lower than the bonding pressure in the second bonding process, so that the distance between the first semiconductor device 1 and the second semiconductor device 2 increases to a preset distance. In the second bonding process step, the preset distance is maintained between the first semiconductor device 1 and the second semiconductor device 2.

[0074] For example, after the second bonding process, the first bonding process further includes a third bonding process, which includes: S210, Pull the upper one of the first semiconductor device and the second semiconductor device upward to a preset position.

[0075] In the second bonding process, the upper one of the first semiconductor 1 and the second semiconductor 2 is held in a preset position.

[0076] In step S210, the upper semiconductor device 1 and the upper semiconductor device 2 are pulled upward to a preset position using a thermosetting bonding device, thereby increasing the distance between the two semiconductor devices. The upper semiconductor device 1 and the upper semiconductor device 2 are then pulled upward to a third preset position, the third distance being 1µm-100µm.

[0077] In this embodiment, after the second bonding process, the first bonding process further includes a third bonding process. The bonding pressure in the third bonding process is lower than that in the second bonding process, increasing the distance between the first semiconductor device 1 and the second semiconductor device 2 to a preset distance. Furthermore, maintaining this preset distance between the first semiconductor device 1 and the second semiconductor device 2 during the second bonding process ensures sufficient spacing, preventing bridging short circuits between adjacent connection sites during the second bonding process. This also ensures uniform filling of the encapsulant, avoids voids, and improves the reliability of the semiconductor structure packaging. Additionally, it can accommodate warpage deformations of 4µm-400µm between the first semiconductor device 1 and the second semiconductor device 2, ensuring effective connection between the first pad 11 and the second pad 21.

[0078] In some embodiments, reference Figure 16 and Figure 19 After the third bonding process and before the second bonding process, the structure formed by the conversion of the low-temperature solder layer 4 has an increased size in the stacking direction of the first semiconductor 1 and the second semiconductor 2, ensuring that the structure converted by the low-temperature solder layer 4 can be adapted to the increased spacing between the first semiconductor 1 and the second semiconductor 2, and keeping the first pad 11 and the second pad 21 connected.

[0079] In one embodiment, reference Figure 17 and Figure 18 as well as Figure 20 , Figure 21 and Figure 22 After forming the interconnect structure, the methods for fabricating semiconductor structures also include: S400, an adhesive layer is filled between the first semiconductor component and the second semiconductor component.

[0080] In step S400, the material of the adhesive layer 6 may include at least one of epoxy resin, phenolic resin, and polyimide. Before filling the adhesive layer 6, the first bonding process may include a third bonding process, and the relative positions of the first semiconductor 1 and the second semiconductor 2 may remain unchanged after the second bonding process.

[0081] In this embodiment, after the connection structure 5 is formed, an adhesive layer 6 is filled between the first semiconductor 1 and the second semiconductor 2. The adhesive layer 6 can seal and protect the connection structure 5, buffer thermal stress and mechanical impact, prevent the connection structure 5 from cracking or corroding, and significantly improve the reliability of the semiconductor structure.

[0082] In one embodiment, reference Figure 7 , Figure 8 , Figure 9 and Figure 23The first bonding process also includes a curing process to solidify the molten low-temperature solder layer to form the first connection. The method for fabricating a semiconductor structure after the curing process and before the second bonding process also includes: S500, an adhesive layer is filled between the first semiconductor component and the second semiconductor component.

[0083] In step S500, the material of the adhesive layer 6 may include at least one of epoxy resin, phenolic resin, and polyimide. Before filling the adhesive layer 6, the first bonding process may include a third bonding process, and the relative positions of the first semiconductor 1 and the second semiconductor 2 may remain unchanged after the second bonding process.

[0084] In this embodiment, after the formation of the first connection portion 51 and before the second bonding process, an adhesive layer 6 is filled between the first semiconductor component 1 and the second semiconductor component 2. The filled adhesive layer 6 can connect and support the first semiconductor component 1 and the second semiconductor component 2, preventing the first semiconductor component 1 and the second semiconductor component 2 from losing their supporting capacity when the high-temperature solder layer 3 melts, thus ensuring the precise controllability of the distance between the first semiconductor component 1 and the second semiconductor component 2. At the same time, the larger spacing between two adjacent connecting solders facilitates the filling of the adhesive layer. Furthermore, the filled adhesive layer 6 can separate the solder layers at adjacent connection positions, preventing bridging and short circuits at adjacent connection positions when the high-temperature solder layer 3 melts, thereby improving the reliability and yield of the semiconductor structure. In addition, after filling the adhesive layer, the shape of the connection structure 5 does not change during the second bonding process, which can reduce the deformation stress of the connection structure 5. Furthermore, it can be set without a third bonding process before the filler adhesive layer 6, which can accommodate the warping deformation of 4µm-2000µm between the first semiconductor 1 and the second semiconductor 2, ensuring the effective connection of the first pad 11 and the second pad 21.

[0085] In one embodiment, both the first pad 11 and the second pad 21 are provided with a high-temperature solder layer 3, and at least one of the first pad 11 and the second pad 21 has a low-temperature solder layer 4 on its high-temperature solder layer 3; or, one of the first pad 11 and the second pad 21 has a high-temperature solder layer 3, and the other of the first pad 11 and the second pad 21 and / or the high-temperature solder layer 3 has a low-temperature solder layer 4. By changing the positions of the high-temperature solder layer 3 and the low-temperature solder layer 4, various configurations can be provided to improve the user experience.

[0086] For example, both the first pad 11 and the second pad 21 are provided with a high-temperature solder layer 3. Alternatively, only the first pad 11 may be provided with a low-temperature solder layer 4, or only the high-temperature solder layer 3 of the second pad 21 may be provided with a low-temperature solder layer 4, or both the high-temperature solder layer 3 of the first pad 11 and the low-temperature solder layer 4 of the second pad 21 may be provided. For example, the first pad 11 may be provided with a high-temperature solder layer 3, and the high-temperature solder layer 3 and / or the second pad 21 may be provided with a low-temperature solder layer 4. Alternatively, the second pad 21 may be provided with a high-temperature solder layer 3, and the high-temperature solder layer 3 and / or the first pad 11 may be provided with a low-temperature solder layer 4.

[0087] In an exemplary embodiment of this disclosure, a semiconductor structure is also proposed, with reference to Figure 9 and Figure 18 The semiconductor structure includes a first semiconductor device 1 and a second semiconductor device 2. A first pad 11 is provided on the bonding surface of the first semiconductor device 1. A second pad 21 is provided on the bonding surface of the second semiconductor device 2. The second semiconductor device 2 and the first semiconductor device 1 are stacked with their bonding surfaces facing each other, and the second pad 21 and the first pad 11 are arranged opposite each other.

[0088] Exemplarily, both the first semiconductor device 1 and the second semiconductor device 2 can be chips. The first semiconductor device 1 and the second semiconductor device 2 can be the same chip or different chips, and the bonding between the chips can adopt the embodiments of this solution. One of the first semiconductor device 1 and the second semiconductor device 2 can be a chip, and the other of the first semiconductor device 1 and the second semiconductor device 2 can be a substrate. The first semiconductor device 1 and the second semiconductor device 2 can also be wafers, and the bonding between wafers can also adopt the embodiments of this solution. One of the first semiconductor device 1 and the second semiconductor device 2 can be a wafer, and the other is a substrate. Exemplarily, the chip can be a memory chip, which can be a dynamic random access memory (DRAM), or a logic chip. Exemplarily, the substrate can be an adapter board or a circuit board.

[0089] Exemplarily, the first pad 11 may protrude from the bonding surface of the first semiconductor device 1. The first pad 11 may also be partially embedded within the first semiconductor device 1 and partially protrude from the bonding surface of the first semiconductor device 1. Furthermore, the bonding surface of the first semiconductor device 1 may expose the surface of the first pad 11. The material of the first pad 11 may be a metallic material or an alloy material. Exemplarily, the material of the first pad 11 may include at least one of copper, tungsten, aluminum, chromium, and nickel, or at least one of an alloy of copper, tungsten, aluminum, chromium, and nickel.

[0090] Exemplarily, the second pad 21 may protrude from the bonding surface of the second semiconductor device 2; the second pad 21 may also be partially embedded within the second semiconductor device 2 and partially protrude from the bonding surface of the second semiconductor device 2; the second pad 21 may also be embedded within the second semiconductor device 2, with the bonding surface of the second semiconductor device 2 exposed. The material of the second pad 21 may be a metallic material or an alloy material. Exemplarily, the material of the second pad 21 may include at least one of copper, tungsten, aluminum, chromium, and nickel, or at least one of an alloy of copper, tungsten, aluminum, chromium, and nickel. The second pad 21 may be formed using processes such as electroplating, physical vapor deposition, atomic layer deposition, chemical vapor deposition, or combinations thereof.

[0091] refer to Figure 9 and Figure 18 The semiconductor structure also includes a connection structure 5. The connection structure 5 is connected between the first pad 11 and the second pad 21. The connection structure 5 includes a first connection portion 51 and a second connection portion 52 connected together. The melting point of the first connection portion 51 is greater than the melting point of the second connection portion 52.

[0092] For example, the first connection portion 51 is formed by solidifying a molten low-temperature solder layer 4, and the second connection portion 52 is formed by solidifying a molten high-temperature solder layer 3. The melting point of the first connection portion 51 is greater than the melting point of the high-temperature solder layer 3, and the melting point of the high-temperature solder layer 3 is greater than the melting point of the low-temperature solder layer 4.

[0093] In this embodiment, the connection structure 5 includes a first connection part 51 and a second connection part 52 connected together. The melting point of the first connection part 51 is greater than that of the second connection part 52, so that different regions of the connection structure 5 have different stiffnesses. When the connection structure 5 is subjected to external loads, the deformation is first concentrated in the low stiffness region, thereby avoiding brittle fracture in the high stiffness region due to stress concentration and avoiding connection failure of the first semiconductor component 1 and the second semiconductor component 2.

[0094] In one embodiment, the first connecting portion 51 is an alloy. The alloy includes a first metallic material and a second metallic material. Exemplarily, the first connecting portion 51 is an alloy formed of the first metallic material and the second metallic material. The first metallic material includes at least one of copper, tungsten, or gold, and the second metallic material includes at least one of tin or indium. The material of the high-temperature solder layer 3 includes at least one of tin-lead alloy, tin-antimony alloy, indium-lead alloy, or indium-antimony alloy, which can form various combinations suitable for different melting requirements.

[0095] For example, among the three materials copper, tungsten, and gold, the first metallic material can include any one material, any two materials, or even three materials. For example, the second metallic material can include only tin, or only indium, or both tin and indium. For example, among the four materials tin-lead alloy, tin-antimony alloy, indium-lead alloy, and indium-antimony alloy, the material of the high-temperature solder layer 3 can include any one material, any two materials, any three materials, or even four materials.

[0096] In one embodiment, reference Figure 9 and Figure 18 The first connecting portion 51 surrounds the outside of the second connecting portion 52, and along the stacking direction of the first semiconductor device 1 and the second semiconductor device 2, the two ends of the first connecting portion 51 are respectively in contact with the first pad 11 and the second pad 21. (Reference) Figure 9 Along the stacking direction of the first semiconductor device 1 and the second semiconductor device 2, the two ends of the second connecting portion 52 are respectively connected to the first pad 11 and the second pad 21; or, refer to Figure 18 The second connection portion 52 has at least one, and along the stacking direction of the first semiconductor 1 and the second semiconductor 2, one end of each second connection portion 52 is connected to the first connection portion 51, and the other end of each second connection portion 52 is in contact with the first pad 11 or the second pad 21.

[0097] In this embodiment, a first connecting portion 51 is provided around the outside of the second connecting portion 52, and the two ends of the first connecting portion 51 are respectively connected to the first pad 11 and the second pad 21. This can reduce the stacking height of the semiconductor structure and improve the integration degree of the semiconductor structure while ensuring that the gap between the first semiconductor component 1 and the second semiconductor component 2 is sufficient.

[0098] For example, the second connection portion 52 may be one, with one end of the second connection portion 52 connected to the first connection portion 51 along the stacking direction of the first semiconductor device 1 and the second semiconductor device 2, and the other end of the second connection portion 52 connected to the first pad 11 or the second pad 21; the second connection portion 52 may also be two, with one end of the two second connection portions 52 connected to the first pad 11 and the second pad 21 respectively along the stacking direction of the first semiconductor device 1 and the second semiconductor device 2, and the other ends of the two second connection portions 52 connected to the first connection portion 51, and the two second connection portions 52 are not connected.

[0099] In one embodiment, the first connecting portion 51 and the second connecting portion 52 are sequentially connected in the stacking direction of the first semiconductor device 1 and the second semiconductor device 2. Alternatively, refer to... Figure 11 and Figure 21 Along the stacking direction of the first semiconductor 1 and the second semiconductor 2, the first connecting part 51 is connected between two second connecting parts 52, and the two second connecting parts 52 are respectively connected to the first pad 11 and the second pad 21, which can ensure that there is a sufficient gap between the first semiconductor 1 and the second semiconductor 2 and ensure the uniformity of the filler between the first semiconductor 1 and the second semiconductor 2.

[0100] In exemplary embodiments of this disclosure, a microbump is also proposed, with reference to Figure 24 Microbumps are formed on a semiconductor device, comprising a high-temperature solder layer 3 and a low-temperature solder layer 4. The high-temperature solder layer 3 is disposed on a pad 11a of the semiconductor device. The low-temperature solder layer 4 is disposed on the high-temperature solder layer 3, and is located on the side of the high-temperature solder layer 3 facing away from the pad 11a. The melting point of the low-temperature solder layer 4 is lower than that of the high-temperature solder layer 3. The low-temperature solder layer 4 is used to melt and solidify to form an alloy. The melting point of the alloy is higher than that of the high-temperature solder layer 3.

[0101] In this embodiment, the microbump includes a high-temperature solder layer 3 and a low-temperature solder layer 4. The melting point of the low-temperature solder layer 4 is lower than that of the high-temperature solder layer 3. The low-temperature solder layer 4 is used to melt and solidify to form an alloy. It can be heated to a lower temperature to melt the low-temperature solder layer 4, realizing the initial connection between the semiconductor device and other semiconductor devices. During the initial connection process, the high-temperature solder layer 3 does not melt and plays a role in spacing control, ensuring that there is at least a spacing between the two semiconductor devices corresponding to the height of the high-temperature solder layer 3, avoiding the spacing being too small. It can also convert the low-temperature solder layer 4 into an alloy, and the melting point of the alloy is lower than that of the high-temperature solder layer. When it is subsequently heated to a higher temperature, the high-temperature solder layer 3 can melt to realize the further connection between the two semiconductor devices. During the further connection process, the alloy does not melt and plays a role in spacing control, ensuring that there is at least a spacing between the two semiconductor devices corresponding to the height of the alloy, avoiding the spacing being too small, avoiding short circuits at adjacent connection positions, and improving the bonding quality of the two semiconductors.

[0102] In one embodiment, the material of the low-temperature solder layer 4 comprises a physically composite first metallic material and a second metallic material. The melting point of the second metallic material is lower than that of the high-temperature solder layer 3, and the melting point of the first metallic material is higher than that of the alloy. The first metallic material comprises at least one of copper, tungsten, or gold, and the second metallic material comprises at least one of tin or indium. The material of the high-temperature solder layer comprises at least one of a tin-lead alloy, a tin-antimony alloy, an indium-lead alloy, or an indium-antimony alloy.

[0103] In this embodiment, the material of the low-temperature solder layer 4 includes a physically composite first metal material and a second metal material. The characteristics of the second metal material can be fully utilized, resulting in a low melting point of the low-temperature solder layer 4, which is easy to melt. At the same time, the characteristics of the first metal material can be utilized to form an alloy with a higher melting point. This alloy is not easy to melt during subsequent processing and use, which significantly improves the stability and heat resistance of the connection between the two semiconductor components.

[0104] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0105] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: A first semiconductor device and a second semiconductor device to be bonded are provided, and the first semiconductor device and the second semiconductor device are stacked with their bonding surfaces facing each other. The bonding surface of the first semiconductor device is provided with a first pad, and the bonding surface of the second semiconductor device is provided with a second pad opposite to the first pad. At least one high-temperature solder layer and at least one low-temperature solder layer are included between the first pad and the second pad, and the high-temperature solder layer is in contact with the first pad and / or the second pad. The melting point of the low-temperature solder layer is lower than the melting point of the high-temperature solder layer. The first semiconductor device and the second semiconductor device are subjected to a first bonding process. The bonding temperature of the first bonding process is between the melting points of the low-temperature solder layer and the high-temperature solder layer. The low-temperature solder layer is transformed into a first connection part. The first pad and the second pad are connected. The melting point of the first connection part is greater than the melting point of the high-temperature solder layer. The first connection part is an alloy. Under conditions where no bonding pressure is applied, the first semiconductor device and the second semiconductor device are subjected to a second bonding process. The bonding temperature of the second bonding process is between the melting point of the high-temperature solder layer and the melting point of the first connection portion. The high-temperature solder layer is transformed into a second connection portion and together with the first connection portion forms a connection structure. The connection structure connects the first pad and the second pad.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The material of the low-temperature solder layer includes a first metal material and a second metal material that are physically composited. The melting point of the second metal material is lower than that of the high-temperature solder layer, and the melting point of the first metal material is higher than that of the first connecting part.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The low-temperature solder layer includes a first metal material layer and a second metal material layer alternately disposed in the stacking direction of the first semiconductor device and the second semiconductor device.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The adjacent first metal material layer and second metal material layer have the same height in the stacking direction of the first semiconductor device and the second semiconductor device.

5. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The low-temperature solder layer comprises a mixed powder layer formed by physically mixing the powder of the first metal material and the powder of the second metal material.

6. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The first metal material includes at least one of copper, tungsten, or gold; the second metal material includes at least one of tin or indium; and the material of the high-temperature solder layer includes at least one of tin-lead alloy, tin-antimony alloy, indium-lead alloy, or indium-antimony alloy.

7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, When the high-temperature solder layer is provided on one of the first pads and the second pads, the outer contours of the projections of the first pads and the second pads on the first plane surround the outer side of the projection of the high-temperature solder layer on the first plane. In the first bonding process step, the high-temperature solder layer contacts the first pads and the second pads, the first connecting portion surrounds the outer side of the high-temperature solder layer, and the first connecting portion contacts and connects with the first pads and the second pads. or, When the first pad and the second pad are respectively provided with the high-temperature solder layer, the outer contour of the projection of the first pad and the second pad on the first plane surrounds the outside of the projection of the high-temperature solder layer on the first plane. Then, in the first bonding process step: the high-temperature solder layer on the first pad and the high-temperature solder layer on the second pad are in contact, the first connecting part surrounds the outside of the two high-temperature solder layers, and the first connecting part is in contact with and connected to the first pad and the second pad. The first plane is parallel to the first pad.

8. The method for fabricating a semiconductor structure according to claim 1 or 7, characterized in that, Both the first pad and the second pad are provided with the high-temperature solder layer, and at least one of the first pad and the second pad is provided with the low-temperature solder layer on the high-temperature solder layer; or, The high-temperature solder layer is provided on one of the first pad and the second pad, and the low-temperature solder layer is provided on the other of the first pad and the second pad and / or on the high-temperature solder layer.

9. The method for fabricating a semiconductor structure according to claim 1, characterized in that, After forming the connection structure, the method for fabricating the semiconductor structure further includes: An adhesive layer is filled between the first semiconductor component and the second semiconductor component.

10. The method for fabricating a semiconductor structure according to claim 1, characterized in that, After forming the first connection portion and before performing the second bonding process, the method for fabricating the semiconductor structure further includes: An adhesive layer is filled between the first semiconductor component and the second semiconductor component.

11. A semiconductor structure, characterized in that, The semiconductor structure is fabricated using the method for fabricating a semiconductor structure according to any one of claims 1-10, and the semiconductor structure comprises: A first semiconductor device, wherein a first pad is provided on the bonding surface of the first semiconductor device; The second semiconductor device is stacked with the first semiconductor device with their bonding surfaces facing each other, and the bonding surface of the second semiconductor device is provided with a second pad that is opposite to the first pad. A connection structure is provided between the first pad and the second pad. The connection structure includes a first connection part and a second connection part connected together, wherein the melting point of the first connection part is greater than the melting point of the second connection part.

12. The semiconductor structure according to claim 11, characterized in that, The first connecting part is an alloy, which includes a first metal material and a second metal material; the first metal material includes at least one of copper, tungsten or gold, the second metal material includes at least one of tin or indium, and the material of the second connecting part includes at least one of tin-lead alloy, tin-antimony alloy, indium-lead alloy or indium-antimony alloy.

13. The semiconductor structure according to claim 11, characterized in that, The first connecting portion surrounds the outside of the second connecting portion, and the two ends of the first connecting portion are respectively in contact with the first pad and the second pad; The two ends of the second connection portion are respectively in contact with the first pad and the second pad; or, the second connection portion has at least one, one end of each second connection portion is in contact with the first connection portion, and the other end of each second connection portion is connected to the first pad or the second pad.

14. The semiconductor structure according to claim 11, characterized in that, The first connecting portion and the second connecting portion are connected sequentially in the stacking direction of the first semiconductor device and the second semiconductor device; Alternatively, along the stacking direction of the first semiconductor device and the second semiconductor device, the first connection portion is connected between two second connection portions, and the two second connection portions are respectively in contact with the first pad and the second pad.

15. A microbump, characterized in that, The microbumps are formed on a semiconductor device, and the microbumps include: A high-temperature solder layer is disposed on the pads of the semiconductor device; A low-temperature solder layer is disposed on the high-temperature solder layer and is located on the side of the high-temperature solder layer away from the solder pad. The melting point of the low-temperature solder layer is lower than that of the high-temperature solder layer. The low-temperature solder layer is used to melt and solidify to form an alloy. The melting point of the alloy is higher than that of the high-temperature solder layer.

16. The microbump according to claim 15, characterized in that, The material of the low-temperature solder layer includes a physically composite first metal material and a second metal material, wherein the melting point of the second metal material is lower than the melting point of the high-temperature solder layer, and the melting point of the first metal material is higher than the melting point of the alloy. The first metal material includes at least one of copper, tungsten, or gold; the second metal material includes at least one of tin or indium; and the material of the high-temperature solder layer includes at least one of tin-lead alloy, tin-antimony alloy, indium-lead alloy, or indium-antimony alloy.

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