Electronic circuit for acquiring the threshold voltage of a power transistor

Abstract

The invention relates to a device (10, 20) for monitoring the health state of a power transistor, comprising: - means (8) for applying to the transistor a very slow trigger voltage (VGS); - means (12-22) for measuring the drop of the gate voltage (VGS) after the Miller plateau.

Description

Technical Field

[0001] This invention relates to the field of power electronics, and more particularly to the field of electrification and hybrid electric systems, especially to the field of electrification and hybrid electric systems in aviation. Background Technology

[0002] Against this backdrop, there is a need for efficient, integrated, reliable, and safe power electronic systems. Power modules for motor control are a critical function requiring significant investment of effort. Introducing wide-bandgap power semiconductor components, such as silicon carbide (SiC) MOSFET transistors (metal-oxide-semiconductor field-effect transistors), into power modules enables a 15% to 30% reduction in onboard mass and volume, and an improvement in electrical efficiency by 2 to 3 percentage points.

[0003] SiC MOSFETs are power semiconductor devices that offer numerous advantages over traditional silicon (Si) MOSFETs, such as higher performance, higher energy efficiency, and better high-temperature stability. However, the adoption of SiC MOSFETs in the aerospace industry still faces several challenges that limit their development and widespread deployment.

[0004] In particular, there is currently no means to non-invasively monitor the reliability of these transistors during continuous operation. This same problem is prevalent in semiconductor transistors based on wide-bandgap semiconductors (e.g., using GaN technology). The term "wide bandgap" should be understood as the energy gap or bandgap height Eg that separates the last occupied state of the valence band from the first free state of the conduction band; it is greater than the energy gap or bandgap height of silicon. Conventional silicon (Si) MOSFETs also suffer from the same problem.

[0005] However, monitoring the health of such transistors, especially wide-bandgap transistors, particularly SiC MOSFETs, is crucial for their adoption in applications requiring high reliability and potentially long lifespans, such as aerospace. This is because the performance of such transistors can degrade due to component aging during operation within power converters. These performance losses arise from changes in inherent physical parameters, particularly in the case of SiC MOSFETs, due to charge trapping within the silicon dioxide (SiO2) gate oxide layer (e.g., in the case of SiC MOSFETs) when defects are present at the interface with the SiC substrate.

[0006] Given the lower manufacturing quality of the gate oxide layer, which itself is subjected to greater electric field stress on SiC MOSFETs, these effects are more pronounced in SiC technology than in Si technology.

[0007] This is because in silicon MOSFETs, the gate oxide (SiO2) typically matches the crystal structure of silicon well. Silicon and silicon dioxide have a natural chemical affinity, which facilitates the growth of a uniform, defect-free natural gate oxide layer. In contrast, silicon carbide (SiC) has a different and more complex crystal structure than silicon. Due to the poor naturalness of the interface between SiC and SiO2, growing a high-quality gate oxide layer on SiC is more difficult.

[0008] The crystal defects in the gate oxide layer of Si MOSFETs are generally fewer and more stable. The fabrication technology of SiO2 on Si is highly mature, enabling the production of high-quality oxide layers with few defects. In the case of SiC MOSFETs, growing the gate oxide on SiC may more easily lead to defects. These defects may include oxygen vacancies, structural flaws, and recombination sites. They may be caused by differences in atomic mobility between SiC and SiO2, thermal stress during the manufacturing process, and other factors.

[0009] All these defects can lead to charge trapping in the gate oxide. This tunneling trapping can occur on the surface, at the SiC / SiO2 interface, or deeper within the oxide. The tunneling effect is a quantum process that allows electrons to "tunnel" through an energy barrier that is typically too high in silicon for electrons to cross. In the context of SiC MOSFETs, the tunneling effect occurs when channel electrons acquire enough kinetic energy under the influence of the gate voltage to pass through and be trapped within the thin gate oxide layer.

[0010] These trapping phenomena on SiC MOSFETs are complex and depend on the bias conditions of the gate oxide (DC component and AC component due to controlled chopping). These phenomena are further exacerbated at high operating temperatures. On one hand, trapping can lead to a decrease in the threshold voltage Vt. TH The channel resistance increases slowly but steadily; on the other hand, it leads to a decrease in the electron mobility µ in the channel. The combination of these two effects results in an increase in channel resistance, which in turn leads to an increase in conduction losses; and on the other hand, it leads to an increase in the magnitude of the Miller plateau, which reduces the switching speed (especially dv / dt during conduction, where lossy components dominate) and increases switching losses.

[0011] For the health of SiC MOSFETs, there are several secondary indicators: on-resistance R DSON And the duration and magnitude of the Miller plateau. While these quantities are also affected by transistor aging, they include several other components, each contributing to mask the inherent changes caused by the aging of those components themselves. Therefore, their relevance to tracking the health of transistors is questionable.

[0012] Other indirect indicators include gate leakage current I0 GSS and drain current I DSS Internal gate resistance R GINT (V) GS ) and characteristic C ISS =f(V) GS (See, in particular, A. El Boubkari, Rapid, Precises and Integrated CMOS Development for Optimal Switching and Internal Protection of Inverters with SiC MOSFET Modules [Development of Rapid, Precision and Integrated CMOS Functionality for Optimal Switching and Internal Protection of Inverters with SiC MOSFET Modules] (HAL Science Platform (hal.science), 2023)):

[0013] • Gate leakage current I GSS This represents an increase of several orders of magnitude between healthy components (hundreds of femtoamperes) and gate-crackled components (approximately 10 mA). Measuring this parameter requires extremely precise and stable differential measurements of the voltage across the external gate resistor, although I... GSS Not as a precursor to irreversible degradation, but as its ultimate indicator. This leakage current measurement as a precursor (before gate oxide cracking) is feasible thanks to a dedicated drive channel with a sensitivity of 30 nA, as described in application PCT / FR2023 / 051145. However, its implementation remains complex.

[0014] • Drain current tracking is based on the measurement of observable quantities on the power side (between the drain and the source) and must have an accuracy on the order of milliamperes, which makes it practically impossible in a converter.

[0015] It has been shown that by using a static characteristic analyzer (e.g., Keysight B1505A), V GS By scanning from negative to positive values, the voltage "flat band" shift of aging components can be found. This can be achieved by scanning R... GINT (V) GS By tracking changes in this value, simulated properties can be obtained. However, this method remains difficult to apply to airborne measurements.

[0016] The changes faithfully reproduce the main indicator of changes in component health status, which remains the threshold voltage V. THHowever, in current technology, when the transistor is integrated into a running power converter and is in chopper mode, this parameter is still not directly measurable in real time. Summary of the Invention

[0017] The present invention aims to solve all or some of the above-mentioned problems.

[0018] In particular, the present invention provides an electronic circuit for measuring the threshold voltage V of a transistor in real time. TH To monitor, for example, the health status of MOSFET power transistors within a power converter.

[0019] This invention particularly relates to a device for tracking or monitoring the health status of a MOSFET power transistor, comprising:

[0020] - Used to provide or apply the turn-on voltage (V) to the MOSFET power transistor. GS Devices comprising at least one resistor (R3, R4) forming an external gate resistance of at least 10 kΩ;

[0021] - Used to measure or estimate gate voltage (V) GS The device that descends after the Miller platform.

[0022] The first device can provide an "ultra-slow" turn-on voltage (V) to the MOSFET power transistor. GS ).

[0023] Transistors are, for example, types based on wide-bandgap semiconductors (e.g., utilizing SiC or GaN technology). The term "wide-bandgap" should be understood as the energy gap or bandgap height Eg that separates the last occupied state of the valence band from the first free state of the conduction band, and is greater than the energy gap or bandgap height of silicon. Alternatively, the transistor can also be a silicon (Si) MOSFET transistor.

[0024] Therefore, the present invention enables the measurement of the gate voltage (V) GS The threshold voltage of the transistor is estimated by the drop after the Miller plateau.

[0025] Therefore, the present invention provides a real-time monitoring device that can be used onboard. Integrating this type of device enables the detection of early signs of degradation and aging of MOSFETs (especially SiC MOSFETs), thereby allowing for rapid intervention to avoid more serious problems.

[0026] According to one embodiment, the monitoring device according to the present invention may include a means for detecting gate voltage (V GS The device or stage that has the zero-crossing point of the derivative of ).

[0027] Optionally, a method for transferring V can be provided. GS A device or comparison level that compares the value of the derivative with a comparison threshold.

[0028] Preferably, the comparison threshold is negative.

[0029] According to a particular embodiment, the apparatus or comparison stage includes means for forming a hysteresis.

[0030] The apparatus according to the invention may further include means for storing the decreased value.

[0031] For example, the device includes at least one sample-and-hold circuit for maintaining the decreased value.

[0032] Devices for storing the minimum value of the decrease may include capacitors. Furthermore, they may be associated with devices that form a switch.

[0033] The device according to the invention may further include a second means for applying a voltage to the MOSFET power transistor, the second means including at least one resistor having a lower value relative to the resistor forming the external gate resistance.

[0034] Such devices may also include means for controlling the first and second devices using pulse width modulation (PWM).

[0035] The device according to the invention may further include features for synchronizing with a current sensor to transmit the gate voltage (V) GS A device for measuring or estimating the drop after the Miller plateau in sync with the load current (which is then preferably zero).

[0036] The device according to the invention may further include a control signal (which may be from a digital control device) for applying a turn-on voltage (V) to the MOSFET power transistor. GS ) device.

[0037] The present invention also relates to a method for monitoring the health status of a power transistor by using the device described above and in the remainder of this application, such as a SiC MOSFET type, p-GaN HEMT type, or Si MOSFET type power transistor, or more generally any other technology of power transistor (providing a high nonlinearity between Cgd and voltage Vds) or Si MOSFET type power transistor.

[0038] The present invention also relates to a power converter or module comprising a plurality of power transistors and at least one device as described above and in the remainder of this application.

[0039] The present invention also relates to an aircraft comprising at least one power converter or module according to the present invention. Attached Figure Description

[0040] -[ Figure 1A ]、[ Figure 1C The diagram illustrates C. GD With V DS The dependency relationship between them is represented as V DS C functions GD curve( Figure 1A ), and the V of SiC MOSFET transistors DS ( Figure 1B ) and V GS ( Figure 1C How do they change over time?

[0041] -[ Figure 2A ]、[ Figure 2B ] indicates the driving voltage V DD For V GS The drop shape (dip) Figure 2A ) and V DS ( Figure 2B The impact of )

[0042] -[ Figure 3 The value V represents the difference between the new component with healthy oxides (curve I) and the stressed component with aged oxides (curve II). GS Waveform comparison;

[0043] -[ Figure 4 [Illustrative representation using V] GS The derivative and direct sampling of the measurement chain are used to simulate the descent.

[0044] -[ Figure 5A ]、[ Figure 5B ] represents V GS and (dV) GS Simulation results of / dt changing over time;

[0045] -[ Figure 6A ]、[ Figure 6B ] indicates and Figures 5A to 5B The same curve, and the output of the sample-and-hold circuit (EB);

[0046] -[ Figure 7A ]、[ Figure 7A1 ]、[ Figure 7B ]and[ Figure 7B1 ]、[ Figure 7C ]、[ Figure 7C1 This indicates one possible embodiment of a device for automatically storing falling objects;

[0047] -[ Figure 8 This schematically illustrates another possible embodiment of the device for storing the descent.

[0048] -[ Figure 9 This schematically illustrates a measurement chain that uses automatic storage during descent for simulated tracking.

[0049] -[ Figure 10A ]、[ Figure 10C ] represents V GS ( Figure 10A ) and (dV GS / dt)( Figure 10C Simulation results of the time-varying waveform, as well as the waveform of interest and the signals used to turn off the switch and turn off the sample-and-hold circuit. Figure 10B );

[0050] -[ Figure 11 ]and[ Figure 12 ] respectively represent Figure 4 and Figure 9 Detailed exemplary embodiments of the circuit;

[0051] -[ Figure 13A ]、[ Figure 13B ]、[ Figure 14A ]and[ Figure 14B This indicates the application of the present invention in pulse width modulation (PWM) control frames;

[0052] -[ Figure 15A ]、[ Figure 15B This indicates the application of the present invention in a three-phase inverter, which involves common-mode control of the low-side transistor (A) and the high-side transistor (B);

[0053] -[ Figure 16 This indicates that the present invention is applied to the switching according to the present invention near the zero point of the load current;

[0054] -[ Figure 17 ] indicates the gate electronic control circuit;

[0055] -[ Figure 18 ]express Figure 17 Example of a control timing diagram for a device;

[0056] -[ Figure 19 [This indicates an embodiment of measurement synchronization according to the present invention using a current sensor.] Detailed Implementation

[0057] This invention relates to a method for monitoring the health status of a power transistor, particularly based on a wide-bandgap semiconductor (e.g., SiC or GaN), comprising a bandgap or energy gap height Eg that separates the last occupied state of the valence band from the first free state of the conduction band, which is greater than the bandgap or energy gap height of silicon. For example, the power transistor is a SiC MOSFET type transistor, or a p-GaN HEMT (gallium nitride high electron mobility transistor), or a power transistor of any other technology (providing a high nonlinearity between Cgd and voltage Vds). However, the invention is also applicable to Si MOSFET type power transistors. In the following description, most of the description is given with respect to SiC MOSFET type transistors.

[0058] According to the present invention, this monitoring method involves monitoring its threshold voltage V. TH However, this quantity cannot be obtained directly. A relatively faithful reproduction of V TH The observable measure of the change is the Miller plateau during the switching period. The amplitude of this plateau depends on several other parameters, as shown in the following formula (1):

[0059] [Formula 1]

[0060]

[0061] Among them, V P It is the amplitude of the Miller platform, I CH It is the load current, G FS It is the transconductance of the transistor, C OSS It is the internal output capacitance of the MOSFET, V DS λ is the drain-source voltage, and λ is a parameter that reflects the "short-channel" effect of the SiC MOSFET and causes a change in the plateau slope.

[0062] To maintain only the effect of VTH on the Miller plateau, it is necessary to minimize the parasitic contribution to the plateau voltage, and therefore minimize I. CH (in order to minimize I) CH / G FS And to obtain a very large "dt" (in order to minimize dV) DS / dt), f(λ, V) DS ) is a parameter specific to transistors and cannot be changed.

[0063] For example, performing a very slow switch on a transistor results in a switching duration that is subsequently longer than when using a very high external gate resistor R. G (several kΩ, for example, R) G The nominal switching duration is longer when the resistance is 10kΩ, while the external gate resistance R of the "nominal" switch is longer. G The nominal value R GNOMFor example, approximately 10Ω: therefore, the switching hysteresis here is 1000 compared to the normal or nominal case (i.e., fast switching with low external gate resistance and zero load current). Then, the effect of parameters not of interest here on the plateau amplitude is minimized, and the plateau duration is increased so that it can be more easily read (e.g. on an oscilloscope) and / or extracted.

[0064] Therefore, for example, we expect R G (External gate resistance) is at least its nominal value R GNOM 100 times.

[0065] In other words, it is expected that by changing the external gate resistance R G The value of (i.e., the resistance applied to the gate of the transistor) is used to slowly or very slowly drive the transistor to switch (while R...). Gint This indicates the internal gate resistance, which is inherent to the transistor and its technology.

[0066] Therefore, during the Miller plateau, the buffer supplies internal gate-source capacitance C. GS The introduced charge is greater than the internal gate-drain capacitance C. GD The charge pumped out.

[0067] For example, according to one embodiment, the current I delivered to the gate by the driver G It can be controlled by the gate drain current I CGD This increase leads to the following situation (the value is specific to the SiC MOSFET component (C2M0080120D) used during the test):

[0068] [Formula 2]

[0069]

[0070] This leads to: R G >>750Ω; therefore, R G It can be equal to approximately 10kΩ.

[0071] With gate resistance R G Compared to a normal 10Ω switch, the switching speed is reduced by about 1000 times.

[0072] Figure 17 An example of gate control electronics 100 for a power transistor 32 (e.g., a SiC MOSFET) is presented. This gate control electronics includes:

[0073] On one hand, a first conventional control device (buffer) 15 (also referred to as "fast") can be set to high impedance via a dedicated control input 17 ("enable fast"). These devices 15 are associated with gate resistors R1-R2 (R1 for turning on and R2 for turning off), which are low-resistance resistors (e.g., typically 10Ω).

[0074] On the other hand, a second device (buffer) 12 (also referred to as "ultra-slow") is connected in parallel with device 15 to the gate of the power transistor 32 to be controlled. These devices 15 are associated with gate resistors R3-R4, which are, for example, 1000 times larger than R1 and R2 (in this example, the values ​​of R3 and R4 are 10kΩ). The power supply (V...) of these two devices 12, 15... DDx and V SSx They can be adjusted independently of each other.

[0075] Figure 17 This refers to a so-called "multi-buffer" architecture, which includes devices or circuits 12, 15 mounted in parallel for controlling power transistors 32 (e.g., such as...). Figure 15A and Figure 15B The power converter shown in the diagram has its gates tightly electronically controlled. The diagram illustrates a system specifically designed for measuring and monitoring V. TH (V) GSTH (This is a control channel (including device 12 and resistors R3 and R4) for tracking the health status of transistors.)

[0076] The device according to the invention, for example, Figure 17 The device is suitable for measuring "high-side" components (e.g., Figure 15A Transistor 421) and "low-side" components (e.g., Figure 15A Transistor 422).

[0077] Figure 18 express Figure 17 An example of a control timing diagram for a device is provided, in which an "ultra-slow" mode is activated when the "fast" mode is disabled, and vice versa. Measurements according to the invention can be performed when the "ultra-slow" mode is activated.

[0078] The inventor observed that V GS (exist Figure 1C The value in the middle corresponds to the drop (dip) that occurs after the Miller plateau.

[0079] This drop occurs at low drain-source voltage V DS (exist Figure 1B (Indicated in the middle) At the internal drain-gate capacitance C GD (exist Figure 1AIn the highly nonlinear region (represented in the figure), starting from time t1, this large capacitance change subsequently generates a charge pump effect from the gate to the drain, thereby affecting the Vt through the high external gate resistance (here: 10kΩ). GS A decline is formed in the middle, and this decline occurs in Figure 1C As can be seen in the text.

[0080] This decline occurred when C GD When it becomes highly nonlinear, it corresponds to the switching dV DS The time t1 at which / dt ends. Therefore, the charge drawn from the gate to the drain will affect C. GS Discharge, thereby helping to reduce V GS On the other hand, the transistor's control circuitry (or "gate driver") injects charge into the gate through an external gate resistor. These two opposing phenomena compete with each other, and when C... GS When the change stops, the contribution of the control circuit becomes dominant, which allows the gate load to be restored and continued, thus enabling switching.

[0081] When the voltage V is reduced DD Experiments were conducted under the condition of (control circuit power supply voltage). These experiments demonstrate the effect of reduced charge contribution from the control circuit on the aforementioned descent phenomenon. Clearly, the minimum descent approaches the intrinsic threshold V. TH This can be explained by the fact that at the end of the platform, that is, where the descent begins, C... GD The current I drawn from the gate to the drain CGD Through the transistor channel, its formation depends on the gate bias V. GS . When I CGD When the gate is discharged, the channel narrows (tightens) and limits the current that can pass through the channel: this slows down the phenomenon and prolongs the duration of the drop.

[0082] This is effective and in V DD As the voltage decreases, because the driver injects very little charge into the gate, this allows the voltage drop to approach and reach the transistor's gate voltage V at the channel on-limit. TH ,like Figure 2A and Figure 2B The diagrams illustrate various voltages between 10V and 20V. DD Value, V GS ( Figure 2A In this diagram, SMU stands for "Source Measurement Unit" and V DS ( Figure 2B The changes are as indicated in these figures.

[0083] As a result, the decrease in gate voltage appears to be related to V THThe image corresponds to a reliable and novel low-noise specification. This drop can be defined as the difference between the level of the Miller plateau and the absolute minimum of the drop. For measuring or estimating the gate voltage drop, favorable conditions are preferably achieved using the following methods:

[0084] - The switching is approximately 1,000 times slower than conventional switching; this can be achieved by using an external gate resistor R that is 1,000 times larger than nominally possible. G To obtain;

[0085] - Zero load current during this conduction period; Figures 15A to 16 The figure illustrates an embodiment of monitoring the health status of transistors within a three-phase power converter for measurement under zero-load current. Figures 15A to 15B The diagram illustrates the simultaneous ultra-slow conduction of three low-side transistors (15A) or three high-side transistors (15B) within a three-phase power inverter. This control strategy allows current to be avoided from flowing through the conducting transistors. Figure 16 The figure illustrates the use of a current sensor 43 on one phase of the motor to synchronize ultra-slow measurements with load current suppression;

[0086] - Reduce the power supply voltage of driver 12 ( Figure 17 V in DD1 For example, the power supply voltage is less than or equal to 10V; while the nominal or "normal" voltage of driver 12 (e.g., between 15V and 20V) is greater than this decrease. This is because, as explained above, at a power supply voltage V... DD As the voltage decreases, the minimum decrease approaches the transistor's inherent threshold. In other words, the decrease, as an indicator of health status, approaches V. TH This leads to a near-physical approximation of charge trapping; the index then becomes increasingly relevant. However, this requires an adjustable power supply V. DD This necessitates the use of additional components, thus making its implementation more complex.

[0087] In nominal V DD (≈20V; in this case, V) DD In the case of no decrease, the change in this decrease (in) Figure 3 The expression is represented as a function of time, where curve I represents these changes in a new transistor with healthy oxides, and curve II represents these changes in a stressed component with aged oxides, relative to V. TH The changes are consistent and further indicate the degradation state of the gate oxide layer.

[0088] The following is a simulated example of tracking the decrease in gate voltage.

[0089] The first embodiment utilizes direct sampling, based on V GS The derivative of V:GS The amplitude of the platform will increase over time depending on the trapping state of the oxide layer, but its overall dynamic characteristics will remain unchanged, such as Figure 3 As shown, this allows for comparison of a new component with healthy oxides (curve I) with a stressed component with aged oxides (in V). GS After being subjected to stress at 35V for 24 hours, the V curve between curves II) GS Waveform.

[0090] Therefore, V GS Finding the zero-crossing point of the derivative appears to be a way to detect the occurrence of a descent. Comparing this derivative with a threshold (preferably an adjustable threshold) allows for the generation of a function for V. GS The control commands for the sample-and-hold circuit. This method is used in V GS The moment when the derivative intersects the threshold is relative to V GS The values ​​are sampled and stored.

[0091] Figure 4 A diagram of the circuit or device 10 used to implement this solution is provided, in which:

[0092] - Devices 8 (control isolators, optocouplers) isolate digital control commands from the rest of the electronic circuitry; these devices 8 form an interface or connection between the digital control commands and the electronic components of the circuitry; they provide “ultra-slow” turn-on control signals; the control signals used to activate these devices are sent by the digital control device (e.g., FPGA);

[0093] - Device 12 (or buffer) controls the transistor 32 under test and allows it to conduct slowly; the gate control signal is output from device 12 and passes through the external gate resistor 12', and the signal V from 12'... GS This includes information about the health status of the transistor being tested;

[0094] - Devices 34 form an instrumentation amplifier (these devices 34 allow for signal replication and isolation), which allows for impedance matching of V GS Reading, reconstruction, and processing are performed; in fact, with such a high gate resistance (10kΩ), even a very small gate leakage current path becomes non-negligible. Therefore, a simple resistor divider bridge cannot be considered for sensing V. GS This is because such a voltage divider bridge will cause current leakage when the total resistance is low, and will be sensitive to noise when the resistance is high.

[0095] -Then, the V obtained at the output of device 12 GS Image application derivative calculation level 14;

[0096] - Threshold comparison level 16 enables the derivative to be compared with a predetermined threshold;

[0097] - The means 18 for forming a latch enables the generation of a control edge based on the comparison result of a threshold and a derivative and maintains it in a specific state.

[0098] The output of device 18 and the V obtained at the output of device 12 GS The data is applied to the input of the sample-and-hold circuit 20. Afterwards, V dip The (one or more) values ​​can be:

[0099] - Used as an indicator of aging changes in transistor 32;

[0100] - and / or digitized via an analog-to-digital converter (ADC) for processing, and then optionally stored in a digital control unit (e.g., FPGA type);

[0101] - Compare over time to track changes in the health status of the transistor 32 being tested.

[0102] exist Figure 11 and Figure 12 In, and the following combinations of these Figure 11 and Figure 12 Exemplary embodiments of various devices 12-23 are given.

[0103] Simulations are performed using ideal components (which come directly from the LTspice library included in the software) with the help of the "LTspice" software.

[0104] The simulation results are in Figure 5A and Figure 5B The diagram shows an "ultra-slow" turn-on process performed on a test bench, where the external gate resistor R... G Very high (e.g., 1,000 times larger than normal or nominal resistance, the value of which is typically around 10Ω), R3 and R4 (as described above) meet pre-defined conditions (e.g., a coefficient of 1,000 as mentioned above), such as R G =10kΩ. Extract V from the oscilloscope as a point file. GS The load curve (its time variation in) Figure 5A (This is represented in the image), and then imported into the simulation software as a voltage source curve. Figure 5B V represents GS The derivative (the derivative obtained at the output of differentiator 14) changes with time.

[0105] As in Figure 5A and Figure 5B As can be seen from this, V GSComparing the derivative of V to a 0V threshold can lead to the risk of false triggering and unwanted edges, especially in the plateau region. This is why a negative safety threshold (e.g., -0.6V) is chosen. This allows for the establishment of a safety margin relative to a 0V threshold, thus avoiding false triggering and obtaining a clear intersection with the negative part of the derivative. This negative part corresponds to V. GS The descent begins in the decreasing zone.

[0106] exist Figure 6A and Figure 6B The waveform 21 at the output of the sample-and-hold circuit 23 (EB) is shown in the figure. When its clock input receives a control edge, its output is maintained at a value (near the falling edge).

[0107] Therefore, it is readily apparent that the output of the sample-and-hold circuit 23 is held at a voltage value close to the falling voltage. The advantage of this "direct" method is its reliance on a small number of components. However, to obtain the most reliable measurement results possible, it is desirable that the control edge of the sample-and-hold circuit occurs at the minimum value of the falling voltage. This can be achieved by adjusting the threshold and bandwidth of the differentiator stage 14.

[0108] Another embodiment employs descending storage, which is based on automatically storing the minimum value of the descending value. It is in Figures 7A to 9 The Chinese side indicated that...

[0109] Figure 7A The device 22a for storing the decrease is schematically shown. This device includes two reverse-biased diodes 221 and 223 arranged in parallel, and a capacitor 224 for storing the decrease value.

[0110] In the first step ( Figure 7A , Figure 7A1 In ), V represents GS The signal charges capacitor 224 until the Miller plateau ends.

[0111] In the second step ( Figure 7B , Figure 7B1 In the figure, the voltage across capacitor 224 decreases, corresponding to the drop after the Miller plateau.

[0112] Finally, in the third step ( Figure 7C , Figure 7C1 In ), when V GS When the charge rises again, capacitor 224 is recharged through forward diode 221.

[0113] In other words, when V GS When it rises again, due to the storage capacitor 224 C MEM The device 22a cannot properly store the drop because it is recharged by the forward diode 221.

[0114] As an alternative, such as Figure 8 As illustrated, therefore, a device 22 including means forming a switch 226 is used upstream of the forward diode 221; these means 226 enable the circuit to be dynamically disconnected in order to prevent capacitor 224 C from MEM An unintended recharging occurs, causing the voltage across the capacitor (excluding leakage current) to remain at a decreased value. For example, from... Figure 7C1 As can be understood, the control of disconnecting device 226 is preferably performed before region 3, and only if V GS >V DIP It can be done immediately.

[0115] like Figure 9 As shown, the switch disconnect command will be generated by latch 18 of the trigger chain. Figure 8 Indicates formation Figure 9 The contents of the device 22 used to store the descending units. Figure 9 The other components have been described above, and reference numeral 32 again indicates the transistor being tested.

[0116] In this configuration, the input to the sample-and-hold circuit 23 (EB) is now the storage capacitor C. MEM The voltage, which corresponds to the minimum drop. Combined with the above... Figure 4 Compared to the described "direct" solution, an analog preprocessing stage is added (for storing the dropout), and this analog preprocessing stage allows the dropout value to be provided at the input of the sample-and-hold circuit 23. Once the dropout value has been obtained by C... MEM The sample-and-hold circuit 23 will receive the shutdown edge, and its output will remain as close as possible to the falling true value.

[0117] The diodes 221 and 223 used in the falling memory stage are preferably diodes compensated by an OP-AMP (operational amplifier) ​​to overcome their threshold voltage.

[0118] Figures 10A to 10C Simulation results show that C MEM The voltage correctly replicates V GS And remain at the decreasing value. For example, in Figure 10B As can be seen, the switch disconnect command (used to prevent V) MEM (The rise again) is sent at the start of the fall. A delay can be introduced on the same signal sent to the shutdown port of sample-and-hold circuit 23 (see [link]). Figure 10A (Implemented through analog means, such as using an RC delay circuit, or digitally at the digital control unit (using latches and digital control units), so that V) MEM Having enough time to decrease to V DIP .

[0119] Figure 11 Indicates the use of simulation to track V GS A detailed simulation embodiment of the descent circuit 10. Figure 12 Indicates the use of simulation to track V GS A detailed simulation embodiment of the descent circuit 20, wherein the descent value is stored.

[0120] exist Figure 11 and Figure 12 middle:

[0121] - The latching device 18 allows the generation of the control edge of the sample-and-hold circuit 23 ( Figure 11 ), and control commands for storing the analog switch of the descending unit 22 ( Figure 12 ) and the "Sample_Ready" signal via isolator 27 ( Figure 11 , 12 The control edge of the chain is used to instruct the digital control unit (e.g., FPGA) to begin acquiring the falling value extracted from the chain's output.

[0122] - The drop voltage extraction chain is illustrated as having a buffer 12 for gate control of a power MOSFET 32 with a high gate resistance;

[0123] - A controlled current source 25 (≈2mA) enables conduction so that C can be accurately measured. GD The C GD Proportional to the duration of the platform;

[0124] - The state of the latching device 18 is initialized based on the signal of the ultra-slow conduction device 8;

[0125] - The derivative comparator stage 16 is equipped with a hysteresis device to avoid possible bounce;

[0126] - Figure 32 indicates the transistor under test;

[0127] - Reference numeral 34 indicates an amplifier arranged at the input of the comparator 14.

[0128] The following combination Figures 13A to 14B The implementation of measuring the falling voltage within a pulse width modulation (PWM) control frame according to the present invention will be described.

[0129] In the case of open circuit and zero load current, during active conduction switching with a high duty cycle, a (according to the invention) "ultra-slow" measurement (of the falling voltage with high gate resistance) can be periodically performed within a PWM frame to allow for V GS The slow charging and drop in measurement provide sufficient time. Figure 13A An example of ultra-slow measurement of the high-side component is given in the paper.

[0130] In order to measure the lower side components ( Figure 13B ( ), we need to wait for the modulation half-cycle so that the duty cycle of the "low side" is at its maximum value.

[0131] To minimize the duration of the measurement and limit its impact on the PWM control frame, Figures 14A to 14B The measurement using a switched gate resistor is illustrated. Using this method, only the plateau and drop regions of interest are slowed down and extended to facilitate measurement and extraction, and to improve the signal-to-noise ratio in that region. This type of "ultra-slow" switching (according to the invention) is called condensed, allowing the drop to be measured even within the chopping cycle (e.g., if the chopping frequency f...). DEC =20 kHz, with period T DEC =50 µs, then measurements can be performed within a maximum of 20 µs. See [reference needed]. Figures 6A to 7C ).

[0132] The following discussion Figure 15A , Figure 15B and Figure 16 The figure illustrates an embodiment for monitoring the health status within a three-phase power converter, allowing measurements to be taken at zero load current.

[0133] Figures 15A to 15B The application of the measurements according to the present invention in common-mode control (zero speed) of a three-phase inverter is presented.

[0134] The switching mechanism according to the invention (referred to as an "ultra-slow" switch) uses three "low-side" MOSFETs 422, 424, and 426 ( Figure 15A Simultaneously on the three "high-side" MOSFETs 421, 423, and 425, and then on the other three. Figure 15B This is performed simultaneously on all three MOSFETs. This allows for switching on without load current that would interfere with the measurement of the dropout. It also provides information about the health status of the three MOSFETs at the same time.

[0135] More precisely, when motor 40 is connected to inverter 42 (including transistors 421-426), it can suppress the current in each phase of the motor, thereby returning to the above-mentioned combination. Figures 13A to 14B The situation described.

[0136] To this end, common-mode control is applied to transistors 421-426, thereby suppressing all voltages formed across motor 40 and bringing the current in each phase towards zero. The motor is preset to zero speed. Once the current is suppressed, the operation combined with the above can be performed. Figures 13A to 14BThe process described is the same as or similar to the process described above; then, the above (e.g., combined with...) Figure 11 or Figure 12 The device described herein is applied to each of transistors 421 to 426.

[0137] Figure 16 The application of the monitoring according to the invention in a “super slow” switch near zero load current is shown: when the motor 40 is started and when there is current in each phase, the “super slow” switch as described above can be performed by synchronizing the process with the current zero crossing point: the measurement according to the invention (referred to as “super slow”) is synchronized with the current sensor 43. Figure 19 This illustrates an embodiment of measurement synchronization according to the invention using this current sensor 43 as described above. The signal from the current sensor is compared to a threshold by the comparison device 45, then a control edge is generated by the device 47, and the control edge is sent to the digital control device 49. Other components 8, 12, and the measurement chain 10 in this figure... Figure 11 ) or 20 ( Figure 12 The above has already been described. Reference numeral 32 again indicates the transistor under test.

Claims

1. A device for tracking the health state of a MOSFET power transistor (32), the device comprising: - Used to apply the turn-on voltage (V) to the MOSFET power transistor. GS The first devices (8, 12) of the transistor include at least one resistor (R3, R4) forming an external gate resistance of at least 10 kΩ to be applied to the gate of the transistor. - Used to measure gate voltage (V) GS The descending device (12-22) following the Miller platform.

2. The device of claim 1, comprising a function for detecting gate voltage (V GS The order of the derivative of ) at the zero-crossing point (14).

3. The device according to claim 2, further comprising a comparator stage (16) for converting V GS The value of the derivative is compared with the comparison threshold.

4. The device according to claim 3, wherein the comparison threshold is negative.

5. The device according to any one of claims 3 or 4, wherein the comparator stage (16) includes means (161) for forming a hysteresis.

6. The device according to any one of claims 1 to 5, comprising means (23, 22, 22a) for storing the decreased value.

7. The device of claim 6, comprising at least one sample-and-hold circuit (23) for maintaining the decreased value.

8. The device according to any one of claims 6 or 7, wherein the means for storing the minimum value of the decrease comprises a capacitor (224).

9. The device according to claim 8, wherein the means for storing the minimum value of the decrease includes means for forming a switch (226).

10. The device according to any one of claims 1 to 9 further includes a second means (15) for applying a voltage to a power MOSFET transistor (32), the means including at least one resistor (R1, R2) having a lower value relative to the resistor forming the external gate resistor (R3, R4).

11. The device of claim 10, further comprising means for controlling the first device (8, 12) and the second device (15) using pulse width modulation (PWM).

12. The device according to any one of claims 1 to 11, further comprising providing a control signal for applying a turn-on voltage (V) to the MOSFET power transistor (32). GS ) device (8).

13. The device according to any one of claims 1 to 12, further comprising means (45, 47, 49) for synchronizing with the current sensor (43).

14. A method for monitoring the health status of, for example, a SiC MOSFET type or a p-GaN HEMT type power transistor or a Si MOSFET type power transistor by using a device according to any one of the preceding claims.

15. A power converter or module comprising a plurality of power transistors (421-426) and at least one device according to any one of claims 1 to 13, the device being coupled to at least one of the transistors.

16. An aircraft comprising at least one power converter or module according to claim 15.

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