Logical channel priority based on synchronization delay status

Abstract

Various aspects of the present disclosure relate to logical channel prioritization based on synchronization delay status. In an aspect, a UE determines a synchronization delay status of data in a first synchronization transmission set. In turn, the UE prioritizes transmission of the data based on the synchronization delay status of the data.

Description

Technical Field

[0001] This disclosure relates to wireless communications, and more specifically to user equipment (UE) and methods for supporting logical channel priority (LCP) based on synchronization delay state. Background Technology

[0002] A wireless communication system may include one or more network communication devices (such as base stations), which may also be referred to as eNodeB (eNB), next-generation NodeB (gNB), or other suitable terms. Each network communication device (such as a base station) may support wireless communication with one or more user communication devices, which may also be referred to as UE, or other suitable terms. The wireless communication system may support wireless communication with one or more user communication devices by utilizing the resources of the wireless communication system (e.g., time resources (e.g., symbols, time slots, subframes, frames, etc.) or frequency resources (e.g., subcarriers, carriers)). Furthermore, the wireless communication system may support wireless communication across a variety of radio access technologies, including third-generation (3G) radio access technology, fourth-generation (4G) radio access technology, fifth-generation (5G) radio access technology, and other suitable radio access technologies beyond 5G (e.g., sixth-generation (6G)).

[0003] Haptic and multimodal communication services can be applied across a wide range of fields, including industry, robotics and telepresence, virtual reality, augmented reality, healthcare, road transportation, serious gaming, education, culture, and smart grids. These services enable applications to communicate information more effectively from more than one source of input and / or output to more than one destination. Inputs and outputs can be different modalities, which may include at least one of the following: video / audio media; information about the environment received by sensors, such as brightness, temperature, humidity, etc.; or tactile (or haptic) data, which can be sensations upon touching a surface (such as pressure, texture, vibration, temperature), or kinesthetic sensations (such as gravity, tension, position awareness).

[0004] For immersive multimodal virtual reality (VR) applications, synchronization between different media components is crucial to avoid negative impacts on the user experience (i.e., viewers detect a lack of synchronization), especially when the synchronization threshold between two or more modalities is less than the application's latency key performance indicator (KPI).

[0005] The Logical Channel Priority (LCP) process does not consider synchronization delay status, but rather the priority of logical channels. When the remaining synchronization delay of the data on the first logical channel is below a threshold, and the priority of the first logical channel is lower than that of the second logical channel which does not have synchronization delay requirements, the data on the first logical channel may not be multiplexed into the uplink (UL) licensed Media Access Control (MAC) Protocol Data Unit (PDU) during MAC PDU assembly, and the data may be discarded. Therefore, the user experience is affected. Summary of the Invention

[0006] This disclosure relates to UEs and methods that support logical channel prioritization based on synchronization delay states. These UEs and methods enable logical channel prioritization based on synchronization delay states, thereby improving the user experience.

[0007] Some implementations of the UE described herein may include a processor and a transceiver coupled to the processor, wherein the processor is configured to: determine the synchronization delay state of data in a synchronized transmission set; and prioritize data transmission based on the synchronization delay state of the data.

[0008] In some implementations, the processor is configured to prioritize data transmission based on the synchronization delay state of the data by prioritizing the transmission of a first type of data in the synchronization transmission set, wherein the synchronization delay state includes a first remaining synchronization delay of the first type of data, the first remaining synchronization delay of the first type of data being lower than a first threshold.

[0009] In some implementations, the processor is configured to prioritize data transmission based on the data's synchronization delay state and a value maintained for the first logical channel (LCH) containing the data.

[0010] In some implementations, the processor is configured to prioritize data transmission based on the data's synchronization delay state, regardless of the value maintained for the first LCH containing the data.

[0011] In some implementations, the processor is configured to prioritize data transmission by one of the following: prioritizing the transmission of data in a first LCH, wherein the first LCH has data of a first type and the first residual synchronization delay of the data of the first type is less than a first threshold; prioritizing the transmission of all data in the synchronization transmission set; or prioritizing the transmission of data of the first type in the synchronization transmission set.

[0012] In some implementations, the processor is configured to prioritize the transmission of first-type data by increasing at least the first priority of the first-type data to the target priority.

[0013] In some implementations, the processor is also configured to: receive configuration for a target priority from a network entity via a transceiver; and determine the target priority based on that configuration.

[0014] In some implementations, the configuration for target priority includes one of the following: absolute target priority value, priority offset value, or factor.

[0015] In some implementations, the processor is configured to increase at least a first priority of first type data to a target priority by one of the following: increasing a second priority of a first LCH to the target priority, wherein the first LCH has first type data; increasing only the first priority of first type data to the target priority; or increasing a third priority of a synchronization transport set to the target priority, wherein the synchronization transport set includes first type data.

[0016] In some implementations, both the first LCH and the second LCH have data of a first type, and the first LCH has a synchronization transport set; and the processor is configured to prioritize the transmission of the first type of data in the synchronization transport set by prioritizing the transmission of the first type of data in the first LCH based on determining one of the following: a first priority of the first LCH is higher than a second priority of the second LCH; or a first residual synchronization delay of the first type of data in the first LCH is less than a second residual synchronization delay of the first type of data in the second LCH.

[0017] In some implementations, the processor is also configured to receive a first indication from a network entity via a transceiver, the first indication indicating whether data should be prioritized for transmission based on the synchronization delay state of the data.

[0018] In some implementations, the data includes a first type of data, wherein the first residual synchronization delay of the first type of data is lower than a first threshold among a plurality of thresholds.

[0019] In some implementations, the processor is configured to prioritize data transmission by: receiving a second indication from a network entity via a transceiver, the second indication specifying the priority ordering of transmissions of a first type of data based on a first threshold; and prioritizing the transmissions of the first type of data based on the second indication and the first threshold.

[0020] In some implementations, the data also includes a third type of data, where the third remaining time of the third type of data is lower than the second threshold among multiple thresholds.

[0021] In some implementations, the processor is configured to prioritize data transmission by increasing the first priority of a first type of data to a first target priority; and increasing the second priority of a third type of data to a second target priority.

[0022] In some implementations, the first logical channel (LCH) has a first type of data, and the second LCH has a third type of data.

[0023] In some implementations, the first logical channel (LCH) has both first-type data and third-type data.

[0024] In some implementations, the processor is configured to prioritize data transmission by prioritizing the transmission of one of the first and third types of data.

[0025] Some implementations of a UE described herein may include a processor and a transceiver coupled to the processor, wherein the processor is configured to: determine the latency state of data based on at least one of a plurality of thresholds; and prioritize data transmission based on one of the plurality of thresholds.

[0026] In some implementations, the processor is configured to maximize data transmission by one of the following: maximizing the transmission of data in a first logical channel (LCH), wherein the first LCH has data of a first type and the first residual synchronization delay of the data of the first type is less than a first threshold; maximizing the transmission of all data in the synchronized transmission set; or maximizing the transmission of data of the first type in the synchronized transmission set.

[0027] Some implementations of the UE described in this document may include a processor and a transceiver coupled to the processor, wherein the processor is configured to: determine the synchronization delay state of data in a synchronized transmission set; and maximize data transmission based on determining that uplink grant is sufficient to accommodate the data.

[0028] Some implementations of the methods described in this paper may include: determining the synchronization delay state of data in a synchronized transmission set; and prioritizing data transmission based on the synchronization delay state of the data.

[0029] Some implementations of the methods described in this paper may include: determining the latency state of data based on at least one of a plurality of thresholds; and prioritizing data transmission based on one of a plurality of thresholds.

[0030] Some implementations of the methods described in this paper may include: determining the synchronization delay state of data in a synchronized transport set; and maximizing data transmission based on determining that uplink grant is sufficient to accommodate the data.

[0031] Some implementations of the processor described herein may include at least one memory and a controller coupled to the at least one memory and configured such that the controller: determines the synchronization delay state of data in a synchronized transmission set; and prioritizes the transmission of data based on the synchronization delay state of the data.

[0032] Some implementations of the processor described herein may include at least one memory and a controller coupled to the at least one memory and configured such that the controller: determines the latency state of data based on at least one of a plurality of thresholds; and prioritizes data transmission based on one of the plurality of thresholds.

[0033] Some implementations of the processor described herein may include at least one memory and a controller coupled to the at least one memory and configured such that the controller: determines the synchronization delay state of data in the synchronous transmission set; and maximizes data transmission based on determining that the uplink grant is sufficient to accommodate the data.

[0034] It should be understood that the summary portion is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0035] Figure 1 An example of a wireless communication system supporting logical channel priority based on synchronization delay state is illustrated in accordance with various aspects of this disclosure;

[0036] Figure 2 The illustration shows an example of traditional logical channel priority.

[0037] Figure 3 The diagram illustrates a flowchart of a MAC PDU process for multiplexing logical channels according to various aspects of this disclosure;

[0038] Figure 4 The diagram illustrates a signaling diagram that shows an example process supporting logical channel priority based on synchronization delay state according to various aspects of this disclosure;

[0039] Figure 5 Examples of synchronous transport sets according to some implementations of this disclosure are illustrated;

[0040] Figure 6 and Figure 7The flowcharts illustrate methods for supporting logical channel priority based on synchronization delay state according to various aspects of this disclosure.

[0041] Figure 8 An example of first LCH data according to various aspects of this disclosure is illustrated;

[0042] Figure 9 The diagram illustrates a flowchart of a method for supporting logical channel priority based on synchronization delay state according to various aspects of this disclosure;

[0043] Figure 10 The diagram illustrates a signaling diagram that shows an example process supporting logical channel priority based on synchronization delay state according to various aspects of this disclosure;

[0044] Figure 11A , Figure 11B ,as well as Figure 11C Examples of first LCH data according to various aspects of this disclosure are illustrated respectively;

[0045] Figure 12 The diagram illustrates a signaling diagram that shows an example process supporting logical channel priority based on synchronization delay state according to various aspects of this disclosure;

[0046] Figure 13 The illustration shows an example of a device that supports logical channel priority based on synchronization delay state, according to some aspects of this disclosure;

[0047] Figure 14 The illustration shows an example of a processor supporting logical channel priority based on synchronization delay state according to various aspects of this disclosure; and

[0048] Figure 15 , Figure 16 and Figure 17 The flowcharts illustrate methods for supporting logical channel priority based on synchronization delay state according to various aspects of this disclosure. Detailed Implementation

[0049] The principles of this disclosure will now be described with reference to some embodiments. It should be understood that these embodiments are described for illustrative purposes only and to assist those skilled in the art in understanding and implementing this disclosure, and do not impose any limitation on the scope of this disclosure. The disclosure described herein can be implemented in various ways other than those described below.

[0050] In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0051] References to "an embodiment," "example embodiment," "embodiment," "some embodiments," etc., in this disclosure indicate that the described embodiments(s) may include a particular feature, structure, or characteristic, but not every embodiment must include that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same(s) embodiments(s). Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, those skilled in the art will recognize that in conjunction with other embodiments (whether explicitly described or not) such a feature, structure, or characteristic may affect such a feature, structure, or characteristic within the scope of their knowledge.

[0052] It should be understood that although the terms “first” and “second” may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may also be referred to as a second element without departing from the scope of the embodiments, and similarly, a second element may also be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the listed terms.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” used herein also include the plural forms. Furthermore, it should be understood that the terms “comprises,” “comprising,” “has,” “having,” “includes,” and / or “including”, when used herein, specify the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof.

[0054] Various aspects of this disclosure are described in the context of wireless communication systems.

[0055] Figure 1An example of a wireless communication system 100 supporting logical channel priority based on synchronization delay state is illustrated according to various aspects of this disclosure. The wireless communication system 100 may include one or more network entities 102 (also referred to as network devices (NEs)), one or more terminal devices or UEs 104, a core network 106, and a packet data network 108. The wireless communication system 100 may support various radio access technologies. In some implementations, the wireless communication system 100 may be a 4G network, such as a Long Term Evolution (LTE) network or an Advanced LTE (LTE-A) network. In some other implementations, the wireless communication system 100 may be a 5G network, such as an NR network. In other implementations, the wireless communication system 100 may be a combination of 4G and 5G networks, or other suitable radio access technologies, including IEEE 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), and IEEE 802.20. The wireless communication system 100 may support radio access technologies beyond 5G. In addition, the wireless communication system 100 can support technologies such as time division multiple access (TDMA), frequency division multiple access (FDMA), or code division multiple access (CDMA).

[0056] Network entity 102 can be distributed throughout a geographical area to form wireless communication system 100. One or more of the network entities 102 described herein can be, include, or may be referred to as network nodes, base stations (BS), network elements, radio access network (RAN) nodes, base transceiver stations, access points, NodeBs, eNodeBs (eNBs), next-generation NodeBs (gNBs), or other suitable terms. Network entity 102 and UE 104 can communicate via communication link 110, which can be a wireless or wired connection. For example, network entity 102 and UE 104 can perform wireless communication (e.g., receive signaling, send signaling) via a Uu interface. Network entity 102 can be collectively referred to as network entity 102, or can be referred to as network entity 102 individually. In the following, some implementations of this disclosure will be described using base stations as examples of network entity 102. Therefore, network entity 102 can be used interchangeably with network entity 102.

[0057] Network entity 102 may provide a geographic coverage area 112 for which network entity 102 supports services (e.g., voice, video, packet data, messaging, broadcasting, etc.) for one or more UEs 104 within the geographic coverage area 112. For example, network entity 102 and UE 104 may support wireless communication of signals associated with services (e.g., voice, video, packet data, messaging, broadcasting, etc.) based on one or more wireless access technologies. In some implementations, network entity 102 may be mobile, for example, a satellite associated with a non-terrestrial network. In some implementations, different geographic coverage areas 112 associated with the same or different radio access technologies may overlap, but different geographic coverage areas 112 may be associated with different network entities 102. The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0058] One or more UEs 104 may be distributed throughout the geographic area of ​​the wireless communication system 100. UE 104 may include or be referred to as a mobile device, wireless device, remote device, remote unit, handheld device, subscriber device, or some other suitable term. In some implementations, UE 104 may be referred to as a unit, station, terminal, or client, etc. Alternatively or additionally, UE 104 may be referred to as an Internet of Things (IoT) device, an Internet of Everything (IoE) device, or a Machine Type Communication (MTC) device, etc. In some implementations, UE 104 may be stationary within the wireless communication system 100. In some other implementations, UE 104 may be mobile within the wireless communication system 100.

[0059] One or more UEs 104 can be devices of different forms or with different capabilities. Figure 1 The diagram illustrates some examples of UE 104. UE 104 is capable of communicating with various types of devices, such as network entity 102, other UEs 104, or network devices (e.g., core network 106, packet data network 108, relay equipment, integrated access and backhaul (IAB) node, or another network device). Figure 1 As shown. Alternatively or concurrently, UE 104 may support communication with other network entities 102 or UE 104 that may be used as relays in wireless communication system 100.

[0060] UE 104 can also support direct wireless communication with other UE 104s via communication link 114. For example, UE 104 can support direct wireless communication with another UE 104 via a device-to-device (D2D) communication link. In some implementations, such as vehicle-to-vehicle (V2V) deployments, vehicle-to-everything (V2X) deployments, or cellular V2X deployments, communication link 114 may be referred to as a sidechain. For example, UE 104 can support direct wireless communication with another UE 104 via a PC5 interface.

[0061] Network entity 102 may support communication with core network 106 or with another network entity 102, or both. For example, network entity 102 may interface with core network 106 via one or more backhaul links 116 (e.g., via S1, N2, N2, or another network interface). Network entities 102 may communicate with each other via backhaul links 116 (e.g., via X2, Xn, or another network interface). In some implementations, network entities 102 may communicate directly with each other (e.g., between network entities 102). In some other implementations, network entities 102 may communicate with each other or indirectly (e.g., via core network 106). In some implementations, one or more network entities 102 may include sub-components, such as access network entities, which may be examples of access node controllers (ANCs). An ANC may communicate with one or more UEs 104 via one or more other access network transport entities (which may be referred to as radio headends, smart radio headends, or transmit-receive points (TRPs)).

[0062] In some implementations, network entity 102 can be configured with a decomposed architecture that can utilize protocol stacks physically or logically distributed across two or more network entities 102, such as an Integrated Access Backhaul (IAB) network, an Open Radio Access Network (O-RAN) (e.g., a network configuration sponsored by the O-RAN Alliance), or a Virtualized RAN (vRAN) (e.g., a Cloud RAN (C-RAN)). For example, network entity 102 may include one or more of a Central Unit (CU), Distributed Unit (DU), Radio Unit (RU), RAN Intelligent Controller (RIC) (e.g., near real-time RIC, non-real-time RIC), Service Management and Orchestration (SMO) system, or any combination thereof.

[0063] An RU can also be referred to as a radio headend, intelligent radio headend, remote radio headend (RRH), remote radio unit (RRU), or transmit-receive point (TRP). In a decomposed RAN architecture, one or more components of network entity 102 can be co-located, or one or more components of network entity 102 can be located in distributed locations (e.g., separate physical locations). In some implementations, one or more network entities 102 in a decomposed RAN architecture can be implemented as virtual units (e.g., virtual CU (VCU), virtual DU (VDU), virtual RU (VRU)).

[0064] The functional decomposition between CU, DU, and RU can be flexible and can support different functions based on the functions performed at the CU, DU, or RU (e.g., network layer functions, protocol layer functions, baseband functions, radio frequency functions, and any combination thereof). For example, a protocol stack functional decomposition can be used between the CU and DU, allowing the CU to support one or more layers of the protocol stack and the DU to support one or more different layers of the protocol stack. In some implementations, the CU can host upper-layer protocol layer (e.g., Layer 3 (L3), Layer 2 (L2)) functions and signaling (e.g., Radio Resource Control (RRC), Serving Data Adaptation Protocol (SDAP), Packet Data Convergence Protocol (PDCP)). The CU can connect to one or more DUs or RUs, and one or more DUs or RUs can host lower-layer protocol layer functions and signaling, such as Layer 1 (L1) (e.g., Physical (PHY) layer) or L2 (e.g., Radio Link Control (RLC) layer, Media Access Control (MAC) layer), and each can be at least partially controlled by the CU.

[0065] Alternatively, a functional split of the protocol stack can be employed between the DU and RU, allowing the DU to support one or more layers of the protocol stack and the RU to support one or more different layers of the protocol stack. The DU can support one or more different cells (e.g., via one or more RUs). In some implementations, the functional split between the CU and DU, or between the DU and RU, can be within the protocol layer (e.g., some functions of the protocol layer can be performed by one of the CU, DU, or RU, while other functions of the protocol layer are performed by different items in the CU, DU, or RU).

[0066] The CU can be further functionally divided into CU control plane (CU-CP) and CU user plane (CU-UP) functions. The CU can be connected to one or more DUs via mid-range communication links (e.g., F1, F1-c, F1-u), and the DUs can be connected to one or more RUs via fronthaul communication links (e.g., open fronthaul (FH) interfaces). In some implementations, the mid-range or fronthaul communication links can be implemented based on interfaces (e.g., channels) between layers of a protocol stack supported by the respective network entity 102 communicating via such communication links.

[0067] Core network 106 can support user authentication, access authorization, tracking, connectivity, and other access, routing, or mobility functions. Core network 106 can be an evolved packet core (EPC) or a 5G core (5GC), which may include control plane entities that manage access and mobility (e.g., a mobility management entity (MME), access and mobility management functions (AMF)) and user plane entities that route packets or interconnects to external networks (e.g., a serving gateway (S-GW), a packet data network (PDN) gateway (P-GW), or a user plane function (UPF)). In some implementations, the control plane entities may manage non-access stratum (NAS) functions, such as mobility, authentication, and bearer management (e.g., data bearers, signaling bearers, etc.) of one or more UEs 104 served by one or more network entities 102 associated with core network 106.

[0068] Core network 106 can communicate with packet data network 108 via one or more backhaul links 116 (e.g., via S1, N2, N2, or another network interface). Packet data network 108 may include application server 118. In some implementations, one or more UEs 104 may communicate with application server 118. UE 104 may establish a session (e.g., PDU session) with core network 106 via network entity 102. Core network 106 can use the established session (e.g., established PDU session) to route services (e.g., control information, data, etc.) between UE 104 and application server 118. PDU session may be an example of a logical connection between UE 104 and core network 106 (e.g., one or more network functions of core network 106).

[0069] In the wireless communication system 100, network entity 102 and UE 104 can use the resources of the wireless communication system 100 (e.g., time resources (e.g., symbols, time slots, subframes, frames, etc.) or frequency resources (e.g., subcarriers, carriers)) to perform various operations (e.g., wireless communication). In some implementations, network entity 102 and UE 104 can support different resource structures. For example, network entity 102 and UE 104 can support different frame structures. In some implementations, such as in 4G, network entity 102 and UE 104 can support a single frame structure. In some other implementations, such as in 5G and other suitable radio access technologies, network entity 102 and UE 104 can support various frame structures (i.e., multiple frame structures). Network entity 102 and UE 104 can support various frame structures based on one or more digital technologies.

[0070] One or more digital technologies may be supported in the wireless communication system 100, and the digital technologies may include subcarrier spacing and cyclic prefix. The first digital technology (e.g., μ =0) can be associated with the first subcarrier spacing (e.g., 15 kHz) and a normal cyclic prefix. In some implementations, the first digital technique (e.g., ...) associated with the first subcarrier spacing (e.g., 15 kHz) is... μ =0) can utilize one time slot per subframe. Second digital technologies (e.g., μ =1) can be associated with the second subcarrier spacing (e.g., 30 kHz) and a normal cyclic prefix. The third digital technology (e.g., μ =2) can be associated with a third subcarrier spacing (e.g., 60 kHz) and a normal cyclic prefix or an extended cyclic prefix. A fourth digital technology (e.g., μ =3) can be associated with a fourth subcarrier spacing (e.g., 120 kHz) and a normal cyclic prefix. A fifth digital technology (e.g., μ =4) can be associated with the fifth subcarrier spacing (e.g., 240 kHz) and the normal cyclic prefix.

[0071] The time intervals of resources (e.g., communication resources) can be organized according to frames (also called radio frames). Each frame can have a duration, for example, 10 milliseconds (ms). In some implementations, each frame can include multiple subframes. For example, each frame can include 10 subframes, and each subframe can have a duration, for example, 1 ms. In some implementations, each frame can have the same duration. In some implementations, each subframe of a frame can have the same duration.

[0072] Alternatively or concurrently, the time intervals of resources (e.g., communication resources) can be organized according to time slots. For example, a subframe may include a certain number (e.g., quantity) of time slots. The number of time slots in each subframe may also depend on one or more digital technologies supported in the wireless communication system 100. For example, a first digital technology, a second digital technology, a third digital technology, a fourth digital technology, and a fifth digital technology (i.e., ...) associated with corresponding subcarrier intervals of 15 kHz, 30 kHz, 60 kHz, 120 kHz, and 240 kHz. μ =0、 μ =1、 μ =2、 μ =3、 μ =4) One time slot per subframe, two time slots per subframe, four time slots per subframe, eight time slots per subframe, and 16 time slots per subframe can be used, respectively. Each time slot can include a certain number (e.g., quantity) of symbols (e.g., OFDM symbols). In some implementations, the number (e.g., quantity) of time slots in a subframe can depend on the digital technique. For a normal cyclic prefix, a time slot can include 14 symbols. For an extended cyclic prefix (e.g., for a 60kHz subcarrier spacing), a time slot can include 12 symbols. The relationship between the number of symbols per time slot, the number of time slots per subframe, and the number of time slots per frame for both normal and extended cyclic prefixes can depend on the digital technique. It should be understood that for the first digital technique (e.g., quantity) associated with the first subcarrier spacing (e.g., 15kHz), μ The reference of =0 can be used interchangeably between subframes and time slots.

[0073] In the wireless communication system 100, the electromagnetic (EM) spectrum can be divided into various categories, frequency bands, frequency channels, etc., based on frequency or wavelength. For example, the wireless communication system 100 can support one or more operating frequency bands, such as frequency range names FR1 (410MHz-7.125GHz), FR2 (24.25GHz-52.6GHz), FR3 (7.125GHz-24.25GHz), FR4 (52.6GHz-114.25GHz), FR4a or FR4-1 (52.6GHz-71GHz), and FR5 (114.25GHz-300GHz). In some implementations, network entity 102 and UE 104 can perform wireless communication on one or more operating frequency bands. In some implementations, FR1 can be used by network entity 102 and UE 104, along with other devices or apparatuses, for cellular communication services (e.g., control information, data). In some implementations, FR2 can be used by network entity 102 and UE 104, along with other devices or apparatuses, for short-range, high data rate capabilities.

[0074] FR1 can be associated with one or more digital technologies (e.g., at least three digital technologies). For example, FR1 can be associated with the following: a first digital technology (e.g., μ =0), which includes a 15kHz subcarrier spacing; second digital technology (e.g., μ =1), which includes a 30kHz subcarrier spacing; third digital technology (e.g., μ =2), which includes a subcarrier spacing of 60 kHz. FR2 can be associated with one or more digital technologies (e.g., at least two digital technologies). For example, FR2 can be associated with a third digital technology (e.g., μ =2), which includes a 60kHz subcarrier spacing; fourth digital technology (e.g., μ =3), which includes a subcarrier spacing of 120kHz.

[0075] As mentioned above, synchronization between different media components is crucial for immersive multimodal VR applications to avoid negatively impacting the user experience (i.e., viewers detecting a lack of synchronization), especially when the synchronization threshold between two or more modes is below the application's latency KPI. Table 1 provides examples of typical synchronization thresholds for immersive multimodal VR applications. Table 1

[0076] In Table 1, for each media component, "latency" refers to the situation where one media component is delayed compared to another. For example, a "visual latency" of 15ms means that haptic data arrives at the UE first (e.g., first at the UE's access layer (AS)) and the visual data is delayed by 15ms compared to the haptic data. Alternatively, a "visual latency" of 15ms means that haptic data is sent to the base station first and the visual data is delayed by 15ms compared to the haptic data. In other words, the synchronization threshold between haptic data and visual data is equal to 15ms.

[0077] As mentioned above, the LCP process does not consider synchronization delay status, but rather the priority of logical channels. When the remaining synchronization delay of the data on the first logical channel is below a threshold, and the priority of the first logical channel is lower than that of the second logical channel which does not have synchronization delay requirements, the data on the first logical channel may not be multiplexed to the UL-licensed MAC PDU during MAC PDU assembly, and the data may be discarded. Therefore, the user experience is affected. This will refer to... Figure 2 Describe it.

[0078] Figure 2 An example of a traditional LCP is illustrated. Figure 2In the example, the priority of LCH#1 is represented by P1, the priority of LCH#2 by P2, and the priority of LCH#3 by P3. P1 is higher than P2, and P2 is higher than P3.

[0079] The remaining time for LCH#1 data is 10ms, and LCH#1 has no synchronization delay requirement.

[0080] Tactile data is carried on LCH#2, and visual data is carried on LCH#3. The tactile and visual data are included in the synchronous transmission set.

[0081] The tactile data arrives at the UE at time T1, and the visual data arrives at time (T1+12ms). As shown in Table 1, the synchronization threshold between the tactile and visual data is 15ms. Therefore, the remaining synchronization delay of the visual data for LCH#3 is 15 minus 12 (ms). That is, the remaining synchronization delay of the visual data for LCH#3 is 3ms. Therefore, the UE should send the visual data for LCH#3 within 3ms after sending the tactile data for LCH#2.

[0082] Because P1 is higher than P2 and P2 is higher than P3, the UE can prioritize allocating resources for UL-authorized LCH#1 and LCH#2 data. In other words, LCH#1 and LCH#2 data are first multiplexed onto the UL-authorized MAC PDU. If the UL authorization is exhausted after the LCH#1 and LCH#2 data are multiplexed, then LCH#3 data will not be multiplexed onto the UL-authorized MAC PDU. If the remaining synchronization delay of the LCH#3 visual data is equal to or less than the threshold and the LCH#3 visual data is not multiplexed onto the MAC PDU for transmission in a timely manner, then the LCH#3 visual data can be discarded. Therefore, the user experience is affected.

[0083] Figure 3 A flowchart of a process 300 for multiplexing a logical channel MAC PDU according to various aspects of this disclosure is illustrated.

[0084] In process 300, each LCH j It has a token bucket (also known as a "bucket") and targets LCH. j The value maintained. For LCH j The value maintained is determined by Bj express.

[0085] The maximum capacity of the token bucket 305 is equal to the Product Priority Bit Rate (PBR) and the Bucket Size Duration (BSD) (i.e., PBR... (BSD). The size of the token bucket 305 is also known as the maximum capacity of the token bucket 305.

[0086] Bj It can represent LCH j The number of tokens in the token bucket. When LCH j When it is established, Bj Initialized to zero. For each LCH j UE 104 should include the following before each instance of the LCP procedure: Bj The product of increasing PBR × T, where T is the product of increasing PBR × T. Bj The time elapsed since the last increase. If Bj If the value is greater than the bucket size (i.e., PBR × BSD), then UE 104 will... Bj Set the bucket size.

[0087] like Figure 3 As shown, at 310, UE 104 injects PBR×T tokens into token bucket 305 at each instance of the LCP process.

[0088] At position 320, UE 104 increments Bj by the product of PBR × T, where T is the product of PBR and T. Bj The time elapsed since the last increase.

[0089] At position 330, UE 104 is determined. Bj Is it greater than zero?

[0090] if Bj If it is greater than zero, then UE 104 will... Bj Decrease is provided to the logical channel j The total size of the MAC SDU. Provided to the logical channel. j The total size of the MAC SDU is represented by Tsdu.

[0091] At 350, UE 104 multiplexes SDU 315 in the MAC PDU.

[0092] At 360, UE 104 determines whether the PBR is satisfied.

[0093] If the PBR is satisfied, UE 104 processes the next LCH at 370.

[0094] If the PBR is not satisfied, procedure 300 continues to box 395. At 395, UE 104 receives packets from the upper layer.

[0095] If UE 104 is determined at 330 Bj If the value is not greater than zero, then UE 104 determines at 380 that there are no available tokens in token bucket 305, and SDU 315 will not be reused in MAC PDU.

[0096] At 390, UE 104 determines that the processing of the LCH is complete, and then the next logical channel with lower priority will be processed.

[0097] In view of the above, this disclosure provides a solution supporting logical channel prioritization based on synchronization delay state. In this solution, a UE determines the synchronization delay state of data in a first synchronized transmission set. Then, the UE prioritizes data transmission based on the synchronization delay state. In this way, logical channel prioritization based on synchronization delay state can be implemented. Therefore, the user experience can be improved.

[0098] In the following text, reference will be made to Figures 4 to 10 The principles of this disclosure are described.

[0099] Figure 4 A signaling diagram is illustrated, illustrating an example process 400 supporting logical channel prioritization based on synchronization delay state according to various aspects of this disclosure. For discussion purposes, reference will be made to... Figure 1 Describe process 400. Process 400 may involve... Figure 1 UE 104 and network entity 102 in the example.

[0100] like Figure 4 As shown, UE 104 determines the synchronization delay status of the data in the 420 synchronous transmission set.

[0101] In some implementations, a synchronous transport set may include packets associated with one or more QoS flows. See later. Figure 5 An example describing a synchronous transport set.

[0102] In some implementations, a set of packets carried by one or more QoS streams and requiring synchronous transmission can be defined as a synchronous transmission set.

[0103] In some implementations, UE 104 can identify packets from the upper-layer synchronization transport set.

[0104] In some implementations, a synchronous transport set may be referred to as a synchronous PDU set. For example, a synchronous transport set may include at least two PDU sets, and each of these two PDU sets is associated with a QoS flow.

[0105] In some implementations, the synchronization transport set may include one or more PDUs associated with a first QoS stream and one or more PDUs associated with a second QoS stream. The first QoS stream and the second QoS stream are QoS streams indicated by the synchronization transport association of the QoS streams.

[0106] Alternatively, in some implementations, the synchronous transport set may include one or more PDU sets associated with the first QoS stream and one or more PDUs associated with the second QoS stream.

[0107] Alternatively, in some implementations, the synchronous transport set may include one or more PDU sets associated with the first QoS stream and one or more PDU sets associated with the second QoS stream.

[0108] In some implementations, a PDU set may include one or more PDUs carrying the payload of an information element generated at the application level. For example, the information element could be a frame or video slice from an XR service. In some implementations, the UE104 application layer requires all PDUs in the PDU set to use the corresponding information element. In other implementations, the application layer can still recover some or all of the information elements even if some PDUs are lost.

[0109] In some implementations, the synchronous transport set may include one or more data bursts associated with a first QoS stream and one or more data bursts associated with a second QoS stream. In some implementations, a data burst may be a collection of multiple PDUs generated and transmitted by an application within a short time period. Alternatively, in some implementations, a data burst may include one or more sets of PDUs.

[0110] In some implementations, a synchronization transport set can be carried on a single data radio bearer (DRB). Alternatively, a synchronization transport set can be carried on multiple DRBs. For example, the multiple DRBs may include a first DRB and a second DRB. For instance, a portion of the data in the synchronization transport set may be carried on the first DRB, while another portion of the data in the synchronization transport set may be carried on the second DRB.

[0111] In some implementations, the data in the synchronized transmission set may include data of a first type. The synchronization delay state of the data may include a first remaining synchronization delay of the first type of data. The first remaining synchronization delay of the first type of data is lower than a first threshold. In other words, the first remaining synchronization delay of the first type of data is equal to or less than the first threshold.

[0112] In some implementations, to determine the synchronization delay state of data in the synchronization transport set, UE 104 can determine the synchronization delay state of each packet in the LCH. For example, LCH packets may include PDCP SDUs corresponding to PDUs in the synchronization transport set.

[0113] In some implementations, if the remaining synchronization delay of a packet is below a first threshold, UE 104 may treat the packet as first-type data. Hereinafter, first-type data is also referred to as synchronization delay-critical data. The first threshold may be configured by network entity 102 or predefined.

[0114] In some implementations, UE 104 can determine the remaining synchronization delay of a packet based on a synchronization timer. For example, UE 104 can start a synchronization timer at its PDCP layer when it receives a packet from an upper layer. UE 104 can determine the remaining synchronization delay of the packet as the remaining time of the synchronization timer. In such an implementation, the first threshold can be related to... remainingTimeThreshold Configure separately. remainingTimeThreshold It is the threshold for the remaining time used to trigger the Delay Status Report (DSR) of the Logical Channel Group (LCG).

[0115] Alternatively, in some implementations, UE 104 can be reused. remainingTimeThreshold As the first threshold. In such an implementation, the synchronization delay state is the same as the delay state based on the remaining time of the discard timer (i.e., the remaining discard time). That is, the synchronization delay key data is the same as the delay key data.

[0116] In some implementations, network entity 102 can configure a first threshold for each UE. For example, network entity 102 can configure a percentage. Then, UE 104 can determine the first threshold as a base threshold. The product of percentages. The base threshold can be the value of the discard timer of the DRB carrying synchronization delay critical data. For example, the base threshold could be equal to 50ms, and the percentage could be equal to 20%. UE 104 can determine the first threshold as 50ms. The product of 20% (ms). In other words, UE 104 can determine the first threshold as 10ms.

[0117] Alternatively, in some implementations, the synchronization transport set may include packet #1 of LCH#1 and packet #2 of LCH#2. Packet #1 arrives at UE 104 before packet #2. UE 104 may determine the remaining synchronization delay of packet #2 based on the relative arrival times between packet #1 and packet #2. Packet #1 of LCH#1 may be either the first or last packet of LCH#1 to arrive at UE 104. Packet #2 of LCH#2 may be either the first or last packet of LCH#2 to arrive at UE 104.

[0118] Alternatively, in some implementations, the synchronization transmission set may include packet #1 of LCH#1 and packet #2 of LCH#2. Packet #1 arrives at UE 104 before packet #2. UE 104 may determine the remaining synchronization delay of packet #2 based on the relative transmission time between packet #1 and packet #2. Packet #1 of LCH#1 may be either the first LCH#1 packet sent by UE 104 or the last LCH#1 packet sent by UE 104. Packet #2 of LCH#2 may be either the first LCH#2 packet sent by UE 104 or the last LCH#2 packet sent by UE 104.

[0119] Alternatively, in some implementations, the synchronization transmission set may include packet #1 of LCH#1 and packet #2 of LCH#2. Packet #1 is sent by UE 104 before packet #2 arrives at UE 104. UE 104 may determine the remaining synchronization delay of packet #2 based on the time difference between the arrival time of packet #2 and the transmission time of packet #1. Packet #1 of LCH#1 may be either the first LCH#1 packet sent by UE 104 or the last LCH#1 packet sent by UE 104. Packet #2 of LCH#2 may be either the first LCH#2 packet sent by UE 104 or the last LCH#2 packet sent by UE 104.

[0120] Continue to refer to Figure 4 UE 104 prioritizes the transmission of data in the synchronized transmission set based on the data's synchronization delay status 430.

[0121] For example, UE 104 can prioritize the transmission of portions of data in a synchronized transmission set based on the data's synchronization delay status. Alternatively, UE 104 can prioritize the transmission of all data in a synchronized transmission set based on the data's synchronization delay status.

[0122] In some implementations, optionally, UE 104 may receive a first indication 410 from network entity 102, the first indication indicating whether data should be prioritized for transmission based on the data's synchronization delay state. If the first indication indicates prioritizing data transmission based on the data's synchronization delay state, then UE 104 may prioritize the transmission of data in the synchronized transmission set based on the data's synchronization delay state.

[0123] In some implementations, the first indication can be for each LCH, DRB, or QoS flow, indicating the priority of data transmission based on the data's synchronization delay state.

[0124] Process 400 enables logical channel prioritization based on synchronization delay state, thus improving the user experience.

[0125] Figure 5 Examples of synchronous transport sets according to some implementations of this disclosure are illustrated. For example... Figure 5 As shown, the SYNC transport set includes one or more PDU sets associated with a first QoS stream and one or more PDUs associated with a second QoS stream. The first QoS stream may be a video stream, and the second QoS stream may be a haptic stream. For example, the SYNC transport set 500 includes a PDU set 510 for the video stream and PDUs 520 and 522 for the haptic stream. PDU set 510 includes PDUs 512, 514, and 516. PDUs 512, 514, and 516 of the video stream are carried on the first DRB. PDUs 520 and 522 are carried on the second DRB.

[0126] In some implementations, UE 104 can prioritize the transmission of data in the synchronization transport set by prioritizing the transmission of data in the first LCH. The synchronization transport set is carried on the first LCH. The first LCH has the synchronization transport set, and the synchronization transport set has data of a first type.

[0127] Alternatively, in some implementations, UE 104 can prioritize data transmission by prioritizing the transmission of all data in the synchronous transmission set.

[0128] Alternatively, in some implementations, UE 104 can prioritize data transmission by prioritizing the transmission of the first type of data in the synchronous transmission set.

[0129] In some implementations, UE 104 can prioritize the transmission of first-type data by increasing at least the first priority of the first-type data to the target priority.

[0130] In some implementations, UE 104 can receive configuration for a target priority from network entity 102. UE 104 can then determine the target priority based on this configuration.

[0131] In some implementations, the configuration for target priority may include an absolute target priority value. For example, the absolute target priority value could be the absolute target priority of data of type 1. UE 104 can increase the first priority of data of type 1 based on the absolute target priority value. In such an implementation, UE 104 can increase the first priority of data of type 1 to the absolute target priority value.

[0132] Alternatively, in some implementations, the configuration for the target priority may include a priority offset value. For example, the priority offset value may be a priority offset value for first-type data. UE 104 may add the priority offset value to the first priority of the first-type data. For example, the first priority of the first-type data may be configured by network entity 102 via RRC signaling. UE 104 may determine the target priority of the first-type data as the first priority minus the priority offset value (i.e., the difference between the first priority and the priority offset value).

[0133] Alternatively, in some implementations, the configuration for the target priority may include a factor. For example, this factor could be a factor for the first type of data. UE 104 can increase the first priority of the first type of data based on this factor. For example, UE 104 can determine the target priority based on the following: floor (factor) First priority), where "floor" indicates floor operation.

[0134] Alternatively or additionally, in some implementations, UE 104 may increase the first priority of the first type of data based on the mapping between the factor and the first remaining synchronization delay of the first type of data. The mapping between the factor and the first remaining synchronization delay of the first type of data may be configured by network entity 102.

[0135] In some implementations, the configuration for target priorities can be configured by network entity 102 for each LCH, DRB, or QoS flow.

[0136] In some implementations, UE 104 can prioritize the transmission of data in a synchronized transport set based on the data's synchronization delay state and a value maintained for the first LCH containing that data. As used herein, for the LCH... j The value maintained is determined by Bj This indicates. This will refer to... Figure 6 Describe it.

[0137] Figure 6 A flowchart illustrating a method 600 supporting logical channel prioritization based on synchronization delay state according to various aspects of this disclosure is shown. Method 600 can be considered as... Figure 4 An example implementation of action 420 in [the document / section]. For discussion purposes, references will be made to [the document / section]. Figure 1 Method 600 is described from the perspective of UE 104.

[0138] Typically, in method 600, UE 104 prioritizes the transmission of data in the synchronized transmission set based on the data's synchronization delay state and the value maintained for the first LCH containing that data. To prioritize the transmission of data in the synchronized transmission set, UE 104 may increase at least a first priority of the first type of data to a target priority during the first round of resource allocation (i.e., based on a value of Bj>0).

[0139] like Figure 6 As shown, at 610, UE 104 can increase at least the first priority of the first type of data in the synchronization transmission set to the target priority. UE 104 can increase the at least first priority of the first type of data during the second round of resource allocation (i.e., regardless of the value of Bj).

[0140] In some implementations, UE 104 can increase at least a first priority of the first type of data to the target priority by increasing the second priority of the first LCH to the target priority. The first LCH contains data of the first type. Alternatively, UE 104 can increase at least a first priority of the first type of data to the target priority by increasing only the first priority of the first type of data to the target priority. Alternatively, UE 104 can increase at least a first priority of the first type of data to the target priority by increasing the third priority of the synchronization transport set to the target priority. The synchronization transport set includes data of the first type. Such implementations will be referred to later. Figure 8 Describe it.

[0141] At position 620, UE 104 can allocate resources to LCH data authorized by UL with Bj>0 in descending priority order. For example, UE 104 can perform... Figure 3 In process 300, resources are allocated to the data of UL-authorized LCHs with Bj>0 in descending order of priority.

[0142] In some implementations, UE 104 can prioritize the transmission of data in a synchronized transport set based on the data's synchronization delay state, regardless of the value maintained for the first LCH containing that data. As used herein, for the LCH... j The value maintained is determined by Bj This indicates. This will refer to... Figure 7 Describe it.

[0143] Figure 7 A flowchart illustrating a method 700 supporting logical channel prioritization based on synchronization delay state according to various aspects of this disclosure is shown. Method 700 can be considered as... Figure 4 An example implementation of action 420 in [the document / section]. For discussion purposes, references will be made to [the document / section]. Figure 1Method 700 is described from the perspective of UE 104.

[0144] Typically, in method 700, UE 104 prioritizes the transmission of data in the synchronized transmission set based on the data's synchronization delay state, regardless of the value maintained for the first LCH containing that data. To prioritize the transmission of data in the synchronized transmission set, UE 104 may increase at least a first priority of the first type of data to a target priority during a second round of resource allocation following the first round of resource allocation.

[0145] like Figure 7 As shown, at 710, UE 104 can execute the first round of resource allocation process to allocate resources in descending order of priority. Bj UL-authorized LCH data allocation resources >0. For example, UE 104 can perform... Figure 3 In process 300, proceed in descending order of priority to... Bj UL-authorized LCH data allocation resources >0.

[0146] At 720, UE 104 will Bj Decrease is provided to LCH j The total size of the MAC SDU.

[0147] At point 730, if any resources remain, UE 104 may increase the priority of the first type of data in the synchronization transmission set to at least the first priority. In other words, UE 104 may increase the priority of the first type of data during the second round of resource allocation.

[0148] If UE 104 has already increased the priority of the first type of data in the synchronization transmission set to the target priority at 710, then UE 104 may not need to increase the priority of the first type of data in the synchronization transmission set to the target priority at 730. In this case, UE 104 uses the target priority at 730.

[0149] and Figure 6Similar to action 610, in some implementations, UE 104 can increase at least a first priority of the first type of data to the target priority by increasing the second priority of the first LCH to the target priority. The first LCH contains data of the first type. Alternatively, UE 104 can increase at least a first priority of the first type of data to the target priority by increasing only the first priority of the first type of data to the target priority. Alternatively, UE 104 can increase at least a first priority of the first type of data to the target priority by increasing the third priority of the synchronization transport set to the target priority. The synchronization transport set includes data of the first type. Such implementations will be referred to later. Figure 8 Describe it.

[0150] At 740, UE 104 can allocate resources to the LCH data authorized by the UL in descending priority order (regardless of...). Bj How much does it value?

[0151] Figure 8 An example of first LCH data according to various aspects of this disclosure is illustrated. Figure 8 As shown, the first LCH has a first synchronization transport set and a second synchronization transport set.

[0152] The first synchronized transmission set includes a first type of data (i.e., synchronization delay-critical data) and a second type of data. The second type of data has a second residual synchronization delay higher than the first threshold. In the following text, the second type of data is also referred to as asynchronous delay-critical data.

[0153] The second synchronous transmission set includes only asynchronous delay critical data.

[0154] In some implementations, UE 104 can increase at least the first priority of the synchronization delay data to the target priority by increasing the priority of the first LCH to the target priority. In other words, UE 104 can increase the priority of all data in the first LCH to the target priority.

[0155] Alternatively, UE 104 can increase at least the first priority of the synchronous delay data to the target priority by increasing the first priority of the synchronous delay data in the first synchronous transmission set to the target priority. UE 104 can keep the first priority of the asynchronous delay data in the first LCH unchanged. That is, UE 104 can keep the first priority of the asynchronous delay data in the first and second synchronous transmission sets unchanged.

[0156] Alternatively, UE 104 can increase at least a first priority of the synchronous delay data to the target priority by increasing the priority of the first synchronous transmission set to the target priority. In other words, UE 104 can increase the priority of all data in the first synchronous transmission set to the target priority. That is, UE 104 can increase the priority of both synchronous delay data and asynchronous delay data in the first synchronous transmission set to the target priority.

[0157] In some implementations, UE 104 can prioritize the transmission of an LCH with data of type 1 over the transmission of another LCH without data of type 1. This will be discussed in a later reference. Figure 9 Describe it.

[0158] Figure 9 A flowchart illustrating a method 900 supporting logical channel prioritization based on synchronization delay state according to various aspects of this disclosure is shown. Method 900 can be considered as... Figure 4 An example implementation of action 420 in [the document / section]. For discussion purposes, references will be made to [the document / section]. Figure 1 Method 900 is described from the perspective of UE 104.

[0159] like Figure 9 As shown, at 910, UE 104 can divide the LCH into at least two groups. For example, UE 104 can divide the LCH into a first group of LCHs and a second group of LCHs. Each LCH in the first group includes data of type 1. Each LCH in the second group does not include data of type 1.

[0160] At 920, in order to prioritize the transmission of LCH data in the first group over the transmission of LCH data in the second group, UE 104 may increase the priority of the first type of LCH data in the first group to the target priority.

[0161] In some implementations, UE 104 can increase the priority of LCH data in the first group to the target priority during the first round of resource allocation.

[0162] Alternatively, UE 104 can increase the priority of LCH data in the first group to the target priority during the second round of resource allocation.

[0163] At 930, UE 104 can allocate resources to the LCH in the first group before allocating resources to the LCH in the second group.

[0164] For example, in the first round of resource allocation, UE 104 can allocate resources in descending order of LCH priority. Bj Data allocation resources for LCH in the first and second groups of UL authorizations >0.

[0165] For another example, during the second round of resource allocation, UE 104 can allocate resources to the data of the first and second groups of LCHs authorized by the UL in descending order of LCH priority, regardless of... Bj What is the value of ?

[0166] In some implementations, the first group may include a first LCH and a second LCH. Each of the first LCH and the second LCH includes data of a first type.

[0167] In this implementation, UE 104 can allocate resources to the first and second LCHs selected for UL authorization (Bj>0) in descending priority order (e.g., original priority or target priority). For example, if the first priority of the first LCH is higher than the second priority of the second LCH, UE 104 can allocate resources to the first LCH before allocating resources to the second LCH. The first priority can be the original priority of the first LCH, and the second priority can be the original priority of the second LCH. The original priority can be configured by network entity 102 via RRC signaling.

[0168] Alternatively, in such an implementation, UE 104 can allocate resources to the data of the first LCH and the second LCH selected by the UL grant for Bj>0 in ascending order of remaining synchronization delay. For example, if the first remaining synchronization delay of the first type of data in the first LCH is less than the second remaining synchronization delay of the first type of data in the second LCH, then UE 104 can allocate resources to the data of the first LCH before allocating resources to the data of the second LCH.

[0169] Alternatively, at 930, UE 104 may allocate resources to the first type of data (i.e., synchronous delay critical data) before allocating resources to the second type of data (i.e., asynchronous delay critical data). For example, if the first LCH has both synchronous delay critical data and asynchronous delay critical data, UE 104 may only increase the priority of the synchronous delay critical data to the target priority.

[0170] Alternatively, at 930, UE 104 may allocate resources to a synchronization transport set that includes synchronization delay critical data before allocating resources to the synchronization transport set that includes asynchronous delay critical data. For example, a first LCH has a first synchronization transport set and a second synchronization transport set. The first synchronization transport set includes synchronization delay critical data. The second synchronization transport set does not include synchronization delay critical data. That is, the second synchronization transport set only includes asynchronous delay critical data. UE 104 may only increase the priority of the first synchronization set that includes synchronization delay critical data to the target priority.

[0171] Figure 10 A signaling diagram is illustrated, illustrating an example process 1000 supporting logical channel priority based on synchronization delay state according to various aspects of this disclosure. For discussion purposes, reference will be made to... Figure 1 Describe process 1000. Process 1000 may involve... Figure 1 UE 104 and network entity 102 in the example.

[0172] like Figure 10 As shown, UE 104 determines the delay status of 1020 data based on at least one of a plurality of thresholds.

[0173] Furthermore, UE 104 prioritizes data transmission based on one of several thresholds 1030.

[0174] In some implementations, the data may include data from a synchronous transmission set. In such an implementation, UE 104 can determine the delay state of the data by determining the synchronization delay state of the data in the synchronous transmission set, as referenced. Figures 4 to 9 For the sake of brevity, the implementation of the synchronization delay state used to determine the data in the synchronous transmission set has been omitted.

[0175] In some implementations, the data may include the references above. Figures 4 to 9 The first type of data (i.e., synchronization delay key data). The first remaining synchronization delay of the first type of data is lower than a first threshold among a plurality of thresholds. In such an implementation, UE 104 can determine the delay state of the data by determining the first remaining synchronization delay of the first type of data based on at least one of the plurality of thresholds.

[0176] Alternatively, in some implementations, UE 104 can determine the data delay state by determining the delay state of the data in the LCH. In such an implementation, UE 104 can determine the data delay state by determining the remaining time of the data discard timer based on at least one of a plurality of thresholds.

[0177] In some implementations, the data may also include a third type of data. The third type of data has a third remaining time in its discard timer that is below a second threshold among multiple thresholds. In such an implementation, UE 104 can determine the data's delay status by determining the third remaining time in the discard timer for the third type of data. Hereinafter, the third type of data is also referred to as delay-critical data.

[0178] In some implementations, UE 104 can prioritize the transmission of one of the first type of data and the third type of data.

[0179] In some implementations, the first LCH has both data of type 1 and data of type 3. Alternatively, the first LCH has data of type 1 and the second LCH has data of type 3.

[0180] In some implementations, optionally, UE 104 may receive 1010 second instruction from network entity 102.

[0181] In some implementations, the second instruction can instruct the prioritization of data transmissions of the first type based on a first threshold. This will refer to... Figure 11A Describe it.

[0182] Figure 11A An example of first LCH data according to various aspects of this disclosure is illustrated. Figure 11A As shown, the first LCH has both first-type data and third-type data. In other words, the first LCH has both synchronization delay-critical data and delay-critical data.

[0183] The second instruction can instruct the prioritization of the transmission of synchronization delay-critical data based on a first threshold. In such an implementation, UE 104 can prioritize the transmission of synchronization delay-critical data based on the first threshold using the second instruction. This implementation simplifies the implementation of UE 104.

[0184] In some implementations, in order to prioritize the transmission of first-type data (i.e., synchronization delay-critical data), UE 104 can increase the first priority of the first-type data to a first target priority. For example, UE 104 can increase the first priority of the first-type data by performing procedure 400 or any of methods 600, 700, and 900.

[0185] In some implementations, network entity 102 can be configured with multiple remainingTimeThresholds To configure multiple thresholds. remainingTimeThresholds One of them can be used as the first threshold.

[0186] In some implementations, the synchronization delay state of the synchronization delay key data can be the same as the delay state of the delay key data based on the remaining time of the discard timer (i.e., the remaining discard time). In other words, the synchronization delay key data can be the same as the delay key data.

[0187] In some implementations, network entity 102 can configure UE 104 to be based on at least which remainingTimeThreshold This is used to prioritize the transmission of critical data with synchronization delays.

[0188] In some implementations, network entity 102 can configure UE 104 to be based on multiple remainingTimeThresholds One of the methods is used to prioritize the transmission of at least some synchronization delay critical data.

[0189] For example, remainingTimeThresholds It can include remainingTimeThreshold#1 and remainingTimeThreshold#2 . RemainingTimeThreshold#1 It equals 5ms, and remainingTimeThreshold#2 Equal to 10ms. Network entity 102 can configure UE 104 to be based on remainingTimeThreshold#2 This is used to prioritize the transmission of critical data with synchronization delays.

[0190] If the remaining synchronization delay of the data in the synchronized transmission set is equal to 6ms, then UE 104 can determine that the remaining synchronization delay is higher than 6ms. remainingTimeThreshold#1 (5ms) and less than remainingTimeThreshold#2 (10ms). In other words, UE 104 can determine the data latency status based on two of a plurality of thresholds. In this case, key synchronization latency data may include remaining synchronization latency higher than 10ms. remainingTimeThreshold#1 (5ms) and less than remainingTimeThreshold#2 Data (10ms).

[0191] Alternatively, if the remaining synchronization delay of the data in the synchronized transmission set is equal to 6ms, then UE 104 can determine that the remaining synchronization delay is less than... remainingTimeThreshold#2 (10ms). In other words, UE 104 can determine the data latency status based on one of several thresholds. In this case, key synchronization latency data may include remaining synchronization latency below [a certain threshold]. remainingTimeThreshold#2 The data.

[0192] It should be noted that in other implementations, UE 104 can determine the data latency status based on more than two of a plurality of thresholds.

[0193] Alternatively, in some implementations, the second indicator may instruct the prioritization of transmissions of the third type of data based on a second threshold. This will refer to... Figure 11B Describe it.

[0194] Figure 11B An example of first LCH data according to various aspects of this disclosure is illustrated. Figure 11B As shown, the first LCH has both first-type data and third-type data. In other words, the first LCH has both synchronization delay-critical data and delay-critical data.

[0195] The second instruction can instruct the prioritization of the transmission of delay-critical data based on a second threshold. In such an implementation, UE 104 can prioritize the transmission of delay-critical data based on the second instruction and the second threshold. This implementation simplifies the implementation of UE 104.

[0196] In some implementations, by default, UE 104 can prioritize the transmission of delay-critical data based on the minimum threshold among multiple thresholds of the LCH carrying the data. In such an implementation, UE 104 does not need to receive a second indication specifying which threshold UE 104 prioritizes the transmission of delay-critical data based on.

[0197] In some implementations, in order to prioritize the transmission of third-type data (i.e., delay-critical data), UE 104 can increase the second priority of the third-type data to the second target priority.

[0198] Alternatively, in some implementations, the second instruction may instruct prioritizing the transmission of first type data based on a first threshold and prioritizing the transmission of third type data based on a second threshold. This will refer to... Figure 11C Describe it.

[0199] Figure 11C An example of first LCH data according to various aspects of this disclosure is illustrated. Figure 11C As shown, the first LCH has both first-type data and third-type data. In other words, the first LCH has both synchronization delay-critical data and delay-critical data.

[0200] The second instruction can instruct the prioritization of the transmission of a first type of data based on a first threshold and the prioritization of the transmission of a third type of data based on a second threshold. In such an implementation, UE 104 can prioritize the transmission of synchronization delay-critical data based on the first threshold and the transmission of delay-critical data based on the second instruction.

[0201] In some implementations, in order to prioritize the transmission of first-type data (i.e., synchronization delay-critical data), UE 104 can increase the first priority of the first-type data to a first target priority. For example, UE 104 can increase the first priority of the first-type data by performing procedure 400 or any of methods 600, 700, and 900.

[0202] In some implementations, in order to prioritize the transmission of third-type data (i.e., delay-critical data), UE 104 can increase the second priority of the third-type data to the second target priority.

[0203] In some implementations, if a piece of data belongs to both the first type and the third type, then after UE104 can individually increase the priority of the data to the target priority, UE104 can use the highest target priority of the data.

[0204] In some implementations, if the first LCH has both synchronization delay-critical data and delay-critical data, then UE 104 can prioritize the transmission of only the third type of data (i.e., delay-critical data). In this case, UE 104 can simply increase the second priority of the third type of data to the second target priority. Such an implementation simplifies the implementation of UE 104.

[0205] It should be noted that, for reference Figures 4 to 9 Some implementations of this disclosure described herein can be applied to process 1000. For the sake of brevity, details of these implementations have been omitted.

[0206] Figure 12 A signaling diagram is illustrated, illustrating an example process 1200 supporting logical channel prioritization based on synchronization delay state according to various aspects of this disclosure. For discussion purposes, reference will be made to... Figure 1 Describe process 1200. Process 1200 may involve... Figure 1 UE 104 and network entity 102 in the example.

[0207] like Figure 12 As shown, UE 104 determines the synchronization delay status of the data in the 1210 synchronous transmission set.

[0208] Figure 12 Action 1210 in the middle is similar to Figure 4 Action 420 in the text. For the sake of brevity, the details of this operation have been omitted.

[0209] Furthermore, if the UL authorization is sufficient to accommodate the data, UE 104 maximizes the transmission of data in the synchronization transport set. For example, if the synchronization transport set is suitable for the resources of the relevant MAC entity, UE 104 can maximize the transmission of synchronization delay-critical data as much as possible.

[0210] Through process 1200, UE 104 maximizes the transmission of data in the synchronous transmission set to ensure the synchronization threshold of multimodal VR applications.

[0211] In some implementations, network entity 102 can configure UE 104 to maximize the transmission of data in the synchronous transmission set for each QoS flow, LCH, or DRB.

[0212] In some implementations, the remaining synchronization delay of packets in the synchronization transmission set is separate from the remaining time of the packet's discard timer. In such implementations, UE 104 can determine the remaining synchronization delay of packets in the synchronization transmission set.

[0213] If the remaining synchronization delay of a packet is below a first threshold, UE 104 can treat the packet as first-type data, i.e., synchronization delay critical data.

[0214] Furthermore, if the UL authorization is sufficient to accommodate the data of the first LCH, then UE 104 can maximize the transmission of the data of the first LCH. The first LCH has a first type of data, and the first residual synchronization delay of the first type of data is lower than a first threshold.

[0215] Alternatively, if the UL authorization is sufficient to accommodate all data in the synchronous transport set, UE 104 can maximize the transmission of all data in the synchronous transport set.

[0216] Alternatively, if the UL authorization is sufficient to accommodate Type I data, UE 104 can maximize the transmission of Type I data in the synchronous transmission set.

[0217] In some implementations, the remaining synchronization delay of packets in the synchronized transport set is the same as the remaining time of the packet's discard timer. In such an implementation, UE 104 can determine the remaining time of the discard timer for packets in the synchronized transport set. For example, UE 104 can set and start the discard timer for packets in the synchronized transport set. For another example, UE 104 can set and start the discard timer for the synchronized transport set.

[0218] If the remaining time is less than a first threshold, UE 104 can treat the packet as first-type data. In this case, first-type data includes delay-critical data. That is, first-type data is the same as third-type data.

[0219] Furthermore, if the UL authorization is sufficient to accommodate the data of the first LCH, then UE 104 can maximize the transmission of the data of the first LCH. The first LCH has a first type of data, and the first residual synchronization delay of the first type of data is lower than a first threshold.

[0220] Alternatively, if the UL authorization is sufficient to accommodate all data in the synchronous transport set, UE 104 can maximize the transmission of all data in the synchronous transport set.

[0221] Alternatively, if the UL authorization is sufficient to accommodate Type I data, UE 104 can maximize the transmission of Type I data in the synchronous transmission set.

[0222] In some implementations, to maximize the transmission of data in the synchronization transport set, UE 104 may determine the size of the synchronization delay critical data, the size of the synchronization transport set, or the size of the LCH containing the synchronization delay critical data. Bj Furthermore, UE 104 can send requests in descending order of priority. Bj UL-authorized LCH data allocation resources >0.

[0223] It should be noted that, for reference Figures 4 to 9 Some implementations of this disclosure described herein can be applied to process 1200. For the sake of brevity, details of these implementations have been omitted.

[0224] Figure 13 An example of a device 1300 supporting logical channel priority according to various aspects of this disclosure is illustrated. Device 1300 may be an example of a network entity 102 or a UE 104 as described herein. Device 1300 may support wireless communication with one or more network entities 102, UE 104, or any combination thereof. Device 1300 may include components for bidirectional communication, including components for transmitting and receiving communications (such as processor 1302, memory 1304, transceiver 1306, and optional I / O controller 13014). These components may communicate electronically or be otherwise coupled (e.g., operational ground, communication ground, functional ground, electronic ground, electrical ground) via one or more interfaces (e.g., a bus).

[0225] Processor 1302, memory 1304, transceiver 1306, or various combinations thereof, or various components thereof, may be examples of components used to perform various aspects of the present disclosure described herein. For example, processor 1302, memory 1304, transceiver 1306, or various combinations thereof, or components thereof, may support methods for performing one or more of the operations described herein.

[0226] In some implementations, processor 1302, memory 1304, transceiver 1306, or various combinations or components thereof may be implemented in hardware (e.g., in a communication management circuitry system). The hardware may include a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, configured to or otherwise supporting components for performing the functions described in this disclosure. In some implementations, processor 1302 and memory 1304 coupled to processor 1302 may be configured to perform one or more functions described herein (e.g., by executing instructions stored in memory 1304 by processor 1302).

[0227] For example, according to the examples disclosed herein, processor 502 may support wireless communication at device 500. Processor 502 may be configured to support components for performing the following: determining the synchronization delay state of data in a synchronized transmission set; and prioritizing data transmission based on the synchronization delay state of the data.

[0228] Alternatively, in some implementations, processor 1302 may be configured to support components for performing the following: determining the latency state of data based on at least one of a plurality of thresholds; and prioritizing data transmission based on one of the plurality of thresholds.

[0229] Alternatively, in some implementations, processor 1302 may be configured to support components for performing the following: determining the synchronization delay state of data in a synchronized transmission set; and maximizing data transmission based on determining that uplink grant is sufficient to accommodate the data.

[0230] Processor 1302 may include intelligent hardware devices (e.g., general-purpose processors, DSPs, CPUs, microcontrollers, ASICs, FPGAs, programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combination thereof). In some implementations, processor 1302 may be configured to use a memory controller to operate a memory array. In some other implementations, the memory controller may be integrated into processor 1302. Processor 1302 may be configured to execute computer-readable instructions stored in memory (e.g., memory 1304) to cause device 1300 to perform various functions of this disclosure.

[0231] Memory 1304 may include random access memory (RAM) and read-only memory (ROM). Memory 1304 may store computer-readable, computer-executable code, including instructions that, when executed by processor 1302, cause device 1300 to perform the various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. In some implementations, the code may not be directly executed by processor 1302, but may cause a computer (e.g., when compiled and executed) to perform the functions described herein. In some implementations, memory 1304 may include a basic I / O system (BIOS) that controls basic hardware or software operations, such as interaction with peripheral components or devices.

[0232] I / O controller 13014 can manage the input and output signals of device 1300. I / O controller 13014 can also manage peripheral devices not integrated into device M02. In some implementations, I / O controller 13014 can represent a physical connection or port to an external peripheral device. In some implementations, I / O controller 13014 can utilize an operating system such as iOS®, Android®, MS Windows®, OS / 2®, UNIX®, LINUX®, or other known operating systems. In some implementations, I / O controller 13014 can be implemented as part of a processor, such as processor 1302. In some implementations, a user can interact with device 1300 via I / O controller 13014 or via hardware components controlled by I / O controller 13014.

[0233] In some implementations, device 1300 may include a single antenna 1310. However, in other implementations, device 1300 may have more than one antenna 1310 (i.e., multiple antennas), including multiple antenna panels or antenna arrays capable of concurrently transmitting or receiving multiple wireless transmissions. Transceiver 1306 may communicate bidirectionally via one or more antennas 1310, wired or wireless links, as described herein. For example, transceiver 1306 may represent a wireless transceiver and may communicate bidirectionally with another wireless transceiver. Transceiver 1306 may also include a modem for modulating packets, providing modulated packets to one or more antennas 1310 for transmission, and demodulating packets received from one or more antennas 1310. Transceiver 1306 may include one or more transmit chains, one or more receive chains, or combinations thereof.

[0234] The transmission chain can be configured to generate and transmit signals (e.g., control information, data, packets). The transmission chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. At least one modulator may be configured to support one or more techniques, such as amplitude modulation (AM), frequency modulation (FM), or digital modulation schemes such as phase shift keying (PSK) or quadrature amplitude modulation (QAM). The transmission chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over a wireless medium. The transmission chain may also include one or more antennas 1310 for transmitting the amplified signal into the air or wireless medium.

[0235] The receiver chain can be configured to receive signals (e.g., control information, data, packets) via a wireless medium. For example, the receiver chain may include one or more antennas 1310 for receiving signals over the air or via a wireless medium. The receiver chain may include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receiver chain may include at least one demodulator configured to demodulate the received signal and acquire transmitted data by reversing the modulation technique applied during signal transmission. The receiver chain may include at least one decoder for decoding the demodulated signal to receive the transmitted data.

[0236] Figure 14 An example of a processor 1400 supporting logical channel priorities according to various aspects of this disclosure is illustrated. Processor 1400 may be an example of a processor configured to perform various operations according to the examples described herein. Processor 1400 may include a controller 1402 configured to perform various operations according to the examples described herein. Processor 1400 may optionally include at least one memory 1404, such as an L1 / L2 / L3 cache. Additionally or alternatively, processor 1400 may optionally include one or more arithmetic logic units (ALUs) 1406. One or more of these components may be electronically communicated or otherwise coupled (e.g., operative ground, communicative ground, functional ground, electronic ground, electrical ground) via one or more interfaces (e.g., buses).

[0237] Processor 1400 may be a processor chipset and includes a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receive, acquire, retrieve, send, output, forward, store, determine, identify, access, write, read) according to the examples described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to the processor chipset or included in the processor chipset (e.g., processor 1400)) or other memory (e.g., random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), etc.).

[0238] Controller 1402 can be configured to manage and coordinate various operations of processor 1400 (e.g., signaling, receiving, acquiring, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, and reading) to enable processor 1400 to support various operations of the UE according to the examples described herein. For example, controller 1402 can operate as a control unit of processor 1400 to generate control signals for managing the operation of various components of processor 1400. These control signals include enabling or disabling functional units, selecting data paths, initiating memory accesses, and coordinating operation timing.

[0239] Controller 1402 can be configured to fetch (e.g., fetch, retrieve, receive) instructions from memory 1404 and determine subsequent instructions(s) to be executed, enabling processor 1400 to support various operations according to the examples described herein. Controller 1402 can be configured to track the memory addresses of instructions associated with memory 1404. Controller 1402 can be configured to decode instructions to determine the operations to be performed and the operands involved. For example, controller 1402 can be configured to interpret instructions and determine control signals to be output to other components of processor 1400, enabling processor 1400 to support various operations according to the examples described herein. Additionally or alternatively, controller 1402 can be configured to manage data flow within processor 1400. Controller 1402 can be configured to control data transfers between registers, arithmetic logic unit (ALU), and other functional units of processor 1400.

[0240] Memory 1404 may include one or more caches (e.g., memory or other memory, such as RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc., native to or included in processor 1400). In some implementations, memory 1404 may reside within or on the processor chipset (e.g., native to processor 1400). In some other implementations, memory 1404 may reside external to the processor chipset (e.g., remote from processor 1400).

[0241] Memory 1404 may store computer-readable, computer-executable code, including instructions that, when executed by processor 1400, cause processor 1400 to perform the various functions described herein. The code may be stored in a non-transitory computer-readable medium, such as system memory or another type of memory. Controller 1402 and / or processor 1400 may be configured to execute computer-readable instructions stored in memory 1404 to cause processor 1400 to perform various functions. For example, processor 1400 and / or controller 1402 may be coupled to or coupled to memory 1404, and processor 1400, controller 1402, and memory 1404 may be configured to perform the various functions described herein. In some examples, processor 1400 may include multiple processors, and memory 1404 may include multiple memories. One or more of the multiple processors may be coupled to one or more of the multiple memories, which may be configured individually or collectively to perform the various functions described herein.

[0242] One or more ALU 1406s can be configured to support a variety of operations as described in the examples herein. In some implementations, one or more ALU 1406s may reside within or on a processor chipset (e.g., processor 1400). In some other implementations, one or more ALU 1406s may reside outside the processor chipset (e.g., processor 1400). One or more ALU 1406s can perform one or more calculations on data, such as addition, subtraction, multiplication, and division. For example, one or more ALU 1406s can receive input operands and an opcode that determines the operation to be performed. One or more ALU 1406s are configured with various logic and arithmetic circuitry, including adders, subtractors, shifters, and logic gates, to process and manipulate data according to the operations. Alternatively or concurrently, one or more ALU 1406 may support logical operations such as AND, OR, XOR, NOR, and NAND, enabling one or more ALU 1406 to handle conditional operations, comparisons, and bitwise operations.

[0243] Based on the examples disclosed herein, processor 600 can support wireless communication. Processor 600 can be configured to support components for performing the following: determining the synchronization delay state of data in a synchronized transmission set; and prioritizing data transmission based on the synchronization delay state of the data.

[0244] Alternatively, in some implementations, the processor 1400 may be configured to support components for performing the following: determining the latency state of data based on at least one of a plurality of thresholds; and prioritizing data transmission based on one of the plurality of thresholds.

[0245] Alternatively, in some implementations, the processor 1400 may be configured to support components for performing the following: determining the synchronization delay state of data in a synchronized transmission set; and maximizing data transmission based on determining that uplink grant is sufficient to accommodate the data.

[0246] Figure 15 A flowchart illustrating a method 1500 supporting logical channel priority based on synchronization delay state according to various aspects of this disclosure is shown. Operation of method 1500 can be implemented by the device or components thereof described herein. For example, operation of method 1500 can be performed by the UE 104 described herein. In some implementations, the device can execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively or concurrently, the device can use dedicated hardware to perform aspects of the described functions.

[0247] At 1510, the method may include determining the synchronization delay state of the data in the synchronized transmission set. The operation at 1510 can be performed according to the examples described herein. In some implementations, aspects of the operation at 1510 may be derived from references... Figure 1 The aforementioned device performs the operation.

[0248] At 1520, the method may include prioritizing data transmission based on the data's synchronization delay state. The operation at 1520 can be performed according to the examples described herein. In some implementations, aspects of the operation at 1520 can be found in the references. Figure 1 The aforementioned device performs the operation.

[0249] Figure 16A flowchart illustrating a method 1600 supporting logical channel priority based on synchronization delay state according to various aspects of this disclosure is shown. Operation of method 1600 can be implemented by the device or components thereof described herein. For example, operation of method 1600 can be performed by the UE 104 described herein. In some implementations, the device can execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively or concurrently, the device can use dedicated hardware to perform aspects of the described functions.

[0250] At 1610, the method may include determining the delay state of the data based on at least one of a plurality of thresholds. The operation of 1610 can be performed according to the examples described herein. In some implementations, aspects of the operation of 1610 may be derived from references... Figure 1 The aforementioned device performs the operation.

[0251] At 1620, the method may include prioritizing data transmission based on one of a plurality of thresholds. The operation at 1620 can be performed according to the examples described herein. In some implementations, aspects of the operation at 1620 can be found in the references. Figure 1 The aforementioned device performs the operation.

[0252] Figure 17 A flowchart illustrating a method 1700 supporting logical channel priority based on synchronization delay state according to various aspects of this disclosure is shown. Operation of method 1700 can be implemented by the device or components thereof described herein. For example, operation of method 1700 can be performed by the UE 104 described herein. In some implementations, the device can execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively or concurrently, the device can use dedicated hardware to perform aspects of the described functions.

[0253] At 1710, the method may include determining the synchronization delay state of the data in the synchronized transport set. The operation of 1710 can be performed according to the examples described herein. In some implementations, aspects of the operation of 1710 may be derived from references... Figure 1 The aforementioned device performs the operation.

[0254] At 1720, the method may include maximizing data transmission based on determining that the uplink grant is sufficient to accommodate the data. The operation at 1720 can be performed according to the examples described herein. In some implementations, aspects of the operation at 1720 can be found in the references. Figure 1 The aforementioned device performs the operation.

[0255] It should be noted that, for reference Figures 1 to 12 The implementations of this disclosure described herein are also applicable to device 1300, processor 1400, and methods 1500, 1600, and 1700.

[0256] It should be noted that the methods described in this paper describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are also possible. Furthermore, aspects from two or more methods can be combined.

[0257] The various illustrative boxes and components disclosed herein can be implemented or performed using a general-purpose processor, DSP, ASIC, CPU, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0258] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located in various locations, including being distributed such that portions of the functions are implemented in different physical locations.

[0259] Computer-readable media include both non-transitory computer storage media and communication media, with communication media including any medium that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer. For example, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable ROM (EEPROM), flash memory, optical disc (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor.

[0260] As used herein, including in the claims, the article “a” preceding an element is unrestricted and should be understood to mean “at least one” or “one or more” of those elements. The terms “a,” “at least one,” “one or more,” and “at least one of one or more” are interchangeable. As used herein, including in the claims, the use of “or” in a list of items (e.g., a list of items beginning with phrases such as “at least one of…” or “one or more of…” or “one or both of…”) indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase “based on” should not be construed as a reference to a closed set of conditions. For example, an example step described as “based on condition A” without departing from the scope of this disclosure could be based on both condition A and condition B. In other words, as used herein, the phrase “based on” should be interpreted in the same manner as the phrase “at least partially based on.” Furthermore, as used herein, including in the claims, “set” can include one or more elements.

[0261] The description provided herein is intended to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A user equipment (UE), comprising: processor; as well as A transceiver, the transceiver being coupled to the processor, The processor is configured as follows: Determine the synchronization delay state of the data in the synchronous transmission set; and The data is prioritized for transmission based on the synchronization delay status of the data.

2. The UE of claim 1, wherein the processor is configured to prioritize the transmission of the data based on the synchronization delay state of the data in the following manner: Prioritize the transmission of data of the first type in the synchronous transmission set, wherein the synchronization delay state includes the first remaining synchronization delay of the first type of data, and the first remaining synchronization delay of the first type of data is lower than a first threshold.

3. The UE of claim 1, wherein the processor is configured to prioritize the transmission of the data in the following manner: The data is prioritized for transmission based on the synchronization delay state of the data and the value maintained for the first logical channel (LCH) containing the data.

4. The UE of claim 1, wherein the processor is configured to prioritize the transmission of the data in the following manner: The data is prioritized for transmission based on the synchronization delay state of the data, regardless of the value maintained for the first logical channel (LCH) containing the data.

5. The UE of claim 1, wherein the processor is configured to prioritize the transmission of the data by one of the following: Data of the first LCH is transmitted preferentially, wherein the first LCH has data of a first type and the first residual synchronization delay of the first type of data is lower than a first threshold. Prioritize the transmission of all data in the synchronous transmission set; or The first type of data in the synchronous transmission set is transmitted with priority.

6. The UE of claim 2, wherein the processor is configured to prioritize the transmission of the first type of data in the following manner: Increase at least the first priority of the first type of data to the target priority.

7. The UE of claim 6, wherein the processor is further configured to: The transceiver receives the configuration for the target priority from the network entity. The target priority is determined based on the configuration.

8. The UE of claim 7, wherein the configuration for the target priority includes one of the following: Absolute target priority value, Priority offset value, or factor.

9. The UE of claim 6, wherein the processor is configured to increase at least the first priority of the first type of data to the target priority by one of the following: Increase the second priority of the first logical channel (LCH) to the target priority, wherein the first LCH has data of the first type; Only the first priority of the first type of data is increased to the target priority; or The third priority of the synchronous transmission set is increased to the target priority, wherein the synchronous transmission set includes data of the first type.

10. The UE of claim 1, wherein the processor is further configured to: The transceiver receives a first indication from the network entity, the first indication indicating whether the data should be prioritized for transmission based on the synchronization delay state of the data.

11. A user equipment (UE), comprising: processor; as well as A transceiver, the transceiver being coupled to the processor, The processor is configured as follows: The data latency status is determined based on at least one of multiple thresholds; and The data is prioritized for transmission based on one of the multiple thresholds.

12. The UE of claim 11, wherein the data includes data of a first type, wherein the first residual synchronization delay of the first type of data is lower than a first threshold among the plurality of thresholds.

13. The UE of claim 12, wherein the processor is configured to prioritize the transmission of the data in the following manner: Receive a second indication from the network entity via the transceiver, the second indication indicating that the first type of data should be prioritized for transmission based on the first threshold; and Based on the second instruction, the first type of data is prioritized for transmission based on the first threshold.

14. The UE of claim 12, wherein the data further comprises a third type of data, wherein the third remaining time of the third type of data is lower than a second threshold among the plurality of thresholds.

15. The UE of claim 14, wherein the processor is configured to prioritize the transmission of the data in the following manner: Increase the first priority of the first type of data to the first target priority; and Increase the second priority of the third type of data to the second target priority.

16. The UE of claim 14, wherein the first logical channel (LCH) has both the first type of data and the third type of data.

17. The UE of claim 16, wherein the processor is configured to prioritize the transmission of the data in the following manner: Prioritize the transmission of one type of data, either the first type or the third type.

18. A user equipment (UE), comprising: processor; as well as A transceiver, the transceiver being coupled to the processor, The processor is configured as follows: Determine the synchronization delay state of the data in the synchronous transmission set; and Based on the determination that the uplink grant is sufficient to accommodate the data, the transmission of the data is maximized.

19. The UE of claim 18, wherein the processor is configured to maximize the transmission of the data by one of the following: To maximize the transmission of data in a first logical channel (LCH), wherein the first LCH has a first type of data and the first residual synchronization delay of the first type of data is less than a first threshold; Maximize the transmission of all data in the synchronous transmission set; or To maximize the transmission of the first type of data in the synchronous transmission set.

20. A processor for wireless communication, comprising: At least one memory; as well as A controller, coupled to the at least one memory, and configured such that the controller: Determine the synchronization delay status of the data in the synchronous transmission set; as well as The data is prioritized for transmission based on the synchronization delay status of the data.

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