Semiconductor device

Abstract

This invention provides a semiconductor device for improving the cooling performance of the central portion of a semiconductor element. The semiconductor device includes a bonding region and a semiconductor element. The bonding region is disposed on a circuit pattern. The semiconductor element is bonded to the bonding region. The bonding region includes a first region and a second region surrounding the first region. The semiconductor element covers the first and second regions and is bonded to the bonding region. The area of ​​the upper surface of the first region is smaller than the area of ​​the upper surface of the second region. The first region is formed of a material with better thermal conductivity than the second region and has any shape selected from cylinders, prisms, cones, and pyramids.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] Semiconductor devices used to control large currents are enlarged to ensure the current flow to each element and made thinner to improve their performance. In such semiconductor devices, semiconductor elements are prone to warping, bulging upwards. Patent Document 1 proposes a technique for suppressing the warping of semiconductor elements by using a pressing member.

[0003] Existing technical documents Patent documents

[0004] Patent Document 1: Japanese Patent No. 7006706 Patent Document 2: Japanese Patent Application Publication No. 2015-095561 Patent Document 3: Japanese Patent Application Publication No. 2004-296723 Summary of the Invention

[0005] The technical problem that the invention aims to solve

[0006] When bonding a warped semiconductor element that bulges upwards to a circuit pattern, the bonding material directly below the center of the semiconductor element becomes thicker. When the bonding material thickness varies, temperature distribution occurs during cooling. Therefore, due to differences in the degree of volume contraction during cooling, voids are more likely to form in areas where the bonding material is thicker.

[0007] During the operation of the inverter in a semiconductor device, the central part of the semiconductor element has the highest temperature. Therefore, such a void will hinder the heat dissipation, i.e., cooling, of the central part of the semiconductor element.

[0008] In order to solve the above-mentioned problems, the purpose of this disclosure is to provide a semiconductor device that improves the cooling performance of the central part of a semiconductor element.

[0009] Technical solutions to solve technical problems

[0010] The semiconductor device disclosed herein includes a bonding region and a semiconductor element. The bonding region is disposed on a circuit pattern. The semiconductor element is bonded to the bonding region. The bonding region includes a first region and a second region surrounding the first region. The semiconductor element covers the first and second regions and is bonded to the bonding region. The area of ​​the upper surface of the first region is smaller than the area of ​​the upper surface of the second region. The first region is formed of a material with better thermal conductivity than the second region and has any shape selected from cylinders, prisms, cones, and pyramids.

[0011] Invention Effects

[0012] According to this disclosure, a semiconductor device can be provided that improves the cooling performance of the central portion of a semiconductor element.

[0013] The purpose, features, aspects, and advantages of this disclosure will become more apparent from the following detailed description and accompanying drawings. Attached Figure Description

[0014] Figure 1 This is a partial cross-sectional view showing only the portion containing the semiconductor element in the structure of the semiconductor device in Embodiment 1.

[0015] Figure 2 This is a top view showing the structure of a semiconductor device.

[0016] Figure 3 This is a diagram showing an example of the materials used to form the first and second regions of the joint area.

[0017] Figure 4 It is a graph showing the relationship between the area of ​​the first region, the area of ​​the second region, the thermal conductivity of the first region, and the thermal conductivity of the second region.

[0018] Figure 5 This is a partial cross-sectional view showing only the portion containing the semiconductor element in the structure of the semiconductor device in Embodiment 4.

[0019] Figure 6 This is a top view showing the structure of a semiconductor device.

[0020] Figure 7 This is a partial cross-sectional view showing only the portion of the semiconductor device in Embodiment 5 that contains semiconductor elements.

[0021] Figure 8 It is a graph showing the relationship between the height of the protrusion, the warpage of the semiconductor element, and the thickness of the bonding material at the end of the semiconductor element. Detailed Implementation

[0022] <Implementation Method 1> Figure 1 This is a partial cross-sectional view showing only the portion containing the semiconductor element 5 in the structure of the semiconductor device 101 in Embodiment 1. The semiconductor device 101 includes an insulating substrate 1, a circuit pattern 2, a bonding region 3, a bonding material 4, and the semiconductor element 5. Figure 2 This is a top view showing the structure of the semiconductor device 101. Figure 2 The diagrams of bonding material 4 and semiconductor element 5 are omitted.

[0023] The insulating substrate 1 is formed, for example, of ceramic. A circuit pattern 2 is provided on the upper surface of the insulating substrate 1. The circuit pattern 2 is formed of a conductive material such as metal.

[0024] A bonding region 3 for bonding semiconductor element 5 is provided at a predetermined position in circuit pattern 2. The surface of bonding region 3 is plated with a metal material such as Ni. The plating process improves the bonding strength between semiconductor element 5 and circuit pattern 2.

[0025] The joining region 3 includes a first region 3A and a second region 3B. The first region 3A contains the center of the joining region 3. The second region 3B surrounds the first region 3A. The area of ​​the upper surface of the first region 3A is smaller than the area of ​​the upper surface of the second region 3B.

[0026] The first region 3A is formed of a different material than the second region 3B, and is formed of a material with better thermal conductivity than the second region 3B. The material of the second region 3B can be the same as the material of the circuit pattern 2 other than the first region 3A. That is, the second region 3B can be a part of the circuit pattern 2 other than the first region 3A. Figure 2 The upper surface of the first region 3A shown is circular, but it can also be polygonal. For example... Figure 1 As shown, the first region 3A runs through the circuit pattern 2. The first region 3A has a cylindrical or polygonal prism shape. The first region 3A can also have any shape among cones and polygons with its sides tilted.

[0027] Semiconductor element 5 is warped upwards in a convex shape relative to circuit pattern 2. Semiconductor element 5 is bonded to bonding region 3 by bonding material 4. Bonding material 4 is a conductive material such as solder. Semiconductor element 5 covers first region 3A and second region 3B and is bonded to bonding region 3.

[0028] Semiconductor element 5 is formed, for example, from a semiconductor such as Si. The semiconductor is preferably a wide-bandgap semiconductor such as SiC, GaN, Ga2O3, GeO2, or diamond. Semiconductor element 5 is a power semiconductor element, a control IC (Integrated Circuit) for controlling the power semiconductor element, etc. Semiconductor element 5 may include, for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a Schottky barrier diode, etc. Alternatively, semiconductor element 5 may include an RC-IGBT (Reverse-Conducting IGBT) in which an IGBT and a freewheeling diode are formed within a single semiconductor substrate.

[0029] In this semiconductor device 101, the cooling performance of the central part of the semiconductor element 5 is improved because the first region 3A has good thermal conductivity.

[0030] In summary, the semiconductor device 101 in Embodiment 1 includes a bonding region 3 and a semiconductor element 5. The bonding region 3 is disposed on the circuit pattern 2. The semiconductor element 5 is bonded to the bonding region 3. The bonding region 3 includes a first region 3A and a second region 3B surrounding the first region 3A. The semiconductor element 5 covers the first region 3A and the second region 3B and is bonded to the bonding region 3. The area of ​​the upper surface of the first region 3A is smaller than the area of ​​the upper surface of the second region 3B. The first region 3A is formed of a material with better thermal conductivity than the second region 3B and has any shape among cylinders, prisms, cones, and pyramids.

[0031] In the manufacturing process of semiconductor device 101, the molten bonding material 4 is cooled and solidified while in contact with the semiconductor element 5 and the bonding region 3. Because a first region 3A has better thermal conductivity than the second region 3B, the bonding material 4 directly below the center of the semiconductor element 5 is locally cooled. Even when the semiconductor element 5 bulges upwards and warps, causing a distribution in the thickness of the bonding material 4, the temperature distribution during the cooling process of the bonding material 4 is minimized. Therefore, voids caused by differences in volume shrinkage of the bonding material 4 corresponding to the temperature distribution are less likely to occur. That is, even when the bonding material 4 is solidified as a whole, the formation of voids can be suppressed.

[0032] Furthermore, even during inverter operation of the semiconductor device 101, the central portion of the semiconductor element 5, which generates a large amount of heat, can be cooled efficiently. Therefore, the operating characteristics of the semiconductor device 101 are improved.

[0033] Furthermore, when the first region 3A has a cone or pyramid shape, the heat generated from the semiconductor element 5 is effectively dissipated to the circuit pattern 2 and the insulating substrate 1 directly below the semiconductor element 5. Therefore, the cooling performance is further improved.

[0034] Furthermore, regarding the technology for suppressing warpage of the semiconductor element 5, Patent Document 2 corrects warpage by clamping both sides of the semiconductor element 5 with protruding electrodes. While the technology described in Patent Documents 1 or 2 corrects the warpage of the semiconductor element 5, it generates stress. Therefore, the semiconductor element 5 is required to be flexible, making it difficult to apply this technology to thin-film semiconductor elements 5. Additionally, Patent Document 3 proposes a heat dissipation structure covering the entire surface directly beneath the semiconductor element 5, but it lacks specific insights into cooling the central portion.

[0035] <Implementation Method 2> Figure 3This is a diagram showing an example of the material used to form the first region 3A and the second region 3B of the joining region 3.

[0036] The first region 3A is formed of a material with a higher thermal conductivity than the material forming the second region 3B. The first region 3A is formed, for example, of any material selected from Cu, Ag, and Au. The second region 3B is formed, for example, of Al or an Al alloy.

[0037] This configuration improves the cooling performance of the central portion of the semiconductor element 5. Because the temperature distribution during the cooling process of the bonding material 4 is reduced, void formation can be suppressed even when the bonding material 4 is completely solidified.

[0038] <Implementation Method 3> The area SA of the first region 3A is a value obtained by multiplying the ratio of the thermal conductivity λB of the second region 3B to the thermal conductivity λA of the first region 3A by the area SB of the second region 3B. Figure 4 It is a graph showing the relationship between the area SA of the first region 3A, the area SB of the second region 3B, the thermal conductivity λA of the first region 3A, and the thermal conductivity λB of the second region 3B.

[0039] This configuration improves the cooling performance of the central portion of the semiconductor element 5. Because the temperature distribution during the cooling process of the bonding material 4 is reduced, void formation can be suppressed even when the bonding material 4 is completely solidified.

[0040] <Implementation Method 4> Figure 5 This is a partial cross-sectional view showing only the portion containing the semiconductor element 5 in the structure of the semiconductor device 104 in Embodiment 4. Figure 6 This is a top view showing the structure of the semiconductor device 104. Figure 6 The diagrams of bonding material 4 and semiconductor element 5 are omitted. Figure 5 and Figure 6 Corresponding to Figure 1 and Figure 2 However, the differences will only be explained below.

[0041] The upper surface of the first region 3A includes a protrusion 3C whose height is higher than the upper surface of the second region 3B. The protrusion 3C is disposed in the center of the bonding region 3. The protrusion 3C is formed of a metal with a higher thermal conductivity than the circuit pattern 2 surrounding the protrusion 3C. Furthermore, the protrusion 3C is formed of a metal with good wettability to the bonding material 4 disposed between the semiconductor element 5 and the bonding region 3.

[0042] In the manufacturing process of semiconductor device 104, bonding material 4 is melted between protrusion 3C and semiconductor element 5, and gas (e.g., air) generated in the molten bonding material 4 is pushed out to the vicinity of protrusion 3C. Furthermore, by providing protrusion 3C, the thickness of bonding material 4 between protrusion 3C and semiconductor element 5 becomes thinner than the thickness of bonding material 4 without protrusion 3C. Therefore, cooling of bonding material 4 on protrusion 3C is promoted, and the temperature distribution during the cooling process is reduced. For example, bonding material 4 on protrusion 3C solidifies faster than bonding material 4 around protrusion 3C. As a result, the formation of voids directly below the center of semiconductor element 5 is suppressed.

[0043] In this way, the cooling performance of the central part of the semiconductor element 5 is improved, and the temperature distribution during the cooling process of the bonding material 4 is reduced. Even when the bonding material 4 is solidified as a whole, the formation of voids can be suppressed.

[0044] <Implementation Method 5> Corresponding to Figure 5 , Figure 7 This is a partial cross-sectional view of the semiconductor device 105 in Embodiment 5, showing only the portion containing the semiconductor element 5. Figure 8 It is a diagram showing the relationship between the height of the protrusion 3C, the warpage of the semiconductor element 5, and the thickness of the bonding material 4 at the end of the semiconductor element 5.

[0045] The height D of the protrusion 3C has a value greater than or equal to the sum of the thickness d2 of the bonding material 4 disposed between the end of the semiconductor element 5 and the upper surface of the second region 3B, and the warpage d1 of the semiconductor element 5. For example, the height of the protrusion 3C has a value greater than or equal to the sum of the minimum thickness of the bonding material 4 that should be ensured at that end and the warpage of the semiconductor element 5.

[0046] In the manufacturing process of semiconductor device 105, bonding material 4 is melted between protrusion 3C and the bent semiconductor element 5, and gas (e.g., air) generated in the molten bonding material 4 is pushed out to the vicinity of protrusion 3C. Furthermore, by providing protrusion 3C, the thickness of bonding material 4 between protrusion 3C and semiconductor element 5 becomes thinner than the thickness of bonding material 4 without protrusion 3C. Therefore, cooling of bonding material 4 on protrusion 3C is promoted, and the temperature distribution during the cooling process is reduced. For example, bonding material 4 on protrusion 3C solidifies faster than bonding material 4 around protrusion 3C. As a result, the formation of voids directly below the center of semiconductor element 5 is suppressed.

[0047] In embodiment 5, the heterogeneous material embedded in the first region 3A, the area occupied by the first region 3A in the bonding region 3, and the protrusion height of the first region 3A are optimized. As a result, the cooling performance of the central portion of the semiconductor element 5 is improved, and the temperature distribution during the cooling process of the bonding material 4 becomes extremely small. Even when the bonding material 4 is completely solidified, the formation of voids can be suppressed.

[0048] While this disclosure has been described in detail, the foregoing description is exemplary in all respects and not restrictive. It is to be understood that numerous variations not illustrated are conceivable.

[0049] In addition, the various implementation methods can be freely combined, or the various implementation methods can be appropriately modified or omitted.

[0050] Label Explanation

[0051] 1 Insulating substrate, 2 Circuit pattern, 3 Bonding area, 3A First area, 3B Second area, 3C Protrusion, 4 Bonding material, 5 Semiconductor element, 101 Semiconductor device, 104 Semiconductor device, 105 Semiconductor device.

Claims

1. A semiconductor device, characterized in that, include: A bonding region is provided in a circuit pattern for bonding semiconductor elements to the circuit pattern; as well as The semiconductor element is bonded to the bonding region. The joining region includes a first region and a second region surrounding the first region. The semiconductor element covers the first region and the second region and is bonded to the bonding region. The area of ​​the upper surface of the first region is smaller than the area of ​​the upper surface of the second region. The first region is formed of a material with better thermal conductivity than the second region, and has any shape among cylinders, prisms, cones, and pyramids.

2. The semiconductor device as claimed in claim 1, characterized in that, The second region is formed of Al or an Al alloy. The first region is formed of any material among Cu, Ag, and Au, which has a higher thermal conductivity than the material forming the second region.

3. The semiconductor device as claimed in claim 1 or 2, characterized in that, The area of ​​the first region has a value obtained by multiplying the ratio of the thermal conductivity of the second region to the thermal conductivity of the first region by the area of ​​the second region.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The upper surface of the first region includes a protrusion that is higher than the upper surface of the second region. The protrusion is formed of a metal with a higher thermal conductivity than the surrounding area and good wettability to the bonding material disposed between the semiconductor element and the bonding region.

5. The semiconductor device as claimed in claim 4, characterized in that, The height of the protrusion has a value greater than or equal to the sum of the thickness of the bonding material disposed between the end of the semiconductor element and the upper surface of the second region and the warpage of the semiconductor element.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The semiconductor element warps upward in a convex shape relative to the circuit pattern.

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