Semiconductor package and method of forming

Abstract

Some embodiments of this document provide a semiconductor package and a method of forming it. The semiconductor package includes a semiconductor die having a first set of conductive structures connected to a substrate having a second set of conductive structures, wherein the height profile of the second set of conductive structures includes curvature relative to the surface of the substrate. This curvature is configured to compensate for warpage (e.g., offset warpage) that may be induced in the semiconductor die and / or the substrate during a reflow process that connects the semiconductor die and the substrate. By compensating for this warpage, the flatness of the interface region containing the solder joints between the first and second sets of conductive structures is increased. Increasing this flatness relative to another semiconductor package containing another substrate with conductive structures but without the profile having the curvature reduces solder joint defects in the semiconductor package.

Description

[0001] Cross-reference of related applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 611,488, filed December 18, 2023, entitled "SEMICONDUCTOR PACKAGE AND METHODS OF FORMATION," and U.S. Non-Provisional Patent Application No. 18 / 960,992, filed November 26, 2024, entitled "SEMICONDUCTOR PACKAGE AND METHODS OF FORMATION," both of which are assigned to their assigns. The disclosure of the earlier applications is considered part of this patent application and is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to semiconductor devices and methods of forming semiconductor devices. For example, this disclosure relates to a semiconductor package and a method of forming it. Background Technology

[0004] A semiconductor package may include a semiconductor substrate, one or more semiconductor electronic components coupled to and / or embedded in the semiconductor substrate, and a housing formed over the semiconductor substrate to encapsulate the one or more semiconductor electronic components. The one or more semiconductor electronic components may be interconnected by electrical interconnects to form one or more semiconductor devices, such as one or more integrated circuits (ICs) (e.g., one or more dies or chips). For example, the semiconductor electronic components and electrical interconnects may be fabricated on a semiconductor wafer to form one or more ICs, after which the semiconductor wafer is diced into dies or chips and then packaged. A semiconductor package may be referred to as a semiconductor chip package containing one or more ICs. A semiconductor package protects the semiconductor electronic components and electrical interconnects from damage and includes mechanisms for connecting the semiconductor electronic components and electrical interconnects to external components (e.g., a circuit substrate), such as through-hole balls, pins, leads, contact pad structures, or other electrically conductive structures. A semiconductor device assembly may be or may include a semiconductor package, multiple semiconductor packages, and / or one or more components of a semiconductor package (e.g., one or more semiconductor devices with or without a housing).

[0005] An electronic system assembly may include multiple semiconductor packages electrically coupled to a carrier substrate (e.g., a circuit substrate). The electronic system assembly may include additional system components electrically coupled to the carrier substrate. The carrier substrate may contain electrical interconnects and conductive paths for interconnecting the system components, which include the multiple semiconductor packages of the electronic system assembly and other system components. Thus, multiple semiconductor packages may be electrically connected to each other and / or electrically connected to one or more additional system components via the carrier substrate to form the electronic system assembly. By way of example, other system components may include passive components (e.g., storage capacitors), processing units (e.g., central processing units (CPUs), graphics processing units (GPUs), microprocessors, and / or microcontrollers), control units (e.g., microcontrollers, memory controllers, and / or power management controllers), or one or more other electronic components. Attached Figure Description

[0006] Figure 1 This is a diagram of an example device that can be manufactured using the techniques described herein.

[0007] Figure 2 This is a diagram of an example memory device that can be manufactured using the techniques described herein.

[0008] Figure 3A and 3B This is a diagram of the example implementation scheme described in this article.

[0009] Figure 4A and 4B This is a diagram of the example implementation scheme described in this article.

[0010] Figure 5 This is a flowchart of an example method associated with forming the substrate described herein.

[0011] Figure 6 This is a flowchart of an example method associated with forming the semiconductor package described herein.

[0012] Figures 7A to 7D These are a series of fabrication operations that can be performed to form a substrate having the set of conductive structures described herein.

[0013] Figure 8 This is a diagram of the example implementation scheme described in this article.

[0014] Figure 9 This is a diagram of the example implementation scheme described in this article. Detailed Implementation

[0015] A semiconductor package (e.g., a semiconductor device assembly) may include a substrate (e.g., and an interposer) and one or more semiconductor components stacked on and / or on the substrate. For example, the semiconductor package may correspond to a flip-chip type semiconductor package, wherein the semiconductor die is attached to the substrate using a combination of conductive structures between the semiconductor die and the substrate. The combination of conductive structures may include a first set of conductive structures (e.g., an array of pillars and / or bump structures) on the semiconductor die, which is connected to a second set of conductive structures (e.g., an array of pad structures or traces) on the substrate. The first and second sets of conductive structures can be connected using a reflow process that creates solder joints between the first and second sets of conductive structures.

[0016] In some cases, the thickness of the semiconductor die can cause thermal stress and / or strain during reflow to lead to die warping. Additionally or alternatively, the substrate may warp during reflow. Warping of the semiconductor die and / or substrate can result in the contours of the first and / or second sets of conductive structures exhibiting curvature that prevents reliable solder joint formation between them. Examples of solder joint defects that may be induced by curvature include non-wetting open-circuit solder joint defects and pillow effect solder joint defects.

[0017] Some embodiments of this document provide a semiconductor package and a method of forming it. The semiconductor package includes a semiconductor die having a first set of conductive structures connected to a substrate having a second set of conductive structures, wherein the height profile of the second set of conductive structures includes curvature relative to the surface of the substrate. The curvature is configured to compensate for warpage (e.g., offset warpage) that may be induced in the semiconductor die and / or substrate during a reflow process that connects the semiconductor die and the substrate. By compensating for warpage, the flatness of the interface region containing the solder joints between the first and second sets of conductive structures is increased. This increased flatness reduces solder joint defects in the semiconductor package relative to another semiconductor package containing another substrate having conductive structures but without a profile having the aforementioned curvature.

[0018] This improves the quality and reliability of semiconductor packaging. By improving the quality and reliability of semiconductor packaging, the amount of resources (e.g., labor, semiconductor manufacturing tools, raw materials, and / or computing resources) needed to support markets that consume semiconductor packaging can be reduced.

[0019] Figure 1This is a diagram of an example device 100 that can be manufactured using the techniques described herein. Device 100 may include any type of device or system comprising one or more integrated circuits 105. For example, device 100 may include memory devices, flash memory devices, NAND memory devices, NOR memory devices, random access memory (RAM) devices, read-only memory (ROM) devices, dynamic RAM (DRAM) devices, static RAM (SRAM) devices, solid-state drives (SSDs), microchips and / or system-on-a-chip (SoCs), and other examples. In some cases, device 100 may be referred to as a semiconductor package, assembly, semiconductor device assembly, or integrated assembly.

[0020] like Figure 1 As shown, device 100 may include one or more integrated circuits 105 disposed on substrate 110, shown as a first integrated circuit 105-1 and a second integrated circuit 105-2. Integrated circuit 105 may include any type of circuitry, such as analog circuits, digital circuits, radio frequency (RF) circuits, power supplies, power management circuits, input / output (I / O) chips, application-specific integrated circuits (ASICs), logic integrated circuits, field-programmable gate arrays (FPGAs), and / or memory integrated circuits (e.g., NAND memory devices, NOR memory devices, RAM devices, or ROM devices), and other examples. Substrate 110 may include a multilayer printed circuit board substrate (PCB), a ceramic substrate, or a silicon substrate having one or more conductive redistribution layers (RDLs), and other examples.

[0021] Integrated circuit 105 may be mounted on or otherwise disposed on the surface of substrate 110. Although, by way of example, device 100 is shown to include two integrated circuits 105, device 100 may include a different number of integrated circuits 105.

[0022] In some embodiments, integrated circuit 105 may comprise a single semiconductor die (sometimes referred to as a die), as shown by die 115-1. In some embodiments, integrated circuit 105 may comprise multiple semiconductor dies 115 (sometimes referred to as dies), as shown by a second integrated circuit 105-2, which is shown as comprising five semiconductor dies 115-2 to 115-6.

[0023] like Figure 1As shown, for an integrated circuit 105 comprising multiple dies 115, the dies 115 can be stacked on top of each other to reduce the footprint of the device 100. In some embodiments, spacers may be present between adjacent dies 115 in the stack to achieve electrical isolation and heat dissipation. The stacked dies 115 may include three-dimensional electrical interconnects (e.g., through-silicon vias (TSVs)) to route electrical signals between the dies 115. Although integrated circuit 105-2 is shown as comprising five dies 115, integrated circuit 105 may comprise a different number of dies 115 (e.g., at least two dies 115). A first die 115-2 (sometimes referred to as the bottom die or substrate die) may be disposed on a substrate 110, a second die 115-3 may be disposed on the first die 115-2, and so on. Figure 1 The diagram shows a die 115 stacked in a straight stack (e.g., with aligned die edges), but in some embodiments, the die 115 may be stacked in a different arrangement (e.g., shingled stack (e.g., with misaligned die edges, which provides space for wire bonding near the edges of the die 115)).

[0024] Device 100 may include a housing 120 that protects internal components of device 100 (e.g., integrated circuit 105) from damage that could cause device 100 to malfunction and from environmental factors (e.g., particles). Depending on the functional requirements of device 100, housing 120 may be a molding compound, plastic (e.g., epoxy plastic), ceramic, or another type of material.

[0025] In some implementations, device 100 may be included as part of a more advanced system (e.g., a computer, mobile phone, network device, SSD, vehicle, or Internet of Things device), for example, by electrically connecting device 100 to circuit board 125 (e.g., a printed circuit board). For example, substrate 110 may be disposed on circuit board 125 such that electrical contacts 130 of substrate 110 (e.g., bonding pad structures) are electrically connected to electrical contacts 135 (e.g., bonding pad structures) of circuit board 125.

[0026] In some embodiments, substrate 110 may be mounted on circuit board 125 using solder balls 140 (e.g., arranged in a ball grid array), which may be fused to form a physical and electrical connection between substrate 110 and circuit board 125. Alternatively, substrate 110 may be mounted on and / or electrically connected to circuit board 125 using another type of connector (e.g., pins or leads). Similarly, integrated circuit 105 may include electrical pad structures (e.g., bonding pad structures) that are electrically connected to corresponding electrical pad structures (e.g., bonding pad structures) on substrate 110 using electrical connections (e.g., wire bonding, bump bonding, or the like). The interconnections between integrated circuit 105, substrate 110, and circuit board 125 enable integrated circuit 105 to receive signals and transmit signals to other components of device 100 and / or more advanced systems.

[0027] In some embodiments, one or more of the dies are flip-chip dies, wherein the flip-chip die includes an array of conductive structures (e.g., pillars or bumps) facing the substrate 110 and connected to pad structures and / or traces on the substrate 110. For example, and as in combination Figure 3A , 3B As described in more detail in sections 4A, 4B, 9 and elsewhere herein, dies 115-1 and / or 115-2 may be connected to pad structures or traces contained in regions 145 and / or 150 of substrate 110 using an array of pillars, solder balls, and / or bumps. Furthermore, and in some embodiments, the thickness of the pad structures and / or traces within regions 145 and / or 150 is varied to create a profile of the pad structures and / or traces that compensates for warpage of die 115-1 and / or substrate within regions 145 and / or 150. By compensating for warpage, defects such as non-wetting open-circuit faults and / or pillow effect faults can be reduced, thereby improving the quality and / or reliability of device 100.

[0028] As indicated above, Figure 1 Provided as an example. Other examples are available in relation to [the example provided]. Figure 1 The descriptions are different.

[0029] Figure 2 This is a diagram of an example memory device 200 manufactured using the techniques described herein. Memory device 200 is an example memory device 200 as described above. Figure 1An example of the described device 100. The memory device 200 can be any electronic device configured to store data in memory. In some embodiments, the memory device 200 can be an electronic device configured to persistently store data in non-volatile memory 205. For example, the memory device 200 can be a hard disk drive, SSD, flash memory device (e.g., NAND flash memory device or NOR flash memory device), Universal Serial Bus (USB) thumb drive, memory card (e.g., Secure Digital (SD) card), secondary storage device, non-volatile memory fast (NVMe) device, and / or embedded multimedia card (eMMC) device.

[0030] As shown, memory device 200 may include non-volatile memory 205, volatile memory 210, and controller 215. Components of memory device 200 may be mounted on or otherwise disposed on substrate 220. In some embodiments, non-volatile memory 205 comprises a single die. Alternatively or additionally, non-volatile memory 205 may comprise multiple dies, such as stacked semiconductor dies 225 (e.g., in a straight stack, a shingled stack, or another type of stack), as described above. Figure 1 describe.

[0031] Non-volatile memory 205 may be configured to retain stored data after power loss of memory device 200. For example, non-volatile memory 205 may include NAND memory or NOR memory. Volatile memory 210 may require power to retain stored data and may lose stored data after power loss of memory device 200. For example, volatile memory 210 may include one or more latches and / or RAM, such as DRAM and / or SRAM. As an example, volatile memory 210 may cache data read from or to be written to non-volatile memory 205, and / or cache instructions to be executed by controller 215.

[0032] Controller 215 may be any device configured to communicate (e.g., via a host interface of memory device 200) with non-volatile memory 205, volatile memory 210, and the host device. For example, controller 215 may include a memory controller, system controller, ASIC, FPGA, processor, microcontroller, and / or one or more processing components. In some embodiments, memory device 200 may be included in a system that includes a host device. The host device may include one or more processors configured to execute instructions and store data in non-volatile memory 205.

[0033] Controller 215 may be configured to control the operation of memory device 200, for example, by executing one or more instructions (sometimes referred to as commands). For example, memory device 200 may store one or more instructions as firmware, and controller 215 may execute said one or more instructions. Alternatively, controller 215 may receive one or more instructions from a host device via a host interface, and may execute said one or more instructions. For example, controller 215 may transmit signals to and / or receive signals from non-volatile memory 205 and / or volatile memory 210 based on one or more instructions, for example, to transfer (e.g., write or program) data to or from all or part of non-volatile memory 205 (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes of non-volatile memory 205), to or from all or part of non-volatile memory 205 (e.g., read), and / or erase all or part of non-volatile memory 205.

[0034] As indicated above, Figure 2 Provided as an example. Other examples are available in relation to [the example provided]. Figure 2 The descriptions are different. Figure 2 The number and arrangement of components shown are provided as examples. In reality, with... Figure 2 Compared to what is shown, there may be additional components, fewer components, different components, or components arranged in a different way.

[0035] Figure 3A and 3B This is a diagram of the example implementation scheme 300 described herein. Implementation scheme 300 may correspond to... Figure 1 The device 100 corresponds to region 145. Alternatively, embodiment 300 may correspond to a semiconductor package comprising a single die (e.g., die 115-1). In embodiment 300, a reflow process connecting substrate 110 and die 115-1 induces a first warpage of substrate 110 and a second warpage of die 115-1. In embodiment 300, the first warpage extends toward die 115-1, and the second warpage extends toward substrate 110. In other words, the warpages of substrate 110 and die 115-1 have opposite curvatures extending toward each other (e.g., curvatures with opposite orientations).

[0036] like Figure 3AAs shown, a set of conductive structures 305 is on a bare die 115-1. The set of conductive structures 305 may include pillar structures 310 and solder balls 315 on (e.g., connected to) the pillar structures 310. The pillar structures 310 may contain a conductive material, such as copper (Cu), gold (Au), silver (Ag), or another suitable conductive material. The solder balls 315 may contain a solderable alloy, such as a tin-lead (Sn-Pb) alloy, a tin-silver-copper (Sn-Ag-Cu) alloy, a tin-copper (Sn-Cu) alloy, or another suitable solderable alloy.

[0037] like Figure 3A Further illustrated, a set of conductive structures 320 is present on the substrate 110. The set of conductive structures 320 may correspond to pad structures, traces, and / or bumps on the substrate 110, as well as other examples. The set of conductive structures 320 may comprise a combination of one or more conductive materials, such as copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), silver (Ag), gold (Au), or another suitable conductive material.

[0038] The set of conductive structures 305 and 320 are connected within the interface region 325. The interface region 325 includes solder joints between solder balls 315 and the set of conductive structures 320, wherein the solder joints are formed through a surface mount technology (SMT) and reflow process, wherein the process temporarily raises the temperature of the solder balls 315 to a liquid or semi-liquid phase, connects the solder balls 315 to the conductive structures 320, and cools the temperature of the solder balls 315 to the solid phase that forms the solder joints.

[0039] like Figure 3A As shown, the bare die 115-1 includes a curvature 330 with a radius of curvature 335, and the substrate 110 includes a curvature 340 with a radius of curvature 345. Furthermore, as... Figure 3A As shown, interface region 325 includes curvature 350 with radius of curvature 355, wherein radius of curvature 355 is greater than radius of curvature 335 and / or radius of curvature 345. In other words, interface region 325 is "flatter" than substrate 110 and / or die 115-1.

[0040] Such as combination Figure 3B In more detail, the height profile of the set of conductive structures 320 relative to the substrate 110 can compensate for curvatures 330 and / or 340 to improve the coplanarity of solder joints within the interface region 325. As an example, implementing this profile can result in a coplanarity of solder joints within the interface region 325 of less than about 10 micrometers (μm). Alternatively or, in other words, implementing this profile can result in a coplanarity of solder joints within the range of about -5 μm to about +5 μm. However, other values ​​and ranges for coplanarity are within the scope of this disclosure.

[0041] Figure 3B Details relating to the set of conductive structures 320 on substrate 110 are shown. For example... Figure 3B As shown, the set of conductive structures 320 includes a distribution of heights (e.g., height H) of a curved profile 360 ​​(e.g., a profile based on a variation in height H) formed relative to the surface 365 of the substrate 110. In some embodiments, the difference in height H across the curved profile 360 ​​(e.g., the difference between H1 and H2) can be as high as about 50 μm. However, other differences in height H are within the scope of this disclosure.

[0042] The bending profile 360 ​​can be determined using one or more modeling techniques to quantify the expected warpage of the substrate 110 and / or die 115-1, such as finite element analysis (FEA) modeling. Alternatively, the bending profile 360 ​​can be determined empirically using interferometry or laser measurement techniques that measure the warpage of the substrate 110 and / or die 115-1 after the SMT and reflow processes connecting the substrate 110 and die 115-1.

[0043] like Figure 3B As shown, the curved profile 360 ​​is a concave profile, wherein the curvature of the curved profile 360 ​​curves toward the surface 365. In some embodiments, the curved profile 360 ​​is a two-dimensional profile. In some embodiments, the curved profile 360 ​​is a three-dimensional profile (e.g., a "bowl-shaped" profile). Furthermore, and in some embodiments, the curved profile 360 ​​is a symmetrical profile (e.g., containing symmetrical curvature).

[0044] As indicated above, Figure 3A and 3B Provided as an example. Other examples are available in relation to [the example provided]. Figure 3A and 3B The descriptions are different.

[0045] Figure 4A and 4B This is a diagram of the example implementation scheme 400 described in this article. Figure 4A and 4B exhibit Figure 1 A detailed view of region 145. In embodiment 400, the reflow process connecting substrate 110 and die 115-1 induces a first warpage of substrate 110 and a second warpage of die 115-1. In embodiment 300, the first warpage extends away from die 115-1, and the second warpage extends away from substrate 110. In other words, the warpages of substrate 110 and die 115-1 have opposite curvatures extending toward each other.

[0046] like Figure 4AAs shown, a set of conductive structures 405 is on a bare die 115-1. The set of conductive structures 405 may include pillar structures 410 and solder balls 415 on (e.g., connected to) the pillar structures 410. The pillar structures 410 may contain a conductive material, such as copper (Cu), gold (Au), silver (Ag), or another suitable conductive material. The solder balls 415 may contain a solderable alloy, such as a tin-lead (Sn-Pb) alloy, a tin-silver-copper (Sn-Ag-Cu) alloy, a tin-copper (Sn-Cu) alloy, or another suitable solderable alloy.

[0047] like Figure 4A Further illustrated, a set of conductive structures 420 is present on the substrate 110. The set of conductive structures 420 may correspond to pad structures, traces, and / or bumps on the substrate 110, as well as other examples. The set of conductive structures 420 may comprise a combination of one or more conductive materials, such as copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), silver (Ag), gold (Au), or another suitable conductive material.

[0048] The set of conductive structures 405 and 420 are connected within the interface region 425. The interface region 425 includes solder joints between solder balls 415 and the set of conductive structures 420, wherein the solder joints are formed through a surface mount technology (SMT) and reflow process, wherein the process temporarily raises the temperature of the solder balls 415 to a liquid or semi-liquid phase, connects the solder balls 415 to the conductive structures 420, and cools the temperature of the solder balls 415 to the solid phase that forms the solder joints.

[0049] like Figure 4A As shown, the bare die 115-1 includes a curvature 430 with a radius of curvature 435, and the substrate 110 includes a curvature 440 with a radius of curvature 445. Furthermore, as... Figure 4A As shown, interface region 425 includes curvature 450 with radius of curvature 455, wherein radius of curvature 455 is greater than radius of curvature 435 and / or radius of curvature 445. In other words, interface region 425 is "flatter" than substrate 110 and / or die 115-1.

[0050] Such as combination Figure 4B In more detail, the height profile of the set of conductive structures 420 relative to the substrate 110 can compensate for curvatures 430 and / or 440 to improve the coplanarity of solder joints within the interface region 425. As an example, implementing this profile can result in a coplanarity of solder joints within the interface region 425 of less than 10 micrometers (μm). Alternatively or, in other words, implementing this profile can result in a coplanarity of solder joints within the range of approximately -5 μm to approximately +5 μm. However, other values ​​and ranges for coplanarity are within the scope of this disclosure.

[0051] Figure 4B Details relating to the set of conductive structures 420 on substrate 110 are shown. For example... Figure 4B As shown, the set of conductive structures 420 includes a distribution of heights (e.g., height H) forming a curved profile 460 (e.g., a profile of height H) relative to the surface 465 of the substrate 110. In some embodiments, the difference in height H across the curved profile 460 (e.g., the difference between H3 and H4) can be as high as about 50 μm. However, other differences in height H are within the scope of this disclosure.

[0052] The bending profile 460 can be determined using one or more modeling techniques, such as FEA modeling, to quantify the expected warpage of the substrate 110 and / or die 115-1. Alternatively, the bending profile 460 can be determined empirically using interferometry or laser measurement techniques that measure the warpage of the substrate 110 and / or die 115-1 after the SMT and reflow processes connecting the substrate 110 and die 115-1.

[0053] like Figure 4B As shown, the curved profile 460 is a convex profile, wherein the curvature of the curved profile 460 bends away from the surface 465. In some embodiments, the curved profile 460 is a two-dimensional profile. In some embodiments, the curved profile 460 is a three-dimensional profile (e.g., a "dome" profile). Furthermore, and in some embodiments, the curved profile 460 is a symmetrical profile (e.g., containing asymmetrical curvature).

[0054] As indicated above, Figure 4A and 4B Provided as an example. Other examples are available in relation to [the example provided]. Figure 4A and 4B The descriptions are different.

[0055] Such as combination Figure 3A , 3B As described in 4A and 4B, a set of conductive structures (e.g., the set of conductive structures 320 and / or 420) formed on a substrate of a semiconductor package (e.g., substrate 110 of device 100) may include curved profiles (e.g., curved profiles 360 and / or 460). The curved profiles can compensate for warpage of the substrate and / or die (e.g., die 115-1) to improve the coplanarity of the solder joints connecting the substrate and the die. This improves the quality and reliability of the semiconductor package. By improving the quality and reliability of the semiconductor package, the amount of resources (e.g., labor, semiconductor manufacturing tools, raw materials, and / or computing resources) required to support the market for consuming semiconductor packages is reduced.

[0056] Figure 5This is a flowchart of an example method 500 associated with forming the substrate described herein. In some embodiments, one or more semiconductor processing tools (e.g., lamination tools, photolithography tools, dispensing tools, electroplating tools, screen printing tools, reflow tools, etching tools, and / or substrate transport tools) of a substrate fabrication facility are executable or configurable to perform method 500. Therefore, components for performing method 500 may comprise one or more semiconductor processing tools and / or one or more components of one or more semiconductor processing tools. Additionally, or alternatively, a non-transitory computer-readable medium may store one or more instructions that, when executed by one or more semiconductor processing tools, cause the one or more semiconductor processing tools to perform method 500.

[0057] like Figure 5 As shown, method 500 may include forming a substrate (block 510). Figure 5 As further shown, method 500 may include forming a set of conductive structures (e.g., the set of conductive structures 320 or 420) on a substrate (e.g., substrate 110), the set of conductive structures having a highly curved profile (e.g., curved profile 360 ​​or 460) relative to the surface of the substrate (e.g., surface 365 or 465) (box 520).

[0058] Method 500 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods or operations described elsewhere herein.

[0059] In the first aspect, the set of conductive structures forming a highly curved profile relative to the surface of the substrate includes at least a portion of the set of conductive structures forming a convex profile that includes a height away from the surface of the substrate.

[0060] In the second aspect, either alone or in combination with the first aspect, the set of conductive structures forming a highly curved profile relative to the surface of the substrate includes at least a portion of the set of conductive structures forming a concave profile that includes the height of the surface facing the substrate.

[0061] In the third aspect, forming the set of conductive structures, either alone or in combination with one or more of the first and second aspects, comprises forming the set of conductive structures from one or more of copper, aluminum, tin, nickel, silver, or gold materials.

[0062] In the fourth aspect, forming the set of conductive structures, either alone or in combination with one or more of the first to third aspects, comprises forming the set of conductive structures on electrical traces on a substrate using a sequence of dry film patterning and electroplating operations, wherein the sequence of dry film patterning and electroplating operations forms a curved profile with a height relative to the surface of the substrate.

[0063] In the fifth aspect, the set of conductive structures is formed, either alone or in combination with one or more of the first to fourth aspects, comprising a conductive material layer formed on a substrate and using a sequence of masking and etching operations, wherein the sequence of masking and etching operations forms a curved profile relative to the height of the surface of the substrate.

[0064] although Figure 5 The instance box for method 500 is displayed, but in some implementations, it is different. Figure 5 Compared to the boxes depicted herein, method 500 may include additional boxes, fewer boxes, different boxes, or boxes arranged in a different manner. Alternatively, two or more boxes of method 500 may be executed in parallel. Method 500 is an example of a method that can be performed by one or more means described herein. These means may perform or be configured to perform one or more other methods based on the operations described herein.

[0065] Figure 6 This is a flowchart of an example method 600 associated with forming a semiconductor package (e.g., device 100) described herein. In some embodiments, one or more semiconductor processing tools (e.g., substrate delivery tools, wafer / die delivery tools, pick-and-place tools, reflow tools, dicing tools, solder screen printing tools, solder printing tools, and / or reflow tools) of a semiconductor package assembly facility may perform method 600 or may be configured to perform method 600. Thus, components for performing method 600 may comprise one or more semiconductor processing tools and / or one or more components of one or more semiconductor processing tools. Additionally, or alternatively, a non-transitory computer-readable medium may store one or more instructions that, when executed by one or more semiconductor processing tools, cause one or more semiconductor processing tools to perform method 600.

[0066] like Figure 6 As shown, method 600 may include receiving a semiconductor die (e.g., die 115-1) having a first set of conductive structures (e.g., the set of conductive structures 305 or 405) on a semiconductor die (box 610). Figure 6 As further shown, method 600 may include a receiving substrate (e.g., substrate 110) having a second set of conductive structures (e.g., said set of conductive structures 320 or 420) on the substrate, and the second set of conductive structures having a profile including a height of curvature (e.g., a curved profile 360 ​​or 460) relative to the surface of the substrate (e.g., surface 365 or 465) (box 620). Figure 6 As further shown, method 600 may include connecting a semiconductor die and a substrate by linking a first set of conductive structures and a second set of conductive structures (box 630).

[0067] Method 600 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods or operations described elsewhere herein.

[0068] In a first aspect, the first set of conductive structures includes an array of solder balls (e.g., solder balls 315 or 415), and connecting the semiconductor die and substrate by linking the first set of conductive structures and the second set of conductive structures includes performing a reflow process that links the solder balls to the second set of conductive structures, resulting in a first curvature of the semiconductor die (e.g., curvature 330 or 430) and a second opposite curvature of the substrate (e.g., curvature 340 or 440).

[0069] In the second aspect, either alone or in combination with the first aspect, a reflow process is performed to form an interface region (e.g., interface region 325 or 425) containing solder joints between the first set of conductive structures and the second set of conductive structures, wherein the radius of curvature of the interface region (e.g., radius of curvature 350 or 450) is greater than the radius of curvature of the first curvature (e.g., radius of curvature 335 or 445).

[0070] In the third aspect, a reflow process is performed alone or in combination with one or more of the first and second aspects to form an interface region containing solder joints between the first set of conductive structures and the second set of conductive structures, wherein the radius of curvature of the interface region is greater than the radius of curvature of the second opposite curvature (e.g., radius of curvature 345 or 445).

[0071] although Figure 6 The example box for method 600 is shown, but in some implementations, it is different from... Figure 6 Compared to the boxes depicted herein, method 600 may include additional boxes, fewer boxes, different boxes, or boxes arranged in a different manner. Alternatively, two or more boxes of method 600 may be executed in parallel. Method 600 is an example of a method that can be performed by one or more means described herein. These means may perform or be configured to perform one or more other methods based on the operations described herein.

[0072] Figures 7A to 7D This demonstrates a series of example fabrication operations 700 that can be performed to form a substrate having the set of conductive structures described herein. In some embodiments, the substrate corresponds to having, for example, bonding... Figure 4A and 4B The substrate 110 of the described set of conductive structures 420. Furthermore, one or more of a series of manufacturing operations 700 may correspond to bonding. Figure 5 Method 500 and / or Figure 6 Method 600 describes one or more boxes.

[0073] like Figure 7AAs shown, a conductive layer 705 is formed on a substrate 110. The conductive layer 705 may comprise a conductive material, such as copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), silver (Ag), gold (Au), or another suitable conductive material. In some embodiments, the conductive layer 705 may be part of or on an electrical trace or pad structure of the substrate 110. The conductive layer 705 may be formed using electroplating, lamination, physical vapor deposition (sputtering), or another suitable deposition technique.

[0074] like Figure 7A Further illustrating this, a masking pattern 710-1 (e.g., a first masking pattern having an opening) is formed on and / or over the conductive layer 705. In some embodiments, the masking pattern 710-1 comprises a dry film material (e.g., a photoresist material) laminated onto and / or over the conductive layer 705 and patterned using photolithography and etching techniques. Figure 7A As shown in the figure, the masking pattern 710-1 (e.g., dry film material) includes a thickness T1.

[0075] like Figure 7A As further shown, conductive structure 420-1 is formed on substrate 110. In some embodiments, the formation of conductive structure 420-1 includes constructing conductive structure 420-1 from conductive layer 705 within openings of masking pattern 710-1 using an electroplating technique. In some embodiments, the height of conductive structure 420 may be approximately equal to the thickness T1.

[0076] like Figure 7B As shown, the set of conductive structures 420 (e.g., including conductive structures 420-1 to 420-n) is formed using a sequence of operations (e.g., iterations), which can be performed using methods such as combining... Figure 7A The described patterning and / or electroplating techniques. For example, and as... Figure 7B As shown, the masking pattern 710-n includes a thickness Tn and is used to form a conductive structure 420.

[0077] Figure 7C A set of conductive structures 420 are shown on the conductive layer 705 after the removal of the masking patterns 710-n. In some embodiments, removing the masking patterns 710 includes using a chemical stripping technique to remove the masking patterns 710 to expose one or more of the set of conductive structures 420.

[0078] Figure 7D The set of conductive structures 420 is shown after a portion of the conductive layer 705 has been removed. (See diagram below.) Figure 7D As shown in the diagram, the set of conductive structures 420 includes, for example, a combination of... Figure 4BThe curved profile 460 is described. In some embodiments, removing a portion of the conductive layer 705 involves using a flash etching technique, wherein another masking pattern of the masking conductive structure 420 is formed over the substrate 110, and the unmasked portion of the conductive layer 705 is removed by rapidly heating and / or vaporizing the unmasked portion.

[0079] Other series of operations can be used to form the set of conductive structures 420 having the curved profile 460. As an example, another series of operations may include forming a single layer of conductive material on the substrate 110 using a series of masking and etching operations. A series of masking and etching operations may sequentially remove portions of the single conductive material layer to different depths to form the curved profile 460. As another example, another series of operations may include a series of deposition and / or printing (e.g., individual printing or batch screen printing) operations to form the set of conductive structures 420 having the curved profile 460.

[0080] As indicated above, Figures 7A to 7D Provided as an example. Other examples are available in relation to [the example provided]. Figures 7A to 7D The descriptions are different.

[0081] Figure 8 This is a diagram of the example implementation scheme 800 described in this document. Implementation scheme 800 may correspond to... Figure 1 The device 100 corresponds to region 145. Alternatively, embodiment 800 may correspond to a semiconductor package comprising a single die (e.g., die 115-1). Embodiment 800 includes a set of conductive structures 805 having a contour 810. Figure 8 As shown, profile 810 is an asymmetric profile (e.g., containing asymmetric curvature), which may be based on the expected warpage of the die (e.g., die 115-1) and / or substrate 110.

[0082] like Figure 8 As shown, contour 810 includes a portion 815 with a curvature of 820° and a portion 825 with a curvature of 830°. For example... Figure 8 As shown in the diagram, curvatures of 820 and 830 can be opposite curvatures.

[0083] In some implementation schemes, and such as Figure 8 As shown, at least a portion of the contour 810 includes a convex curvature (e.g., a portion 815 including a curvature 820 that bends away from the surface 835 of the substrate 110). Furthermore, and in some embodiments as shown... Figure 8 As shown, at least a portion of the profile 810 includes a concave curvature (e.g., a portion 825 including a curvature 830 that bends toward the surface 835 of the substrate 110).

[0084] As indicated above, Figure 8 Provided as an example. Other examples are available in relation to [the example provided]. Figure 8 The descriptions are different.

[0085] Figure 9 This is a diagram of the example implementation scheme 900 described in this document. Implementation scheme 900 may correspond to... Figure 1 The device 100 is located in region 150. Alternatively, embodiment 900 may correspond to a semiconductor package comprising a stack of multiple dies (e.g., dies 115-2 and 115-3).

[0086] In embodiment 900, the reflow process connecting the substrate 110 and the stack of multiple dies induces a first warpage of the substrate 110 and a second warpage of the stack of multiple dies. In embodiment 900, the first warpage extends toward the stack of multiple dies, and the second warpage extends toward the substrate 110. In other words, the warpages of the substrate 110 and the stack of multiple dies are opposite curvatures extending toward each other. However, and in some embodiments, the warpages of the substrate 110 and the stack of multiple dies are opposite curvatures extending away from each other.

[0087] like Figure 9 As shown, a set of conductive structures 905 is on a bare die 115-2. The set of conductive structures 905 may include pillar structures 910 and solder balls 915 on (e.g., connected to) the pillar structures 910. The pillar structures 910 may contain a conductive material, such as copper (Cu), gold (Au), silver (Ag), or another suitable conductive material. The solder balls 915 may contain a solderable alloy, such as a tin-lead (Sn-Pb) alloy, a tin-silver-copper (Sn-Ag-Cu) alloy, a tin-copper (Sn-Cu) alloy, or another suitable solderable alloy.

[0088] like Figure 9 Further illustrated, a set of conductive structures 920 is present on the substrate 110. The set of conductive structures 920 may correspond to pad structures, traces, and / or bumps on the substrate 110, as well as other examples. The set of conductive structures 920 may comprise a combination of one or more conductive materials, such as copper (Cu), aluminum (Al), tin (Sn), nickel (Ni), silver (Ag), gold (Au), or another suitable conductive material.

[0089] The set of conductive structures 905 and 920 are connected within the interface region 925. The interface region 925 includes solder joints between solder balls 915 and the set of conductive structures 920, wherein the solder joints are formed through an SMT and reflow process, wherein the process temporarily raises the temperature of the solder balls 915 to a liquid or semi-liquid phase, connects the solder balls 915 to the conductive structures 920, and cools the temperature of the solder balls 915 to the solid phase that forms the solder joints.

[0090] like Figure 9As shown, dies 115-2 and 115-3 are joined together using solder balls 930. Solder balls 930 may comprise a solderable alloy, such as a tin-lead (Sn-Pb) alloy, a tin-silver-copper (Sn-Ag-Cu) alloy, a tin-copper (Sn-Cu) alloy, or another suitable solderable alloy, and can connect the pad structure of die 115-2 to the backside overlay and / or traces of die 115-3. Alternatively, dies 115-2 and 115-3 may be joined using an adhesive (e.g., a layer of tape) or another suitable bonding structure.

[0091] In some implementations, dies 115-2 and 115-3 are memory dies used as part of a high-bandwidth memory (HBM) application. In other words, a device containing dies 115-2 and 115-3 (e.g., Figure 1 The device 100 may be a semiconductor package for HBM applications, such as artificial intelligence (AI) applications, machine learning applications, high-performance computing (HPC) applications, or virtual reality applications, and other instances.

[0092] like Figure 9 As shown, the stack of multiple bare dies includes a curvature 935 with a radius of curvature of 940, and the substrate 110 includes a curvature 945 with a radius of curvature of 950. Furthermore, as... Figure 9 As shown, interface region 925 includes curvature 955 with a radius of curvature 960, wherein curvature 960 is greater than radius of curvature 940 and / or radius of curvature 950. In other words, interface region 925 is "flatter" than substrate 110 and / or the stack of multiple dies including dies 115-2 and 115-3.

[0093] As indicated above, Figure 9 Provided as an example. Other examples are available in relation to [the example provided]. Figure 9 The descriptions are different.

[0094] In some embodiments, a semiconductor device assembly includes a semiconductor die comprising: a first set of conductive structures on the semiconductor die; and a substrate connected to the semiconductor die and including: a second set of conductive structures on the substrate, wherein the profile of the height of the second set of conductive structures relative to the surface of the substrate includes curvature, and wherein the second set of conductive structures is connected to the first set of conductive structures.

[0095] In some embodiments, a semiconductor device assembly includes: a semiconductor die including a first set of conductive structures on the semiconductor die; and a substrate coupled to the semiconductor die and including a second set of conductive structures on the substrate, wherein the profile of the height of the second set of conductive structures relative to the surface of the substrate includes curvature, and wherein the second set of conductive structures is coupled to the first set of conductive structures.

[0096] In some embodiments, a method includes forming a substrate; and forming a set of conductive structures on the substrate, the set of conductive structures having a highly curved profile relative to the surface of the substrate.

[0097] In some embodiments, a method includes: receiving a semiconductor die having a first set of conductive structures; receiving a substrate having a second set of conductive structures having a profile including a height with curvature relative to a surface of the substrate; and connecting the semiconductor die and the substrate by concatenating the first set of conductive structures and the second set of conductive structures.

[0098] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications and variations may be made based on the foregoing disclosure or may be derived from the practice of the implementations described herein.

[0099] The orientations of the various elements in the figures are shown as examples, and these examples are illustrative and can be rotated relative to the depicted orientation. The descriptions provided herein and the appended claims relate to any structure having the described relationships between various features, whether the structure is in the specific orientation shown in the figures or rotated relative to that orientation. Similarly, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” “middle,” “left,” and “right,” etc., are used herein to describe the relationship of one element to one or more other elements illustrated in the figures. Spatial relative terms are intended to cover different orientations of elements, structures, and / or assemblies in use or operation other than those depicted in the figures. Structures and / or assemblies may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are to be interpreted accordingly. Furthermore, unless otherwise indicated, the cross-sectional views in the figures only show features within the plane of the cross-section and do not show material behind the plane of the cross-section in order to simplify the figures.

[0100] As used herein, the terms “generally” and “about” mean “within reasonable tolerances of manufacturing and measurement.” As used herein, “meets the threshold” may, depending on the context, refer to a value greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, or similar.

[0101] Even in specific combinations of features recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features can be combined in ways not specifically recited in the claims or disclosed in the specification. For example, this disclosure includes each dependent claim in the claim set in combination with each other individual claim in that claim set, and each combination of multiple claims in that claim set. As used herein, the phrase “at least one of” in the list of items refers to any combination of those items containing a single member. As an example, “at least one of a, b, or c” is intended to cover a, b, c, a + b, a + c, b + c, and a + b + c, as well as any combination having multiple identical elements (e.g., a + a, a + a + a, a + a + b, a + a + c, a + b + b, a + c + c, b + b, b + b + b, b + b + c, c + c, and c + c + c, or any other ordering of a, b, and c).

[0102] No element, action, or instruction used herein should be construed as critical or necessary unless explicitly stated otherwise. Furthermore, as used herein, the article “a / an” is intended to include one or more items and is interchangeable with “one or more.” Additionally, as used herein, the article “the” is intended to include one or more items referenced in conjunction with the article “the” and is interchangeable with “the one or more.” If only one item is desired, then the phrase “only one,” “single,” or similar language is used. Furthermore, as used herein, the term “has / have / having” or similar is intended to be an open-ended term that does not limit the element it modifies (e.g., an element “having” A may also have B). Furthermore, the phrase “based on” is intended to mean “at least partially based on,” unless explicitly stated otherwise. As used herein, the term “multiple” can be replaced with “plural” and vice versa. Moreover, as used herein, the term “or” is intended to be inclusive when used in a series and is interchangeable with “and / or” unless otherwise expressly stated (e.g., if used in combination with “either one” or “only one of…”).

Claims

1. A semiconductor device assembly comprising: Semiconductor dies, comprising: A first set of conductive structures is located on the semiconductor die; and A substrate, which is connected to the semiconductor die and includes: The second set of conductive structures is located on the substrate. The contour of the height of the second set of conductive structures relative to the surface of the substrate includes curvature, and The second group of conductive structures is connected to the first group of conductive structures.

2. The semiconductor device assembly of claim 1, wherein the profile is a two-dimensional profile and the curvature is a convex curvature that bends away from the surface.

3. The semiconductor device assembly of claim 1, wherein the profile is a three-dimensional profile and the curvature is a convex curvature that bends away from the surface.

4. The semiconductor device assembly of claim 1, wherein the profile is a two-dimensional profile and the curvature is a concave curvature bending toward the surface.

5. The semiconductor device assembly of claim 1, wherein the profile is a three-dimensional profile and the curvature is a concave curvature bending toward the surface.

6. The semiconductor device assembly of claim 1, wherein the curvature is a symmetrical curvature.

7. The semiconductor device assembly of claim 1, wherein the curvature is asymmetric curvature.

8. The semiconductor device assembly of claim 1, wherein the curvature is a first curvature, wherein the profile includes a first portion comprising the first curvature, and wherein the profile further comprises: The second part has a second curvature that is opposite to the first curvature.

9. A semiconductor device assembly comprising: A semiconductor die, comprising a first set of conductive structures on the semiconductor die; and A substrate, coupled to the semiconductor die and including a second set of conductive structures on the substrate. The contour of the height of the second set of conductive structures relative to the surface of the substrate includes curvature, and The second set of conductive structures is coupled to the first set of conductive structures.

10. The semiconductor device assembly of claim 9, wherein the second set of conductive structures comprises: An array of pad structures.

11. The semiconductor device assembly of claim 9, wherein the second set of conductive structures comprises: An array of electrical traces.

12. The semiconductor device assembly of claim 9, wherein the first set of conductive structures comprises: Array of solder balls on an array of column structures The solder ball array forms solder joints with the second set of conductive structures along the interface region that connects the solder balls to the second set of conductive structures.

13. The semiconductor device assembly of claim 9, wherein the substrate corresponds to: Printed circuit board substrate, Ceramic substrate, or Silicon substrate.

14. The semiconductor device assembly of claim 9, wherein the semiconductor die corresponds to: Memory integrated circuit die, logic integrated circuit bare die, or Application-specific integrated circuit (ASIC) bare die.

15. The semiconductor device assembly of claim 9, wherein the semiconductor die is a first semiconductor die, and the semiconductor device assembly further comprises: A second semiconductor die is stacked on top of the first semiconductor die.

16. A method comprising: Forming a substrate; and A set of conductive structures is formed on the substrate, the set of conductive structures having a highly curved profile relative to the surface of the substrate.

17. The method of claim 16, wherein forming the set of conductive structures having the curved profile with a height relative to the surface of the substrate comprises: At least a portion of the set of conductive structures is formed to include a convex profile with a height opposite to the surface of the substrate.

18. The method of claim 16, wherein forming the set of conductive structures having the curved profile with a height relative to the surface of the substrate comprises: At least a portion of the set of conductive structures is formed to include a concave profile with a height of the surface facing the substrate.

19. The method of claim 16, wherein forming the set of conductive structures comprises forming the set of conductive structures by one or more of the following: copper materials Aluminum materials Tin materials Nickel materials Silver material, or gold material.

20. The method of claim 16, wherein forming the set of conductive structures comprises: The set of conductive structures is formed on the electrical traces of the substrate using a sequence of dry film patterning and electroplating operations. The sequence of dry film patterning and electroplating operations forms the curved profile at a height relative to the surface of the substrate.

21. The method of claim 16, wherein forming the set of conductive structures comprises: A single layer of conductive material is formed on the substrate using a sequence of masking and etching operations. The sequence of masking and etching operations forms the curved profile relative to the height of the surface of the substrate.

22. A method comprising: Receive a semiconductor die having a first set of conductive structures on the semiconductor die; A receiving substrate having a second set of conductive structures having a height profile that includes curvature relative to the surface of the substrate; and The semiconductor die and the substrate are connected by linking the first set of conductive structures and the second set of conductive structures.

23. The method of claim 22, wherein the first set of conductive structures comprises an array of solder balls, and The connection between the semiconductor die and the substrate by linking the first set of conductive structures and the second set of conductive structures includes: Performing a reflow process to connect the solder balls to the second set of conductive structures results in a first curvature of the semiconductor die and a second opposite curvature of the substrate.

24. The method of claim 23, wherein performing the reflow process forms an interface region including solder joints between the first set of conductive structures and the second set of conductive structures. The radius of curvature of the interface region is greater than the radius of curvature of the first curvature.

25. The method of claim 23, wherein performing the reflow process forms an interface region including solder joints between the first set of conductive structures and the second set of conductive structures. The radius of curvature of the interface region is greater than the radius of curvature of the second opposite curvature.

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