Semiconductor polishing quality control method and system based on online detection

Abstract

The present application relates to the online detection-based semiconductor polishing quality control method and system, relates to the semiconductor polishing technical field, and the method comprises the following steps: analyzing the mapping relationship parameter of the polishing target of the semiconductor structure and the process chain. According to the mapping relationship parameter, the anchor point analysis of each process quality is carried out, and the process anchor chain is constructed. The online detection data is collected, the semiconductor structure and the process quality anchor point analysis matching are carried out according to the process anchor chain, and the quality anchor point sequence of the current process is established. According to the quality anchor point sequence of the current process, the polishing parameter search of the current process is carried out, the polishing control parameter is obtained, and the current process control is carried out. The technical problem that the dynamic adjustment mechanism for different area differentiation polishing demand is lacked in the prior art, leading to poor polishing quality consistency and high defect rate. The technical effect of significantly improving wafer polishing precision, product yield, and guaranteeing overall processing production efficiency is realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor polishing technology, and more specifically to a semiconductor polishing quality control method and system based on online detection. Background Technology

[0002] Semiconductor wafer polishing is a core process in chip manufacturing. Polishing quality directly determines the surface flatness, roughness, and degree of various structural defects on the wafer, thus affecting the chip's electrical performance, yield, and service life. Currently, wafer polishing processes mostly use standardized process parameters to carry out rough polishing, fine polishing, and precision polishing throughout the entire process. However, due to the differences in polishing requirements for different structural regions and under different deviation states, a standardized process is difficult to match the differentiated polishing targets of each region, easily leading to over-polishing or under-polishing issues. Furthermore, current polishing processes are all inspected after polishing is completed, and quality defects can only be detected offline after processing. This lack of dynamic quality control and adjustment during process execution not only increases rework costs but also easily leads to batch scrap, making it difficult to meet the high-precision polishing quality control requirements of semiconductor wafers in advanced processes.

[0003] Therefore, the lack of a dynamic adjustment mechanism in the existing technology to meet the different polishing needs of different regions leads to technical problems such as poor polishing quality consistency and high defect rate. Summary of the Invention

[0004] This application provides a semiconductor polishing quality control method and system based on online detection, solving the technical problem in existing technologies that lack a dynamic adjustment mechanism for the differentiated polishing needs of different regions, leading to poor polishing quality consistency and high defect rates. It achieves precise matching of polishing requirements for different semiconductor structural parts, quantifies process constraints and constructs a hierarchical quality anchor chain, and dynamically optimizes polishing parameters based on online detection, significantly improving wafer polishing accuracy and finished product yield while ensuring overall processing efficiency.

[0005] This application provides a semiconductor polishing quality control method based on online detection. The method includes: parsing the mapping relationship parameters between the semiconductor structure polishing target and the process chain; performing anchor point analysis on the quality of each process according to the mapping relationship parameters to construct a process anchor point chain; collecting online detection data, performing semiconductor structure and process quality anchor point analysis and matching according to the process anchor point chain to establish a quality anchor point sequence for the current process; and searching for polishing parameters for the current process according to the quality anchor point sequence to obtain polishing control parameters and perform processing control for the current process.

[0006] In the implementation method, the mapping relationship parameters between the polishing targets of the semiconductor structure and the process chain are analyzed, including: analyzing the polishing targets of each structural part according to the semiconductor structure to obtain the polishing target feature distribution; performing process target and process polishing constraint analysis on the process chain based on the polishing target feature distribution to obtain process chain constraint parameters; and establishing the mapping relationship parameters between the polishing target features of each part of the semiconductor and the process chain based on the process chain constraint parameters. The process chain includes rough polishing, fine polishing, and precision polishing.

[0007] In the implementation method, the polishing target analysis of each structural part of the semiconductor structure is performed to obtain the polishing target feature distribution. This includes: determining the corresponding structural partitioning method according to the application type of the semiconductor and partitioning the semiconductor structure; and performing polishing feature analysis of each partition according to the application requirements of the structural partition to obtain the polishing target feature distribution. The polishing target features describe the polishing target requirements corresponding to each structure, including flatness target value, roughness target value, dish-shaped indentation depth limit, erosion depth limit, and allowable scratch depth upper limit.

[0008] In the implementation method, the structural partitioning method includes: partitioning the semiconductor structure according to the functional structure, including the central area, the edge area, and the wiring area; partitioning the semiconductor structure according to the layout structure, including the chip array area, the dicing area, the test structure area, the alignment mark area, the wafer notch area, and the edge exclusion area; and partitioning the semiconductor structure according to the process history, including the dish-shaped recess area and the thickness deviation area.

[0009] In the implementation method, the process chain is analyzed for each process target and process polishing constraint based on the polishing target feature distribution to obtain process chain constraint parameters. This includes: identifying the process parameter range corresponding to each structural part achieving the qualified polishing target in each process based on historical process data, and establishing a process requirement benchmark library; calculating the dependency coefficient of each process based on the process requirement benchmark library and historical deviation correction records, whereby the dependency coefficient reflects the probability that a deviation in the current process will be completely corrected by subsequent processes; setting a backtracking penalty factor based on the dependency coefficient and historical correction cost data to identify key processes that cannot be corrected by subsequent processes or whose correction cost exceeds a threshold; generating a set of constraint parameters for each structural part in each process based on the process requirement benchmark library, dependency coefficient, and backtracking penalty factor, and labeling each constraint parameter with a mandatory constraint coefficient; and establishing a process constraint list based on the constraint parameter set and mandatory constraint coefficient to obtain the process chain constraint parameters.

[0010] In the implementation method, anchor point analysis of the quality of each process is performed according to the mapping relationship parameters to construct a process anchor point chain, including: extracting process constraint parameters of each semiconductor part and each process according to the mapping relationship parameters, the process constraint parameters including removal amount range, pressure limit, endpoint detection sensitivity and forced constraint coefficient; setting a forced constraint coefficient threshold, determining whether the forced constraint coefficient is greater than the forced constraint coefficient threshold, if it is greater, then the physical quantity or region involved in the corresponding constraint parameter is determined as a quality anchor point, the quality anchor point includes time anchor point, spatial anchor point and event anchor point; according to the process sequence, the quality anchor points of each part in each process are sequentially connected, and the association rules between anchor points are established according to the dependency coefficient between processes to obtain the process anchor point chain.

[0011] In the implementation, online detection data is collected, and semiconductor structure and process quality anchor points are analyzed and matched according to the process anchor point chain to establish the quality anchor point sequence of the current process. This includes: retrieving all candidate anchor points and trigger conditions related to the corresponding process and part from the process anchor point chain based on the current polishing process number and the semiconductor structure part being polished on the current wafer; comparing the real-time collected detection data with the trigger conditions of the candidate anchor points one by one; and outputting the anchor points that meet the conditions according to the priority of constraint strength based on the trigger comparison results, as the quality anchor point sequence of the current process.

[0012] In the implementation, polishing parameters for the current process are searched based on the quality anchor point sequence to obtain polishing control parameters. This includes: for each active anchor point in the quality anchor point sequence, searching for a set of candidate control parameters corresponding to the anchor point from a preset parameter mapping library. The candidate control parameters include the adjustment amount of partition pressure, the adjustment amount of polishing head speed, the adjustment amount of polishing fluid flow rate, and the adjustment amount of dressing pressure. If there is only one anchor point in the sequence, the candidate parameters corresponding to the anchor point are directly output as the polishing control parameters for the current process. If there are multiple anchor points in the sequence, the corresponding candidate parameters are weighted and fused according to the priority weight of each anchor point to obtain comprehensive control parameters. If the quality anchor point sequence is empty, the default polishing control parameters are output, indicating that no additional adjustment is required for the current process.

[0013] This application also provides a semiconductor polishing quality control system based on online detection. The system includes: a parsing module for parsing the mapping relationship parameters between the semiconductor structure polishing target and the process chain; an anchor point chain construction module for performing anchor point analysis on the quality of each process according to the mapping relationship parameters and constructing a process anchor point chain; an anchor point sequence acquisition module for collecting online detection data, performing semiconductor structure and process quality anchor point analysis and matching according to the process anchor point chain, and establishing a quality anchor point sequence for the current process; and a processing control module for searching for polishing parameters for the current process according to the quality anchor point sequence of the current process, obtaining polishing control parameters, and performing processing control for the current process.

[0014] The semiconductor polishing quality control method based on online detection proposed in this application addresses the technical problem of poor polishing quality consistency and high defect rate caused by the lack of a dynamic adjustment mechanism for the differentiated polishing needs of different regions in existing technologies. This method achieves precise matching of polishing requirements for different semiconductor structural parts, quantifies process constraints and constructs a hierarchical quality anchor chain, and dynamically optimizes polishing parameters based on online detection. This significantly improves wafer polishing accuracy and finished product yield while ensuring overall processing efficiency. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments of this disclosure will be briefly described below. Flowcharts are used in this application to illustrate the operations performed by the system according to the embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed precisely in sequence. Instead, various steps can be processed in reverse order or simultaneously as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0016] Figure 1 This is a schematic diagram of the semiconductor polishing quality control method based on online detection provided in an embodiment of this application.

[0017] Figure 2 This is a schematic diagram of the structure of a semiconductor polishing quality control system based on online detection, provided in an embodiment of this application.

[0018] Figure labeling: Parsing module 11, anchor chain construction module 12, anchor sequence acquisition module 13, processing control module 14. Detailed Implementation

[0019] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0020] Example 1: This application provides a semiconductor polishing quality control method based on online detection, such as... Figure 1 As shown, the method includes: Step S100: Analyze the mapping relationship parameters between the semiconductor structure polishing target and the process chain; Furthermore, step S100 further includes: analyzing the polishing targets of each structural part according to the semiconductor structure to obtain the polishing target feature distribution; performing process target and process polishing constraint analysis on the process chain according to the polishing target feature distribution to obtain process chain constraint parameters; and establishing the mapping relationship parameters between the polishing target features of each part of the semiconductor and the process chain according to the process chain constraint parameters.

[0021] Specifically, based on the application type of the semiconductor, the corresponding structural partitioning method is determined. The polishing targets of each structural part are analyzed according to the structural partitioning method to obtain the polishing target feature distribution. The structural partitioning methods include: partitioning the semiconductor structure according to functional structure, including the central area, edge area, and wiring area; partitioning the semiconductor structure according to layout structure, including the chip array area, dicing area, test structure area, alignment mark area, wafer notch area, and edge exclusion area; and partitioning the semiconductor structure according to process history, including dish-shaped recess area and thickness deviation area. Subsequently, based on the polishing target feature distribution, the process chain is analyzed for each process target and process polishing constraint to obtain process chain constraint parameters. The process chain includes coarse polishing, fine polishing, and precision polishing. The process chain constraint parameters include the removal amount range, pressure limit, endpoint detection sensitivity, and forced constraint coefficient. The forced constraint coefficient is used to characterize the forced control level of each process constraint parameter in quality control, and its value range is [0, 1]. A larger mandatory constraint coefficient corresponds to a smaller deviation in the constraint parameter, which must be strictly controlled within a specified range. A smaller mandatory constraint coefficient, closer to 0, corresponds to a larger deviation in the constraint parameter, indicating a higher tolerance for deviation and allowing adjustment within a certain range. Based on the obtained process chain constraint parameters, a mapping relationship parameter is constructed between the polishing target features of each semiconductor part and the process chain. Specifically, the polishing target features of each semiconductor part are bound to the corresponding rough polishing, fine polishing, and high-precision polishing execution processes, along with specific removal amounts, pressure values, endpoint detection trigger conditions, and mandatory constraint thresholds. This parameter mapping ensures that the polishing requirements of different parts match the process requirements of the corresponding processes. The mandatory constraint coefficient of each constraint parameter is the result of normalizing the backoff penalty factor, which is processed using deviation standardization.

[0022] Furthermore, the step of analyzing the polishing targets of each structural part according to the semiconductor structure to obtain the polishing target feature distribution also includes: determining the corresponding structural partitioning method according to the application type of the semiconductor and partitioning the semiconductor structure; analyzing the polishing features of each partition according to the application requirements of the structural partition to obtain the polishing target feature distribution, wherein the polishing target features describe the polishing target requirements corresponding to each structure, including flatness target value, roughness target value, dish-shaped indentation depth limit, erosion depth limit and allowable scratch depth upper limit.

[0023] Specifically, the chip type of the wafer to be processed is first determined to identify the end-application type. For example, the chips on the wafer to be processed are categorized as high-precision logic chips, high-capacity memory chips, high-voltage power chips, and precision sensing chips. Different types of chips have different polishing control focuses and structural partitioning methods. Based on the characteristics of the application type, a mapping relationship between application type and structural partitioning method is constructed by professional technicians, resulting in an application type-structural partitioning method mapping table. The structural partitioning methods include: semiconductor structure partitioning according to functional structure, semiconductor structure partitioning according to layout structure, and semiconductor structure partitioning according to process history. According to functional structure, the semiconductor structure is divided into a central area, an edge area, and a wiring area. According to layout structure, the semiconductor structure is divided into a chip array area, a dicing area, a test structure area, an alignment mark area, a wafer notch area, and an edge exclusion area. According to process history, the semiconductor structure is divided into a dish-shaped depression area and a thickness deviation area. For example, automotive power chips prioritize controlling the structural integrity of the edge area while having high tolerance for microscopic scratches in the central area, so functional structure partitioning can be used. Memory chips prioritize controlling dish-shaped depressions and erosion defects in the chip array area, so process history partitioning can be used. Based on the application type-structure partitioning method mapping table, the semiconductor structure is partitioned according to the application type of the semiconductor by matching the corresponding structure partitioning method in the mapping table.

[0024] Furthermore, based on the application requirements of the structural partitions, since these requirements typically include specific polishing requirements such as flatness and roughness, the polishing requirements are matched with each partition to obtain the polishing characteristics of each partition. These polishing characteristics are then analyzed to obtain specific requirement parameter values, such as converting flatness requirements into specific flatness target values, thus obtaining the polishing target feature distribution. These polishing target features describe the polishing target requirements corresponding to each structure, including flatness target values, roughness target values, dish-shaped recess depth limits, erosion depth limits, and upper limits for allowable scratch depth. The flatness target value is the optimal standard value for the surface undulations of the corresponding structural region on the wafer, reflecting the overall flatness of the region; the smaller the value, the higher the flatness. The roughness target value is the standard for the fineness of the unevenness of the wafer's micro-surface, directly affecting circuit conductivity and thin film deposition bonding effects. The dish-shaped recess depth limit is the maximum allowable depth of dish-shaped recess defects caused by differences in polishing rates in the wafer's metal wiring and dielectric layer regions; exceeding this limit will lead to short circuits and device failure. The erosion depth limit is the maximum permissible depth to which the wafer dielectric layer and thin film layer are eroded due to excessive polishing. It is used to control structural layer loss caused by excessive polishing. The upper limit of the permissible scratch depth is the maximum depth of polishing scratches that the wafer surface can tolerate. Excessively deep scratches will damage the circuit structure, reduce chip yield, and shorten chip lifespan.

[0025] Furthermore, based on the polishing target feature distribution, the process chain is analyzed for each process target and polishing constraint to obtain the process chain constraint parameters. This includes: identifying the range of process parameters corresponding to each structural part achieving the qualified polishing target in each process based on historical process data, and establishing a process requirement benchmark library; calculating the dependency coefficient of each process based on the process requirement benchmark library and historical deviation correction records, whereby the dependency coefficient reflects the probability that a deviation in the current process will be completely corrected by subsequent processes; setting a backtracking penalty factor based on the dependency coefficient and historical correction cost data to identify key processes that cannot be corrected by subsequent processes or whose correction cost exceeds a threshold; generating a set of constraint parameters for each structural part in each process based on the process requirement benchmark library, dependency coefficient, and backtracking penalty factor, and labeling each constraint parameter with a mandatory constraint coefficient; and establishing a process constraint list based on the constraint parameter set and mandatory constraint coefficient to obtain the process chain constraint parameters.

[0026] Specifically, a massive amount of historical polishing process data for various types and processes of semiconductor wafers is acquired. This historical polishing process data includes polishing processes corresponding to specific wafer structural partitions, parameter settings during process execution, deviation parameters and deviation parameter correction records, process parameter ranges corresponding to polishing targets, correction cost data records, and qualification / non-qualification indicators. Based on the process parameter ranges corresponding to achieving qualified polishing targets for each structural part in each process, a process requirement benchmark library is established. This library stores all valid process parameter ranges for each wafer structural partition under each process that can meet the final qualified polishing target. Subsequently, based on the process requirement benchmark library and historical deviation correction records, a dependency coefficient for each process is calculated. This dependency coefficient reflects the probability that a deviation in the current process will be completely corrected, repaired, or offset by subsequent processes. A higher coefficient indicates higher tolerance for deviation in the current process; a lower coefficient indicates that the deviation in the current process is irreversible and affects the quality of the final product.

[0027] When generating the dependency coefficient, historical deviation and correction records for each process are retrieved from the production system. The number of cases where parameters exceeded limits or indicators deviated in each process is statistically analyzed, and the number of cases where incomplete repairs and scrapping were achieved through subsequent process fine-tuning and parameter compensation. The repair success rate is calculated based on the number of fully repaired and unsuccessful cases, which is equal to the ratio of the number of fully repaired and unsuccessful cases to the sum of the number of fully repaired and unsuccessful cases. The dependency coefficient is equal to the calculated repair success rate.

[0028] Furthermore, the historical correction cost data includes the correction costs after deviations occurred in each process. The correction costs are the comprehensive economic losses, including mass production time costs, wafer material loss costs, polishing pad / polishing fluid consumable costs, yield loss costs, etc.

[0029] Based on the dependency coefficient and historical correction cost data, a rollback penalty factor is set. The rollback penalty factor is the ratio of normalized correction cost data to the dependency coefficient. The lower the dependency coefficient and the higher the correction cost, the larger the corresponding rollback penalty factor value, indicating that the loss caused by process deviation is more severe and the control priority is higher. Conversely, the loss caused by process deviation is less severe and the control priority is lower. The dependency coefficient is calculated based on the number of cases that achieve complete repair and the number of cases that fail to be repaired and are scrapped, which is the repair success rate. The repair success rate is equal to the ratio of the number of cases that achieve complete repair and the sum of the number of cases that achieve complete repair and the number of cases that fail to be repaired and are scrapped. The dependency coefficient is obtained based on the repair success rate. The normalized correction cost data is obtained using deviation standardization. The maximum correction cost data is the maximum required cost for a complete and qualified repair after the corresponding process deviation occurs, and the minimum correction cost data is the minimum required cost for a complete and qualified repair after the corresponding process deviation occurs. The maximum and minimum required costs are economic loss data resulting from the addition of labor costs, wafer material loss costs, polishing pad / polishing fluid consumable costs, yield loss costs, etc.

[0030] Furthermore, a preset backoff penalty factor threshold is established. When the backoff penalty factor is greater than or equal to the threshold, it can be determined that the deviation generated by the process cannot be completely corrected by subsequent processes, thus identifying key processes that cannot be corrected by subsequent processes or whose correction cost exceeds the threshold. For each semiconductor structure partition and each polishing process, the parameter range of the process requirement benchmark library is retrieved, and the dependency coefficient and backoff penalty factor of the corresponding process are matched to generate a constraint parameter set, including: the allowable removal range of each process, the upper and lower limits of polishing pressure, the speed adjustment range, the endpoint detection sensitivity, and the corresponding dependency coefficient and backoff penalty factor. A forced constraint coefficient is marked for each constraint parameter according to the normalized backoff penalty factor. A forced constraint coefficient of 1 indicates that the corresponding constraint parameter cannot be corrected; the larger the forced constraint coefficient, the smaller the deviation that the corresponding constraint parameter can generate; the smaller the forced constraint coefficient, the larger the deviation that the corresponding constraint parameter can generate. A process constraint list is established based on the constraint parameter set and the forced constraint coefficient to obtain the process chain constraint parameters.

[0031] Step S200: Perform anchor point analysis on the quality of each process based on the mapping relationship parameters, and construct a process anchor point chain.

[0032] Furthermore, step S200 also includes: extracting process constraint parameters for each semiconductor part and each process according to the mapping relationship parameters. The process constraint parameters include the removal amount range, pressure limit, endpoint detection sensitivity, and forced constraint coefficient; setting a forced constraint coefficient threshold, determining whether the forced constraint coefficient is greater than the forced constraint coefficient threshold, and if it is greater, determining the physical quantity or region involved in the corresponding constraint parameter as a quality anchor point. The quality anchor points include time anchor points, spatial anchor points, and event anchor points; sequentially connecting the quality anchor points of each part in each process according to the process sequence, and establishing association rules between anchor points based on the dependency coefficient between processes to obtain the process anchor point chain.

[0033] Specifically, process constraint parameters for each semiconductor part and each process are extracted based on the mapping relationship parameters between the polishing target characteristics and the process chain. These process constraint parameters include the removal range, pressure limit, endpoint detection sensitivity, and forced constraint coefficient. An example of process constraint parameters for the rough polishing process is: removal range 80-120nm, pressure limit 18-22kPa, endpoint detection sensitivity 0.8μm / s, and forced constraint coefficient 0.85. A forced constraint coefficient threshold is preset. This threshold is determined by professional technicians based on actual production needs. All parameters exceeding the forced constraint coefficient threshold are identified as quality anchor points, and those less than or equal to it are not set. The quality anchor points include time anchor points, spatial anchor points, and event anchor points. Time anchor points are key control points for the corresponding process in terms of polishing duration and endpoint detection time nodes. For example, the rough polishing process mandates that the polishing duration not exceed the specified range, and endpoint detection triggering requires meeting a fixed time threshold; this time threshold is the time anchor point. Spatial anchors correspond to specific areas within a semiconductor structure partition that require key control, such as the fine polishing process area corresponding to the dish-shaped recess control of the chip array area in a memory chip. This controlled area is the spatial anchor. Event anchors correspond to detection nodes triggered during process execution, used to determine whether the real-time polishing execution parameters are within the process constraint parameter range. For example, the polishing head pressure determination during wafer rough polishing; if it does not meet the process constraint parameter range, the corresponding event anchor is triggered. Following the sequence of rough polishing, fine polishing, and finishing, the quality anchors of each semiconductor structure partition in the corresponding process are sequentially connected in series. Association rules between anchors are established based on the calculated inter-process dependency coefficient. The association rules are as follows: if the anchor parameter in the previous process exceeds the constraint range and the forced constraint coefficient is greater than a threshold, combined with the current process dependency coefficient, if the current process dependency coefficient is lower than a preset dependency threshold, the process is directly paused and parameter correction is performed; if the dependency coefficient is higher than the threshold, the constraint range of the corresponding parameter in the current process is allowed to be lowered, reserving space for deviation correction. After the association rules are established, a chain of process anchors connecting the entire process is obtained.

[0034] Step S300: Collect online detection data, perform semiconductor structure and process quality anchor point analysis and matching according to the process anchor point chain, and establish the quality anchor point sequence of the current process; Furthermore, step S300 also includes: retrieving all candidate anchor points and trigger conditions related to the corresponding process and part from the process anchor point chain according to the current polishing process number and the semiconductor structure part being polished on the current wafer; comparing the real-time collected detection data with the trigger conditions of the candidate anchor points one by one; and outputting the anchor points that meet the conditions according to the priority of the constraint strength based on the trigger comparison results, as the quality anchor point sequence of the current process.

[0035] Specifically, during the polishing process, the system reads equipment process parameters and workstation information in real time to obtain the current polishing process number, accurately determine whether the equipment is in the rough polishing, fine polishing, or precision polishing process, and obtains the semiconductor structure part of the wafer being processed to determine the current polishing area, such as the chip array area, dicing area, test structure area, alignment mark area, wafer notch area, edge exclusion area, etc. For example, the system determines in real time that the current process number is 3, corresponding to the precision polishing process, and the current processed structure part is the chip array area of ​​a 12-inch memory chip. Using this as an anchor point, it retrieves all candidate anchor points and trigger conditions related to the corresponding process and part. From the captured sub-links, it fully retrieves all anchor points corresponding to the process and area, including time anchor points, spatial anchor points, and event anchor points. Simultaneously, it retrieves the exclusive trigger conditions bound to each anchor point. The trigger conditions are anchor point verification conditions that include quantitative rules such as parameter threshold ranges, allowable deviation ranges, and anomaly judgment boundaries. The system utilizes an in-situ optical inspection device on the wafer surface, a pressure sensor on the polishing head, a spindle speed encoder, and an acoustic sensor for endpoint detection to collect real-time online inspection data for the current process. This data includes the real-time removal rate of the current processing area, the current polishing pressure, the actual spindle speed, the rate of change of acoustic impedance on the wafer surface, and the current cumulative polishing time. This real-time inspection data is compared one by one with the trigger conditions of all candidate anchor points retrieved from the process anchor point chain to determine if the current process's real-time status meets the corresponding anchor point's trigger conditions. All anchor points that meet the trigger conditions are the key nodes requiring control in the current process. These anchor points are then prioritized according to their corresponding mandatory constraint coefficients from high to low, and a sorted list of anchor points is output. This list serves as the quality anchor point sequence for the current process, used for subsequent quality control actions performed according to priority. Higher priority anchor points require priority execution of inspection, adjustment, and anomaly detection actions to prevent deviations from affecting the final polishing quality. If no anchor point meets the trigger conditions, the process proceeds directly to the next process without additional control actions, reducing unnecessary inspection actions that consume processing time and ensuring polishing efficiency.

[0036] Step S400: Search for polishing parameters for the current process based on the quality anchor point sequence of the current process, obtain polishing control parameters, and perform processing control for the current process.

[0037] Furthermore, step S400 also includes: based on each activated anchor point in the quality anchor point sequence, searching for a set of candidate control parameters corresponding to the anchor point from a preset parameter mapping library, wherein the candidate control parameters include the partition pressure adjustment amount, polishing head speed adjustment amount, polishing fluid flow rate adjustment amount, and dressing pressure adjustment amount; if there is only one anchor point in the sequence, the candidate parameters corresponding to the anchor point are directly output as the polishing control parameters of the current process; if there are multiple anchor points in the sequence, the corresponding candidate parameters are weighted and fused according to the priority weight of each anchor point to obtain comprehensive control parameters; if the quality anchor point sequence is empty, the default polishing control parameters are output, indicating that no additional adjustment is required for the current process.

[0038] Specifically, when constructing the pre-set parameter mapping library, it is necessary to first integrate historical online inspection data of all marked qualified and unqualified results throughout the entire wafer fabrication process, the trigger status of corresponding anchor points, and the polishing adjustment parameters used. The anchor point trigger condition range, the current online inspection deviation, and the finally adopted effective adjustment parameters are then bound together. This binding information is then categorized and stored according to anchor point type, structural partition, and process number, ensuring that each anchor point corresponds to a set of valid candidate control parameters verified in production under different deviation ranges. Furthermore, after each batch of wafer processing is completed, the parameter mapping library is dynamically updated based on the final polishing quality inspection results, supplementing with new valid parameter combinations and eliminating adjustment parameters that have been repeatedly verified as invalid, ensuring the effectiveness and adaptability of the candidate control parameters in the mapping library. Based on each activated anchor point in the quality anchor point sequence, the corresponding candidate control parameter set is retrieved from the pre-set parameter mapping library. These candidate control parameters include partition pressure adjustment, polishing head speed adjustment, polishing slurry flow rate adjustment, and dressing pressure adjustment. The adjustment of partition pressure is a correction value for the partition pressure corresponding to different semiconductor structure partitions. For specific control areas marked by spatial anchor points, the actual removal rate of the current area is corrected by adjusting the applied pressure of the corresponding partition, ensuring that the final removal amount of the area meets the target requirements. The adjustment of polishing head speed is a correction value for the deviation between the actual spindle speed and the set speed. The adjustment of polishing slurry flow rate is a correction value for adjusting the polishing slurry supply per unit time in the current process. The adjustment of dressing pressure is a correction value for the pressure applied by the dressing disc during the online dressing process of the polishing pad. If there is only one active anchor point in the current quality anchor point sequence, the candidate control parameters corresponding to that anchor point are directly output as the polishing control parameters for the current process and sent to the control system of the polishing equipment for parameter adjustment. If the current quality anchor point sequence contains multiple active anchor points, i.e., multiple key nodes that simultaneously trigger control requirements, the forced constraint coefficient corresponding to each anchor point is used as the priority weight. The candidate control parameters of each dimension matched by the parameter mapping library corresponding to all anchor points are weighted and summed to obtain the comprehensive polishing control parameters of each dimension for the current process of each anchor point, avoiding conflicts between adjustment targets of multiple anchor points and ensuring the rationality of parameter adjustment. If the current quality anchor point sequence is empty, it means that all parameters of the current process meet the constraint requirements and no additional adjustment is needed. The default polishing control parameters preset in the process file are directly output, and the current processing state is maintained to continue running.

[0039] Subsequently, the candidate control parameter set matching each activated anchor point is retrieved one by one from the pre-built parameter mapping library. The parameter mapping library stores the adjustment direction and adjustment amount reference values ​​of various polishing parameters corresponding to different types of anchor points and different deviation states. For example, when the time anchor point triggers the current cumulative polishing time to exceed the allowable range deviation, the corresponding candidate control parameter is the adjustment of the endpoint detection early trigger amount. When the spatial anchor point triggers the chip array area dish indentation depth deviation to exceed the limit, the corresponding candidate control parameters are the partition polishing pressure reduction value and the polishing fluid flow rate adjustment amount. After completing the retrieval of candidate parameters for all activation anchor points, the adjustment amounts of all candidate parameters are weighted and averaged according to their corresponding priority weights to obtain the comprehensive adjustment amounts for zone pressure, polishing head speed, polishing fluid flow rate, and dressing pressure. This results in the integrated comprehensive polishing control parameters for the current process, which are then output to the polishing equipment's control system for parameter adjustment, completing the processing control for the current process. In this process's quality control flow, if the system evaluates and attempts to match all potential candidate anchor point data and finds no valid anchor point that meets the set trigger criteria, the quality anchor point sequence is determined to be empty. The system will automatically skip the parameter optimization and adjustment stage and directly call and output the preset default polishing control parameter configuration for the current process. At this point, the production process will continue to use the original processing parameter settings without any additional modifications or calibrations, thus maintaining the continuity and stability of production operations.

[0040] This application provides a semiconductor polishing quality control method based on online detection, including: acquiring process chain constraint parameters, constructing a process anchor point chain based on mapping relationship parameters, obtaining the quality anchor point sequence of the current process through online detection data matching, and finally obtaining polishing control parameters adapted to the current processing state based on sequence weighted fusion, thereby achieving precise dynamic control of polishing quality. By introducing a dependency coefficient to quantify the repairability probability of inter-process deviations and combining a backoff penalty factor to identify key control processes and set mandatory constraint coefficients, control resources can be allocated in a targeted manner, ensuring the accuracy of quality control while avoiding excessive detection that affects processing efficiency. Based on the process anchor point chain, key control points of each process are prioritized, and parameters are dynamically adjusted according to the weight of deviation impact, effectively reducing yield loss caused by irreversible deviations and adapting to the polishing processing quality control needs of semiconductor wafers with different structural partitions and different processes. This solves the technical problem in existing technologies of lacking a dynamic adjustment mechanism for the differentiated polishing needs of different regions, resulting in poor polishing quality consistency and high defect rate. This technology achieves precise matching of polishing requirements for different semiconductor structural parts, quantifies process constraints and constructs a hierarchical quality anchor chain, and dynamically optimizes polishing parameters based on online detection, significantly improving wafer polishing accuracy and finished product yield while ensuring overall processing and production efficiency.

[0041] Example 2, based on the same inventive concept as the online detection-based semiconductor polishing quality control method in the foregoing examples, such as... Figure 2 As shown, this application provides a semiconductor polishing quality control system based on online detection. The system and method embodiments in this application are based on the same inventive concept.

[0042] The semiconductor polishing quality control system based on online detection according to embodiments of the present invention solves the technical problem in the prior art of lacking a dynamic adjustment mechanism for the differentiated polishing needs of different regions, resulting in poor polishing quality consistency and high defect rate. It achieves precise matching of polishing requirements for different semiconductor structural parts, quantifies process constraints and constructs a hierarchical quality anchor chain, and dynamically optimizes polishing parameters based on online detection, significantly improving wafer polishing accuracy and finished product yield while ensuring overall processing efficiency. The semiconductor polishing quality control system based on online detection includes: a parsing module 11, an anchor chain construction module 12, an anchor sequence acquisition module 13, and a processing control module 14.

[0043] The parsing module 11 is used to parse the mapping relationship parameters between the semiconductor structure polishing target and the process chain; the anchor point chain construction module 12 is used to perform anchor point analysis of the quality of each process according to the mapping relationship parameters and construct the process anchor point chain; the anchor point sequence acquisition module 13 is used to collect online detection data, perform semiconductor structure and process quality anchor point analysis and matching according to the process anchor point chain, and establish the quality anchor point sequence of the current process; the processing control module 14 is used to search for polishing parameters of the current process according to the quality anchor point sequence of the current process, obtain polishing control parameters, and perform processing control of the current process.

[0044] The specific configuration of the analysis module 11 will be described in detail below. The analysis module 11 may further include: analyzing the mapping relationship parameters between the polishing targets of the semiconductor structure and the process chain, including: analyzing the polishing targets of each structural part according to the semiconductor structure to obtain the polishing target feature distribution; performing process target and process polishing constraint analysis on the process chain based on the polishing target feature distribution to obtain process chain constraint parameters; and establishing the mapping relationship parameters between the polishing target features of each part of the semiconductor and the process chain based on the process chain constraint parameters. The process chain includes coarse polishing, fine polishing, and precision polishing.

[0045] The specific configuration of the analysis module 11 will be described in detail below. The analysis module 11 may further include: analyzing the polishing target of each structural part according to the semiconductor structure to obtain the polishing target feature distribution, including: determining the corresponding structural partitioning method according to the application type of the semiconductor and partitioning the semiconductor structure; analyzing the polishing feature of each partition according to the application requirement characteristics of the structural partition to obtain the polishing target feature distribution, wherein the polishing target features describe the polishing target requirements corresponding to each structure, including flatness target value, roughness target value, dish-shaped indentation depth limit, erosion depth limit, and allowable scratch depth upper limit.

[0046] The specific configuration of the parsing module 11 will be described in detail below. The parsing module 11 may further include: the structural partitioning method includes: partitioning the semiconductor structure according to the functional structure, including the central area, the edge area, and the wiring area; partitioning the semiconductor structure according to the layout structure, including the chip array area, the dicing area, the test structure area, the alignment mark area, the wafer notch area, and the edge exclusion area; and partitioning the semiconductor structure according to the process history, including the dish-shaped recess area and the thickness deviation area.

[0047] The specific configuration of the analysis module 11 will be described in detail below. The analysis module 11 may further include: performing process target and process polishing constraint analysis on the process chain based on the polishing target feature distribution to obtain process chain constraint parameters, including: identifying the range of process parameters corresponding to each structural part achieving the qualified polishing target in each process based on historical process data, and establishing a process requirement benchmark library; calculating the dependency coefficient of each process based on the process requirement benchmark library and historical deviation correction records, the dependency coefficient reflecting the probability that a deviation in the current process will be completely corrected by subsequent processes; setting a backtracking penalty factor based on the dependency coefficient and historical correction cost data, and identifying key processes that cannot be corrected by subsequent processes or whose correction cost exceeds a threshold; generating a set of constraint parameters for each structural part in each process based on the process requirement benchmark library, dependency coefficient, and backtracking penalty factor, and labeling each constraint parameter with a forced constraint coefficient; and establishing a process constraint list based on the constraint parameter set and forced constraint coefficient to obtain the process chain constraint parameters.

[0048] The specific configuration of the anchor chain construction module 12 will be described in detail below. The anchor chain construction module 12 may further include: performing anchor point analysis on the quality of each process according to the mapping relationship parameters, and constructing a process anchor chain, including: extracting process constraint parameters for each semiconductor part and each process according to the mapping relationship parameters; the process constraint parameters include the removal range, pressure limit, endpoint detection sensitivity, and forced constraint coefficient; setting a forced constraint coefficient threshold, determining whether the forced constraint coefficient is greater than the forced constraint coefficient threshold, and if it is greater, determining the physical quantity or region involved in the corresponding constraint parameter as a quality anchor point; the quality anchor points include time anchor points, spatial anchor points, and event anchor points; sequentially connecting the quality anchor points of each part in each process according to the process sequence, and establishing association rules between anchor points based on the dependency coefficient between processes to obtain the process anchor chain.

[0049] The specific configuration of the anchor point sequence acquisition module 13 will be described in detail below. The anchor point sequence acquisition module 13 may further include: collecting online detection data, performing semiconductor structure and process quality anchor point analysis and matching according to the process anchor point chain, and establishing a quality anchor point sequence for the current process, including: retrieving all candidate anchor points and triggering conditions related to the corresponding process and location from the process anchor point chain based on the current polishing process number and the semiconductor structure part currently being polished on the wafer; comparing the real-time collected detection data with the triggering conditions of the candidate anchor points one by one; and, based on the trigger comparison results, prioritizing and outputting the anchor points that meet the conditions according to their constraint strength as the quality anchor point sequence for the current process.

[0050] The specific configuration of the processing control module 14 will be described in detail below. The processing control module 14 may further include: searching for polishing parameters for the current process based on the quality anchor point sequence of the current process to obtain polishing control parameters, including: searching for a set of candidate control parameters corresponding to each activated anchor point in the quality anchor point sequence from a preset parameter mapping library; the candidate control parameters include partition pressure adjustment, polishing head rotation speed adjustment, polishing fluid flow rate adjustment, and dressing pressure adjustment; if there is only one anchor point in the sequence, the candidate parameters corresponding to the anchor point are directly output as the polishing control parameters for the current process; if there are multiple anchor points in the sequence, the corresponding candidate parameters are weighted and fused according to the priority weight of each anchor point to obtain comprehensive control parameters; if the quality anchor point sequence is empty, the default polishing control parameters are output, indicating that no additional adjustment is required for the current process.

[0051] The semiconductor polishing quality control system based on online detection provided in the embodiments of the present invention can execute the semiconductor polishing quality control method based on online detection provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method.

[0052] Although this application makes various references to certain modules in the system according to the embodiments of this application, any number of different modules can be used and run on user terminals and / or servers. The various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy distinction between each other and are not used to limit the scope of protection of this invention.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A semiconductor polishing quality control method based on online detection, characterized in that, include: Analyze the mapping parameters between semiconductor structure polishing targets and process chains; Based on the mapping relationship parameters, perform anchor point analysis on the quality of each process and construct a process anchor point chain; Collect online detection data, perform semiconductor structure and process quality anchor point analysis and matching according to the process anchor point chain, and establish the quality anchor point sequence of the current process. Based on the quality anchor point sequence of the current process, the polishing parameters of the current process are searched to obtain the polishing control parameters, and the processing control of the current process is performed. The mapping parameters between the polishing target of the semiconductor structure and the process chain are analyzed, including: Polishing target analysis is performed on each structural part of the semiconductor structure to obtain the feature distribution of the polishing target; Based on the distribution of polishing target characteristics, the process chain is analyzed for each process target and process polishing constraint to obtain process chain constraint parameters. Based on the process chain constraint parameters, establish the mapping relationship parameters between the polishing target features of each part of the semiconductor and the process chain; Based on the polishing target feature distribution, the process chain is analyzed for each process target and process polishing constraint to obtain process chain constraint parameters, including: Based on historical process data, identify the range of process parameters corresponding to the qualified polishing target of each structural part in each process, and establish a process requirement benchmark library. Based on the process requirement benchmark library and historical deviation correction records, calculate the dependency coefficient of each process. The dependency coefficient reflects the probability that a deviation in the current process will be completely corrected by subsequent processes. Based on the dependency coefficient and historical correction cost data, a backoff penalty factor is set to identify key processes that cannot be corrected by subsequent processes or whose correction costs exceed a threshold. Based on the process requirement benchmark library, dependency coefficient, and backoff penalty factor, generate a set of constraint parameters for each structural part in each process, and label each constraint parameter with a mandatory constraint coefficient. Based on the set of constraint parameters and the forced constraint coefficients, a process constraint list is established to obtain the process chain constraint parameters; Based on the mapping relationship parameters, anchor point analysis is performed on the quality of each process to construct a process anchor point chain, including: Based on the mapping relationship parameters, process constraint parameters for each semiconductor part and each process are extracted. The process constraint parameters include the removal amount range, pressure limit, endpoint detection sensitivity, and forced constraint coefficient. Set a mandatory constraint coefficient threshold, and determine whether the mandatory constraint coefficient is greater than the mandatory constraint coefficient threshold. If it is greater, the physical quantity or region involved in the corresponding constraint parameter is determined as a mass anchor point. The mass anchor point includes time anchor point, spatial anchor point and event anchor point. According to the sequence of processes, the quality anchor points of each part in each process are connected in series, and the association rules between anchor points are established based on the dependency coefficient between processes to obtain the process anchor point chain.

2. The semiconductor polishing quality control method based on online detection according to claim 1, characterized in that, The process chain includes rough polishing, fine polishing, and precision polishing.

3. The semiconductor polishing quality control method based on online detection according to claim 1, characterized in that, Polishing target analysis is performed on each structural part of the semiconductor structure to obtain the polishing target feature distribution, including: Based on the application type of semiconductors, determine the corresponding structural partitioning method and partition the semiconductor structure accordingly; Based on the application requirements of the structural partitions, the polishing features of each partition are analyzed to obtain the polishing target feature distribution. The polishing target features describe the polishing target requirements corresponding to each structure, including the flatness target value, roughness target value, dish-shaped indentation depth limit, erosion depth limit, and allowable scratch depth upper limit.

4. The semiconductor polishing quality control method based on online detection according to claim 3, characterized in that, The structural partitioning methods include: Semiconductor structures are partitioned according to their functional structure, including the central region, the edge region, and the wiring region; The semiconductor structure is divided into partitions according to the layout structure, including chip array area, dicing area, test structure area, alignment mark area, wafer notch area, and edge exclusion area; The semiconductor structure is divided into regions based on the process history, including dish-shaped recessed regions and thickness deviation regions.

5. The semiconductor polishing quality control method based on online detection according to claim 1, characterized in that, Collect online testing data, perform semiconductor structure and process quality anchor point analysis and matching according to the process anchor point chain, and establish the quality anchor point sequence for the current process, including: Based on the current polishing process number and the semiconductor structure part currently being polished on the wafer, retrieve all candidate anchor points and trigger conditions related to the corresponding process and part from the process anchor point chain; The real-time collected detection data is compared one by one with the triggering conditions of the candidate anchor points; Based on the trigger comparison results, the anchor points that meet the conditions are sorted by constraint strength and output as the quality anchor point sequence for the current process.

6. The semiconductor polishing quality control method based on online detection according to claim 1, characterized in that, Based on the quality anchor point sequence of the current process, the polishing parameters of the current process are searched to obtain the polishing control parameters, including: Based on each activated anchor point in the quality anchor point sequence, a set of candidate control parameters corresponding to the anchor point is searched from a preset parameter mapping library. The candidate control parameters include the partition pressure adjustment amount, polishing head speed adjustment amount, polishing fluid flow rate adjustment amount, and dressing pressure adjustment amount. If there is only one anchor point in the sequence, the candidate parameter corresponding to the anchor point is directly output as the polishing control parameter of the current process. If the sequence contains multiple anchor points, the corresponding candidate parameters are weighted and fused according to the priority of each anchor point to obtain the comprehensive control parameters; if the quality anchor point sequence is empty, the default polishing control parameters are output, indicating that no additional adjustment is required for the current process.

7. A semiconductor polishing quality control system based on online detection, characterized in that, The system is used to execute the semiconductor polishing quality control method based on online detection as described in any one of claims 1-6, comprising: The analysis module is used to analyze the mapping relationship parameters between the polishing target of the semiconductor structure and the process chain; An anchor chain construction module is used to perform anchor point analysis on the quality of each process based on the mapping relationship parameters, and to construct a process anchor chain; The anchor point sequence acquisition module is used to collect online detection data, perform semiconductor structure and process quality anchor point analysis and matching according to the process anchor point chain, and establish the quality anchor point sequence of the current process. The processing control module is used to search for polishing parameters for the current process based on the quality anchor point sequence of the current process, obtain polishing control parameters, and perform processing control for the current process.

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