Highly configurable system level online testing method

Abstract

The present application relates to the technical field of integrated circuit testing, in particular to a highly configurable system-level online testing method, comprising the following steps: extracting a physical resource mapping configuration table, generating a logical pin physical channel index mapping table, arranging a power-on sequence and compensating for a delay to form a parallel synchronous function test driving pulse chain, constructing a chip power consumption thermal resistance state diagram and generating a self-matching thermal compensation system-level online testing evaluation table, executing a gating decision and decoding a protocol payload, and generating a chip quality multi-dimensional judgment sorting and grading code. In the present application, resource flexible mapping is achieved by constructing a bus bridge matrix, significantly improving system versatility, line interference is eliminated by path planning to optimize signal integrity, electrical parameter consistency is maintained by combining an active heat compensation mechanism, temperature control accuracy is enhanced and measurement error is reduced, failure modes are traced back by protocol decoding and internal defects are deeply excavated, and testing coverage and chip sorting reliability are comprehensively strengthened.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and in particular to a highly configurable system-level online testing method. Background Technology

[0002] The field of integrated circuit testing technology involves the comprehensive verification of the functionality, performance, and reliability of semiconductor chips. This encompasses physical defect detection, logic function verification, and electrical parameter measurement from the wafer stage to the packaged product. Core aspects include designing test vectors, controlling the signal interaction between the test equipment and the device under test (DUT), and evaluating the chip's stability under different process angles, voltages, and temperatures. With the widespread adoption of integrated circuit process miniaturization and multi-chip packaging technologies, chips integrate multiple processing cores, large-scale memory cells, and high-speed analog interfaces, making timing, thermal coupling, and multi-domain interaction defects difficult to fully cover through traditional production testing. Traditional highly configurable system-level in-circuit testing methods refer to the overall functional and stress verification of the chip by simulating a real-world terminal application environment after packaging testing. Traditional methods employ a dedicated hardware testing platform customized for the target chip model. This involves running a pre-programmed bootloader inside the chip to guide the operating system into a working state. The test host then sends a pre-set set of logic instructions to the chip via a physical interface to trigger its internal computational logic, memory access, and peripheral data communication. The chip's hardware and software performance is confirmed by capturing bus data packets, monitoring pin levels, and analyzing runtime log files. The entire testing process relies on pre-designed hardware circuit traces and linear test procedures written for each individual chip.

[0003] Traditional highly configurable system-level online testing methods rely on dedicated hardware platforms designed for target chip models. This results in a lack of versatility and flexible scheduling of test resources when faced with differentiated chip architectures. Fixed hardware circuit routing makes high-speed signal transmission susceptible to parasitic capacitance and reflection interference. Simply relying on preset linear processes cannot effectively capture complex thermal coupling fluctuations within the chip package. There is a lack of real-time compensation mechanisms for dynamic changes in junction temperature, making it difficult to accurately locate deep-seated logic failures caused by hardware and software collaboration, thus limiting chip test coverage and sorting accuracy. Summary of the Invention

[0004] To address the technical problems existing in the prior art, embodiments of the present invention provide a highly configurable system-level online testing method, comprising the following steps: To achieve the above objectives, the present invention adopts the following technical solution: a highly configurable system-level online testing method, comprising the following steps: S1: Extract the capacity and pin electrical limits of the ATE test channel, configure the relay array of the test machine, map the underlying communication protocol to the serial transceiver to build the underlying communication bus bridge matrix, bind the physical coordinate system of the test base and lock the signal integrity constraints, and obtain the physical resource mapping configuration table; S2: Load the target chip pin specifications according to the physical resource mapping configuration table, set the comparison reference voltage, plan the signal transmission path to eliminate line reflection interference, generate dynamic channel allocation routing instructions, align vector logic names with machine physical channels, and generate a logic pin physical channel index mapping table. S3: Based on the physical channel index mapping table of the logic pins, arrange the power-on sequence and waveform trigger parameter output timing edge trigger control netlist, align the global precision clock source and compensate for channel delay, push the test vector into the pin drive unit at full speed, and integrate to form a parallel synchronous function test drive pulse chain; S4: Based on the parallel synchronization function test drive pulse chain, analyze the junction temperature fluctuation law to construct the chip power consumption and thermal resistance situation diagram, adjust the output dynamic drive cooling power of the active temperature control base, bind electrical measurement parameters in the temperature stability window, and generate a self-matching thermal compensation system-level online test evaluation table. S5: Based on the self-matching thermal compensation system-level online test evaluation table, perform gating decision comparison of expected vectors in the target sampling window, locate logic defects according to functional test response results, decode protocol payload to trace internal failure modes, classify sorting levels and interact with robot controller, and generate chip quality multi-dimensional judgment sorting and grading codes.

[0005] As a further embodiment of the present invention, the physical resource mapping configuration table includes a machine port interconnection matrix, relay node logic status, and link impedance compensation vector; the logic pin physical channel index mapping table includes pin attribute feature vectors, signal routing switching weights, and physical path occupancy masks; the parallel synchronization function test drive pulse chain includes a phase alignment timing reference, an excitation waveform synthesis operator, and a multi-channel synchronization status identifier; the self-matching thermal compensation system-level online test evaluation table includes a steady-state junction temperature deviation limit, power consumption feedback adjustment coefficient, and thermal sensitivity drift constant; and the chip quality multi-dimensional judgment, sorting, and grading code includes a defect distribution feature entropy value, a failure mode weight index, and a logic function health score.

[0006] As a further aspect of the present invention, the specific steps of the physical resource mapping configuration table are as follows: S101: Extract the ATE test channel capacity and load board wiring constraints, analyze the pin voltage domain and current drive capability limitations, configure the relay array and pin driver range parameters in the interface board, identify the physical link between the test machine and the load board, and generate a hardware interface topology connection diagram. S102: Call the hardware interface topology connection diagram, map the underlying communication protocol to the FPGA serial transceiver, allocate direct memory access buffer blocks, establish a timing synchronization bridging mechanism between differentiated rate test channels, configure multiplexer logic, and construct the underlying communication bus bridging matrix. S103: Based on the underlying communication bus bridging matrix, bind the physical channel resources of the test machine to the coordinate system of the target test stand, lock the pin impedance matching parameters and high-speed signal integrity constraints, instantiate the underlying test hardware netlist, and obtain the physical resource mapping configuration table.

[0007] As a further aspect of the present invention, the specific steps of the physical resource mapping configuration table are as follows: S101: Extract the ATE test channel capacity and load board wiring constraints, analyze the pin voltage domain and current drive capability limitations, configure the relay array and pin driver range parameters in the interface board, identify the physical link between the test machine and the load board, and generate a hardware interface topology connection diagram. S102: Call the hardware interface topology connection diagram, map the underlying communication protocol to the FPGA serial transceiver, allocate direct memory access buffer blocks, establish a timing synchronization bridging mechanism between differentiated rate test channels, configure multiplexer logic, and construct the underlying communication bus bridging matrix. S103: Based on the underlying communication bus bridging matrix, bind the physical channel resources of the test machine to the coordinate system of the target test stand, lock the pin impedance matching parameters and high-speed signal integrity constraints, instantiate the underlying test hardware netlist, and obtain the physical resource mapping configuration table.

[0008] As a further aspect of the present invention, the preferred transmission path of the planned test signal within the interface board refers to calculating the distributed inductance per unit length between the test signal line and the reference ground plane based on the signal frequency requirements in the pin timing and level attribute domain, adjusting the closing sequence of the relay contacts of the high-frequency switching matrix, and obtaining a physical trace with transmission line impedance matching compensation.

[0009] As a further aspect of the present invention, the specific steps of the parallel synchronization function test drive pulse chain are as follows: S301: Based on the physical channel index mapping table of the logic pins, parse the standard test vector file, arrange the chip power-on sequence and reset wait cycle, define the cross boundary of multiple clock domains, configure the edge trigger type of the waveform format generator, and output the timing edge trigger control netlist. S302: Based on the timing edge triggering control netlist, adjust the phase-locked loop network inside the FPGA of the machine tool, align the excitation signal to the global clock source, plan the nanosecond-level trace delay compensation between the differentiated test channels, lock the multi-channel waveform transmission phase, and generate a synchronous pulse drive sequence. S303: Receive the synchronous pulse drive sequence, drive the instrument memory control unit to push the test vector data into the pin drive electronic unit at full speed, apply a high-speed excitation signal wave that strictly conforms to the timing specification to the chip pin according to the preset waveform format, and establish a parallel synchronous function test drive pulse chain.

[0010] As a further aspect of the present invention, the delineation of the multi-clock domain cross boundary refers to identifying the frequency ratio and phase deviation between the differentiated asynchronous clocks within the chip, configuring the address pointer access range of synchronous triggers or buffer memories at the physical nodes of signal cross-clock transmission, and obtaining timing boundary constraints that meet the metastable filtering requirements.

[0011] As a further aspect of the present invention, the specific steps of the self-matching thermal compensation system-level online test and evaluation table are as follows: S401: Based on the parallel synchronization function test drive pulse chain, synchronously measure the forward voltage drop change of the thermistor inside the chip, analyze the heat dissipation characteristics of the package and the transient fluctuation law of the junction temperature, map the current environmental heat distribution load, and construct the chip power consumption thermal resistance status diagram. S402: Call the power consumption and thermal resistance status diagram of the chip, control the active temperature control base on the top of the test machine, adjust the flow rate of the liquid cooling pipeline or the dynamic driving power of the semiconductor cooling chip according to the deviation of the junction temperature from the target value, identify the closed-loop heat offset circuit, and generate an active heat compensation adjustment curve. S403: Based on the active thermal compensation adjustment curve, maintain the test environment at an extremely fast constant temperature, lock the temperature stability window period, and perform static electrical parameter and leakage current measurements of the chip. Bind the transient power consumption to the thermal compensation loop state in the time domain to generate a self-matching thermal compensation system-level online test evaluation table.

[0012] As a further aspect of the present invention, the specific steps of the chip quality multi-dimensional judgment, sorting, and grading code are as follows: S501: Based on the self-matching thermal compensation system-level online test and evaluation table, the output level is selected and decided within the preset sampling window, compared with the expected vector mask, the timing offset and level state abnormality points are located, and the response signal timing mask comparison set is output. S502: Based on the timing mask comparison set of the response signal, decode the internal payload of the bus protocol, trace the failure mode of the internal logic module or memory unit that caused the error flag, lock the physical distribution area of ​​the logic defect inside the die, and generate a device logic function defect distribution map. S503: Determine the chip yield rate based on the device logic function defect distribution map, classify the physical rejection and downgraded use warehouse level according to the failure parameter deviation, transmit the absolute coordinates of the test seat and the sorting category to the robot control center, and generate a multi-dimensional judgment sorting and grading code for chip quality.

[0013] As a further aspect of the present invention, the step of classifying physical rejection and degraded use warehousing levels based on the deviation of failure parameters refers to comparing the measured deviation of failure parameters with the preset performance degradation tolerance value level by level, allocating chips that do not meet the basic functional requirements to the physical rejection warehousing level, and allocating chips that meet the core functions but whose target time-frequency indicators are reduced to the degraded use warehousing level, thereby obtaining sorting categories with differentiated performance levels.

[0014] Compared with the prior art, the advantages and positive effects of the present invention are as follows: In this invention, by extracting the equipment capacity and pin limitations and constructing a low-level bus bridge matrix, flexible mapping between test resources and physical hardware is achieved, significantly improving the versatility and configuration efficiency of the test system. Signal transmission path planning and dynamic routing instructions are used to eliminate line reflection interference, optimize high-speed signal integrity, and enhance data transmission stability. Combining junction temperature fluctuation patterns and active temperature control to drive power output, a self-matching thermal compensation evaluation mechanism is established to ensure that the chip maintains electrical parameter consistency under complex power consumption conditions, enhances temperature control accuracy, and reduces measurement errors caused by thermal drift. By executing gating decisions and decoding protocol payloads, accurate failure mode tracing and multi-dimensional quality judgment are achieved, internal logic defects are deeply explored, and chip test coverage and sorting reliability are comprehensively improved. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the steps of the present invention; Figure 2 This is a detailed schematic diagram of S1 of the present invention; Figure 3 This is a detailed schematic diagram of S2 of the present invention; Figure 4 This is a detailed schematic diagram of S3 of the present invention; Figure 5 This is a detailed schematic diagram of S4 of the present invention; Figure 6 This is a detailed schematic diagram of S5 of the present invention. Detailed Implementation

[0017] The technical solution of the present invention will now be described with reference to the accompanying drawings.

[0018] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0019] This invention provides a highly configurable system-level online testing method. In practical applications, such as during the online functional verification, temperature control measurement, and sorting interaction of target chips on a semiconductor packaging and testing production line, the chip under test (DUT) is fixed to the test socket. The ATE test machine forms a closed test link through interface boards, load boards, relay arrays, serial transceivers, pin driver components, active temperature control bases, and a robotic arm control center. This method revolves around physical resource extraction, logic pin binding, parallel pulse driving, thermal compensation measurement, and quality grading output. Each processing step uses test programs, chip datasheets, machine hardware descriptions, load board routing constraints, and test socket coordinate information as input sources, and completes subsequent connections through status identifiers, routing instructions, control netlists, evaluation records, and sorting codes.

[0020] Please see Figure 1 and Figure 2 S1: ATE test channel capacity refers to the type of hardware resources available for driving, sampling, power supply, and communication at the test instrument port. Pin electrical limitations refer to the engineering rules in the chip specification that constrain power domains, ground return current, input / output direction, comparison level, drive capability, and protection boundaries. When configuring the test instrument relay array, first obtain the port connection relationship from the test instrument hardware description file, and then incorporate the relay contacts, load board traces, test socket contacts, and serial transceiver ports on the interface board into the same physical connection diagram. The underlying communication protocol refers to the protocol constraints used to transmit excitation vectors, response data, and control states between the ATE control logic, FPGA serial transceiver, and chip communication interface. The underlying communication bus bridging matrix refers to the data object that establishes the correspondence between protocol channels, serial transceivers, buffers, multiplexing paths, and test instrument ports. The test socket physical coordinate system refers to the spatial correspondence between chip pin placement points, test socket contact positions, robotic arm pick-and-place references, and load board connection points. Signal integrity constraints refer to impedance matching, return paths, crosstalk suppression, and reflection control rules in high-speed traces. After binding is completed, the machine port interconnection matrix, relay node logic status and link impedance compensation vector are written into the same configuration object. Abnormal channels are reserved with occupied or pending confirmation status for subsequent pin loading and path planning avoidance, and physical resource mapping configuration table is obtained.

[0021] S101: The ATE test channel capacity is obtained from the equipment resource description, interface board configuration record, and load board connection file. Load board routing constraints are derived from the routing topology, connection level, return path, and test socket contact allocation information. When analyzing pin voltage domain and current drive capability limitations, the power, ground, reset, clock, general input / output, and high-speed communication pins are first identified according to the chip datasheet. Then, the compatibility of different electrical attributes with the equipment drive, sampling, and power supply channels is checked. The relay array in the interface board is used to establish a switchable connection between the equipment port and the load board path. The pin driver position parameters are used to limit the electrical boundaries of the corresponding channel for applying excitation or receiving response to the chip pins. When identifying the physical link between the test machine and the load board, the connection description, relay contact status, interface board port number, and test socket contact coordinates are combined into topology nodes, and topology edges represent conductive physical paths. If there are missing, duplicate, inconsistent directions, or unconfirmed contact status in the hardware description, the relevant link is marked as not directly callable, and the source of the error and the affected port are recorded; for confirmed links, the connection relationship between ports, relays, wiring and contacts is preserved, and a hardware interface topology connectivity diagram is generated.

[0022] S102: When calling the hardware interface topology connectivity diagram, first read the conductive paths between the machine port, relay contacts, load board traces, and test socket contacts. Then, according to the chip communication interface and test program requirements, allocate control protocols, data protocols, and status readback protocols to the FPGA serial transceiver. The FPGA serial transceiver refers to the communication execution unit within the machine responsible for serialization, deserialization, link training, and status readback. The direct memory access buffer block refers to the buffer area that moves test vectors, protocol payloads, and response data between the machine control storage and the FPGA logic. When establishing a timing synchronization bridging mechanism between differentiated rate test channels, a unified handshake relationship is established according to the protocol role, trigger source, and response direction of each channel, ensuring that stimulus transmission, status readback, and buffer movement are identified within the same control link. The multiplexer logic is used to select the current test path on shared physical resources and avoid conflicting paths based on the relay array status. If the protocol field is inconsistent with the serial transceiver link capability, the relevant channel is written to an unbridgeable state; if there is a conflict between buffer block occupancy and vector relocation, the relevant bridging item is delayed in activation, and the available bridging relationship is output to the subsequent binding process to build the underlying communication bus bridging matrix.

[0023] S103: Based on the underlying communication bus bridging matrix, when binding the physical channel resources of the test equipment to the coordinate system of the target test socket, a spatially consistent positioning relationship is first established according to the test socket contact coordinates, chip placement direction, load board connection points, and robot arm pick-and-place reference. Then, available equipment ports and confirmed bridging channels are assigned to the corresponding chip pin landing points. Pin impedance matching parameters refer to the engineering configuration describing the matching relationship between the drive path and the chip pin termination state. High-speed signal integrity constraints refer to the set of rules that constrain reflection, return current, crosstalk, and edge distortion in the interface board and load board paths. Underlying test hardware netlist instantiation is to solidify the equipment ports, relay contacts, serial transceivers, multiplexing paths, load board traces, and test socket coordinates into a connection list that can be called by the test program. If the coordinate binding finds missing contacts, duplicate channel occupation, or chip placement direction inconsistent with the test socket direction, the relevant path is written into the resource binding abnormal state, and the alternative path and the reason for disabling are retained; the verified path forms the equipment port interconnection matrix, relay node logic state, and link impedance compensation vector, and obtains the physical resource mapping configuration table.

[0024] Please see Figure 1 and Figure 3 S2: When loading the target chip pin specifications according to the physical resource mapping configuration table, the logic pin name, pin type, electrical boundary, timing role, and protocol attribute are first obtained from the chip datasheet. Then, they are matched item by item with the machine port, test socket coordinates, bridging channel, and disabled state in the physical resource mapping configuration table. The comparison reference voltage refers to the engineering judgment benchmark used to distinguish the level state when the output response is sampled. Its source is the chip datasheet, test program, and machine comparator configuration record. When planning the signal transmission path, the internal wiring of the interface board, the relay closing state, the multiplexer selection state, and the load board path are comprehensively checked to ensure that high-frequency signals preferentially enter the physical path that meets the conditions of complete return path, impedance matching, and channel idleness. The dynamic channel allocation routing instruction refers to the instruction object that controls the relay array, multiplexer, and physical channel occupancy status. After output, it is used to complete the binding of virtual signals to the machine channel. The vector logic name refers to the name used to identify the chip pin and waveform role in the test vector table. The machine physical channel refers to the ATE hardware port that is actually driven or sampled. After alignment, the pin attribute feature vector, signal routing switching weight, and physical path occupancy mask are incorporated into the same index object to generate a logical pin physical channel index mapping table.

[0025] S201: When loading the power, ground, and I / O pin types defined in the chip datasheet based on the physical resource mapping configuration table, the power pins are first matched with the power supply channel, protection loop, and return path; the ground pins are matched with the reference plane and test socket return contacts; and the I / O pins are then matched with the drive sampling channel according to their input, output, bidirectional, clock, reset, and communication roles. Preset high / low level judgment boundaries for inputs are used to distinguish logic states during excitation or sampling. The output comparison reference voltage is used by the comparator to interpret the chip's response level. Electrical absolute rating boundaries are used to limit the electrical conditions applied to the pins by the testing equipment from exceeding the chip datasheet limits. The pin timing and level attribute fields refer to data objects that record pin type, direction, trigger relationship, reference voltage, drive limits, and sampling conditions. These are generated from sources including the chip datasheet, test program pin list, and physical resource mapping configuration table. If the logical name in the test vector table is inconsistent with the naming in the specification, the name is marked as pending verification, and the matched pin attributes are retained. If the pin type is incompatible with the physical channel capability, the relevant pin is written to an unbindable state to prevent subsequent routing from assigning incompatible channels to the target chip, and to establish the pin timing and level attribute domain.

[0026] S202: When configuring a high-frequency switching matrix based on pin timing and level attribute domains, first read the signal role, edge triggering requirements, drive direction, and comparison reference conditions of each logic pin. Then, combine the relay status, path occupancy status, and signal integrity constraints in the physical resource mapping configuration table to select the internal transmission path of the interface board. A high-frequency switching matrix refers to a configurable switching network composed of relay contacts, multiplexers, and controllable paths, used to connect the machine channel to the target test socket contact. When planning the preferred path for test signal transmission, priority is given to paths with continuous return paths, available path occupancy, termination status conforming to pin attributes, and limited adjacent interference. Residual parasitic capacitance and transmission line reflection interference are suppressed through contact closing sequence, path avoidance, termination matching, and return constraints. Pin topology routing priority refers to the sorting rules formed among multiple candidate physical traces based on signal role, electrical compatibility, path status, and historical anomaly records. It is not expressed numerically but driven by engineering rules for path selection. If the preferred path is occupied or in an abnormal state, the backup path is enabled under the same constraints, and the switching reason is written into the routing control object to generate a dynamic channel allocation routing instruction.

[0027] S203: When aligning the execution address based on the dynamic channel allocation routing instruction, the logical pin name in the test vector table is first matched with the pin role in the pin timing and level attribute domain, then matched with the available physical paths in the dynamic channel allocation routing instruction, and finally assigned to the physical instrument's real-time output channel or sampling channel. Virtual test signals refer to the logical excitation, sampling time, expected response, and mask determination information described in the test vector. Physical instrument pin drivers refer to the hardware execution components that actually output level excitation to the test socket contacts or receive response signals. During the binding process, power, ground, reset, clock, input / output, and high-speed communication signals enter their respective compatible physical channels. Channels that are already occupied or restricted by an exception flag do not participate in the binding. If the same logical pin matches multiple candidate channels, the target channel is reserved according to routing priority and electrical compatibility rules; if multiple logical pins point to the same physical channel, the conflict relationship is written into the occupancy mask and duplicate binding is blocked. The output object includes the logical name, instrument port, test socket coordinates, channel status, drive direction, sampling conditions, and exception flag, generating a logical pin physical channel index mapping table.

[0028] Please see Figure 1 and Figure 4 S3: When arranging the power-on sequence and waveform trigger parameters based on the logic pin physical channel index mapping table, first read the physical channel, power supply role, reset relationship, clock domain, and sampling mask corresponding to each logic pin, and then establish the timing control chain according to the power supply dependency, reset release relationship, and waveform description in the test vector table in the chip specification. The timing edge trigger control netlist refers to the data object that records the connection relationship between power-on startup, reset wait, clock trigger, data excitation, sampling gating, and response decision. The global precision clock source refers to the clock source that provides a unified reference for channel transmission and sampling within the machine. Channel delay compensation refers to the control processing that corrects the transmission time of each channel based on physical path differences, interface board wiring status, and channel calibration records. Before the test vector enters the pin driver component, it is first distributed to the corresponding physical channel according to the index mapping table, and then enters the driver buffer according to the timing edge trigger control netlist. The phase alignment timing reference, excitation waveform synthesis operator, and multi-channel synchronization status identifier are written into the same pulse chain object, so that the excitation of each channel is output under unified control conditions, and integrated to form a parallel synchronous function test drive pulse chain.

[0029] S301: When parsing standard test vector files based on the logic pin physical channel index mapping table, the logic pin names, waveform formats, expected responses, mask relationships, reset states, and clock domain identifiers in the vector file are read item by item and checked for consistency with the physical channels, pin roles, and drive directions in the index mapping table. The chip power-on sequence is determined by the power pin attributes, reset dependencies, interface initialization sequence, and test program control relationships. The reset wait period is described in the text as wait states and release conditions, without specifying the exact duration. The multi-clock domain cross boundary refers to the controlled transmission boundary at the intersection of asynchronous clock signals within the chip. At this boundary, cross-domain signals are constrained by the access range of synchronous flip-flops or buffer memory address pointers to prevent metastability from propagating to subsequent logic. The edge trigger type of the waveform format generator is configured based on the drive edge, sampling edge, and hold relationship in the vector. If the vector file has inconsistent formats, mismatched logic names, missing waveform segments, or unresolvable sampling masks, the abnormal items are marked and prevented from entering subsequent transmit control; the verified vector items form the trigger relationship between power-on, reset, clock, excitation, and sampling, and output the timing edge trigger control netlist.

[0030] S302: When adjusting the internal phase-locked loop (PLL) network of the FPGA based on the timing edge trigger control netlist, the trigger events, transmit phases, sampling gating signals, and response readback windows of each channel are first aligned to the global precision clock source. Then, inter-channel delay compensation control is generated based on the physical channel routing status, interface board path, load board connection, and channel calibration records. The PLL network refers to the clock control structure within the FPGA used to generate, allocate, and constrain the reference clock, enabling different physical channels to transmit excitation waveforms under the same timing reference. The synchronization pulse drive sequence refers to the control data arranged according to the trigger netlist, including channel identifier, transmit order, waveform role, synchronization status, and readback relationship. During channel compensation, channels that have completed phase locking and path verification are marked as transmitable, while channels with unconfirmed locking status or abnormal channel feedback are marked as temporarily suspended and fed back to the timing edge trigger control netlist to prevent unsynchronized channels from outputting to chip pins. The waveform transmit phase of each available channel is uniformly constrained, and the channel status and trigger relationship are written into the transmit control data to generate the synchronization pulse drive sequence.

[0031] S303: After receiving the synchronous pulse drive sequence, the instrument's memory control process reads the test vector data according to the channel identifier and vector segment relationship, and writes the vector data into the drive buffer of the corresponding pin drive electronic component. The pin drive electronic component refers to the instrument execution component that converts the test vector into electrical excitation of the chip pin and receives the response status. Its inputs are the synchronous pulse drive sequence, test vector data, and index mapping table, and its output is a high-speed excitation signal wave applied to the test socket contact. The preset waveform format is used to limit the drive level, edge triggering, hold relationship, and sampling coordination mode. Before driving, the channel synchronization status, buffer status, and route occupancy status are checked. If the buffer transmission fails, the channel status is invalid, the route is occupied, or the driver does not return a ready confirmation, the corresponding channel enters the transmit blocking state, and the logic pin, physical channel, and vector segment are associated and written into the exception record; the confirmed channel loads the excitation waveform to the chip pin according to the synchronous pulse drive sequence, so that the power supply, reset, clock, and data excitation run under the same timing control, and establishes a parallel synchronous function test drive pulse chain.

[0032] Please see Figure 1 and Figure 5 S4: When analyzing junction temperature fluctuation patterns based on the parallel synchronous function test drive pulse chain, thermal feedback acquisition and excitation state are performed synchronously. The feedback from the internal thermistor diode, power supply state, excitation channel state, and temperature control base response of the chip jointly form a thermal state record. The chip power consumption thermal resistance situation diagram refers to the data object describing the relationship between the excitation pulse chain, chip heating state, package heat dissipation, environmental heat load, and active temperature control response. The sources include pin drive state, thermistor measurement records, electrical measurement records, and temperature control loop feedback. The active temperature control base refers to the temperature control execution structure that is in thermal contact with the test socket or chip package, used to output cooling power through liquid cooling pipes or semiconductor cooling chips. The temperature stability window refers to the time period during which the thermal feedback state continuously meets the electrical measurement requirements. The electrical measurement parameters are only bound to the thermal compensation state within this window to avoid thermal drift affecting the response judgment. The steady-state junction temperature deviation limit, power consumption feedback adjustment coefficient, and thermal sensitivity drift constant are all recorded in an engineering rule manner, including their source, meaning, and participating links, without outputting specific values. Transient power consumption, thermal compensation status, and measurement results are uniformly written into the evaluation object to generate a self-matching thermal compensation system-level online test evaluation table.

[0033] S401: When synchronously measuring the forward voltage drop change of the internal thermistor of the test drive pulse chain based on parallel synchronization function, the acquisition channel first checks against the logic pin physical channel index mapping table to confirm that the thermistor measurement path, power supply path, and excitation path are all in an effective binding state. The thermistor forward voltage drop change serves as the electrical characterization source of the junction temperature state and is recorded synchronously with the power supply, clock, data drive, and sampling states in the current excitation pulse chain. The package heat dissipation characteristics are described through the feedback relationship between the chip package, test socket contact surface, active temperature control base, and ambient heat load. The transient fluctuation law of junction temperature is characterized by the change sequence, change direction, and temperature control response relationship of the thermal feedback state, without numerical derivation. The current ambient heat distribution load comes from the temperature control base feedback, test socket contact state, and surrounding heat exchange state records. If thermistor feedback is missing, the acquisition channel and index mapping are inconsistent, the temperature control base feedback is interrupted, or the measurement record cannot be bound to the excitation state, the corresponding thermal state is marked as incomplete and will be subject to restricted processing in subsequent temperature control adjustments; the effective thermal feedback and excitation state are written into the thermal state diagram to construct the chip power consumption thermal resistance situation diagram.

[0034] S402: When calling the chip power consumption and thermal resistance situation diagram to control the active temperature control base on the top of the test bench, it first reads the junction temperature state, transient power consumption state, package heat dissipation record, and ambient heat distribution load, and then determines the deviation category of the thermal state relative to the target operating state. The output objects of the active temperature control base include liquid cooling pipeline flow control and semiconductor refrigeration chip drive control. Both enter the corresponding adjustment path according to the direction of thermal state deviation, thermal feedback stability, and electrical measurement requirements. The closed-loop heat offset loop refers to the feedback link formed between the heat generated by the excitation, the package conduction path, the cooling output of the temperature control base, and the feedback of the thermistor, which is used to keep the thermal state under control within the window required for electrical measurement. If no confirmation is received from the temperature control base after the control command is issued, or if the feedback direction is inconsistent with the control target, the corresponding control record is marked as unconfirmed, and subsequent use of that period as a stable measurement window is prevented. If the liquid cooling pipeline or semiconductor refrigeration chip returns to an abnormal state, the temperature control adjustment enters a safety constraint, and the source of the abnormality is written into the situation diagram. The cooling output confirmed by feedback is bound to the junction temperature state in chronological order to generate an active heat compensation adjustment curve.

[0035] S403: When maintaining a rapid constant temperature in the test environment based on the active thermal compensation adjustment curve, first check the output status of the temperature control base, the feedback status of the thermistor diode, the excitation pulse chain status, and the status of the electrical measurement channel. After confirming that the thermal feedback has entered a stable category that can be used for measurement, lock the temperature stabilization window period. The chip's static electrical parameters and leakage current measurements are only performed within the effective window. The measurement records are synchronously bound with transient power consumption, thermal compensation circuit status, power supply path, sampling channel, and test base coordinates. The self-matching thermal compensation system-level online test evaluation table refers to a data object that uniformly organizes electrical measurement conditions, thermal compensation status, steady-state junction temperature deviation limit, power consumption feedback adjustment coefficient, thermal sensitivity drift constant, and anomaly identifier, serving as the basis for subsequent gating decisions and graded judgments. If the stabilization window is interrupted by thermal feedback anomalies, measurement path anomalies, unconfirmed temperature control commands, or unmet sampling conditions, the relevant measurement results are marked as environmental-related anomalies and do not directly enter the chip failure judgment; the electrothermal binding records formed within the effective window are retained for response judgment, fault tracing, and sorting code generation, generating the self-matching thermal compensation system-level online test evaluation table.

[0036] Please see Figure 1 and Figure 6 S5: When executing the gating decision within the target sampling window based on the self-matching thermal compensation system-level online test evaluation table, first confirm that the thermal compensation state, electrical measurement state, and channel synchronization state corresponding to the sampling window can all be used for response interpretation, and then compare the chip output level with the expected vector mask according to rules. The expected vector mask refers to the judgment data used in the test vector table to identify the valid comparison bit, ignored bit, and protocol response field. The functional test response result refers to the level state, timing state, and protocol load state returned by the chip under parallel excitation. Logic defect location is completed jointly based on the response abnormality site, the logic pin physical channel index mapping table, the timing edge trigger control netlist, and the thermal compensation evaluation record, avoiding misclassification of temperature control abnormalities, drive abnormalities, or channel abnormalities as internal chip defects. Protocol payload decoding is used to trace the internal logic circuit, memory array area, or interface state corresponding to the error flag bit. The sorting level is formed based on the defect distribution characteristic entropy value, failure mode weight index, and logic function health score engineering rules, and is transmitted to the robot control center along with the test base coordinates to generate a multi-dimensional judgment sorting and grading code for chip quality.

[0037] S501: When the output level is selected and decided within the preset sampling window based on the self-matching thermal compensation system-level online test and evaluation table, the sampling window is first checked against the temperature stability window, electrical measurement status, and synchronous pulse drive sequence to confirm that the response signal originates from a valid drive chain and a valid thermal compensation status. Output level selection and decision refers to reading the response status according to the sampling position and masking rules in the test vector table, and matching the response status with the logical positions allowed for comparison in the expected vector mask. Timing offset refers to the response status not falling into the controlled position corresponding to the preset sampling relationship; level status abnormality refers to the response level being inconsistent with the expected logical state. Both need to be classified in conjunction with the channel synchronization status, drive buffer status, and thermal compensation evaluation records. If the thermal compensation status corresponding to the sampling window is unavailable, the response is marked as an environmental association anomaly; if the response data is duplicated, missing, or the transmission link is unconfirmed, the response is marked as a data link anomaly, and the source path and related channel identifier are retained. Valid responses, abnormal locations, masking rules, sampling windows, and thermal compensation status together form a traceable comparison object, resulting in an output response signal timing mask comparison set.

[0038] S502: When decoding the internal payload of the bus protocol based on the response signal timing mask comparison set, the payload category, control state, error flag, and readback field are first read according to the protocol frame structure. Then, the decoding result is checked against the logic pin physical channel index mapping table, timing edge trigger control netlist, and self-matching thermal compensation system-level online test evaluation table for consistency verification. Internal failure modes refer to the abnormal categories of internal logic circuits, memory array areas, or interface states pointed to by response anomalies, protocol error flags, timing offsets, and level state anomalies. The physical distribution area inside the die is determined by the pin connection relationship, protocol field attribution, logic function partitioning, and test socket coordinate mapping, and is used to trace external response anomalies back to the internal functional location of the chip. If the protocol payload cannot be parsed, the relevant response is not directly used as an internal failure conclusion, but is marked as a protocol unresolvable state, and the original response, sampling window, and channel source are retained for verification. If the decoding result is associated with a drive chain anomaly or thermal compensation anomaly, the defect classification is constrained to external condition anomalies. The abnormal response and physical area mapping relationship verified through consistency verification are written into the defect record to generate a device logic function defect distribution map.

[0039] S503: When determining the chip yield rate based on the device logic function defect distribution map, first read the defect distribution area, failure mode category, functional response status, protocol decoding result, and thermal compensation evaluation status. Then, compare the failure parameter deviation level by level according to the preset performance degradation tolerance rule. Failure parameter deviation refers to the engineering characterization of the deviation of the measurement response from the functional requirements, electrical boundaries, timing relationship, and protocol status. The sorting category consists of physical rejection bins and degraded use bins. Physical rejection bins are used to receive chips that do not meet the basic functional requirements, while degraded use bins are used to receive chips that meet the core functions but have reduced target time and frequency capabilities. The absolute coordinates of the test socket refer to the coordinate information required by the robot control center to identify the current position of the chip. The sorting category is bound to the coordinate information to form the basis for pick-and-place control. If the robot control center does not return a confirmation instruction, the sorting grade code is retained in the pending retransmission state, and the chip does not enter the pick-and-place action; if the coordinate information is inconsistent with the current test socket state, the pick-and-place control is blocked and a coordinate verification anomaly is output. The defect distribution, failure mode weights, logic function health status, test fixture coordinates, and sorting categories are determined and written into the final sorting object to generate a multi-dimensional chip quality judgment sorting and grading code.

[0040] The above embodiments illustrate preferred embodiments of the present invention. Any equivalent adjustments to the technical solution based on software engineering methods are within the scope of protection, including but not limited to: implementing algorithm logic using different programming languages, refactoring functional modules into services, adjusting data interaction protocols, and optimizing resource scheduling strategies. Any implementation scheme derived from reasonable modifications to the data processing flow, service call chain, or system architecture layer without departing from the core technology of the present invention should be considered within the protection scope defined by the technical solution of the present invention.

Claims

1. A highly configurable system-level online testing method, characterized in that, Includes the following steps: S1: Extract the capacity and pin electrical limits of the ATE test channel, configure the relay array of the test machine, map the underlying communication protocol to the serial transceiver to build the underlying communication bus bridge matrix, bind the physical coordinate system of the test base and lock the signal integrity constraints, and obtain the physical resource mapping configuration table; S2: Load the target chip pin specifications according to the physical resource mapping configuration table, set the comparison reference voltage, plan the signal transmission path to eliminate line reflection interference, generate dynamic channel allocation routing instructions, align vector logic names with machine physical channels, and generate a logic pin physical channel index mapping table. S3: Based on the physical channel index mapping table of the logic pins, arrange the power-on sequence and waveform trigger parameter output timing edge trigger control netlist, align the global precision clock source and compensate for channel delay, push the test vector into the pin drive unit at full speed, and integrate to form a parallel synchronous function test drive pulse chain; S4: Based on the parallel synchronization function test drive pulse chain, analyze the junction temperature fluctuation law to construct the chip power consumption and thermal resistance situation diagram, adjust the output dynamic drive cooling power of the active temperature control base, bind electrical measurement parameters in the temperature stability window, and generate a self-matching thermal compensation system-level online test evaluation table. S5: Based on the self-matching thermal compensation system-level online test evaluation table, perform gating decision comparison of expected vectors in the target sampling window, locate logic defects according to functional test response results, decode protocol payload to trace internal failure modes, classify sorting levels and interact with robot controller, and generate chip quality multi-dimensional judgment sorting and grading codes.

2. The highly configurable system-level online testing method according to claim 1, characterized in that, The physical resource mapping configuration table includes a machine port interconnection matrix, relay node logic status, and link impedance compensation vector. The logic pin physical channel index mapping table includes pin attribute feature vectors, signal routing switching weights, and physical path occupancy masks. The parallel synchronization function test drive pulse chain includes phase alignment timing references, excitation waveform synthesis operators, and multi-channel synchronization status identifiers. The self-matching thermal compensation system-level online test evaluation table includes steady-state junction temperature deviation limits, power consumption feedback adjustment coefficients, and thermal sensitivity drift constants. The chip quality multi-dimensional judgment, sorting, and grading code includes defect distribution feature entropy values, failure mode weighting indices, and logic function health scores.

3. The highly configurable system-level online testing method according to claim 1, characterized in that, The specific steps for setting up the physical resource mapping configuration table are as follows: S101: Extract the ATE test channel capacity and load board wiring constraints, analyze the pin voltage domain and current drive capability limitations, configure the relay array and pin driver range parameters in the interface board, identify the physical link between the test machine and the load board, and generate a hardware interface topology connection diagram. S102: Call the hardware interface topology connection diagram, map the underlying communication protocol to the FPGA serial transceiver, allocate direct memory access buffer blocks, establish a timing synchronization bridging mechanism between differentiated rate test channels, configure multiplexer logic, and construct the underlying communication bus bridging matrix. S103: Based on the underlying communication bus bridging matrix, bind the physical channel resources of the test machine to the coordinate system of the target test stand, lock the pin impedance matching parameters and high-speed signal integrity constraints, instantiate the underlying test hardware netlist, and obtain the physical resource mapping configuration table.

4. The highly configurable system-level online testing method according to claim 3, characterized in that, The specific steps for establishing the logic pin physical channel index mapping table are as follows: S201: Based on the physical resource mapping configuration table, load the power, ground and I / O pin types defined in the chip specification, set the preset threshold for input high and low levels and the output comparison reference voltage, define the electrical absolute rated boundary of each pin, and establish the pin timing and level attribute domain; S202: Based on the pin timing and level attribute domain, configure a high-frequency switching matrix, plan the preferred transmission path of the test signal inside the interface board, eliminate residual parasitic capacitance and transmission line reflection interference, lock the pin topology routing priority, and generate dynamic channel allocation routing instructions. S203: Based on the dynamic channel allocation routing instruction, align the logical pin names in the test vector table with the real-time output channels of the physical machine, bind the virtual test signals to the pin drivers of the physical machine, and generate a logical pin physical channel index mapping table.

5. The highly configurable system-level online testing method according to claim 4, characterized in that, The preferred transmission path of the planned test signal inside the interface board refers to calculating the distributed inductance per unit length between the test signal line and the reference ground plane based on the signal frequency requirements in the pin timing and level attribute domain, adjusting the closing sequence of the relay contacts of the high-frequency switching matrix, and obtaining a physical trace with transmission line impedance matching compensation.

6. The highly configurable system-level online testing method according to claim 4, characterized in that, The specific steps for testing the parallel synchronization function drive pulse chain are as follows: S301: Based on the physical channel index mapping table of the logic pins, parse the standard test vector file, arrange the chip power-on sequence and reset wait cycle, define the cross boundary of multiple clock domains, configure the edge trigger type of the waveform format generator, and output the timing edge trigger control netlist. S302: Based on the timing edge triggering control netlist, adjust the phase-locked loop network inside the FPGA of the machine tool, align the excitation signal to the global clock source, plan the nanosecond-level trace delay compensation between the differentiated test channels, lock the multi-channel waveform transmission phase, and generate a synchronous pulse drive sequence. S303: Receive the synchronous pulse drive sequence, drive the instrument memory control unit to push the test vector data into the pin drive electronic unit at full speed, apply a high-speed excitation signal wave that strictly conforms to the timing specification to the chip pin according to the preset waveform format, and establish a parallel synchronous function test drive pulse chain.

7. The highly configurable system-level online testing method according to claim 6, characterized in that, The delineation of the multi-clock domain cross boundary refers to identifying the frequency ratio and phase deviation between differentiated asynchronous clocks within the chip, configuring the address pointer access range of synchronous triggers or buffer memories at the physical nodes of signal cross-clock transmission, and obtaining timing boundary constraints that meet the metastability filtering requirements.

8. The highly configurable system-level online testing method according to claim 6, characterized in that, The specific steps for the self-matching thermal compensation system-level online test and evaluation form are as follows: S401: Based on the parallel synchronization function test drive pulse chain, synchronously measure the forward voltage drop change of the thermistor inside the chip, analyze the heat dissipation characteristics of the package and the transient fluctuation law of the junction temperature, map the current environmental heat distribution load, and construct the chip power consumption thermal resistance status diagram. S402: Call the power consumption and thermal resistance status diagram of the chip, control the active temperature control base on the top of the test machine, adjust the flow rate of the liquid cooling pipeline or the dynamic driving power of the semiconductor cooling chip according to the deviation of the junction temperature from the target value, identify the closed-loop heat offset circuit, and generate an active heat compensation adjustment curve. S403: Based on the active thermal compensation adjustment curve, maintain the test environment at an extremely fast constant temperature, lock the temperature stability window period, and perform static electrical parameter and leakage current measurements of the chip. Bind the transient power consumption to the thermal compensation loop state in the time domain to generate a self-matching thermal compensation system-level online test evaluation table.

9. The highly configurable system-level online testing method according to claim 8, characterized in that, The specific steps for the multi-dimensional chip quality determination, sorting, and grading code are as follows: S501: Based on the self-matching thermal compensation system-level online test and evaluation table, the output level is selected and decided within the preset sampling window, compared with the expected vector mask, the timing offset and level state abnormality points are located, and the response signal timing mask comparison set is output. S502: Based on the timing mask comparison set of the response signal, decode the internal payload of the bus protocol, trace the failure mode of the internal logic module or memory unit that caused the error flag, lock the physical distribution area of ​​the logic defect inside the die, and generate a device logic function defect distribution map. S503: Determine the chip yield rate based on the device logic function defect distribution map, classify the physical rejection and downgraded use warehouse level according to the failure parameter deviation, transmit the absolute coordinates of the test seat and the sorting category to the robot control center, and generate a multi-dimensional judgment sorting and grading code for chip quality.

10. The highly configurable system-level online testing method according to claim 9, characterized in that, The step of classifying physical rejection and degraded use warehouse levels based on the deviation of failure parameters refers to comparing the measured deviation of failure parameters with the preset performance degradation tolerance value level by level. Chips that do not meet the basic functional requirements are assigned to the physical rejection warehouse, while chips that meet the core functions but whose target time and frequency indicators are reduced are assigned to the degraded use warehouse, thus obtaining sorting categories with differentiated performance levels.

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