Ion chip-oriented integrated grating coupler design method

Abstract

The application discloses an ion chip-oriented integrated grating coupler design method, and belongs to the field of integrated optoelectronic device design, which comprises the following steps: constructing a simulation model, so that the beam waist height of outgoing light is equal to the trapping height of ions, and basic structure parameters are obtained; coarsely adjusting the depth parameter of the basic structure parameters, so that the first corresponding relationship between the depth parameter and the beam waist diameter is obtained; selecting the adjustment range of the depth parameter, finely adjusting the depth parameter in the range to obtain the second corresponding relationship between the depth parameter and the beam waist height; and according to the actual trapping height of the ions, the optimal value of the depth parameter is obtained from the second corresponding relationship, and the design is completed. The technical scheme of the application establishes a one-to-one mapping relationship between the beam waist height of outgoing light and the etching depth of the coupling grating, and only one reverse design is needed to complete all design requirements of the same batch of ion chips for different trapping heights, thereby reducing the design period, improving the manufacturing efficiency of the integrated grating coupler, and reducing the cost.

Description

Technical Field

[0001] This invention belongs to the field of integrated optoelectronic device design, specifically relating to an integrated grating coupler design method for ion chips. Background Technology

[0002] Optical integrated-chip ion traps achieve precise manipulation and measurement of qubits by integrating ion trap electrodes, laser waveguides, laser sources, photodetectors, and other necessary optical components onto a single chip. An integrated grating coupler first couples light into a grating, then focuses the emitted light onto trapped ions for addressing, thereby controlling the qubits within the ion chip. Therefore, integrated grating couplers play a crucial role in the practical applications of ion trap quantum computing, especially in the scalable evolution of quantum computing.

[0003] In chip ion traps, the trapped ions are only on the order of micrometers, which places high demands on the focusing accuracy of the addressing beam. If the beam cannot be accurately focused on the location of the trapped ions, the ion entanglement fidelity will decrease, and subsequent optical manipulation of the trapped ions will be difficult to perform effectively.

[0004] Existing technologies typically employ reverse engineering, using multi-parameter scanning of simulation models to optimize structural parameters of the grating coupler, such as the grating period and duty cycle. This approach is highly complex, computationally resource-intensive, and extremely time-consuming. For example, a simple one-dimensional grating coupler requires several days of continuous computation to iteratively determine a set of structural parameters. Adjusting any single parameter will require even more days to obtain a new result. Summary of the Invention

[0005] Based on this, the integrated grating coupler design method for ion chips provided by the present invention obtains the relationship between the depth parameters of the integrated grating coupler and the corresponding waist height and waist diameter based on the structural parameters obtained through a reverse design. It then determines the adjustment range of the depth parameters based on the target value of the waist diameter, and finally determines the optimal depth parameters within the depth parameter adjustment range based on the target value of the waist height. This avoids iterative optimization of all parameters and solves the problems of high resource consumption and long computation time in existing technologies.

[0006] To achieve the above objectives, this invention provides a design method for an integrated grating coupler for ion chips. The integrated grating coupler includes a coupling grating for coupling and emitting incident light, such that the beam waist of the emitted light is positioned on trapped ions within the ion chip. The design method includes the following steps: S1: Setting the trapping height of the trapped ions in the ion chip, constructing and optimizing a simulation model of the integrated grating coupler so that the beam waist height of the emitted light equals the trapping height, and obtaining structural parameters; S2: Coarsely adjusting the depth parameter in the structural parameters, calculating the simulation model, and obtaining a first correspondence between the depth parameter and the beam waist diameter; S3: Selecting an adjustment range for the depth parameter based on the beam waist diameter requirements of the ion chip; S4: Finely adjusting the depth parameter within the adjustment range, calculating the simulation model, and obtaining a second correspondence between the depth parameter and the beam waist height; S5: Determining the optimal value of the depth parameter based on the second correspondence according to the actual trapping height of the trapped ions, to complete the design. Wherein, the depth parameter is the grating etching depth. In particular, when the coupling grating is a fully etched grating, the grating etching depth is equal to the waveguide layer thickness.

[0007] Specifically, the integrated grating coupler includes a substrate, a lower cladding, a waveguide layer, and an upper cladding layer arranged sequentially. The waveguide layer has grooves forming the coupling grating. The coupling grating couples the incident light and allows it to exit from the upper cladding, forming a waisted focal spot. The vertical distance between the waisted focal spot and the surface of the coupling grating is the waist height, and the diameter of the waisted focal spot is the waist diameter.

[0008] Preferably, the structural parameters include grating period, duty cycle, grating length, depth parameter, waveguide layer thickness, upper cladding layer thickness, and lower cladding layer thickness.

[0009] Specifically, step S2, which involves obtaining the first correspondence between the depth parameter and the beam waist diameter, includes: setting a reference line in the light field of the simulation model, such that the reference line extends along the grating direction of the coupled grating; fitting the light intensity variation on the reference line to obtain a fitting function; and measuring the peak value of the fitting function. The width at the reference line is taken as the beam width; the height of the reference line is adjusted, the beam width is measured, and the minimum value of the beam width is taken as the beam waist diameter.

[0010] Further, the step of obtaining the second correspondence between the depth parameter and the waist height in step S4 includes: adjusting the height of the reference line and taking the height of the reference line corresponding to the minimum beam width as the waist height.

[0011] Specifically, the fitting function is Where I is light intensity, For amplitude, These are the spatial coordinates along the direction of the baseline. The spatial coordinates of the peak position. This is the width parameter.

[0012] Preferably, when the operating wavelength is 729 nm, the trapping height is 120 μm, the substrate material is Si, the waveguide layer material is Si3N4, and the upper and lower cladding layers are both made of SiO2, the structural parameters of the integrated grating coupler are set as follows: the duty cycle is 0.66, the grating etching depth is 0.17 μm, the grating length is 34.89 μm, the upper cladding thickness is 13 μm, the lower cladding thickness is 2.7 μm, and the waveguide layer thickness is 0.27 μm.

[0013] Furthermore, the step of constructing and optimizing the simulation model of the integrated grating coupler in step S1 includes iterative optimization based on performance indicators; the performance indicators include the beam waist height, diffraction efficiency, coupling efficiency, coupling strength, operating wavelength, target angle, effective refractive index of the waveguide layer, and refractive index of the upper cladding layer.

[0014] The technical solution provided by this invention has the following beneficial effects:

[0015] The technical solution provided by this invention optimizes the simulation model of the integrated grating coupler and establishes a one-to-one mapping relationship between the beam waist height of the emitted light and the etching depth of the coupling grating. Only one reverse design is needed to complete all design requirements for different trapping heights of the same batch of ion chips, reducing the design cycle, improving the manufacturing efficiency of the integrated grating coupler, and reducing costs. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the integrated grating coupler design method according to an embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram of the integrated grating coupler model structure according to an embodiment of the present invention.

[0018] Figure 3 This is a light intensity distribution diagram of the integrated grating coupler according to an embodiment of the present invention.

[0019] Figure 4 This illustrates the effect of variations in grating etching depth on the optical field in embodiments of the present invention. Figure 4 (a) is a curve showing the change of beam waist height with grating etching depth in an embodiment of the present invention; Figure 4(b) is the curve showing the change of beam waist diameter with grating etching depth in an embodiment of the present invention.

[0020] Figure 5 This is a schematic diagram of a test system with an integrated grating coupler.

[0021] Figure 6 This illustrates the effect of variations in grating etching depth on the optical field in Embodiment 2 of the present invention. Figure 6 (a) is the curve showing the change of beam waist height with grating etching depth in Embodiment 2 of the present invention; Figure 6 (b) is the curve showing the change of the beam waist diameter with the grating etching depth in Embodiment 2 of the present invention.

[0022] Figure 7 This illustrates the effect of variations in waveguide layer thickness on the optical field in Embodiment 3 of the present invention. Figure 7 (a) is the curve showing the change of waist height with waveguide layer thickness in Embodiment 3 of the present invention; Figure 7 (b) is the curve showing the change of the waist diameter as a function of the waveguide layer thickness in Embodiment 3 of the present invention.

[0023] Figure 8 This illustrates the effect of variations in waveguide layer thickness on the optical field in Embodiment 4 of the present invention. Figure 8 (a) is the curve showing the change of waist height as a function of waveguide layer thickness in Embodiment 4 of the present invention; Figure 8 (b) is the curve showing the change of the waist diameter as a function of the waveguide layer thickness in Embodiment 4 of the present invention.

[0024] The labels in the diagram represent:

[0025] 1. Incident light; 2. Trapped ions; 3. Substrate; 4. Lower cladding; 5. Upper cladding; 6. Waveguide layer; 7. Outgoing light; 8. Laser; 9. Ion chip; 10. Beam analyzer; 11. Computer; 12. Optical fiber; 13. Test platform. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0027] Example 1

[0028] Please see the appendix Figure 1 , Figure 1This is a flowchart illustrating the integrated grating coupler design method according to an embodiment of the present invention. As shown in the figure, the steps of the integrated grating coupler design method for the ion chip 9 include: S1: Setting the trapping height of the trapped ions 2 in the ion chip 9, constructing and optimizing a simulation model of the integrated grating coupler, making the beam waist height of the emitted light 7 equal to the trapping height, and obtaining structural parameters; S2: Coarsely adjusting the depth parameter in the structural parameters, calculating the simulation model, and obtaining a first correspondence between the depth parameter and the beam waist diameter; S3: Selecting an adjustment range for the depth parameter according to the beam waist diameter requirements of the ion chip 9; S4: Finely adjusting the depth parameter within the adjustment range, calculating the simulation model, and obtaining a second correspondence between the depth parameter and the beam waist height; S5: Determining the optimal value of the depth parameter based on the second correspondence according to the actual trapping height of the trapped ions 2, to complete the design. Wherein, the depth parameter is the grating etching depth.

[0029] In this embodiment of the invention, when parameters change, there is no need to perform full parameter optimization. Instead, the integrated grating coupler of the ion chip 9 can be fine-tuned by scanning the single parameter of the grating etching depth. This avoids the complex calculation of iterative structural parameters, thereby reducing the consumption of computing resources, shortening the calculation time, and improving design efficiency.

[0030] Please see the appendix Figure 2 , Figure 2 This is a schematic diagram of the integrated grating coupler model structure according to an embodiment of the present invention. Exemplarily, in this embodiment, the integrated grating coupler has a layered structure, including a substrate 3, a cladding layer, and a waveguide layer 6. The substrate 3 provides mechanical support. The cladding layer is divided into an upper cladding layer 5 and a lower cladding layer 4. The lower cladding layer 4 is placed on the substrate 3 to isolate the optical field from the substrate 3 and reduce leakage loss. The upper cladding layer 5 protects the waveguide layer 6 and controls the optical field. The waveguide layer 6 is placed between the upper cladding layer 5 and the lower cladding layer 4. The waveguide layer 6 has grooves forming a grating. In this embodiment, the period of the grooves is variable, and the grating formed is an apodization grating, which is mainly used for focusing. In the integrated grating coupler of this embodiment, incident light 1 enters the waveguide layer 6 through end-face coupling, is transmitted to the coupling grating, undergoes diffraction of different orders, propagates through the surface of the coupling grating of the waveguide layer 6 to the upper cladding layer 5, and then exits from the upper cladding layer 5, forming an outgoing light 7 with a focusing effect. The emitted light 7 has a waist, the vertical distance between the waist focal spot and the surface of the waveguide layer 6 is the waist height, and the diameter of the waist focal spot is the waist diameter.

[0031] In this embodiment of the invention, a semi-etching process is used to etch the grating of the integrated grating coupler. Specifically, this embodiment employs an inductively coupled plasma (ICP) etching process. ICP etching utilizes a high-frequency electromagnetic field to excite plasma and etch the material surface. During ICP etching, the etching gas generates high-density plasma under the action of an RF power supply, bombarding the surface of waveguide layer 6. This causes the chemical bonds in the waveguide layer 6 material to break, generating volatile substances that detach from the surface of waveguide layer 6, forming etching defects. The ICP etching process includes sample surface cleaning, sample loading, etching parameter setting, etching process control, and post-etching sample cleaning. By controlling parameters such as gas type, flow rate, and RF power during the etching process, highly selective and anisotropic etching of materials can be achieved, which is commonly used in the fabrication of micro and nanostructures.

[0032] For example, in this embodiment of the invention, step S1 includes: constructing a two-dimensional simulation model of the integrated grating coupler using the Finite-Difference Time-Domain (FDTD) method. The operating wavelength of the integrated grating coupler is set to 729 nm, the material of the substrate 3 is Si, the material of the upper cladding layer 5 is SiO2, the material of the lower cladding layer 4 is SiO2, the ion trapping height in the chip is 120 μm, and the material of the waveguide layer 6 is SiN. X In one or other embodiments of the present invention, the waveguide layer 6 may also be made of Si3N4. Based on the performance indicators such as the beam waist height, diffraction efficiency, coupling efficiency, coupling strength, target wavelength, target angle, effective refractive index of the waveguide layer 6, and refractive index of the upper cladding layer 5, the embodiments of the present invention employ an optimization algorithm to optimize the simulation model of the integrated grating coupler, obtaining a set of structural parameters for the integrated grating coupler. The specific structural parameters obtained through a reverse design simulation optimization process in the embodiments of the present invention are as follows: the duty cycle is 0.66, the grating etching depth is 0.17 μm, the grating length is 34.89 μm, the thickness of the upper cladding layer 5 is 13 μm, the thickness of the lower cladding layer 4 is 2.7 μm, and the thickness of the waveguide layer 6 is 0.27 μm.

[0033] Please see the appendix Figure 3 , Figure 3 This is a light intensity distribution diagram of the integrated grating coupler according to an embodiment of the present invention. In the diagram, the horizontal axis represents spatial coordinates, the vertical axis represents the height of the baseline, and the color scale represents light intensity. Figure 3 The size range of the color swatch is 3.11 × 10. -6 ~0.272W / m 2As shown in the figure, when the target operating wavelength is 729nm, the full parameter optimization performed by reverse engineering in this embodiment of the invention results in a beam waist height of approximately 120μm for the emitted light 7, which is equal to the preset trapping height.

[0034] In this embodiment of the invention, since the emitted light 7 is used to address the trapped ions 2 in the ion chip 9, the system has high requirements for the beam waist diameter of the emitted light 7. For example, the ion chip 9 requires a beam waist diameter of 4~5μm, and the adjustment range of the grating etching depth can be selected based on this requirement. Within this adjustment range, the grating etching depth is further finely adjusted, and a second correspondence between the grating etching depth and the beam waist height can be obtained through simulation. Since errors are inevitably introduced during experimental fabrication, the structural parameters optimized based on the simulation model need to be adjusted multiple times to ensure that the beam waist height of the emitted light 7 matches the trapping height of the trapped ions 2 in the ion chip 9. During this process, due to the coherence of the coupled grating, the structural parameters are interconnected. Existing technologies require comprehensive optimization of the structural parameters with each adjustment, which not only consumes a large amount of computational resources but also makes the fabrication iteration of the integrated grating coupler extremely complex, severely impacting experimental efficiency. By providing a second correspondence between the beam waist height and the grating etching depth within the debugging range, this embodiment of the invention not only ensures that the beam waist diameter meets the requirements, but also simplifies the design iteration process of the integrated grating coupler and improves efficiency.

[0035] For example, in this embodiment of the invention, the beam waist diameter needs to be limited to within 4~5 μm. This allows the emitted light 7 to address and manipulate the trapped ions 2 without causing crosstalk to neighboring ions. Please refer to the appendix. Figure 4 , Figure 4 The figure illustrates the effect of variations in grating etching depth on the optical field in embodiments of the present invention. All coordinates in the figure are in μm. Figure 4 (a) is a curve showing the change of waist height with grating etching depth in an embodiment of the present invention. The horizontal axis in the figure is the grating etching depth, and the vertical axis is the waist height. Figure 4 The waist height shown in (a) is the vertical distance between the waist focal spot and the surface of waveguide layer 6, reflecting the second correspondence between grating etching depth and waist height. As can be seen from the figure, the waist height decreases with increasing grating etching depth. Figure 4 (b) is a curve showing the variation of the beam waist diameter with the grating etching depth in an embodiment of the present invention. The horizontal axis in the figure represents the grating etching depth, and the vertical axis represents the beam waist diameter. Figure 4(b) reflects the first correspondence between grating etching depth and beam waist diameter. When the grating etching depth varies within the range of 0.02–0.14 μm, the beam waist diameter fluctuates within the range of 6.5–7.25 μm, both exceeding the required 4–5 μm range for beam waist diameter, making it unsuitable for trapped ion manipulation. When the grating etching depth is within the range of 0.14–0.17 μm, the beam waist diameter is consistently less than 4.5 μm and greater than 5 μm, suitable for trapped ion manipulation. According to… Figure 4 (b) It can be seen that when the required beam waist diameter of the ion chip 9 is 4~5μm, the adjustable range of the grating etching depth is 0.14~0.17μm. Figure 4 (a) shows that the beam waist height varies from approximately 119 to 127 μm when the grating etching depth ranges from 0.14 to 0.17 μm, which includes the actual trapping height of trapped ion 2.

[0036] In this embodiment of the invention, to verify the accuracy of the integrated grating coupler design method of the present invention, the designed integrated grating coupler is fabricated to form an ion chip 9 before experimental verification. The fabrication process of the integrated grating coupler includes: wafer surface cleaning, i.e., cleaning of the surface of the lower cladding layer 4, growth of waveguide thin film, grating and waveguide structure characterization, fabrication of waveguide layer 6, and fabrication of upper cladding layer 5.

[0037] Exemplarily, the fabrication of integrated grating couplers involves high-precision micro / nano fabrication, particularly nanolithography and etching processes. The wafer surface cleaning step includes: thoroughly cleaning the wafer with organic solvents (acetone and isopropanol solutions) to remove surface grease and impurities. Subsequently, rinsing with deionized water removes any remaining organic solvents. Finally, plasma treatment is used to remove any residual organic solvents, ensuring the wafer surface achieves the required cleanliness. The waveguide thin film growth step includes: depositing a SiNx layer as waveguide layer 6 using plasma-enhanced chemical vapor deposition (PECVD) to fabricate the grating coupler and end-face coupler; the thickness of waveguide layer 6 is typically hundreds of nanometers. The grating structure patterning step includes: first, uniformly coating a photoresist layer onto the SiNx material surface to form a photosensitive protective layer. Then, using electron beam etching, fine exposure is performed on the photoresist layer according to a predetermined design pattern to form the desired grating structure. Finally, the photoresist in the exposed areas is removed by a development process, exposing the areas of SiNx material that need to be etched, preparing for subsequent etching steps. This process ensures the precision and consistency of the grating structure, which is crucial for achieving high-quality emitted light spots. The steps for fabricating waveguide layer 6 include: deeply etching the SiNx material using ICP etching technology to form a precise grating structure, completing all processes for the end-face coupler and the grating coupler. The steps for fabricating the upper cladding layer 5 include: depositing a layer of SiO2 on the surface of waveguide layer 6 as the upper cladding layer 5 using a PECVD process.

[0038] Please see the appendix Figure 5 , Figure 5 This is a schematic diagram of a test system structure integrating a grating coupler. Figure 5 The test system shown tests the beam waist height of the fabricated ion chip 9 containing an integrated grating coupler. As shown in the figure, the test system for the integrated grating coupler in this embodiment of the invention includes an ion chip 9 (with an integrated grating coupler on its surface), a test platform 13, a laser 8, an optical fiber 12, a beam analyzer 10, and a computer 11. The test platform 13 is connected to a displacement stage for finely adjusting the position of the ion chip 9. The laser 8 provides laser light according to the operating wavelength of the integrated grating coupler. The optical fiber 12 is used to transmit the laser light from the laser 8 to the integrated grating coupler. The beam analyzer 10 is used to collect the light intensity distribution at different reference heights. The computer 11 is used to process the light intensity distribution collected by the beam analyzer 10 and obtain the actual beam waist height of the integrated grating coupler.

[0039] Example 2

[0040] The design method steps of Embodiment 2 of the present invention are the same as those of Embodiment 1. In Embodiment 2 of the present invention, the ion chip 9 has a beam waist diameter requirement of 7.5~8.5μm, the working wavelength of the integrated grating coupler is 866nm, and the structural parameters are basically the same as those of Embodiment 1. The difference from the structural parameters of Embodiment 1 is that the grating period of the coupling grating in the embodiment of the present invention is variable, with a variation range of 0.39~0.41, a duty cycle of 0.67μm, and a grating length of 28.01μm.

[0041] Please see the appendix Figure 6 , Figure 6 This illustrates the effect of variations in grating etching depth on the optical field in Embodiment 2 of the present invention. All coordinates in the figure are in μm. Figure 6 (a) is a curve showing the change in beam waist height as a function of grating etching depth in Embodiment 2 of the present invention. The horizontal axis represents the grating etching depth, and the vertical axis represents the beam waist height. Figure 6 The waist height shown in (a) is the vertical distance between the waist focal spot and the surface of waveguide layer 6, reflecting the second correspondence between the grating etching depth and the waist height in this embodiment of the invention. As can be seen from the figure, within the range of grating etching depth variation, the waist height basically decreases with the increase of grating etching depth. Figure 6 (b) is the curve showing the change of the beam waist diameter with the grating etching depth in Embodiment 2 of the present invention. The horizontal axis represents the grating etching depth, and the vertical axis represents the beam waist diameter. Figure 6 (b) reflects the first correspondence between grating etching depth and beam waist diameter. When the grating etching depth ranges from 0.10 to 0.11 μm and from 0.16 to 0.17 μm, the beam waist diameter decreases with increasing grating etching depth; when the grating etching depth ranges from 0.11 to 0.16 μm, the beam waist diameter increases with increasing grating etching depth. Figure 6 (b) It can be seen that when the target value of the beam waist diameter is 7.5~8.5μm, the adjustment range of the grating etching depth is 0.10~0.12μm. Combined with... Figure 6 (a) It can be seen that the waist height varies from approximately 136 to 139 μm in the embodiments of the present invention. In addition, as shown in the figure, when the grating etching depth is 0.17 μm, the corresponding waist diameter is 8.5 μm, and the trapping height is as low as 119.5 μm.

[0042] Example 3

[0043] In Embodiment 3 of the present invention, the semi-etching process used in Embodiment 1 is replaced with a full etching process. The depth parameter is the thickness of the waveguide layer 6. Other conditions and structural parameters are the same as in Embodiment 1. The ion chip 9 requires a waist diameter of 4~5μm.

[0044] Please see the appendix Figure 7 , Figure 7This illustrates the effect of variations in waveguide layer thickness on the optical field in Embodiment 3 of the present invention. All coordinates in the figure are in μm. Figure 7 (a) is the curve of the waist height as a function of the waveguide layer thickness in Embodiment 3 of the present invention. The horizontal axis in the figure is the thickness of the waveguide layer 6, and the vertical axis is the waist height. Figure 7 The waist height shown in (a) is the vertical distance between the waist focal spot and the upper surface of waveguide layer 6, reflecting the second correspondence between the thickness of waveguide layer 6 and the waist height. As can be seen from the figure, the waist height increases with the increase of the thickness of waveguide layer 6. Figure 7 (b) is the curve of the waist diameter as a function of the waveguide layer thickness in Embodiment 3 of the present invention. The horizontal axis in the figure is the thickness of the waveguide layer 6, and the vertical axis is the waist diameter. Figure 7 (b) reflects the first correspondence between the thickness of waveguide layer 6 and the waist diameter. When the thickness of waveguide layer 6 is in the range of 0.12~0.15μm, the waist diameter decreases with increasing waveguide layer 6 thickness. When the thickness of waveguide layer 6 is in the range of 0.15~0.18μm, the waist diameter does not change significantly with increasing waveguide layer 6 thickness, remaining basically stable around 4.5μm. When the thickness of waveguide layer 6 is in the range of 0.18~0.22μm, the waist diameter increases with increasing waveguide layer 6 thickness. Specifically, when the thickness of waveguide layer 6 is in the range of 0.15~0.18μm, the waist diameter is basically maintained in the range of 4~5μm, which meets the requirements of the waist diameter in the embodiments of the present invention. However, when the thickness of waveguide layer 6 is less than 0.15μm or greater than 0.18μm, the waist diameter will be significantly greater than 5μm and is not suitable for performing the manipulation of trapped ions 2. According to Figure 7 (b) It can be seen that when the target value of the beam waist diameter is 4~5μm, the adjustment range of the thickness of waveguide layer 6 is 0.15~0.18μm. Figure 7 When the thickness of waveguide layer 6 is read in (a) in the range of 0.15~0.18 μm, the beam waist height varies in the range of approximately 110~124 μm, which includes the actual ion trapping height.

[0045] Example 4

[0046] In this embodiment of the invention, the semi-etching process used in Embodiment 2 is replaced with a full etching process. The depth parameter is the thickness of the waveguide layer 6, and the requirement for the waist diameter of the ion chip 9 is 7.5~8.5μm. The design method steps, other conditions, and structural parameter settings are the same as in Embodiment 2.

[0047] Please see the appendix Figure 8 , Figure 8 This illustrates the effect of variations in waveguide layer thickness on the optical field in Embodiment 4 of the present invention. All coordinates in the figure are in μm. Figure 8(a) is a curve showing the variation of the waist height with the waveguide layer thickness in Embodiment 4 of the present invention. The horizontal axis represents the thickness of the waveguide layer 6, and the vertical axis represents the waist height. Figure 8 (a) shows the waist height, which is the vertical distance between the waist and the upper surface of the waveguide layer, reflecting the second correspondence between the thickness of the waveguide layer 6 and the waist height. Within the range of variations in the thickness of the waveguide layer 6, the waist height increases with the increase of the thickness of the waveguide layer 6. Figure 8 (b) is the curve showing the change of the waist diameter as a function of the thickness of the waveguide layer 6 in Embodiment 4 of the present invention. The horizontal axis represents the thickness of the waveguide layer 6, and the vertical axis represents the waist diameter. Figure 8 (b) reflects the first correspondence between the thickness of waveguide layer 6 and the waist diameter. When the thickness of waveguide layer 6 is in the range of 0.12~0.14μm, the waist diameter increases with the increase of the thickness of waveguide layer 6. When the thickness of waveguide layer 6 is in the range of 0.14~0.15μm, the waist diameter decreases rapidly with the increase of the thickness of waveguide layer 6. When the thickness of waveguide layer 6 is in the range of 0.15~0.18μm, the waist diameter is basically stable around 8.50μm. When the thickness of waveguide layer 6 is in the range of 0.18~0.22μm, the waist diameter first increases and then decreases with the increase of the thickness of waveguide layer 6, but basically varies within the range of 8.50~9.50μm. Figure 8 (b) It can be seen that when the target value of the beam waist diameter is specifically 7.5~8.5μm, the adjustment range of the thickness of waveguide layer 6 is 0.15~0.18μm. Combined with... Figure 8 (a) It can be seen that in the embodiments of the present invention, the variation range of the waist height is approximately 114~123μm, which includes the actual ion trapping height.

[0048] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A design method for an integrated grating coupler for ion chips, wherein the integrated grating coupler includes a coupling grating for coupling and emitting incident light, such that the beam waist of the emitted light is positioned on trapped ions within the ion chip, characterized in that... The design method includes the following steps: S1: Set the trapping height of the trapped ions in the ion chip, construct and optimize the simulation model of the integrated grating coupler, make the beam waist height of the emitted light equal to the trapping height, and obtain the structural parameters; S2: Coarsely adjust the depth parameter in the structural parameters, calculate the simulation model, and obtain the first correspondence between the depth parameter and the waist diameter; S3: Select the adjustment range of the depth parameter according to the requirements of the ion chip for the waist diameter; S4: Fine-tune the depth parameter within the debugging range, calculate the simulation model, and obtain the second correspondence between the depth parameter and the waist height; S5: Based on the actual trapping height of the trapped ions, the optimal value of the depth parameter is obtained from the second correspondence to complete the design; The depth parameter is the grating etching depth.

2. The integrated grating coupler design method according to claim 1, characterized in that, The integrated grating coupler includes a substrate, a lower cladding, a waveguide layer, and an upper cladding layer arranged sequentially; the waveguide layer has grooves to form the coupling grating; the coupling grating is used to couple the incident light and emit it from the upper cladding to form a waist focal spot; the vertical distance between the waist focal spot and the surface of the coupling grating is the waist height, and the diameter of the waist focal spot is the waist diameter.

3. The integrated grating coupler design method according to claim 2, characterized in that, The structural parameters include grating period, duty cycle, grating length, depth parameter, waveguide layer thickness, upper cladding layer thickness, and lower cladding layer thickness.

4. The integrated grating coupler design method according to claim 1, characterized in that, The step S2, which involves obtaining the first correspondence between the depth parameter and the waist diameter, includes: A reference line is set in the light field of the simulation model, and the reference line extends along the grating direction of the coupled grating; The light intensity variation along the baseline is fitted to obtain the fitting function; Measure the peak value of the fitted function The width at that point is taken as the beam width; Adjust the height of the baseline, measure the beam width, and use the minimum value of the beam width as the beam waist diameter.

5. The integrated grating coupler design method according to claim 4, characterized in that, Step S4, which involves obtaining the second correspondence between the depth parameter and the beam waist height, includes: adjusting the height of the reference line and using the height of the reference line corresponding to the minimum beam width as the beam waist height.

6. The integrated grating coupler design method according to claim 4, characterized in that, The fitting function is: , Where I represents light intensity. For amplitude, These are the spatial coordinates along the direction of the baseline. The spatial coordinates of the peak position. This is the width parameter.

7. The integrated grating coupler design method according to claim 3, characterized in that, When the operating wavelength is 729 nm, the trapping height is 120 μm, the substrate material is Si, the waveguide layer material is Si3N4, and both the upper and lower cladding layers are made of SiO2, the structural parameters of the integrated grating coupler are set as follows: the duty cycle is 0.66, the grating etching depth is 0.17 μm, the grating length is 34.89 μm, the thickness of the upper cladding layer is 13 μm, the thickness of the lower cladding layer is 2.7 μm, and the thickness of the waveguide layer is 0.27 μm.

8. The integrated grating coupler design method according to claim 2, characterized in that, The step of constructing and optimizing the simulation model of the integrated grating coupler in step S1 includes iterative optimization based on performance indicators; the performance indicators include the beam waist height, diffraction efficiency, coupling efficiency, coupling strength, operating wavelength, target angle, effective refractive index of the waveguide layer, and refractive index of the upper cladding layer.

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