Silicon-based selective area epitaxy electroabsorption modulator and method of fabrication

Abstract

The application provides a silicon-based selective area epitaxy electro-absorption modulator and a preparation method, and relates to the technical field of electro-absorption modulators. The modulator comprises a patterned substrate comprising silicon and defining a groove; a buffer layer arranged in the groove by selective area epitaxy and having a top higher than the upper end of the groove; an active region layer, a cap layer and a contact layer arranged on the buffer layer in sequence; a first electrode electrically connected to the contact layer; a second electrode arranged on the side of the patterned substrate away from the buffer layer; and an insulating structure arranged on both sides of the cap layer and the contact layer. The first electrode comprises a window electrode arranged on the contact layer, a pad electrode arranged on the side of the insulating structure away from the patterned substrate, and a bridge electrode extending along the sidewall of the insulating structure and connecting the window electrode and the pad electrode. The structure is conducive to improving the integration stability of the electro-absorption modulator and the silicon-based optoelectronic platform, and reducing the parasitic influence of electrode lead-out on the active modulation region during high-speed modulation.

Description

Technical Field

[0001] This application relates to the field of electroabsorption modulator technology, and more specifically, to a silicon-based selective epitaxial electroabsorption modulator and its fabrication method. Background Technology

[0002] Silicon-based optoelectronic integrated circuits utilize silicon-based process platforms to realize optical signal transmission, modulation, and processing, and have significant application value in scenarios such as high-speed interconnects, data centers, and on-chip optical interconnects. Electro-absorption modulators can modify the absorption characteristics of the active region of a semiconductor by applying an external electric field, thereby achieving intensity modulation of the transmitted optical signal. They feature small device size, low driving power consumption, and high modulation rate. However, the electro-absorption active materials used to achieve high modulation efficiency typically involve III-V group semiconductor materials, which differ from silicon-based optoelectronic platforms in terms of lattice matching, thermal expansion, and interface continuity. If integration is achieved using bonding or other methods, problems such as interface gaps, increased thermal resistance, or discontinuous coupling interfaces may be introduced at the heterogeneous material interfaces, thus affecting optical loss, heat dissipation capacity, and long-term reliability.

[0003] On the other hand, in high-speed modulation, electroabsorption modulators not only need to form a stable and effective modulation electric field in the active region, but also need to introduce external driving signals into a small-sized active modulation region. If the spatial relationship between the electrode contact area, the external pad electrode, and the active region is not designed properly, a large electrode area or an unreasonable metal lead-out path can easily introduce parasitic capacitance, parasitic coupling, or additional optical losses near the active modulation region, thereby limiting the modulation bandwidth and modulation efficiency.

[0004] Therefore, improving the integration stability of silicon-based electroabsorption modulators and silicon-based optoelectronic platforms, and taking into account the parasitic effects caused by the loading of the modulation electric field in the active region and the extraction of electrodes during high-speed modulation, has become a technical problem that needs to be further solved. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this application provides a silicon-based selective epitaxial electroabsorption modulator and its fabrication method.

[0006] In a first aspect, this application discloses a silicon-based selective epitaxial electroabsorption modulator, comprising: A patterned substrate, including silicon and defined by trenches; A buffer layer is epitaxially disposed within the trench, with its top end higher than the top end of the trench, and its lattice orientation is consistent with that of the patterned substrate; an active region layer is epitaxially disposed on the buffer layer and its lattice orientation is consistent with that of the buffer layer, configured to modulate the passing optical signal under an applied electric field; a capping layer is epitaxially disposed on the active region layer and its lattice orientation is consistent with that of the active region layer; and a contact layer is epitaxially disposed on the capping layer and its lattice orientation is consistent with that of the capping layer. A first electrode is electrically connected to the contact layer; a second electrode is disposed on the side of the patterned substrate opposite to the buffer layer and cooperates with the first electrode to apply a modulated electric field to the active region layer; and An insulating structure is disposed on both sides of the cover layer and the contact layer; The first electrode includes a window electrode disposed on the contact layer, a pad electrode disposed on the side of the insulating structure away from the patterned substrate, and a bridge electrode extending along the sidewall of the insulating structure and electrically connecting the window electrode to the pad electrode.

[0007] Optionally, the insulating structure includes a first insulating layer disposed on both sides of the cover layer and the contact layer, a second insulating layer disposed on the first insulating layer, and a passivation layer disposed on the second insulating layer; The top of the first insulating layer is flush with the top of the contact layer, the second insulating layer does not cover the top of the contact layer, the pad electrode is disposed on the passivation layer, and the bridge electrode extends along the sidewall of the second insulating layer.

[0008] Optionally, the relative permittivity of at least one of the first insulating layer, the second insulating layer, and the passivation layer is less than half the relative permittivity of at least one of the active region layer, the capping layer, and the contact layer.

[0009] Optionally, at least one of the first insulating layer and the second insulating layer comprises benzocyclobutene or polyimide.

[0010] Optionally, the buffer layer includes a lower buffer layer disposed in the trench, a middle buffer layer disposed on the lower buffer layer, and an upper buffer layer disposed on the middle buffer layer; The lower buffer layer comprises gallium arsenide, the middle buffer layer comprises at least one of indium gallium arsenide phosphide and indium phosphide, and the upper buffer layer comprises indium phosphide.

[0011] Optionally, the lattice mismatch between the middle buffer layer and the lower buffer layer, and the lattice mismatch between the upper buffer layer and the middle buffer layer, are both no higher than 4%.

[0012] Optionally, the active region layer includes at least one of indium gallium arsenide phosphide and indium gallium aluminum arsenide, the capping layer includes indium phosphide, and the contact layer includes indium gallium arsenide.

[0013] Secondly, this application discloses a method for fabricating a silicon-based selective region epitaxial electroabsorption modulator, characterized by comprising: Provides a patterned substrate comprising silicon and defined trenches; A buffer layer, including an upper buffer layer, is formed within the trench by selective extension. During the formation of the upper buffer layer, when the current growth surface of the upper buffer layer is within a predetermined height window with the upper end of the trench as a reference, transition compensation growth is performed to form a transition compensation layer segment in the upper buffer layer that spans the upper end of the trench. The transition compensation growth includes supplying a group III source in a pulsed manner under the condition of continuous supply of group V source, and the group III source supply duty cycle within the predetermined height window is lower than the group III source supply duty cycle in the upper buffer layer growth stage before and after the transition compensation growth. Continue forming the upper buffer layer, such that the top of the upper buffer layer is higher than the upper end of the trench; and An active region layer is formed on the upper buffer layer by selective region extension.

[0014] Optionally, the predetermined height window includes a clamping release sub-window located below the upper end of the groove and a free expansion sub-window located above the upper end of the groove; Within the clamping release sub-window, the transition compensation growth is performed according to the first group III source supply duty cycle; Within the free-expanding sub-window, the transition compensation growth is performed according to the second group III source supply duty cycle; The duty cycle of the second group III source supply is less than that of the first group III source supply.

[0015] Optionally, before forming the active region layer, the preparation method further includes: Interrupt the Group III source supply and maintain the Group V source supply to perform a hold process on the top of the upper buffer layer; After the holding process, the Group III source supply is restored to form the active region layer on top of the upper buffer layer.

[0016] Compared with existing technologies, this application achieves a stable bond between the epitaxial structure of the electroabsorption modulator and the silicon substrate by selectively epitaxially forming a continuous buffer layer, active region layer, capping layer, and contact layer in a silicon-based trench. This reduces interface defects and thermal resistance, improving the integration stability of the device. Simultaneously, a modulation electric field is formed between the contact layer and the back side of the substrate, enabling effective light absorption modulation of the active region. Furthermore, an insulating structure supports the epitaxial mesa, and electrical connections are achieved through window electrodes, pad electrodes, and bridge electrodes extending along the sidewalls. This keeps the external electrodes away from the active modulation region, ensuring the modulation electric field is applied while reducing parasitic effects, thereby improving the high-speed modulation performance of the device. Attached Figure Description

[0017] Figure 1 A schematic diagram of a silicon-based selective epitaxial electroabsorption modulator structure provided in an embodiment of this application; Figure 2 An embodiment provided in this application Figure 1 Schematic diagram of the lower buffer layer, middle buffer layer, upper buffer layer, active area layer, capping layer, and contact layer; Figure 3 An S21 curve of the small-signal response of a silicon-based selective epitaxial electroabsorption modulator provided in an embodiment of this application; Figure 4 The S11 curve of the small-signal response of a silicon-based selective epitaxial electroabsorption modulator provided in the embodiments of this application.

[0018] Reference numerals: 1. Patterned substrate; 2. Buffer layer; 3. Lower buffer layer; 4. Middle buffer layer; 5. Upper buffer layer; 6. Active region layer; 7. Cap layer; 8. Contact layer; 9. First insulating layer; 10. Second insulating layer; 11. Window electrode; 12. Passivation layer; 13. Pad electrode; 14. Bridge electrode. Detailed Implementation

[0019] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0020] In some embodiments, such as Figure 1 and Figure 2 As shown, the silicon-based selective epitaxial electroabsorption modulator may include a patterned substrate 1, a buffer layer 2, an active region layer 6, a capping layer 7, a contact layer 8, a first electrode, a second electrode, and an insulating structure. The first electrode may include a window electrode 11, a pad electrode 13, and a bridge electrode 14. Figure 1The first insulating layer 9, the second insulating layer 10, and the passivation layer 12 shown can together serve as one implementation of an insulating structure. The second electrode can be disposed on the side of the patterned substrate 1 opposite to the buffer layer 2.

[0021] The patterned substrate 1 comprises silicon. The silicon can be a single-crystal silicon substrate, a silicon layer in a silicon-on-insulator substrate, or other silicon-containing substrate suitable for use in silicon-based optoelectronic integrated circuits. The patterned substrate 1 defines trenches, which are formed by photolithography and etching processes. In this document, "the upper end of the trench" can be understood as the height position corresponding to the trench opening, or the height position corresponding to the area where the trench sidewall intersects with the upper surface of the patterned substrate 1. The trenches define the growth area for subsequent selective epitaxy, allowing III-V group epitaxial materials to be formed within the predetermined area, thereby facilitating positional matching with other optical or electrical structures in the silicon-based optoelectronic integrated circuit.

[0022] Buffer layer 2 is disposed within the trench via selective epitaxy. In some embodiments, a dielectric mask with openings can be formed on a patterned substrate 1 to expose the trench region, and buffer layer 2 can be grown within the trench using metal-organic chemical vapor deposition, molecular beam epitaxy, or other epitaxial processes suitable for III-V group semiconductor materials. The top of buffer layer 2 is higher than the top of the trench, meaning that buffer layer 2 does not only fill the interior of the trench but extends upwards at least partially beyond the trench opening. Thus, buffer layer 2 can provide a support base above the trench for continued epitaxial growth of the active region layer 6. During the trench-confined selective epitaxy process, the trench sidewalls can block or terminate the propagation of defects caused by lattice mismatch; simultaneously, multi-level buffer layers can provide a step-by-step transition between adjacent materials to reduce the risk of defects directly extending to the active region layer 6. The term "consistent lattice orientation" as used herein is primarily used to describe the epitaxial inheritance relationship between epitaxial layers and does not exclude the presence of a small number of dislocations, stacking faults, or other crystal defects in the epitaxial layers.

[0023] In this paper, "consistent lattice orientation" does not require the absence of any lattice defects between adjacent layers. Rather, it refers to the epitaxial inheritance relationship maintained between adjacent crystal layers formed through epitaxial growth in their principal crystal orientation or principal crystal plane orientation. For example, the consistent lattice orientation of buffer layer 2 with that of patterned substrate 1 indicates that buffer layer 2 is epitaxially grown based on the crystal orientation provided by patterned substrate 1, ensuring that the principal crystal orientation of buffer layer 2 is consistent with or substantially consistent with the corresponding crystal orientation of patterned substrate 1. This approach can reduce the impact of discontinuities at heterogeneous material interfaces on device stability in bonded integration methods.

[0024] The active region layer 6 is epitaxially disposed on the buffer layer 2 and has the same lattice orientation as the buffer layer 2. The active region layer 6 is used to modulate the passing optical signal under the action of an applied electric field. Specifically, when a modulation voltage is applied between the first electrode and the second electrode, a modulation electric field is formed in the active region layer 6. This modulation electric field can change the absorption characteristics of the active region layer 6 for a predetermined wavelength optical signal, thereby achieving modulation of the optical signal intensity. The capping layer 7 is epitaxially disposed on the active region layer 6 and has the same lattice orientation as the active region layer 6; the contact layer 8 is epitaxially disposed on the capping layer 7 and has the same lattice orientation as the capping layer 7. The capping layer 7 can be used to form a transition or constraint between the active region layer 6 and the contact layer 8, and the contact layer 8 can be used to form an electrical connection with the first electrode.

[0025] In some embodiments, the silicon-based selective epitaxial electroabsorption modulator can be a waveguide-type electroabsorption modulator. The optical signal propagates along the longitudinal direction of the modulator and passes through the absorptive waveguide region including the active region layer 6. The active region layer 6 can be part of the absorptive waveguide core layer or the absorptive waveguide region, and the buffer layer 2, capping layer 7, and surrounding dielectric structure can collectively define the optical field distribution with the active region layer 6. The term "window" in the window electrode 11 refers to the electrode contact window that forms a local electrical contact with the contact layer 8, rather than limiting the optical signal to be incident from the normal direction of the window electrode 11. The optical signal can be input from one end face of the modulator or the silicon-based waveguide coupled thereto and propagates along the extension direction of the active region layer 6, undergoing absorption modulation under the action of an applied modulation electric field during propagation.

[0026] For example, the longitudinal modulation length of the modulator can be from 10 micrometers to 1 millimeter, and the transverse waveguide width can be from 50 nanometers to 5 micrometers. At least one optical end face can be provided with an anti-reflection coating to reduce the impact of end face reflection on the modulation output.

[0027] The first electrode is electrically connected to the contact layer 8. A second electrode is disposed on the side of the patterned substrate 1 opposite to the buffer layer 2 and cooperates with the first electrode to apply a modulated electric field to the active region layer 6. In some embodiments, the second electrode may be a metal electrode formed on the back side of the patterned substrate 1, or it may be an N-type electrode layer electrically connected to a conductive region on the back side of the patterned substrate 1. The voltage applied between the first and second electrodes can cause the active region layer 6 to be in a reverse biased or other electric field state suitable for generating electro-absorption modulation.

[0028] An insulating structure is disposed on both sides of the cover layer 7 and the contact layer 8. The insulating structure can consist of one or more layers of insulating material, used to electrically isolate the sides of the cover layer 7 and the contact layer 8, and to provide structural support for the lead-out of the first electrode. The material of the insulating structure can be a dielectric material suitable for semiconductor optoelectronic device processes, such as organic low-dielectric-constant materials, inorganic dielectric materials, or a combination of both. The specific number of layers, thickness, and material of the insulating structure can be set according to the electrode lead-out location, process compatibility, and parasitic capacitance control requirements.

[0029] The first electrode includes a window electrode 11, a pad electrode 13, and a bridge electrode 14. The window electrode 11 is disposed on the contact layer 8 to form a local electrical contact with the contact layer 8. The pad electrode 13 is disposed on the side of the insulating structure away from the patterned substrate 1 and is used to connect to an external driving circuit, probe, electrical connection terminal, or subsequent interconnect structure. The bridge electrode 14 extends along the sidewall of the insulating structure and electrically connects the window electrode 11 to the pad electrode 13. Through this structure, the window electrode 11 can be held near the contact layer 8 to achieve modulation electric field loading, while the pad electrode 13 can be arranged at a position relatively far from the active region layer 6, and the two are electrically connected through the bridge electrode 14.

[0030] In the above structure, the buffer layer 2, active region layer 6, capping layer 7, and contact layer 8 are selectively epitaxially formed on the trenches and above the patterned substrate 1, enabling the main epitaxial layer of the electroabsorption modulator to form a stable bond with the silicon-based platform. The first electrode and the second electrode jointly apply a modulation electric field to the active region layer 6, enabling this epitaxial layer to function as an electroabsorption modulation structure. The insulating structure, in conjunction with the window electrode 11, pad electrode 13, and bridge electrode 14, separates the external electrode lead-out area from the local contact area near the active modulation area, thereby reducing the parasitic effects caused by the large-area external electrode being directly arranged near the active region layer 6 while ensuring the modulation electric field is applied.

[0031] In some embodiments, the contact layer 8 can be a p-type heavily doped indium gallium arsenide contact layer, the capping layer 7 can be a p-type or lightly p-type indium phosphide capping layer, the active region layer 6 can be an intrinsic or lightly doped absorption layer, and at least a portion of the upper buffer layer 5, the middle buffer layer 4, the lower buffer layer 3, and the patterned substrate 1 can be n-type or conductive regions electrically connected to the second electrode. The window electrode 11 forms a p-side electrical connection with the contact layer 8, and the second electrode forms an n-side electrical connection with the side of the patterned substrate 1 opposite to the buffer layer 2. When the first electrode is reverse biased relative to the second electrode, the active region layer 6 is located between the p-side conductive region and the n-side conductive region, so that the modulation electric field is mainly formed in the active region layer 6 and its adjacent depletion region, thereby changing the absorption characteristics of the active region layer 6 for the transmitted optical signal.

[0032] Optionally, where the contact layer 8 needs to form a local electrical connection and the pad electrode 13 needs to be properly isolated from the active modulation region, a layered insulation structure can be used to define the electrode contact area and electrode lead-out path to reduce the parasitic effects of the electrode lead-out structure during high-speed modulation. In some embodiments, such as Figure 1 As shown, the insulating structure may include a first insulating layer 9, a second insulating layer 10, and a passivation layer 12.

[0033] A first insulating layer 9 is disposed on both sides of the capping layer 7 and the contact layer 8. The first insulating layer 9 can fill or cover the lateral areas on both sides of the capping layer 7 and the contact layer 8, and make the top of the first insulating layer 9 flush with the top of the contact layer 8. In this document, "top flush" can be understood as the top of the first insulating layer 9 being at the same height or substantially at the same height as the top of the contact layer 8; in actual processes, due to process tolerances in deposition, coating, curing, etching, or planarization, a slight height difference that does not affect the electrical connection between the window electrode 11 and the contact layer 8 is allowed. With this arrangement, the first insulating layer 9 can provide planarization support on both sides of the contact layer 8, while leaving the top of the contact layer 8 as the contact area for forming the window electrode 11.

[0034] The second insulating layer 10 is disposed on the first insulating layer 9, and the second insulating layer 10 does not cover the top of the contact layer 8. In this document, "does not cover the top of the contact layer" means that the second insulating layer 10 at least avoids the top region of the contact layer 8 used to form the window electrode 11, without requiring that there be no lateral adjacency or partial edge contact between the second insulating layer 10 and the contact layer 8. The second insulating layer 10 may form a sidewall region on the side of the contact layer 8 to support the bridge electrode 14, allowing the bridge electrode 14 to extend along the sidewall of the second insulating layer 10 from the window electrode 11 to the pad electrode 13.

[0035] A passivation layer 12 is disposed on the second insulating layer 10. The passivation layer 12 can be used to cover at least a portion of the surface of the second insulating layer 10 and provide a bearing area for the pad electrode 13. In some embodiments, the pad electrode 13 is disposed on the passivation layer 12, the window electrode 11 is disposed on the contact layer 8, and the bridge electrode 14 extends along the sidewall of the second insulating layer 10 and electrically connects the window electrode 11 and the pad electrode 13. Thus, the window electrode 11 can be used to form a partial contact with the contact layer 8, the pad electrode 13 can be used to connect to an external drive circuit or interconnect structure, and the bridge electrode 14 is used to form an electrical connection path between the two. This electrode lead-out method is beneficial for keeping the pad electrode 13 away from the active modulation region near the contact layer 8, and for providing support to the bridge electrode 14 through the sidewall of the second insulating layer 10, thereby reducing the influence of the pad electrode 13 and the bridge electrode 14 on the electric field distribution and parasitic capacitance near the active modulation region.

[0036] In some embodiments, at least one of the first insulating layer 9, the second insulating layer 10, and the passivation layer 12 may be made of a material whose relative permittivity is less than half that of at least one of the active region layer 6, the capping layer 7, and the contact layer 8. Here, "relative permittivity less than half that of at least one of the active region layer 6, the capping layer 7, and the contact layer 8" can be used to compare the dielectric constants of materials under the same test frequency or the same process design conditions.

[0037] For example, in one embodiment, the first insulating layer 9 and the second insulating layer 10 can be made of organic dielectric materials with low relative permittivity, and the passivation layer 12 can be made of silicon oxide, silicon nitride, or other dielectric materials suitable for passivation of semiconductor devices. By using materials with low relative permittivity for at least part of the insulating structure, the parasitic capacitive coupling around the window electrode 11, bridge electrode 14, and pad electrode 13 can be reduced, which is beneficial to improving the electrode lead-out performance under high-speed modulation.

[0038] For example, the first insulating layer 9 and the second insulating layer 10 may be made of benzocyclobutene or polyimide, whose relative permittivity may be less than half of the relative permittivity of the active region layer 6; or, the passivation layer 12 and the second insulating layer 10 below the pad electrode 13 may be made of a low-dielectric-constant dielectric to reduce the parasitic capacitive coupling between the pad electrode 13 and the semiconductor epitaxial mesa.

[0039] In some embodiments, at least one of the first insulating layer 9 and the second insulating layer 10 comprises benzocyclobutene or polyimide. Both benzocyclobutene and polyimide can serve as organic insulating materials suitable for use in semiconductor optoelectronic devices, forming dielectric structures with electrical isolation and planarization functions. In specific fabrication, the first insulating layer 9 and the second insulating layer 10 can be formed by spin coating, exposure and development, thermal curing, etching, or other suitable patterning processes. Taking polyimide as an example, polyimide material can be first coated onto the lateral region of the epitaxial mesa, and after patterning and curing, the first insulating layer 9 can be formed; then, the second insulating layer 10 can be formed on the first insulating layer 9, with the second insulating layer 10 avoiding the window electrode formation region at the top of the contact layer 8. Taking benzocyclobutene as an example, it can also be coated and cured to form a low-dielectric-constant insulating layer to support the bridge electrode 14 and reduce the parasitic effects of the electrode lead-out structure.

[0040] It should be noted that the specific materials, thicknesses, and fabrication processes of the first insulating layer 9, the second insulating layer 10, and the passivation layer 12 can be set according to the device's operating wavelength, modulation rate, metal electrode structure, and process compatibility. The above embodiments are only used to illustrate the cooperation relationship between the insulating structure and the window electrode 11, the pad electrode 13, and the bridge electrode 14, and do not limit the insulating structure to using only specific materials or specific thicknesses.

[0041] Optionally, when forming a III-V group electroabsorption epitaxial layer on a patterned substrate 1 including silicon, lattice abrupt changes between adjacent materials can be reduced through multi-level buffering, so that the active region layer 6 can be formed on a relatively stable epitaxial support layer.

[0042] In some embodiments, such as Figure 2 As shown, buffer layer 2 may include lower buffer layer 3, middle buffer layer 4 and upper buffer layer 5.

[0043] The lower buffer layer 3 is disposed within the trench defined by the patterned substrate 1. The lower buffer layer 3 may include gallium arsenide. In one implementable example, the patterned substrate 1 may be a silicon substrate or a silicon layer in a silicon-based optoelectronic integrated circuit. The trench is first formed by etching, and then the lower buffer layer 3 is formed by selective epitaxy in the exposed area of ​​the trench. The lower buffer layer 3 can serve as an initial epitaxial layer for transitioning from a silicon material system to a III-V group material system, providing an epitaxial basis for the subsequent intermediate buffer layer 4.

[0044] A middle buffer layer 4 is disposed on the lower buffer layer 3. The middle buffer layer 4 may include at least one of indium gallium arsenide phosphide and indium phosphide. In one embodiment, the middle buffer layer 4 may be an indium gallium arsenide phosphide layer; in another embodiment, the middle buffer layer 4 may include an indium gallium arsenide phosphide sublayer and an indium phosphide sublayer. The middle buffer layer 4 can be used to form a material transition between the lower buffer layer 3 and the upper buffer layer 5, enabling the upper buffer layer 5 to continue epitaxial growth under conditions of small lattice abrupt changes.

[0045] An upper buffer layer 5 is disposed on the middle buffer layer 4. The upper buffer layer 5 may include indium phosphide. The top of the upper buffer layer 5 may be higher than the upper end of the trench, so that the buffer layer 2 not only fills the interior of the trench, but also extends at least partially above the trench. Thus, the upper buffer layer 5 can provide an epitaxial bearing surface for the subsequent active region layer 6, allowing the active region layer 6, the capping layer 7, and the contact layer 8 to be continuously formed on the buffer layer 2.

[0046] In one specific embodiment, the patterned substrate 1 is a silicon substrate, the lower buffer layer 3 is a gallium arsenide layer, the middle buffer layer 4 includes an indium gallium arsenide phosphide layer and / or an indium phosphide transition layer, and the upper buffer layer 5 is an indium phosphide layer. An active region layer 6 is formed on the upper buffer layer 5, a capping layer 7 is formed on the active region layer 6, and a contact layer 8 is formed on the capping layer 7. These layers can be formed using metal-organic chemical vapor deposition, molecular beam epitaxy, or other selective epitaxy processes suitable for III-V group semiconductor materials. During epitaxy, the composition and thickness of each layer can be adjusted by controlling process conditions such as the supply of III and V group sources, epitaxy temperature, reaction chamber pressure, and growth time. These process conditions can be set according to the target operating wavelength, target modulation efficiency, and epitaxy equipment type.

[0047] In some embodiments, the upper buffer layer 5 may include a transition compensation segment that spans the upper end of the trench. This transition compensation segment may be formed when the current growth surface of the upper buffer layer 5 approaches and crosses the upper end of the trench, in order to provide a relatively flat epitaxial base surface for the subsequent active region layer 6.

[0048] In some embodiments, the lattice mismatch between the middle buffer layer 4 and the lower buffer layer 3, and the lattice mismatch between the upper buffer layer 5 and the middle buffer layer 4, are both no higher than 4%. In this text, the lattice mismatch can be determined as the ratio of the absolute value of the difference in lattice constants between two adjacent layers in the room-temperature relaxation state along the in-plane direction of the epitaxial interface to the lattice constant of the lower layer. For alloy materials, their lattice constants can be determined based on the equivalent lattice constants corresponding to the target composition; for example, they can be determined by linear interpolation of the lattice constants of the component materials based on the composition ratio. By keeping the lattice mismatch between adjacent layers at a low level, the defect density and interface discontinuity risk caused by lattice abrupt changes between adjacent epitaxial layers can be reduced, thereby improving the epitaxial quality of the subsequent active region layer 6.

[0049] In some embodiments, the active layer 6 comprises at least one of indium gallium arsenide phosphide (IGaAs) and indium gallium aluminum arsenide (IAA). The active layer 6 may be a bulk absorption layer, a multi-quantum-well absorption layer, or other semiconductor absorption structures capable of altering light absorption characteristics under an applied electric field. In one example, the active layer 6 may be formed using IGaAs, with its absorption edge corresponding to the operating wavelength band for transmitting optical signals in a silicon-based optoelectronic integrated circuit. In another example, the active layer 6 may be formed using IGaAs to meet design requirements for different operating wavelengths, absorption coefficients, or modulation rates.

[0050] The capping layer 7 may include indium phosphide. The capping layer 7 is disposed on the active region layer 6 and can be used to cover and transition the active region layer 6, and provide an epitaxial basis for the formation of the contact layer 8. In some embodiments, the capping layer 7 may also serve as an isolation or constraint layer between the active region layer 6 and the contact layer 8 to reduce the direct impact of the contact layer 8 on the light absorption region of the active region layer 6.

[0051] Contact layer 8 may include indium gallium arsenide (IGaAs). Contact layer 8 is disposed on capping layer 7 and serves to form an electrical connection with window electrode 11. IGaAs material can be used as a contact layer material suitable for III-V group semiconductor devices, which is beneficial for reducing the contact resistance between window electrode 11 and contact layer 8. In this embodiment, the first electrode is electrically connected to contact layer 8 through window electrode 11, and the second electrode is disposed on the side of patterned substrate 1 facing away from buffer layer 2. The two electrodes cooperate to apply a modulation electric field to active region layer 6, enabling active region layer 6 to electrically absorb and modulate the passing optical signal.

[0052] It should be noted that the above material combination is only one feasible example. The specific materials, composition ratios and thicknesses of the lower buffer layer 3, middle buffer layer 4, upper buffer layer 5, active region layer 6, capping layer 7 and contact layer 8 can be adjusted according to the crystal orientation, trench size, target operating wavelength and modulator performance requirements of the patterned substrate 1, as long as a buffer layer suitable for epitaxial growth and electro-absorption modulation of the active region layer 6 can be formed on the patterned substrate 1.

[0053] In some embodiments, the high-speed modulation performance of the silicon-based selective epitaxial electroabsorption modulator described above can be characterized by small-signal response testing or simulation. Figure 3 The diagram schematically illustrates the S21 curve of the small-signal response of a silicon-based selective epitaxial electroabsorption modulator provided in an embodiment of this application. S21 can be used to characterize the modulator's transmission response or electro-optic modulation response at different radio frequency frequencies. For example, as shown... Figure 3 As shown, in one embodiment, the -3dB bandwidth of the small-signal response can reach approximately 120 GHz, indicating that the electroabsorption modulator can maintain an effective modulation response over a higher frequency range. This result corresponds to the aforementioned window electrode 11, pad electrode 13, bridge electrode 14, and low-parasitic electrode lead-out structure, illustrating that this structure has good bandwidth potential in high-speed modulation scenarios.

[0054] Figure 4 The diagram schematically illustrates the S11 curve of the small-signal response of a silicon-based selective epitaxial electroabsorption modulator provided in an embodiment of this application. S11 can be used to characterize the reflection or impedance matching at the modulator's RF input. For example, as shown... Figure 4 As shown, in one embodiment, the S11 curve can be below -20dB near 30GHz, below -10dB at 60GHz, and below -4dB at 120GHz. These results indicate that within the corresponding frequency range, the modulator's RF input can maintain a certain impedance matching capability, thereby helping to reduce the impact of RF signal reflection on the high-speed modulation response.

[0055] As the active layer 6 material, the longitudinal modulation length of the modulator, the size of the window electrode 11, the size of the bridge electrode 14, the layout of the pad electrode 13, the insulating structure material, and the external test port conditions change, the specific values ​​of the S21 curve and the S11 curve can change accordingly.

[0056] In some embodiments, this application also provides a method for fabricating a silicon-based selected region epitaxial electroabsorption modulator. A further problem addressed by this method is: when the buffer layer 2 needs to continue growing from the inside of the trench to above the top of the trench, and an active region layer 6 is to be formed above it, how to reduce the impact of abrupt changes in the growth front near the top of the trench on the subsequent epitaxial basal surface of the active region layer 6 during the transition of the growth environment from a confined state within the trench walls to an open state above the trench.

[0057] Specifically, a patterned substrate 1 comprising silicon and defining trenches can be provided first. The patterned substrate 1 can be a silicon substrate, a silicon layer in a silicon-on-insulator substrate, or other silicon-containing substrate. The trenches can be formed by photolithography and etching, and their positions are used to define the growth area for subsequent selected epitaxy. For example, the width of the trench can be from 0.2 micrometers to 5 micrometers, and the depth can be from 0.2 micrometers to 3 micrometers; in a specific example, the trench width is 1 micrometer and the depth is 1 micrometer.

[0058] Subsequently, a buffer layer 2, including the upper buffer layer 5, is formed within the trench via selective epitaxy. Selective epitaxy can be achieved using a metal-organic chemical vapor deposition (MOCVD) apparatus. For example, when forming the indium phosphide upper buffer layer 5, a Group III source may include trimethylindium, and a Group V source may include phosphine or tert-butylphosphine; when forming a layer containing gallium or arsenic, a Group III source may also include trimethylgallium or triethylgallium, and a Group V source may also include arsine. The above source materials are merely examples; specific source materials can be selected based on the equipment type, target material system, and safety process specifications.

[0059] During the formation of the upper buffer layer 5, transition compensation growth is performed when the current growth surface of the upper buffer layer 5 is located within a predetermined height window based on the upper end of the trench. In this text, the "current growth surface" can be understood as the uppermost epitaxial growth surface of the upper buffer layer 5 during the epitaxial process; the "predetermined height window based on the upper end of the trench" can be understood as a process control range set around the trench opening height. For example, this predetermined height window can be a height range from 50 nm below the upper end of the trench to 100 nm above the upper end of the trench, or it can be a height range from 100 nm below the upper end of the trench to 200 nm above the upper end of the trench. The specific range of this predetermined height window can be determined based on the trench depth, trench width, epitaxial rate, and target upper buffer layer thickness.

[0060] Transition compensation growth performed within a predetermined height window is used to form a transition compensation segment in the upper buffer layer 5 that spans the upper end of the trench. This transition compensation segment is part of the upper buffer layer 5 and its location spans the growth transition region near the upper end of the trench. Because epitaxial growth inside the trench is confined by the trench sidewalls, while the lateral constraint on epitaxial growth above the trench is weakened, local changes in growth rate, facet morphology, or surface smoothness may occur when the current growth surface passes the upper end of the trench. By setting a transition compensation segment within this height window, the upper buffer layer 5 can provide a more stable epitaxial support foundation for the subsequent active region layer 6 after crossing the upper end of the trench.

[0061] In some embodiments, transition-compensation growth includes supplying a group III source in a pulsed manner while continuously supplying a group V source. Here, "continuously supplying a group V source" can be understood as maintaining a continuous or substantially continuous supply of the group V precursor during transition-compensation growth to preserve the group V environment on the epitaxial surface; "supplying a group III source in a pulsed manner" can be understood as alternating between a supply state and an interrupted state of the group III source during transition-compensation growth. In this way, the duty cycle of the group III source supply within a predetermined height window can be reduced while maintaining protection of the group V source.

[0062] In this paper, "Group III source supply duty cycle" can be understood as the ratio between the duration of Group III source supply in a supply cycle and the total duration of that supply cycle. In some embodiments, the upper buffer layer growth stages before and after transition compensation growth can be performed by continuously supplying Group III sources or supplying Group III sources with a higher duty cycle; while within a predetermined height window, a pulsed supply mode with a lower Group III source supply duty cycle can be used. Thus, the Group III source supply duty cycle within the predetermined height window is lower than the Group III source supply duty cycle in the upper buffer layer growth stages before and after transition compensation growth.

[0063] For example, the trench width is 1 micrometer and the depth is 1 micrometer. An indium phosphide upper buffer layer 5 is formed using a metal-organic chemical vapor deposition (MOCVD) apparatus. When the current growth surface is approximately 50 nanometers below the top of the trench, epitaxial growth is performed according to the normal upper buffer layer growth stage. When the current growth surface enters a predetermined height window (50 nanometers below to 100 nanometers above the top of the trench), transition compensation growth begins. In this transition compensation growth, a group V source is continuously supplied, and a group III source is pulsed according to a supply cycle. For example, a supply cycle is 4 seconds, with a group III source supply for 1 second and a group III source interruption for 3 seconds, resulting in a group III source supply duty cycle of 25%. During the upper buffer layer growth stage before and after the predetermined height window, the group III source can be continuously supplied or supplied at a duty cycle higher than 25%. This supply method reduces the net deposition rate within the trench opening height window, allowing the current growth surface more sufficient time for surface migration and morphology adjustment as it passes the top of the trench.

[0064] For example, a supply cycle is 5 seconds, with a 2-second supply of Group III source and a 3-second interruption of Group III source, resulting in a 40% duty cycle for the Group III source supply. During the upper buffer layer growth stages before and after the predetermined height window, the Group III source supply duty cycle can be 80% to 100%. This embodiment can be used in scenarios with large trench widths or low epitaxial rates. It should be noted that the above supply cycle, supply duration, and interruption duration are example values. Other supply cycles and duty cycles can be used under different reaction chamber volumes, gas switching response times, target epitaxial rates, and trench sizes, as long as the Group III source supply duty cycle within the predetermined height window is lower than the Group III source supply duty cycle during the upper buffer layer growth stages before and after transition compensation growth.

[0065] After the transition compensation growth is completed, the upper buffer layer 5 can be formed, with its top higher than the top of the trench. At this point, the upper buffer layer 5 can form an upper region above the trench for further epitaxy. Subsequently, the active region layer 6 is formed on the upper buffer layer 5 through selective epitaxy. The active region layer 6 can be a semiconductor absorption layer capable of changing its light absorption characteristics under an applied electric field, such as a bulk material absorption layer or a multi-quantum-well absorption layer. Since the transition compensation layer is located in the region where the upper buffer layer 5 crosses the top of the trench, the subsequently formed active region layer 6 can be built on the transition-compensated upper buffer layer 5, thereby reducing the impact of the trench opening transition region on the uniformity of the lower interface of the active region layer 6.

[0066] In some embodiments, the predetermined height window can be further divided into a clamping release sub-window and a free expansion sub-window. A further problem addressed by this embodiment is that the lateral growth constraints of the current growth surface of the upper buffer layer 5 are different below and above the top of the trench. If the same Group III source supply duty cycle is used throughout the predetermined height window, it may be difficult to simultaneously achieve both the epitaxial continuity of the trench inner wall confinement stage and the surface planarization of the free expansion stage above the trench.

[0067] Specifically, the clamping-release sub-window is located below the upper end of the trench, corresponding to the height range where the current growth surface is close to the upper end of the trench but is still at least partially affected by the lateral confinement of the trench sidewalls. The free-spreading sub-window is located above the upper end of the trench, corresponding to the height range where the lateral constraint weakens after the current growth surface crosses the upper end of the trench, and the epitaxial material begins to spread freely upwards towards the trench. Within the clamping-release sub-window, transition-compensated growth can be performed according to the first group III source supply duty cycle; within the free-spreading sub-window, transition-compensated growth can be performed according to the second group III source supply duty cycle, where the second group III source supply duty cycle is less than the first group III source supply duty cycle. Thus, when the current growth surface enters the free-spreading stage above the trench, the net supply ratio of group III sources can be further reduced, prolonging the surface migration and rearrangement time to suppress local growth abrupt changes above the trench opening.

[0068] For example, the trench depth is 1 micrometer, and the predetermined height window is from 50 nanometers below the top of the trench to 100 nanometers above the top of the trench. The clamping-release sub-window extends from 50 nanometers below the top of the trench to the top of the trench, and the free-spreading sub-window extends from the top of the trench to 100 nanometers above the top of the trench. Within the clamping-release sub-window, the supply cycle can be 5 seconds, with a Group III source supply for 2 seconds and a Group III source interruption for 3 seconds, corresponding to a first Group III source supply duty cycle of 40%. Within the free-spreading sub-window, the supply cycle can be 5 seconds, with a Group III source supply for 1 second and a Group III source interruption for 4 seconds, corresponding to a second Group III source supply duty cycle of 20%. Within both sub-windows, the Group V source maintains continuous or substantially continuous supply. This segmented supply method allows the upper buffer layer 5 to maintain epitaxial continuity as it approaches the top of the trench, and further reduces the net deposition rate after crossing the top of the trench, thereby minimizing abrupt changes in surface morphology during the free-spreading stage.

[0069] For example, the clamping-release sub-window can be set from 80 nm below the top of the trench to the top of the trench, and the free-expansion sub-window can be set from the top of the trench to 150 nm above the top of the trench. The duty cycle of the first group III source supply within the clamping-release sub-window can be 50%, and the duty cycle of the second group III source supply within the free-expansion sub-window can be 25% to 35%. This embodiment is applicable to situations where the trench is deep, the lateral widening near the trench opening is significant, or the epitaxial growth rate is high during the normal growth stage. It should be noted that the duty cycle of the first group III source supply and the duty cycle of the second group III source supply are not limited to the specific values ​​mentioned above, as long as the duty cycle of the second group III source supply is less than the duty cycle of the first group III source supply, and both can meet the requirements of transition compensation growth for continuous growth and surface morphology adjustment of the upper buffer layer 5.

[0070] In some embodiments, the preparation method may further include performing a retention treatment on the top of the upper buffer layer 5 before forming the active region layer 6. This embodiment further addresses the issue that even if the upper buffer layer 5 has already grown across the upper end of the trench through transition compensation, its top surface may still exhibit uneven distribution of adsorbed species, insufficient surface rearrangement, or residual effects of reaction chamber precursors before entering the epitaxial growth of the active region layer 6. If the epitaxial growth of the active region layer 6 is started directly, local component fluctuations or interface states may be introduced at the lower interface of the active region layer 6.

[0071] The hold-up process may include interrupting the supply of a group III source while maintaining the supply of a group V source. During the hold-up process, the group III source is interrupted, so that group III deposition essentially ceases on top of the upper buffer layer 5; the group V source is maintained, keeping the top of the upper buffer layer 5 in a group V atmosphere suitable for surface stability of group III-V materials. After the hold-up process is completed, the supply of the group III source is restored to form an active region layer 6 on top of the upper buffer layer 5. This process provides time for surface migration and reconstruction on top of the upper buffer layer 5 before the active region layer 6 begins epitaxy, thereby facilitating the formation of a more stable lower interface of the active region layer 6.

[0072] For example, after the growth of the upper buffer layer 5 is completed and the top of the upper buffer layer 5 is higher than the top of the trench, while maintaining the reaction chamber temperature at or near the growth temperature of the upper buffer layer 5, the supply of group III source is interrupted, and group V source is continuously supplied for a holding time of 5 to 60 seconds. For example, the holding time can be 10 seconds, 20 seconds, or 30 seconds. After the holding process is completed, the supply of group III source for forming the active region layer 6 is resumed, and the corresponding group V source is supplied again to form the active region layer 6 on top of the upper buffer layer 5.

[0073] For example, the upper buffer layer 5 is an indium phosphide layer, and the group V source can be phosphine or tert-butylphosphine. Before forming the active region layer 6, a group III source such as trimethylindium can be turned off or interrupted, and the supply of phosphine or tert-butylphosphine can be maintained for 20 seconds to perform a holding process on the top of the upper buffer layer 5. Subsequently, the supply of the group III source required to form the active region layer 6 is restored, for example, the indium source, gallium source and / or aluminum source is restored, and in conjunction with the corresponding group V source, indium gallium arsenide phosphide or indium gallium aluminum arsenide active region layer 6 is formed on the top of the upper buffer layer 5. In this embodiment, the holding process is performed after the upper buffer layer 5 is grown and before the active region layer 6 begins epitaxy, and can serve as an interface preparation step between the upper buffer layer 5 and the active region layer 6.

[0074] It should be noted that the clamping and release sub-window, the free expansion sub-window, the group III source supply duty cycle, the supply cycle, and the holding processing time can all be adjusted according to the trench size, the material of the upper buffer layer 5, the target epitaxial rate, the gas switching response time of the reaction chamber, and the material system of the active region layer 6. The above embodiment is used to illustrate one possible implementation of segmented transition compensation growth within a predetermined height window and the holding processing before the formation of the active region layer 6, and is not limited to using only the specific values ​​mentioned above.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A silicon-based selective epitaxial electroabsorption modulator, characterized in that, include: A patterned substrate, including silicon and defined by trenches; A buffer layer is epitaxially disposed within the trench, with its top end higher than the top end of the trench, and its lattice orientation is consistent with that of the patterned substrate; an active region layer is epitaxially disposed on the buffer layer and its lattice orientation is consistent with that of the buffer layer, configured to modulate the passing optical signal under an applied electric field; a capping layer is epitaxially disposed on the active region layer and its lattice orientation is consistent with that of the active region layer; and a contact layer is epitaxially disposed on the capping layer and its lattice orientation is consistent with that of the capping layer. The first electrode is electrically connected to the contact layer; The second electrode is disposed on the side of the patterned substrate away from the buffer layer and cooperates with the first electrode to apply a modulated electric field to the active region layer. as well as An insulating structure is disposed on both sides of the cover layer and the contact layer; The first electrode includes a window electrode disposed on the contact layer, a pad electrode disposed on the side of the insulating structure away from the patterned substrate, and a bridge electrode extending along the sidewall of the insulating structure and electrically connecting the window electrode to the pad electrode. The insulating structure includes a first insulating layer disposed on both sides of the cover layer and the contact layer, a second insulating layer disposed on the first insulating layer, and a passivation layer disposed on the second insulating layer; The top of the first insulating layer is flush with the top of the contact layer, the second insulating layer does not cover the top of the contact layer, the pad electrode is disposed on the passivation layer, and the bridge electrode extends along the sidewall of the second insulating layer.

2. The silicon-based selective epitaxial electroabsorption modulator according to claim 1, characterized in that, The relative permittivity of at least one of the first insulating layer, the second insulating layer, and the passivation layer is less than half the relative permittivity of at least one of the active region layer, the capping layer, and the contact layer.

3. The silicon-based selective epitaxial electroabsorption modulator according to claim 1, characterized in that, At least one of the first insulating layer and the second insulating layer comprises benzocyclobutene or polyimide.

4. The silicon-based selective epitaxial electroabsorption modulator according to claim 1, characterized in that, The buffer layer includes a lower buffer layer disposed in the trench, a middle buffer layer disposed on the lower buffer layer, and an upper buffer layer disposed on the middle buffer layer; The lower buffer layer comprises gallium arsenide, the middle buffer layer comprises at least one of indium gallium arsenide phosphide and indium phosphide, and the upper buffer layer comprises indium phosphide.

5. The silicon-based selective epitaxial electroabsorption modulator according to claim 4, characterized in that, The lattice mismatch between the middle buffer layer and the lower buffer layer, and the lattice mismatch between the upper buffer layer and the middle buffer layer, are both no higher than 4%.

6. The silicon-based selective epitaxial electroabsorption modulator according to claim 1, characterized in that, The active region layer includes at least one of indium gallium arsenide phosphide and indium gallium aluminum arsenide, the capping layer includes indium phosphide, and the contact layer includes indium gallium arsenide.

7. A method for fabricating a silicon-based selective epitaxial electroabsorption modulator, characterized in that, include: Provides a patterned substrate comprising silicon and defined trenches; A buffer layer, including an upper buffer layer, is formed within the trench by selective extension. During the formation of the upper buffer layer, when the current growth surface of the upper buffer layer is within a predetermined height window with the upper end of the trench as a reference, transition compensation growth is performed to form a transition compensation layer segment in the upper buffer layer that spans the upper end of the trench. The transition compensation growth includes supplying a group III source in a pulsed manner under the condition of continuous supply of group V source, and the group III source supply duty cycle within the predetermined height window is lower than the group III source supply duty cycle in the upper buffer layer growth stage before and after the transition compensation growth. Continue forming the upper buffer layer, such that the top of the upper buffer layer is higher than the upper end of the trench; and An active region layer is formed on the upper buffer layer by selective region epitaxy; The predetermined height window includes a clamping release sub-window located below the upper end of the groove and a free expansion sub-window located above the upper end of the groove; Within the clamping release sub-window, the transition compensation growth is performed according to the first group III source supply duty cycle; Within the free-expanding sub-window, the transition compensation growth is performed according to the second group III source supply duty cycle; The duty cycle of the second group III source supply is less than that of the first group III source supply.

8. The preparation method according to claim 7, characterized in that, Before forming the active region layer, the preparation method further includes: Interrupt the Group III source supply and maintain the Group V source supply to perform a hold process on the top of the upper buffer layer; After the holding process, the Group III source supply is restored to form the active region layer on top of the upper buffer layer.

Images