A pulse signal simulation method, system, device and computer storage medium

Abstract

The application discloses a pulse signal simulation method, system, device and computer storage medium, relates to the field of time synchronization technology, is applied to an embedded device, determines a system clock, and the system clock is obtained by calibration after the embedded device interacts with a time server through a network time protocol; a current pulse signal corresponding to a target pulse signal output by a hardware timer in the embedded device is collected; a phase error of the current pulse signal relative to the target pulse signal is generated based on the system clock; a trigger threshold adjustment amount for reducing the phase error is generated; the pulse trigger threshold of the hardware timer is adjusted by applying the trigger threshold adjustment amount, so that the pulse signal output by the hardware timer is calibrated. Taking NTP time service as a reference, the pulse signal simulation is realized in combination with the hardware timer of the embedded device, hardware cost is reduced, and the size of the device is reduced; and the cycle stability and microsecond-level precision of the pulse signal are ensured.

Description

Technical Field

[0001] This application relates to the field of time synchronization technology, and more specifically, to a pulse signal simulation method, system, device, and computer storage medium. Background Technology

[0002] In applications with stringent time synchronization requirements, a precise clock reference is the cornerstone of normal and collaborative system operation. Taking a 1 Pulse Per Second (1PPS) signal as an example, as a standard time frequency signal, its rising or falling edge precisely corresponds to every whole second of Coordinated Universal Time (UTC), serving as the physical carrier for achieving microsecond or even nanosecond-level time synchronization.

[0003] Currently, high-precision time synchronization can be achieved using dedicated hardware modules, such as satellite timing modules, atomic clocks, rubidium clocks, and other high-precision time and frequency devices, as well as dedicated time and frequency chips. However, these hardware modules are costly and cannot be used in low-cost embedded devices such as industrial IoT gateways, edge computing nodes, and small monitoring terminals, thus limiting their application.

[0004] In summary, how to perform pulse signal simulation on embedded devices at low cost and with high accuracy is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a pulse signal simulation method, which can, to some extent, solve the technical problem of how to perform pulse signal simulation on embedded devices at low cost and with high accuracy. This application also provides a pulse signal simulation system, an electronic device, and a computer-readable storage medium.

[0006] To achieve the above objectives, this application provides the following technical solution: A pulse signal simulation method, applied to embedded devices, includes: The system clock is determined, which is calibrated by the embedded device after interacting with a time server via a network time protocol. Acquire the current pulse signal corresponding to the target pulse signal output by the hardware timer in the embedded device; Based on the system clock, the phase error of the current pulse signal relative to the target pulse signal is generated; Generate a trigger threshold adjustment amount to reduce the phase error; The trigger threshold adjustment amount is applied to adjust the pulse trigger threshold of the hardware timer in order to calibrate the pulse signal output by the hardware timer.

[0007] Preferably, generating the trigger threshold adjustment amount to reduce the phase error includes: The phase error is processed by a PID control algorithm to obtain the phase adjustment amount; The phase adjustment amount is converted according to the counting period of the hardware timer to obtain the trigger threshold adjustment amount.

[0008] Preferred options also include: Detect whether the time synchronization with the time server is interrupted; In response to a time synchronization interruption with the time server, the target historical value of the recorded pulse trigger threshold is obtained; The target historical value is used to set the pulse trigger threshold in order to maintain the pulse signal output by the hardware timer.

[0009] Preferably, obtaining the recorded target historical value of the pulse trigger threshold includes: Obtain the original historical value of the recorded pulse trigger threshold and the corresponding temperature value; Collect the current temperature value from the hardware timer; Among the original historical values, the historical values ​​whose temperature values ​​match the current temperature value are used as the target historical values.

[0010] Preferably, detecting whether time synchronization with the time server is interrupted includes: Monitor the time synchronization connection status and the deviation value of the synchronization results with the time server; If multiple consecutive time synchronization connection states indicate connection failure, and / or multiple consecutive deviation values ​​exceed a preset threshold, then the time synchronization with the time server is determined to be interrupted.

[0011] Preferably, the system clock is determined, which is calibrated by the embedded device after interacting with a time server via a network time protocol, including: Send a time request message to the time server via the Network Time Protocol and record the first timestamp; Receive the response message corresponding to the time request message returned by the time server via the Network Time Protocol, and record the second timestamp; The response message is parsed to obtain a third timestamp and a fourth timestamp. The third timestamp includes the timestamp recorded by the time server after receiving the time request message. The fourth timestamp includes the timestamp of the time server sending the response message. Based on the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp, a time deviation between the embedded device and the time server is generated; The system clock of the embedded device is calibrated based on the time deviation.

[0012] Preferably, before acquiring the current pulse signal corresponding to the target pulse signal output by the hardware timer in the embedded device, the method further includes: Configure the hardware timer of the embedded device to edge-triggered mode; Determine the counting period of the hardware timer; Based on the counting period, an initial count value is generated to trigger the target pulse signal; Based on the system clock, the pulse trigger threshold of the hardware timer is configured to the initial count value.

[0013] A pulse signal simulation system, applied to embedded devices, includes: The system clock determination module is used to determine the system clock, which is calibrated by the embedded device after interacting with a time server through a network time protocol. The pulse signal acquisition module is used to acquire the current pulse signal corresponding to the target pulse signal output by the hardware timer in the embedded device; A phase error generation module is used to generate a phase error of the current pulse signal relative to the target pulse signal based on the system clock. A phase error compensation module is used to generate a trigger threshold adjustment amount to reduce the phase error; The pulse adjustment module is used to adjust the pulse trigger threshold of the hardware timer by applying the trigger threshold adjustment amount, so as to calibrate the pulse signal output by the hardware timer.

[0014] An electronic device, comprising: Memory, used to store computer programs; A processor for implementing the steps of any of the methods described above when executing the computer program.

[0015] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the methods described above.

[0016] This application provides a pulse signal simulation method applied to embedded devices. The method involves determining the system clock, which is calibrated by the embedded device after interacting with a time server via a network time protocol. It acquires the current pulse signal corresponding to the target pulse signal output by a hardware timer in the embedded device. Based on the system clock, it generates the phase error of the current pulse signal relative to the target pulse signal. It generates a trigger threshold adjustment amount to reduce the phase error. The trigger threshold adjustment amount is applied to adjust the pulse trigger threshold of the hardware timer to calibrate the pulse signal output by the hardware timer. This application utilizes an NTP time server, calibrating the system clock based on NTP time synchronization, and combines this with the embedded device's built-in hardware timer to simulate the pulse signal. This eliminates the need for expensive additional equipment such as satellite time synchronization modules, high-precision time and frequency devices, and dedicated time and frequency chips, reducing hardware costs and device size. Furthermore, by outputting pulses through a hardware timer, it avoids the problem of software timers being affected by operating system scheduling, ensuring the periodic stability of the pulse signal. Additionally, the phase error adjustment achieves microsecond-level accuracy for the pulse signal. This application also provides a pulse signal simulation system, electronic device, and computer-readable storage medium that solve corresponding technical problems. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 A flowchart illustrating a pulse signal simulation method provided in this application embodiment; Figure 2 The flowchart shows a pulse signal simulation method based on PID control. Figure 3 Here is a flowchart of a time-based pulse signal simulation method; Figure 4 This is a schematic diagram of the structure of a pulse signal simulation system provided in an embodiment of this application; Figure 5 This is a structural diagram of a computer device according to an exemplary embodiment. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0020] Please see Figure 1 , Figure 1 This is a flowchart of a pulse signal simulation method provided in an embodiment of this application.

[0021] This application provides a pulse signal simulation method, applied to embedded devices, which may include the following steps: Step S101: Determine the system clock. The system clock is calibrated by the embedded device after interacting with the time server through the network time protocol.

[0022] In practical applications, the internal clock of embedded devices is configured based on the system clock, which needs to be synchronized with Coordinated Universal Time (UTC) so that the internal clock of the embedded device can be synchronized with UTC. Therefore, embedded devices need to interact with a time server via the Network Time Protocol (NTP) and then calibrate the system clock based on the interaction results. The time server provides UTC and can be an NTP server, etc.

[0023] In an exemplary embodiment, after the embedded device starts up, it can first initialize the network protocol stack, establish a network connection with a pre-configured NTP server through the Ethernet interface, such as using the NTPv4 protocol to perform bidirectional time message interaction with the NTP server, and then calibrate the system clock according to the interaction result to obtain a standard second-level reference time.

[0024] It should be noted that the time synchronization principle of the NTPv4 protocol is as follows: there is a fixed time deviation θ between the system clock of the embedded device and the standard time of the NTP server, and the network transmission has an uncertain propagation delay δ. In order to solve for θ and δ simultaneously, the NTP protocol adopts a bidirectional message exchange method, establishing a system of equations by recording four timestamps. Based on this, during the process of determining the system clock (which is calibrated by the embedded device after interacting with the time server through the network time protocol), the embedded device can send a time request message to the time server through the network time protocol, recording the first timestamp T1, i.e., the sending timestamp. The first timestamp can be obtained by the embedded device's operating system when the time request message enters the transport layer of the network protocol stack; its accuracy is affected by the operating system's clock resolution. After receiving the time request message, the NTP server records the current value of the server's system clock, denoted as the receiving timestamp T2. After processing the time request message, the NTP server constructs a response message, recording the current value of the server's system clock at the time the response message is sent. To send timestamp T3, the NTP server encapsulates timestamps T1, T2, and T3 in a response message and sends it back to the embedded device. The embedded device then receives the response message corresponding to the time request message from the time server via the Network Time Protocol (NTP), and records the second timestamp T4. The response message is parsed to obtain the third timestamp T2 and the fourth timestamp T3. The third timestamp includes the timestamp recorded by the time server after receiving the time request message, and the fourth timestamp includes the timestamp of the time server sending the response message. Based on the first, second, third, and fourth timestamps, the time deviation between the embedded device and the time server is generated. The embedded device's system clock is then calibrated according to the time deviation. In this way, the deviation between the embedded device's system clock and the NTP standard time can be controlled within 10 milliseconds, providing a good foundation for accurate pulse signal simulation later.

[0025] In a specific application scenario, during the generation of the time deviation between the embedded device and the time server, the time elapsed from the embedded device sending a time request message to the NTP server receiving the request is T2-T1=δ+θ. This is because the embedded device's time is ahead of the standard time θ, so the interval measured by the embedded device includes the deviation term. The time elapsed from the NTP server sending a response to the embedded device receiving the response is T4-T3=δ-θ. This is because the NTP server's time is the standard time, and the T4 recorded by the embedded device includes the deviation θ. Solving these two equations simultaneously, we get δ=[(T4-T1)-(T3-T2)] / 2 and θ=[(T2-T1)+(T3-T4)] / 2, where δ is half of the network round-trip delay, i.e., the estimated one-way propagation delay, and θ is the time deviation of the embedded device's system clock relative to the standard time. When θ is positive, it indicates that the embedded device's system clock is ahead of the standard time; when θ is negative, it indicates that the embedded device's system clock is behind the standard time.

[0026] In specific application scenarios, when calibrating the system clock of an embedded device based on time deviation, either a gradual adjustment method or a direct jump method can be used. The gradual adjustment method fine-tunes the frequency of the embedded device's system clock, allowing it to smoothly approach the standard time, and is suitable for situations with small deviations. The direct jump method directly sets the embedded device's system clock to the standard time, suitable for situations with large deviations or scenarios where time monotonicity requirements are not high. In this application, considering that the NTP synchronization period is short, ranging from seconds to tens of seconds, and the deviation of a single synchronization is usually small, the gradual adjustment method can be used to avoid the impact of time jumps on the upper-level applications of the embedded device. Of course, there are other methods for calibrating the system clock, which are not specifically limited here.

[0027] It should also be noted that, in order to maintain the real-time performance of the system time, the NTP synchronization period between the embedded device and the NTP server can be set to 5 seconds, 10 seconds, 15 seconds, etc. Taking 10 seconds as an example, the above-mentioned bidirectional message exchange and clock calibration steps are repeated every 10 seconds to continuously update the system clock of the embedded device, so as to ensure the real-time performance and accuracy of the system clock.

[0028] Step S102: Acquire the current pulse signal corresponding to the target pulse signal output by the hardware timer in the embedded device.

[0029] In practical applications, after determining the system clock, a hardware timer in the embedded device can be used to simulate the output of the target pulse signal. The target pulse signal can be 1 PPS, or a pulse signal every 3 seconds, etc. However, considering that the accuracy of the hardware timer is limited by the crystal oscillator frequency accuracy, assuming a nominal frequency deviation of ±10ppm to ±50ppm, the actual period of 1 second may deviate by 10 to 50 microseconds. Furthermore, the crystal oscillator frequency will drift with temperature changes. These deviations and drifts will cause the pulse period output by the hardware timer to deviate from the target pulse signal, resulting in significant phase errors over time. To ensure that the pulse signal simulated by the hardware timer is consistent with the target pulse signal, the current pulse signal output by the hardware timer in the embedded device, corresponding to the target pulse signal, can be acquired and used to adjust the hardware timer.

[0030] In an exemplary embodiment, the pulse signal can be set according to the counting period of the hardware timer and can be triggered at the edge of the hardware timer. Based on this, before acquiring the current pulse signal output by the hardware timer in the embedded device that corresponds to the target pulse signal, during the initial configuration of the hardware timer according to the target pulse signal, the hardware timer of the embedded device can be configured to edge-triggered mode. This means that when the hardware timer reaches the trigger threshold, it generates a level transition on the output pin, such as transitioning from low level to high level or from high level to low level, forming a pulse edge. During this process, the device tree of the embedded device can be used to... The device tree (DBT) configures on-chip hardware timers. The device tree is a data structure used to describe the hardware resource configuration of an embedded device. Through the timer nodes in the device tree, parameters such as the clock source, interrupt number, and operating mode of the hardware timer can be configured. The counting period of the hardware timer, i.e., the physical duration corresponding to a single tick, can be determined by the input clock frequency of the hardware timer. Based on the counting period, an initial count value is generated to trigger the target pulse signal. Using the system clock as a reference, the pulse trigger threshold of the hardware timer is configured as the initial count value. Thus, after the hardware counter accumulates to the pulse trigger threshold, it will output a pulse signal at the edge, the period of which is close to the period of the target pulse signal.

[0031] For ease of understanding, assume the target pulse signal is 1PPS and the input clock frequency of the hardware timer is 19.2MHz. Therefore, the duration of a single tick is: T tick=1 / 19200000≈52.083333 nanoseconds (ns). Based on the theoretical count value corresponding to 1 microsecond (μs): 1000ns / 52.083333ns≈19.2 ticks, if the pulse trigger threshold of the timer is set to the count value corresponding to 1 second, the count value corresponding to 1 second is 19200000. Therefore, the pulse trigger threshold of the hardware timer needs to be set to the initial count value of 19200000. In this way, the hardware timer starts counting from 0, and the count value increments by 1 with each clock pulse (tick). When the count value reaches 19200000, a comparison match event is generated, triggering an interrupt and changing the level state of the output pin. Then, by using the automatic reload or periodic mode of the hardware timer to achieve continuous periodic triggering, a stable pulse signal with a period of 1 second can be output.

[0032] Step S103: Based on the system clock, generate the phase error of the current pulse signal relative to the target pulse signal.

[0033] In practical applications, when adjusting the hardware timer based on the current pulse signal, the phase error between the current pulse signal and the target pulse signal can be generated first, based on the system clock. For example, the timestamp t of the system clock corresponding to the current pulse signal can be determined. dev Determine the timestamp t of the system clock corresponding to the target pulse signal. ntp , will t dev With t ntp The difference is taken as the phase error Δτ, that is, Δτ=t dev -t ntp When Δτ is positive, it indicates that the rising edge of the pulse output by the hardware timer is later than the target pulse signal, i.e., pulse lag. When Δτ is negative, it indicates that the rising edge of the pulse output by the hardware timer is earlier than the target pulse signal, i.e., pulse lead. For ease of understanding, assume that the current pulse signal output by the hardware timer belongs to the 3rd round of pulse signals, and its corresponding system clock timestamp is t. dev =1699999999.000002s, while the timestamp of the system clock corresponding to the third round of target pulse signal is t. ntp =1699999999.000000s, then Δτ=2μs, indicating that the pulse output by the hardware timer is delayed by 2 microseconds.

[0034] It should be noted that, in determining the system clock timestamp corresponding to the current pulse signal, the current pulse signal output by the hardware timer can be acquired using a general-purpose input / output (GPIO) pin. For example, the output pin of the hardware timer can be connected to a GPIO input pin, and this GPIO pin can be configured to rise-edge interrupt trigger mode. When the edge of the hardware timer output pulse arrives, the GPIO interrupt is triggered, and the interrupt service routine immediately reads the current system timestamp t. dev In determining the timestamp of the system clock corresponding to the target pulse signal, the embedded device can obtain it via the NTP protocol. For example, the embedded device can calculate the expected arrival time of the target pulse signal based on the current system time and the known time deviation θ. Alternatively, after each NTP synchronization is completed, the embedded device can record the standard time of the synchronization moment as a reference, calculate the expected arrival time of each target pulse signal, and then determine t based on the expected arrival time of the target pulse signal. ntp .

[0035] It should also be noted that the accuracy of phase error acquisition directly affects the performance of pulse signal compensation. In GPIO interrupt mode, the delay between the actual occurrence of the pulse rising edge and the interrupt service routine reading the timestamp introduces measurement error. This measurement error includes hardware interrupt latency, operating system interrupt response latency, and the software overhead of reading the system timestamp. To reduce this error, GPIO interrupts can be set to high priority to ensure timely interrupt response; and operations in the interrupt service routine should be minimized, exiting only after reading the timestamp. Of course, t can also be determined using other methods. dev For example, the capture function of a hardware timer can be used to determine t. dev This application does not specifically limit the scope of these provisions.

[0036] Step S104: Generate the trigger threshold adjustment amount to reduce phase error.

[0037] Step S105: Apply the trigger threshold adjustment amount to adjust the pulse trigger threshold of the hardware timer in order to calibrate the pulse signal output by the hardware timer.

[0038] In practical applications, after generating the phase error, a trigger threshold adjustment amount ΔN can be generated to reduce the phase error. This adjustment amount is then used to adjust the pulse trigger threshold of the hardware timer. For example, the current count value N0 of the hardware timer's pulse trigger threshold is determined, and the trigger threshold adjustment amount is subtracted from the current count value to obtain a corrected count value N′, where N′ = N0 - ΔN. The hardware timer's pulse trigger threshold is then set to this corrected count value to calibrate the pulse signal output by the hardware timer, making the output pulse signal closer to the target pulse signal. Thus, when the hardware timer's pulse is lagging (Δτ is positive), the counting period can be shortened by decreasing the trigger threshold, allowing the hardware timer to trigger the output after fewer ticks, thereby allowing the rising edge of the next pulse to arrive earlier and offsetting the lag error. Conversely, when the pulse is leading (Δτ is negative), the counting period can be extended by increasing the trigger threshold, causing the pulse to arrive later.

[0039] It should be noted that when the current pulse signal is the pulse signal initially generated by the hardware timer, taking 19.2 ticks as an example, since the count value of the hardware timer must be an integer, it is not possible to directly implement a non-integer count such as 19.2 ticks. Therefore, it is not possible to accurately represent 1 microsecond in a single count, which causes the initially generated pulse signal to deviate from 1PPS. However, after adjusting the pulse trigger threshold of the hardware timer according to the trigger threshold adjustment amount, the pulse signal generated by the hardware timer can be made closer to 1PPS.

[0040] This application provides a pulse signal simulation method applied to embedded devices. The method involves determining the system clock, which is calibrated by the embedded device after interacting with a time server via a network time protocol. It acquires the current pulse signal output by a hardware timer in the embedded device, corresponding to a target pulse signal. Based on the system clock, it generates the phase error of the current pulse signal relative to the target pulse signal. It then generates a trigger threshold adjustment amount to reduce the phase error. Finally, it applies this adjustment amount to adjust the pulse trigger threshold of the hardware timer, thereby calibrating the pulse signal output by the hardware timer. This application utilizes an NTP time server to calibrate the system clock based on NTP time synchronization. Combined with the embedded device's built-in hardware timer, it achieves pulse signal simulation without requiring expensive additional equipment such as satellite time synchronization modules, high-precision time and frequency devices, and dedicated time and frequency chips, thus reducing hardware costs and device size. Furthermore, by outputting pulses through a hardware timer, it avoids the problem of software timers being affected by operating system scheduling, ensuring the periodic stability of the pulse signal. Additionally, the phase error adjustment achieves microsecond-level accuracy for the pulse signal.

[0041] Based on the above embodiments, the accuracy of the generated trigger threshold adjustment amount will affect the magnitude of the error between the simulated pulse signal and the target pulse signal. To minimize this error, please refer to... Figure 2 The pulse signal simulation method provided in this application embodiment, applied to embedded devices, may include the following steps: Step S201: Determine the system clock. The system clock is calibrated by the embedded device after interacting with the time server through the network time protocol.

[0042] Step S202: Acquire the current pulse signal corresponding to the target pulse signal output by the hardware timer in the embedded device.

[0043] Step S203: Based on the system clock, generate the phase error of the current pulse signal relative to the target pulse signal.

[0044] Step S204: Process the phase error using a PID control algorithm to obtain the phase adjustment amount.

[0045] Step S205: Based on the counting period of the hardware timer, convert the phase adjustment amount to obtain the trigger threshold adjustment amount.

[0046] In practical applications, PID (Proportional-Integral-Derivative) control is a closed-loop control algorithm. Its principle is to generate a control quantity based on the deviation between the output and the target value through a linear combination of proportional, integral, and derivative components, making the output approach the target value. It has strong steady-state error elimination capability and high robustness. Therefore, in generating the trigger threshold adjustment quantity to reduce phase error, the PID control algorithm can process the phase error to obtain the phase adjustment quantity ΔN(k). Since the phase adjustment quantity is described by phase angle, it is also necessary to convert the phase adjustment quantity according to the counting period of the hardware timer to obtain the trigger threshold adjustment quantity ΔN, where ΔN = ΔN(k) / T. tick The pulse trigger threshold of the hardware timer is adjusted according to the trigger threshold adjustment amount. In this way, the steady-state error of the trigger threshold adjustment amount can be eliminated by using a PID control algorithm, and the robustness of generating the trigger threshold adjustment amount is improved, making the solution applicable to more types of embedded devices.

[0047] In the exemplary embodiment, if a PID closed-loop control algorithm is used as the error compensation mechanism, the process of generating the phase adjustment amount by taking the phase error Δτ as input can be expressed as follows: Where k represents the k-th calibration period, Δτ(k) represents the phase error of the k-th calibration, and Δτ(k-1) represents the phase error of the previous measurement. K p ,K i , K d These are the proportional coefficient, integral coefficient, and differential coefficient, respectively, and ΔN(k) represents the phase adjustment amount in the kth iteration.

[0048] It should be noted that the proportional term The function of proportional control is to provide an immediate response to the current error. The larger the error, the greater the required correction. The proportional term determines the speed of the response, but proportional control alone cannot eliminate steady-state error. Integral term The function of the integral term is to accumulate historical errors and eliminate steady-state errors. Even if the current error is very small, as long as there are positive or negative accumulated errors in the past, the integral term will continue to generate a corrective effect until the accumulated error is zero. The integral term can overcome the static deviation of the crystal oscillator frequency, such as the fixed deviation between the nominal frequency and the true frequency of the crystal oscillator. (Differential term) The function of the differential term is to perform predictive correction based on the trend of error changes. When the error is increasing, the differential term generates an additional correction to suppress further increase in error; when the error is decreasing, the differential term has a reverse effect to prevent overshoot. The differential term helps improve stability and reduce overshoot. The selection of the proportional, integral, and differential coefficients needs to be adjusted according to factors such as the crystal oscillator characteristics, timer resolution, and NTP timing accuracy of the specific equipment. Specifically, an excessively large proportional coefficient will cause system oscillation, while an excessively small coefficient will result in slow convergence; an excessively large integral coefficient will lead to integral saturation, while an excessively small coefficient will fail to effectively eliminate steady-state error; an excessively large differential coefficient will amplify noise, while an excessively small coefficient will result in insufficient damping. In specific application scenarios, refer to... K p =0.8, K i =0.1, K d =0.05 to determine the value of the corresponding coefficient. For ease of understanding, taking 1PPS as an example again, then ΔN=2μs / 52.083ns≈38.4≈38. Therefore, 38 can be used as the trigger threshold adjustment amount.

[0049] It should also be noted that the above error acquisition and PID correction process can be repeated once per pulse cycle, for example, once every 1 second. That is, in each cycle, the phase error of the current pulse is measured, the new trigger threshold adjustment is calculated, and the trigger threshold register of the hardware timer is updated. During this process, since the hardware timer usually supports dynamic modification of the trigger threshold during operation, the correction can be completed without interrupting the hardware timer counting, ensuring the stability of the output pulse signal. Correspondingly, after multiple iterations, under the action of the integral term of the PID controller, the steady-state error gradually approaches zero. When it enters steady state, the trigger threshold of the hardware timer will fluctuate slightly around an average value. The fluctuation amplitude depends on the measurement noise and the setting of the PID parameters. In this embodiment, after iterative convergence, the error of the 1PPS analog signal can be stabilized within 1 microsecond.

[0050] It is understood that this embodiment only uses PID control as an example to describe the generation process of the trigger threshold adjustment. In specific application scenarios, the trigger threshold adjustment can be generated flexibly. For example, it can be generated by combining Kalman filtering and PID. For instance, Kalman filtering is applied to the phase error to obtain the filter error, and the filter error is processed by the PID control algorithm to obtain the phase adjustment. According to the counting period of the hardware timer, the phase adjustment is converted to obtain the trigger threshold adjustment. Kalman filtering is used to eliminate noise in the phase error, further improving the accuracy of the generated trigger threshold adjustment, thereby improving the accuracy of the simulated pulse signal. In addition, to avoid noise introduced by frequent adjustments, the adjustment trigger conditions can be restricted. For example, when the phase error is less than a certain threshold, such as less than 0.1µs, the hardware timer is not adjusted, and the pulse trigger threshold of the hardware timer remains unchanged.

[0051] Step S206: Apply the trigger threshold adjustment amount to adjust the pulse trigger threshold of the hardware timer in order to calibrate the pulse signal output by the hardware timer.

[0052] Based on the above embodiments, if the embedded device cannot interact with the time server, such as due to network interruption between the embedded device and the time server, time server failure, or the embedded device moving to a no-signal area, the system clock loses its external reference and will gradually drift due to free oscillation of the crystal oscillator. This causes the 1PPS signal accuracy to deteriorate over time, failing to meet the continuous time synchronization requirement. To solve this problem, please refer to [link to relevant documentation]. Figure 3 The pulse signal simulation method provided in this application embodiment, applied to embedded devices, may include the following steps: Step S301: Determine the system clock. The system clock is calibrated by the embedded device after interacting with the time server through the network time protocol.

[0053] Step S302: Acquire the current pulse signal corresponding to the target pulse signal output by the hardware timer in the embedded device.

[0054] Step S303: Based on the system clock, generate the phase error of the current pulse signal relative to the target pulse signal.

[0055] Step S304: Generate the trigger threshold adjustment amount to reduce phase error.

[0056] Step S305: Apply the trigger threshold adjustment amount to adjust the pulse trigger threshold of the hardware timer in order to calibrate the pulse signal output by the hardware timer.

[0057] Step S306: Detect whether the time synchronization with the time server is interrupted. If the time synchronization with the time server is interrupted, then execute step S307.

[0058] Step S307: Obtain the recorded target historical value of the pulse trigger threshold.

[0059] Step S308: Set the pulse trigger threshold using the target historical value to maintain the pulse signal output by the hardware timer.

[0060] In practical applications, the timing synchronization with the time server can be checked first. If the timing synchronization between the embedded device and the time server is normal, the pulse trigger threshold of the hardware timer can be adjusted. If the timing synchronization between the embedded device and the time server is interrupted, a timekeeping mode can be entered, and the output pulse signal can be kept stable within a certain range based on the recorded historical values ​​of the pulse trigger threshold. In this way, since the recorded historical values ​​of the pulse trigger threshold are all the trigger thresholds configured by the hardware timer for the target output pulse signal, adjusting the trigger threshold of the hardware timer with reference to the historical values ​​can ensure that the output pulse signal fluctuates around the target pulse signal and does not continuously deviate from the target pulse signal.

[0061] In an exemplary embodiment, during the process of maintaining the output pulse signal stable within a certain range based on the recorded historical values ​​of the pulse trigger threshold, a target historical value of the recorded pulse trigger threshold can be obtained. The method for obtaining the target historical value can be flexibly set according to actual needs; for example, the most recently stored 100 historical values ​​can be used as the target historical value. The target historical value is applied to set the pulse trigger threshold to maintain the pulse signal output by the hardware timer. In this process, since the integral term of the PID controller has converged to a stable value during long-term closed-loop calibration, this value reflects the average deviation of the crystal oscillator frequency from the nominal value. In the absence of an external timing reference, the average value of the target historical value can be used to set the pulse trigger threshold so that the hardware timer outputs a pulse signal as close as possible to the target pulse signal. In addition, the target historical value can be processed by linear regression, polynomial fitting, Kalman filter and other methods to obtain a more accurate pulse trigger threshold. For example, linear regression or polynomial fitting can be performed on the target historical value, and the current time can be substituted into the fitting function to obtain the first trigger threshold benchmark correction amount. The Kalman filter can be used to estimate the state of the target historical value to obtain the second trigger threshold benchmark correction amount. The average value of the target historical value, the first trigger threshold benchmark correction amount and the second trigger threshold benchmark correction amount can be weighted and fused to obtain the weighted fused value. This weighted fused value is used as the set value of the hardware timer pulse trigger threshold.

[0062] In specific application scenarios, changes in ambient temperature can affect the crystal oscillator frequency of the hardware timer, causing a deviation between the simulated pulse signal and the target pulse signal. To reduce this deviation, the crystal oscillator temperature compensation mechanism of the hardware timer can be used to further adjust the pulse trigger threshold of the hardware timer. For example, in the process of obtaining the target historical value of the recorded pulse trigger threshold, the original historical value of the recorded pulse trigger threshold and the corresponding temperature value can be obtained; the current temperature value of the hardware timer can be collected; and the historical value whose temperature value matches the current temperature value in the original historical value can be used as the target historical value. In this way, the target historical value corresponds to the current temperature value of the hardware timer. Since the current temperature value is related to the crystal oscillator temperature compensation mechanism, the target historical value can be considered as a reference value related to the crystal oscillator temperature compensation mechanism. Therefore, if the pulse trigger threshold of the hardware timer is adjusted in the future, it is equivalent to adjusting it based on the historical reference value related to the crystal oscillator temperature compensation mechanism. This can eliminate the error caused by the timing interruption and also eliminate the influence of the ambient temperature change on the crystal oscillator frequency, thereby improving the accuracy of the simulated pulse signal. Taking the above 1PPS as an example, experimental verification shows that the error of the 1PPS signal during the timing phase does not exceed 5µs / minute.

[0063] In an exemplary embodiment, the detection method for time synchronization interruption can be flexibly determined according to actual needs. For example, during the process of detecting whether time synchronization with the time server is interrupted, the time synchronization connection status and the deviation value of the synchronization result can be monitored. In response to multiple consecutive time synchronization connection statuses indicating connection failure, and / or multiple consecutive deviation values ​​exceeding a preset threshold, a time synchronization interruption with the time server is determined. Here, multiple consecutive values ​​can be three, four, etc. Furthermore, after each time synchronization is completed, the embedded device can also record the time deviation value and timestamp of this synchronization to form a historical deviation record for monitoring time synchronization stability.

[0064] To facilitate understanding of the present application's solution, assuming that 1PPS is implemented in edge computing scenarios such as vehicle-to-everything (V2X) terminal devices, industrial IoT gateways, and RISC-V architecture embedded Linux devices, the implementation process of the present application's solution in each scenario can be as follows. For detailed explanations of each step, please refer to the above embodiments, which will not be repeated here.

[0065] Exemplary Example 1: Application Scenario of Vehicle-Mounted V2X Terminal Equipment.

[0066] Vehicle-to-everything (V2X) terminal equipment is used to achieve high-precision time synchronization between vehicle-to-vehicle (V2V) communication, vehicle-to-infrastructure (V2I) communication, and vehicle-to-cloud (V2C) platforms. V2X applications require high time synchronization accuracy. For example, in V2V communication, the timeliness of vehicle location information directly affects the accuracy of collision warnings; in V2I communication, the traffic signal phase information broadcast by roadside units (RSUs) needs to be strictly aligned with the vehicle's local time. The process of simulating 1PPS by the vehicle-mounted terminal is as follows.

[0067] Step 1: Vehicle-mounted NTP Time Synchronization and Multi-Source Backup: After powering on, the vehicle-mounted terminal establishes a connection with the T-BOX (Telematics BOX) via the vehicle Ethernet. As a vehicle-mounted communication hub, the T-BOX typically has the capability to communicate with external networks (such as 4G / 5G cellular networks) and can obtain standard time from roadside units (RSUs) or cloud-based NTP servers. The vehicle-mounted terminal uses the NTPv4 protocol and enables hardware timestamps for bidirectional message exchange, recording four timestamps: T1 (vehicle-mounted terminal sends request time), T2 (RSU receives request time), T3 (RSU sends response time), and T4 (terminal receives response time). The network latency Δt and time deviation θ are calculated using formulas, and the terminal system clock is calibrated to ensure that the synchronized system clock deviates from the NTP standard time by less than 8 milliseconds. Considering the rapid changes in network topology caused by high-speed vehicle movement in V2X scenarios, the NTP synchronization period is set to 3 seconds to adapt to high-frequency data interaction and rapidly changing network environments.

[0068] The vehicle-mounted terminal monitors the NTP connection status in real time, while simultaneously initializing the BeiDou short message module and periodically checking satellite signal strength. When NTP fails to synchronize twice consecutively (the synchronization timeout can be set to 1 second), it automatically switches to BeiDou short message time synchronization to obtain standard second-level reference time, ensuring uninterrupted time reference. The BeiDou short message module receives time information broadcast by BeiDou satellites and outputs standard second-level reference time with an accuracy down to the nanosecond level.

[0069] Step 2: Onboard Hardware Timer Anti-interference Configuration: Configure the on-chip high-precision timer through the device tree to enable the timer anti-interference mode. Specific measures for the anti-interference mode include: disabling unnecessary interrupt sources to reduce the impact of CPU scheduling on timer counting and trigger timing; setting the timer interrupt to the highest priority to ensure timely response to timer trigger events. Configure the timer to rising edge trigger mode with an output level of 1.8V to match the level requirements of the V2X communication module.

[0070] Based on the standard second-level reference time obtained in the first step, the initial trigger threshold of the timer is set to 1,000,000, corresponding to a 1-second cycle. Since vibrations exist in the vehicle environment, pulse signals may exhibit glitches, i.e., multiple jumps within a short period. This embodiment configures a timer anti-shake function. The basic principle of anti-shake is: after detecting a pulse edge, a short anti-shake window is initiated, such as 100 microseconds. During this window period, any additional edge jumps are ignored; only edges that stably persist beyond the window period are considered valid pulse edges.

[0071] Step 3: V2X Scenario-Based Error Calibration: First, error acquisition is achieved using the timestamp pin of the V2X communication module. During this process, the V2X communication module typically has a dedicated timestamp input pin for receiving external 1PPS signals and timestamping internal data packets. The pulse signal output by the timer can be connected to this timestamp pin. Simultaneously, the module internally obtains the standard second pulse timestamp via NTP / BeiDou time synchronization to calculate the phase error Δτ. PID closed-loop calibration uses parameters adapted to the V2X scenario. K p =0.85、 K i =0.09、 K d =0.06, correcting the timer trigger threshold, ultimately stabilizing the 1PPS analog signal error within 1 microsecond, meeting the accuracy requirements of V2X multi-device time synchronization.

[0072] Step 4: Vehicle-mounted timekeeping mode: Timekeeping trigger condition: When both NTP and BeiDou time synchronization are interrupted, such as when the vehicle enters a long tunnel with no network signal or satellite signal, the vehicle-mounted timekeeping mode will be automatically activated.

[0073] Timing parameter retrieval: Retrieve the trigger threshold correction values ​​from the most recent 200 times from the historical calibration parameter library, and calculate the baseline correction value N using a linear regression algorithm. avg The basic principle of linear regression is as follows: assuming the trigger threshold correction changes linearly with time, corresponding to the linear drift of the crystal oscillator frequency, the trend of the correction over time is obtained by performing least-squares linear fitting on historical data points. This trend is then extrapolated to the current moment to obtain the most likely estimate of the correction. During the timekeeping period, the trigger threshold is fine-tuned to ensure that the timekeeping accuracy does not exceed 3 microseconds / minute. When the vehicle exits the tunnel and resumes NTP or BeiDou signal, it automatically exits the timekeeping mode and resumes high-precision 1PPS signal output within 1 second.

[0074] Exemplary Example 2: Industrial IoT Gateway Application Scenarios.

[0075] Industrial IoT gateways are deployed in factory workshops, connecting various industrial sensors, actuators, and programmable logic controllers. They require a 1PPS signal to achieve time synchronization of sensor data acquisition, ensuring that data from different sensors have a consistent time reference, facilitating subsequent data fusion and fault diagnosis. The pulse signal simulation process can be as follows.

[0076] Step 1: NTP Time Synchronization and System Clock Calibration: After the industrial IoT gateway starts up, it initializes the network module and establishes a connection with the local NTP server in the factory via 100Mbps Ethernet. It uses the NTPv4 protocol and enables hardware timestamps to reduce software latency in network packet reception / transmission. Four timestamps are recorded according to the bidirectional packet exchange process. The network latency Δt and time deviation θ are calculated, and the system clock is calibrated to ensure the post-synchronization deviation is less than 5 milliseconds. The NTP synchronization period is set to 5 seconds. Simultaneously, the deviation value of each synchronization is recorded for subsequent crystal oscillator drift trend analysis. For example, by analyzing the changing patterns of the deviation value sequence, the drift direction and rate of the crystal oscillator frequency can be estimated.

[0077] Step 2: Hardware Timer Configuration and Initial Pulse Output: Configure the on-chip high-precision timer via the device tree, enable the timer clock, configure it to edge-triggered mode, and set the output level to active high to match the level requirements of industrial sensors. Assuming the crystal oscillator frequency of the industrial IoT gateway is 24MHz, the duration of a single timer tick is: T tick =1 / 24000000 ≈ 41.666667 nanoseconds. To achieve microsecond-level frequency division accuracy, the frequency division factor is set to 24. At this time, the counting clock frequency is 24MHz / 24=1MHz, and the counting period is 1 microsecond. Based on the standard second-level reference time obtained in the first step, the initial trigger threshold of the timer is set to 1000000, corresponding to a 1-second period. When the count reaches the threshold, an interrupt is generated and an initial pulse signal is output.

[0078] Step 3: Error Acquisition and PID Closed-Loop Calibration: The rising edge of the initial pulse signal is acquired using the GPIO pin, and the standard second pulse timestamp is obtained via NTP to calculate the phase error Δτ. The calibrated PID parameters are then used. K p =0.8、 K i =0.1、 K d The value is calculated as 0.05 to obtain the trigger threshold adjustment amount ΔN, which is used to correct the timer trigger threshold and stabilize the 1PPS signal error within 1 microsecond.

[0079] Step 4: Timekeeping Mode During NTP Interruption: When three consecutive NTP synchronization failures occur (synchronization timeout can be 2 seconds), an NTP interruption is identified, and timekeeping mode is activated. The historical calibration parameter library is called, which stores the trigger threshold correction amounts and corresponding temperature values ​​for the most recent 200 calibrations. Based on the current temperature, matching historical parameters are selected to calculate the baseline correction amount N. avg During the timekeeping period, the trigger threshold is fine-tuned every minute to ensure that the timekeeping accuracy does not exceed 5 microseconds / minute. Once NTP recovers, the system automatically exits timekeeping mode and re-executes steps one through three.

[0080] Exemplary Example 3: Edge computing device based on RISC-V architecture with dual timer redundancy.

[0081] Edge computing devices are deployed at the network edge, close to the data source, and have high requirements for power consumption and reliability. The process of simulating pulse signals can be as follows.

[0082] Step 1: NTP Time Synchronization and Multi-Source Time Backup: After device startup, it prioritizes establishing a connection with a public NTP server via Gigabit Ethernet, using the NTPv4 protocol for bidirectional message exchange, calculating network latency and time deviation, calibrating the system clock, and ensuring the deviation is less than 8 milliseconds after synchronization; the NTP synchronization period is set to 8 seconds to balance real-time performance and power consumption. Simultaneously, the GPS module is initialized as a backup time source, monitoring GPS signal strength in real time. When NTP is interrupted and the GPS signal is normal, GPS time synchronization is switched to the reference time source. When both fail, a timekeeping mode is activated.

[0083] Step 2: Dual Timer Redundancy Configuration and Initial Pulse Output: This embodiment configures two hardware timers: a master timer and a backup timer. The master timer uses a 48MHz crystal oscillator as its clock source, with a division factor set to 48. The counting clock frequency is 48MHz / 48=1MHz, the counting period is 1 microsecond, and the initial trigger threshold is 1,000,000. The backup timer uses a 32kHz RTC (Real-Time Clock) as its clock source. The backup timer's division factor is set to 32, 32.768kHz / 32≈1.024kHz, approximately 1ms. The counting period is approximately 1 millisecond, and the initial trigger threshold is 1000, corresponding to a period of approximately 1 second.

[0084] The output pulse periods of the master timer and the standby timer are compared in real time. The comparison method is as follows: at the rising edge of each output pulse of the standby timer, the current count value of the master timer is read, the actual count of the master timer in that period is calculated, and compared with the expected value of 1,000,000. When the deviation of the master timer exceeds 2 microseconds, that is, the actual count value of the master timer in one period deviates from 1,000,000 by more than 2 counts, the output of the standby timer is automatically switched, and an alarm can be triggered at the same time.

[0085] Step 3: Error Acquisition and Joint Calibration with PID and Kalman Filtering: Acquire the phase error Δτ between the rising edge of the main timer output pulse and the NTP standard second pulse. Since edge computing devices may be deployed in complex network environments (such as factories or industrial parks), significant network latency jitter can lead to substantial measurement noise in the timestamp of the NTP standard second pulse. Directly feeding the noisy Δτ into the PID controller could cause drastic fluctuations in the PID output, affecting the stability of the 1PPS signal. Therefore, a Kalman filter is added before PID control to eliminate error fluctuations caused by transient interference. The Kalman-filtered error is then used as the PID input, employing optimized PID parameters. K p =0.7、 K i =0.12、 K d The value is calculated as 0.06 to obtain the trigger threshold adjustment amount ΔN, which is used to correct the main timer trigger threshold. Every 10 calibrations, the errors of the main and backup timers are compared, and the redundancy switching threshold is updated to ensure the stability of the output pulse.

[0086] Step 4: Low-power timekeeping mode: When NTP is interrupted and GPS fails, low-power timekeeping mode is activated. For example, during timekeeping, the device no longer needs high-frequency CPU operation and high-speed network communication. Therefore, the CPU frequency can be reduced, and the clock and power of non-essential peripherals such as gigabit Ethernet module, WiFi module, and USB controller can be turned off. Only hardware timers, storage modules (used to read historical calibration parameters) and necessary wake-up timers are kept running.

[0087] The historical calibration parameter library can be accessed to store the trigger threshold corrections and corresponding CPU frequency and temperature data for the most recent 300 calibrations. Based on parameters such as temperature under the current low-power condition, the baseline correction amount N can be calculated. avg Set the master timer trigger threshold. During the timekeeping period, the device wakes up the CPU every 2 minutes to collect the current temperature and fine-tune the trigger threshold to ensure that the timekeeping accuracy does not exceed 3 microseconds / minute, and then enters low-power mode again. When NTP or GPS recovers, it automatically exits low-power mode, restarts the Ethernet module, and executes steps one through three to resume normal operation.

[0088] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of a pulse signal simulation system provided in an embodiment of this application.

[0089] This application provides a pulse signal simulation system, applied to an embedded device, which may include: The system clock determination module 101 is used to determine the system clock, which is calibrated by the embedded device after interacting with the time server through a network time protocol. The pulse signal acquisition module 102 is used to acquire the current pulse signal corresponding to the target pulse signal output by the hardware timer in the embedded device; The phase error generation module 103 is used to generate the phase error of the current pulse signal relative to the target pulse signal based on the system clock. The phase error compensation module 104 is used to generate a trigger threshold adjustment amount to reduce phase error; The pulse adjustment module 105 is used to adjust the pulse trigger threshold of the hardware timer by applying a trigger threshold adjustment amount, so as to calibrate the pulse signal output by the hardware timer.

[0090] This application provides a pulse signal simulation system applied to embedded devices, wherein the phase error compensation module may include: The PID processing unit is used to process the phase error through the PID control algorithm to obtain the phase adjustment amount; The phase error compensation unit is used to convert the phase adjustment amount according to the counting period of the hardware timer to obtain the trigger threshold adjustment amount.

[0091] This application provides a pulse signal simulation system for use in embedded devices, which may further include: The detection module is used to detect whether the time synchronization with the time server is interrupted. The timekeeping processing module is used to respond to time synchronization interruptions with the time server by obtaining the recorded target historical value of the pulse trigger threshold; and setting the pulse trigger threshold using the target historical value to maintain the pulse signal output by the hardware timer.

[0092] This application provides a pulse signal simulation system applied to an embedded device, wherein the timekeeping processing module may include: The historical value acquisition unit is used to acquire the original historical value of the recorded pulse trigger threshold and the corresponding temperature value; Temperature acquisition unit, used to acquire the current temperature value of the hardware timer; The filtering unit is used to select historical values ​​whose temperature values ​​match the current temperature value from the original historical values ​​as target historical values.

[0093] This application provides a pulse signal simulation system applied to an embedded device, wherein the detection module may include: The monitoring unit is used to monitor the time synchronization connection status and the deviation value of the synchronization results with the time server; The detection unit is used to determine that the time synchronization with the time server is interrupted when multiple consecutive time synchronization connection states indicate connection failure and / or multiple consecutive deviation values ​​exceed a preset threshold.

[0094] This application provides a pulse signal simulation system applied to an embedded device, wherein the system clock determination module may include: The first recording unit is used to send a time request message to the time server via the network time protocol and record the first timestamp. The message receiving unit is used to receive the response message corresponding to the time request message returned by the time server via the Network Time Protocol, and record the second timestamp; The message parsing unit is used to parse the response message to obtain the third timestamp and the fourth timestamp. The third timestamp includes the timestamp recorded by the time server after receiving the time request message, and the fourth timestamp includes the timestamp of the time server sending the response message. The deviation generation unit is used to generate the time deviation between the embedded device and the time server based on the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp. The calibration unit is used to calibrate the system clock of the embedded device based on the time deviation.

[0095] This application provides a pulse signal simulation system for use in embedded devices, which may further include: The configuration module is used to configure the hardware timer of the embedded device to edge-triggered mode before the pulse signal acquisition module acquires the current pulse signal corresponding to the target pulse signal output by the hardware timer in the embedded device. The period determination module is used to determine the counting period of the hardware timer; The initial configuration module is used to generate an initial count value for triggering the target pulse signal based on the counting period; and to configure the pulse trigger threshold of the hardware timer as the initial count value based on the system clock.

[0096] Furthermore, embodiments of this application also provide a computer device. Figure 5 This is a structural diagram of a computer device 20 according to an exemplary embodiment. The content of the diagram should not be considered as any limitation on the scope of this application.

[0097] Figure 5This is a schematic diagram of the structure of a computer device 20 provided in an embodiment of this application. Specifically, the computer device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the pulse signal simulation method disclosed in any of the foregoing embodiments. Furthermore, the computer device 20 in this embodiment may specifically be a server.

[0098] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the computer device 20; the communication interface 24 can create a data transmission channel between the computer device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0099] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222 and video data 223, etc., and the storage method can be temporary storage or permanent storage.

[0100] The operating system 221 manages and controls the various hardware devices on the computer device 20 and the computer program 222 to enable the processor 21 to perform operations and processing on the data 223 in the memory 22. It can be Windows Server, Netware, Unix, Linux, etc. The computer program 222, in addition to including a computer program capable of performing the pulse signal simulation method executed by the computer device 20 as disclosed in any of the foregoing embodiments, may further include computer programs capable of performing other specific tasks. The data 223 may include various data collected by the computer device 20.

[0101] It should be noted that the computer equipment can specifically be a module capable of realizing positioning and communication functions or a terminal device containing a module, etc. The terminal device can specifically be a mobile terminal and / or a smart device, etc. The mobile terminal can specifically be at least one of mobile phones, tablets, laptops, etc. The smart device can specifically be at least one of smartwatches, smart refrigerators, smart speakers, smart washing machines, smart TVs, etc. The module can specifically be any one of 2G communication modules, 3G communication modules, 4G communication modules, 5G communication modules, NB-IoT communication modules, etc.

[0102] Furthermore, this application also discloses a computer storage medium storing a computer program. When the computer program is loaded and executed by a processor, it implements the pulse signal simulation method steps disclosed in any of the foregoing embodiments.

[0103] Furthermore, the present application provides a computer program product including a computer program / instructions that, when executed by a processor, implement the steps of the pulse signal simulation method described in any of the preceding embodiments.

[0104] For descriptions of relevant parts in the pulse signal simulation system, electronic device, and computer-readable storage medium provided in the embodiments of this application, please refer to the detailed descriptions of the corresponding parts in the pulse signal simulation method provided in the embodiments of this application, and they will not be repeated here. Furthermore, parts of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0105] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0106] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A pulse signal simulation method, characterized in that, Used in embedded devices, including: The system clock is determined, and the system clock is calibrated by the embedded device after interacting with a time server through a network time protocol; Acquire the current pulse signal corresponding to the target pulse signal output by the hardware timer in the embedded device; Based on the system clock, the phase error of the current pulse signal relative to the target pulse signal is generated; Generate a trigger threshold adjustment amount to reduce the phase error; The trigger threshold adjustment amount is applied to adjust the pulse trigger threshold of the hardware timer in order to calibrate the pulse signal output by the hardware timer.

2. The method according to claim 1, characterized in that, Generating a trigger threshold adjustment amount to reduce the phase error includes: The phase error is processed by a PID control algorithm to obtain the phase adjustment amount; The phase adjustment amount is converted according to the counting period of the hardware timer to obtain the trigger threshold adjustment amount.

3. The method according to claim 1, characterized in that, Also includes: Detect whether the time synchronization with the time server is interrupted; In response to a time synchronization interruption with the time server, the target historical value of the recorded pulse trigger threshold is obtained; The target historical value is used to set the pulse trigger threshold in order to maintain the pulse signal output by the hardware timer.

4. The method according to claim 3, characterized in that, Obtaining the recorded target historical value of the pulse trigger threshold includes: Obtain the original historical value of the recorded pulse trigger threshold and the corresponding temperature value; Collect the current temperature value from the hardware timer; Among the original historical values, the historical values ​​whose temperature values ​​match the current temperature value are used as the target historical values.

5. The method according to claim 3, characterized in that, Detecting whether time synchronization with the time server is interrupted includes: Monitor the time synchronization connection status and the deviation value of the synchronization results with the time server; If multiple consecutive time synchronization connection states indicate connection failure, and / or multiple consecutive deviation values ​​exceed a preset threshold, then the time synchronization with the time server is determined to be interrupted.

6. The method according to claim 1, characterized in that, Determining the system clock, which is calibrated by the embedded device after interacting with a time server via a network time protocol, includes: Send a time request message to the time server via the Network Time Protocol and record the first timestamp; Receive the response message corresponding to the time request message returned by the time server via the Network Time Protocol, and record the second timestamp; The response message is parsed to obtain a third timestamp and a fourth timestamp. The third timestamp includes the timestamp recorded by the time server after receiving the time request message. The fourth timestamp includes the timestamp of the time server sending the response message. Based on the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp, a time deviation between the embedded device and the time server is generated; The system clock of the embedded device is calibrated based on the time deviation.

7. The method according to claim 1, characterized in that, Before acquiring the current pulse signal corresponding to the target pulse signal output by the hardware timer in the embedded device, the process also includes: Configure the hardware timer of the embedded device to edge-triggered mode; Determine the counting period of the hardware timer; Based on the counting period, an initial count value is generated to trigger the target pulse signal; Based on the system clock, the pulse trigger threshold of the hardware timer is configured to the initial count value.

8. A pulse signal simulation system, characterized in that, Used in embedded devices, including: The system clock determination module is used to determine the system clock, which is calibrated by the embedded device after interacting with a time server through a network time protocol. The pulse signal acquisition module is used to acquire the current pulse signal corresponding to the target pulse signal output by the hardware timer in the embedded device; A phase error generation module is used to generate a phase error of the current pulse signal relative to the target pulse signal based on the system clock. A phase error compensation module is used to generate a trigger threshold adjustment amount to reduce the phase error; The pulse adjustment module is used to adjust the pulse trigger threshold of the hardware timer by applying the trigger threshold adjustment amount, so as to calibrate the pulse signal output by the hardware timer.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the method as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method as described in any one of claims 1 to 7.

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