System on chip supporting memory access control and method of memory access control

Abstract

A system-on-chip supporting memory access control and a memory access control method are disclosed. The system-on-chip comprises: an internal memory configured to store a device configuration file of a physical device; a processor core configured to read the device configuration file from the internal memory in response to a configuration instruction initiated by a driver of the physical device for a system memory management unit; configure memory access configuration information of the physical device in the system memory management unit through an inter-process communication interface provided by a microkernel according to device configuration information in the device configuration file; and the system memory management unit configured to perform memory access control on the physical device based on the memory access configuration information of the physical device in response to a direct memory access request initiated by the physical device. The present disclosure can implement memory access control on a physical device in a system-on-chip based on a microkernel architecture.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a system-on-a-chip that supports memory access control, a memory access control method, a storage medium, and an electronic device. Background Technology

[0002] Currently, System-on-Chip (SoC) places extremely high demands on the reliability, security, and modular scalability of the operating system. Microkernel architecture, with its advantages of streamlined kernel-mode functionality, isolated user-mode services, and strong fault tolerance, has gradually become the mainstream kernel architecture for SoC.

[0003] Microkernels employ a minimalist "kernel minimization" architecture, where physical device drivers are migrated from kernel mode to user mode. This renders the original kernel-mode memory access control mechanism incapable of controlling memory access for user-mode physical device drivers, leading to memory access security risks. Therefore, a memory access control scheme for on-chip systems based on a microkernel architecture is urgently needed. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a system-on-a-chip (SoC) supporting memory access control, a memory access control method, a storage medium, and an electronic device, to implement memory access control of physical devices in a SoC based on a microkernel architecture.

[0005] A first aspect of this disclosure provides a system-on-chip that supports memory access control, comprising: The internal memory is configured to store device configuration files corresponding to the physical devices. The processor core is configured as follows: In response to a configuration instruction initiated by the driver corresponding to the physical device against the system memory management unit, the device configuration file corresponding to the physical device is read from the internal memory; Based on the device configuration information for the system memory management unit included in the device configuration file, the memory access configuration information corresponding to the physical device is configured in the system memory management unit through the inter-process communication interface provided by the microkernel; The system memory management unit is configured as follows: In response to a direct memory access request initiated by the physical device, memory access control is performed on the physical device based on the memory access configuration information corresponding to the physical device.

[0006] A second aspect of this disclosure provides a memory access control method based on a system-on-a-chip, comprising: The processor core responds to the configuration instructions initiated by the driver corresponding to the physical device against the system memory management unit, and reads the device configuration file corresponding to the physical device from the internal memory; The processor core configures the memory access configuration information corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel, based on the device configuration information for the system memory management unit included in the device configuration file. In response to a direct memory access request initiated by the physical device, the system memory management unit performs memory access control on the physical device based on the memory access configuration information corresponding to the physical device.

[0007] A third aspect of this disclosure provides a computer-readable storage medium storing a computer program that is executed by a processor to perform the system-on-a-chip memory access control method provided in the second aspect of the disclosure.

[0008] A fourth aspect of this disclosure provides an electronic device comprising: a processor; a memory for storing executable instructions of the processor; the processor being configured to read the executable instructions from the memory and execute the instructions to implement the system-on-chip memory access control method provided in the second aspect of the disclosure.

[0009] A fifth aspect of this disclosure provides a computer program product in which, when instructions in the computer program product are executed by a processor, the system-on-a-chip memory access control method provided in a second aspect of this disclosure is executed.

[0010] This disclosure provides a system-on-a-chip (SoC) supporting memory access control, a memory access control method, a storage medium, and an electronic device. The SoC includes: internal memory configured to store a device configuration file corresponding to a physical device; a processor core configured to: read the device configuration file corresponding to the physical device from the internal memory in response to a configuration instruction initiated by the driver of the physical device against the system memory management unit; and configure memory access configuration information corresponding to the physical device in the system memory management unit based on the device configuration information for the system memory management unit included in the device configuration file, through an inter-process communication interface provided by the microkernel. The system memory management unit is configured to: perform memory access control on the physical device based on the memory access configuration information corresponding to the physical device in response to a direct memory access request initiated by the physical device. In this disclosure, the device configuration file corresponding to the physical device can be flexibly configured with device configuration information for the system memory management unit. The processor core, in response to a configuration instruction initiated by the driver of the physical device against the system memory management unit, can read the device configuration information in the device configuration file corresponding to the physical device, and further configure the memory access configuration information corresponding to the physical device in the system memory management unit based on the device configuration information, through an inter-process communication interface provided by the microkernel. In this way, in a microkernel-based system-on-a-chip, although the drivers for physical devices are migrated from kernel mode to user mode, the system memory management unit can still perform memory access control on the physical devices based on the memory access configuration information corresponding to the physical devices, thereby reducing memory access security risks. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the structure of a system-on-a-chip that supports memory access control, provided by an exemplary embodiment of this disclosure.

[0012] Figure 2 This is a flowchart illustrating a system-on-a-chip memory access control method provided in an exemplary embodiment of this disclosure.

[0013] Figure 3 This is a flowchart illustrating a system-on-chip memory access control method provided in another exemplary embodiment of this disclosure.

[0014] Figure 4 This is a flowchart illustrating a system-on-chip memory access control method provided in another exemplary embodiment of this disclosure.

[0015] Figure 5 This is a flowchart illustrating a system-on-chip memory access control method provided in another exemplary embodiment of this disclosure.

[0016] Figure 6This is a flowchart illustrating a system-on-chip memory access control method provided in another exemplary embodiment of this disclosure.

[0017] Figure 7 This is a flowchart illustrating a system-on-chip memory access control method provided in another exemplary embodiment of this disclosure.

[0018] Figure 8 This is a flowchart illustrating a system-on-chip memory access control method provided in another exemplary embodiment of this disclosure.

[0019] Figure 9 This is a flowchart illustrating a system-on-chip memory access control method provided in another exemplary embodiment of this disclosure.

[0020] Figure 10 This is a flowchart illustrating a system-on-chip memory access control method provided in another exemplary embodiment of this disclosure.

[0021] Figure 11 This is a flowchart illustrating a system-on-chip memory access control method provided in another exemplary embodiment of this disclosure.

[0022] Figure 12 This is a flowchart illustrating a system-on-chip memory access control method provided in another exemplary embodiment of this disclosure.

[0023] Figure 13 This is a flowchart illustrating a system-on-chip memory access control method provided in another exemplary embodiment of this disclosure.

[0024] Figure 14 This is a flowchart illustrating a system-on-chip memory access control method provided in another exemplary embodiment of this disclosure.

[0025] Figure 15 This is a flowchart illustrating a system-on-chip memory access control method provided in another exemplary embodiment of this disclosure.

[0026] Figure 16 This is a flowchart illustrating a system-on-chip memory access control method provided in another exemplary embodiment of this disclosure.

[0027] Figure 17 This is a structural diagram of an electronic device provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0028] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0029] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0030] Application Overview The system-on-a-chip in this disclosure can be applied to electronic devices such as intelligent driving vehicle terminals, robot control terminals, and augmented reality interactive devices.

[0031] Currently, System-on-Chip (SoC) places extremely high demands on the reliability, security, and modular scalability of the operating system. Microkernel architecture, due to its advantages such as streamlined kernel-mode functionality, isolated user-mode services, and strong fault tolerance, has gradually become the mainstream kernel architecture for SoC.

[0032] Microkernels employ a minimalist "kernel minimization" architecture, where physical device drivers are migrated from kernel mode to user mode. This renders the original kernel-mode memory access control mechanism incapable of controlling memory access for user-mode physical device drivers, leading to memory access security risks. Therefore, a memory access control scheme for on-chip systems based on a microkernel architecture is urgently needed.

[0033] In this embodiment of the disclosure, the system-on-chip supporting memory access control includes: an internal memory configured to store a device configuration file corresponding to a physical device; a processor core configured to: read the device configuration file corresponding to the physical device from the internal memory in response to a configuration instruction initiated by the driver of the physical device for the system memory management unit; and configure memory access configuration information corresponding to the physical device in the system memory management unit through an inter-process communication interface provided by the microkernel, based on the device configuration information for the system memory management unit included in the device configuration file; and a system memory management unit configured to: perform memory access control on the physical device based on the memory access configuration information corresponding to the physical device in response to a direct memory access request initiated by the physical device.

[0034] Exemplary System Figure 1 This is a schematic diagram of the structure of a system-on-chip supporting memory access control provided by an exemplary embodiment of this disclosure. For example... Figure 1 As shown, the system-on-a-chip 100 supporting memory access control includes a processor core 110, an internal memory 120, and a system memory management unit 130. The processor core 110 is electrically connected to both the internal memory 120 and the system memory management unit 130.

[0035] Internal memory 120 is configured to store device configuration files corresponding to physical devices.

[0036] The processor core 110 is configured to: read the device configuration file corresponding to the physical device from the internal memory 120 in response to the configuration instruction initiated by the driver corresponding to the physical device for the system memory management unit 130; and configure the memory access configuration information corresponding to the physical device in the system memory management unit 130 through the inter-process communication interface provided by the microkernel, based on the device configuration information for the system memory management unit 130 included in the device configuration file.

[0037] The system memory management unit 130 is configured to: in response to a direct memory access request initiated by a physical device, perform memory access control on the physical device based on the memory access configuration information corresponding to the physical device.

[0038] For example, the internal memory 120 stores a device configuration file corresponding to the physical device. This device configuration file includes device configuration information for the system memory management unit 130; the device configuration information consists of configuration parameters related to configuring memory access configuration information in the system memory management unit 130. Optionally, the device configuration file can be stored using Device Tree Source (DTS) node information, or it can be stored using other suitable data structures; this disclosure does not limit this approach.

[0039] Physical devices, also known as external devices or peripherals, are hardware devices integrated within the system-on-a-chip (SoC) or connected to the SoC via an external bus that require memory access through the system memory management unit 130. These physical devices include, but are not limited to, communication devices, timing devices, multimedia devices, and storage devices.

[0040] Processor core 110 can be a general-purpose application processor core used to run a microkernel-based operating system. It is responsible for configuration instructions initiated by the driver corresponding to the physical device, parsing the device configuration file of the physical device, and proxying the execution of configuration operations on memory access configuration information in the system memory management unit 130. Processor core 110 includes, but is not limited to, a central processing unit (CPU) and a microcontroller unit (MCU).

[0041] The system memory management unit 130 is a dedicated hardware device integrated within the system-on-a-chip (SoC) to respond to direct memory access requests initiated by physical devices and to perform memory access control on the physical devices. Memory access control includes, but is not limited to, address translation and permission checks. The memory access configuration information in the system memory management unit 130 is the configuration information used to implement memory access control on the physical devices.

[0042] When a physical device needs to configure its memory access configuration information in the system memory management unit 130, the device's driver can send configuration instructions to the processor core 110. Different configuration operations require different configuration instructions. For example, establishing a binding relationship requires a binding instruction, while unbinding requires an unbinding instruction. After receiving the configuration instructions for the system memory management unit 130, the processor core 110 can read the device configuration file for the physical device from the internal memory 120. Then, the processor core 110 can parse the device configuration file to obtain the device configuration information for the system memory management unit 130. Afterward, the processor core 110 can configure the memory access configuration information for the physical device in the system memory management unit 130 using the inter-process communication (IPC) interface provided by the microkernel, based on the device configuration information. Subsequently, when the physical device needs to access memory, it can send a direct memory access request. Accordingly, after receiving a direct memory access request from a physical device, the system memory management unit 130 can perform memory access control on the physical device.

[0043] In this embodiment, the device configuration file corresponding to the physical device can be flexibly configured with device configuration information for the system memory management unit 130. In response to configuration instructions initiated by the driver corresponding to the physical device for the system memory management unit 130, the processor core 110 can read the device configuration information for the system memory management unit from the device configuration file corresponding to the physical device, and further configure the memory access configuration information corresponding to the physical device in the system memory management unit based on the device configuration information through the inter-process communication interface provided by the microkernel. Thus, in a microkernel-based system-on-a-chip, although the driver for the physical device migrates from kernel mode to user mode, the system memory management unit can still perform memory access control on the physical device based on the memory access configuration information corresponding to the physical device, thereby reducing memory access security risks.

[0044] In one optional implementation, the configuration instructions include binding instructions. The processor core 110 is specifically configured to: respond to a binding instruction initiated by the driver corresponding to the physical device against the system memory management unit 130, based on the device information of the physical device carried in the binding instruction, read the device configuration file corresponding to the physical device from the internal memory 120, and obtain the flow identifier and context descriptor of the physical device, including the device configuration information, from the device configuration file; based on the flow identifier, configure the binding relationship between the physical device and the system memory management unit 130 in the system memory management unit 130 through the inter-process communication interface provided by the microkernel, and configure the flow table entry and context descriptor corresponding to the physical device in the flow table of the system memory management unit 130. The memory access configuration information includes the binding relationship between the physical device and the system memory management unit 130, and the flow table entry and context descriptor corresponding to the physical device configured in the flow table of the system memory management unit 130.

[0045] For example, when a physical device needs to access memory through the system memory management unit 130, the physical device needs to establish a binding relationship with the system memory management unit 130 first. To establish this binding relationship, the memory access configuration information that the processor core 110 needs to configure in the system memory management unit 130 includes the binding relationship between the physical device and the system memory management unit 130, as well as the flow table entry and context descriptor corresponding to the physical device in the flow table of the system memory management unit 130. Accordingly, the driver corresponding to the physical device can send a binding instruction to the processor core 110 for the system memory management unit 130; the binding instruction may carry device information of the physical device. After receiving the binding instruction, the processor core 110 can read the device configuration file corresponding to the physical device from the internal memory 120 based on the device information of the physical device in the binding instruction; the device configuration information in the device configuration file may include the stream ID and context descriptor (CD) of the physical device. The stream ID is an identifier used by the system memory management unit 130 to uniquely distinguish different physical devices, and different physical devices correspond to different stream IDs. Context descriptors are used to define the address translation rules for physical devices. These rules include, but are not limited to, the direct translation of virtual addresses (VA) to physical addresses (PA) (i.e., Stage 1 Translation) and the translation of virtual addresses to intermediate physical addresses (IPA) before being translated to physical addresses (i.e., Stage 2 Translation).

[0046] After reading the device configuration file corresponding to the physical device, processor core 110 parses the configuration file to obtain the flow identifier and context descriptor of the physical device from the device configuration information. Then, based on the flow identifier, processor core 110 configures a global binding relationship between the physical device corresponding to the flow identifier and system memory management unit 130 in the driver of system memory management unit 130 through the inter-process communication interface provided by the microkernel, enabling system memory management unit 130 to subsequently control memory access to the physical device. In an optional embodiment, processor core 110 can establish a device structure corresponding to the physical device in the driver of system memory management unit 130. This device structure may include device information, flow identifier, context descriptor, etc. After establishing the device structure, processor core 110 can send it to the driver of the physical device, so that when the driver of the physical device initiates an unbinding request from system memory management unit 130, it can directly read the flow identifier of the physical device from the device structure. After the processor core 110 establishes a global binding relationship between the physical device and the system memory management unit 130, it can further create a flow table entry corresponding to the physical device in the flow table of the system memory management unit 130 based on the flow identifier through the inter-process communication interface provided by the microkernel, and configure the context descriptor corresponding to the physical device in the flow table entry.

[0047] In this embodiment, when binding a physical device to the system memory management unit 130, the physical device driver only needs to send a binding instruction to the processor core for the system memory management unit 130. The processor core 110 can then obtain the device information of the physical device from the binding instruction, read the device configuration file from the internal memory 120 based on the device information, and obtain the flow identifier and context descriptor of the physical device from the device configuration information in the device configuration file. Then, the processor core 110 uses the inter-process communication interface provided by the microkernel to implement the binding of the physical device to the system memory management unit 130 and the configuration operations of the flow table entries and context descriptors based on the flow identifier and context descriptor. In this way, the physical device driver can achieve binding with the system memory management unit 130 without extensive code modifications and microkernel adaptation.

[0048] In an optional implementation, the configuration instructions further include unbinding instructions. The processor core 110 is also configured to: in response to an unbinding instruction initiated by the driver corresponding to the physical device against the system memory management unit 130, based on the flow identifier of the physical device carried in the unbinding instruction, and through the inter-process communication interface provided by the microkernel, to unbind the physical device from the system memory management unit 130, and to delete the flow table entry and context descriptor corresponding to the physical device from the flow table of the system memory management unit 130.

[0049] For example, when a physical device does not need to access memory through the system memory management unit 130, the physical device can be unbound from the system memory management unit 130. The driver corresponding to the physical device can obtain the flow identifier of the physical device from the device structure corresponding to the physical device. Then, the driver corresponding to the physical device can send an unbinding instruction to the processor core 110 for the system memory management unit 130; wherein, the unbinding instruction may carry the flow identifier of the physical device. After receiving the unbinding instruction, the processor core 110 can, through the inter-process communication interface provided by the microkernel, based on the flow identifier of the physical device, remove the global binding relationship between the physical device and the system memory management unit 130 in the driver of the system memory management unit 130, so that the system memory management unit 130 will no longer perform memory access control on the physical device. In an optional embodiment, the processor core 110 can further, through the inter-process communication interface provided by the microkernel, based on the flow identifier, delete the device structure corresponding to the physical device in the driver of the system memory management unit 130, and delete the device structure corresponding to the physical device in the driver of the physical device. Subsequently, the processor core 110 can further delete the flow table entry and context descriptor corresponding to the physical device in the flow table of the system memory management unit 130 based on the flow identifier through the inter-process communication interface provided by the microkernel.

[0050] In this embodiment, when the physical device is unbound from the system memory management unit 130, the physical device driver only needs to initiate an unbinding instruction for the system memory management unit 130. The processor core 110 automatically obtains the flow identifier from the unbinding instruction and, through the inter-process communication interface provided by the microkernel, realizes the unbinding of the physical device from the system memory management unit 130 and the deletion of flow table entries and context descriptors. In this way, the physical device driver can achieve unbinding from the system memory management unit 130 without extensive code modifications and microkernel adaptation.

[0051] In an optional implementation, the configuration instructions further include address mapping initialization instructions. The processor core 110 is specifically configured to: respond to an address mapping initialization instruction initiated by the driver corresponding to the physical device against the system memory management unit 130; based on the device information of the physical device carried in the address mapping initialization instruction; read the device configuration file of the physical device from the internal memory 120; and obtain the address mapping method and address mapping information corresponding to the physical device, including the device configuration information, from the device configuration file; based on the address mapping method and address mapping information, initialize the address mapping configuration information corresponding to the physical device in the system memory management unit 130 through the inter-process communication interface provided by the microkernel. The address mapping information is used to indicate the address mapping relationship between virtual addresses and physical addresses, and the memory access configuration information includes the address mapping configuration information.

[0052] For example, after a physical device establishes a binding relationship with the system memory management unit 130, the physical device needs to initialize the address mapping configuration information corresponding to the physical device in the system memory management unit 130. At this time, the memory access configuration information that the processor core 110 needs to configure in the system memory management unit 130 includes the address mapping configuration information corresponding to the physical device. Accordingly, the driver corresponding to the physical device can send an address mapping initialization instruction to the processor core 110 for the system memory management unit 130; wherein, the address mapping initialization instruction carries the device information of the physical device. After receiving the address mapping initialization instruction, the processor core 110 can further read the device configuration file corresponding to the physical device from the internal memory 120 based on the device information of the physical device. The device configuration information in the device configuration file can include the address mapping method and address mapping information corresponding to the physical device. The address mapping method is used to indicate the address mapping method between the virtual address and the physical address, which can include three address mapping methods: static address mapping method, dynamic address mapping method, and dynamic-static address mapping method. The address mapping information is used to indicate the address mapping relationship between the virtual address and the physical address, which can include static address mapping relationship, dynamic address mapping relationship, and dynamic-static address mapping relationship. In static address mapping, the mapping between virtual addresses and physical addresses remains fixed. In dynamic address mapping, the mapping between virtual addresses and physical addresses changes dynamically. In a combination of static and dynamic address mapping, some virtual address mappings remain fixed while others change dynamically. Static address mapping typically corresponds to static address mapping relationships, dynamic address mapping typically corresponds to dynamic address mapping relationships, and static-dynamic address mapping typically corresponds to static-dynamic address mapping relationships.

[0053] After reading the device configuration file of the physical device, the processor core 110 can parse the device configuration file and read the address mapping method and address mapping information corresponding to the physical device from the device configuration information in the device configuration file. Then, the processor core 110 can initialize the address mapping configuration information corresponding to the physical device in the system memory management unit 130 based on the address mapping method and address mapping information through the inter-process communication interface provided by the microkernel. For different address mapping methods and address mapping information, the initialization operation of the address mapping configuration information corresponding to the physical device in the system memory management unit 130 by the processor core 110 is different. The detailed processing process of the processor core 110 initializing the address mapping configuration information corresponding to the physical device in the system memory management unit 130 will be described later in this disclosure, and will not be repeated here.

[0054] It should be noted that after the processor core 100 initializes the address mapping configuration information corresponding to the physical device, it can update the device structure corresponding to the physical device in the driver of the system memory management unit 130 based on the address mapping method and address mapping information corresponding to the physical device. After the processor core 110 updates the device structure corresponding to the physical device, it can send the device structure to the driver corresponding to the physical device.

[0055] In this embodiment, different address mapping methods and their corresponding address mapping information can be flexibly configured in the device configuration files of different physical devices. Subsequently, when the physical device driver initializes the address mapping of the system memory management unit 130, the physical device driver only needs to initiate an address mapping initialization instruction for the system memory management unit 130. The processor core 110 automatically obtains the address mapping method and its corresponding address mapping information from the physical device's device configuration file, and initializes the address mapping configuration information corresponding to the physical device based on the address mapping method and its corresponding address mapping information through the inter-process communication interface provided by the microkernel. In this way, under the microkernel architecture, the system memory management unit 130 can support multiple address mapping methods.

[0056] In one optional implementation, the address mapping information includes a static address mapping relationship between virtual addresses and physical addresses, and the address mapping configuration information includes the page table corresponding to the physical device. The processor core 110 is specifically configured to: when the address mapping method is determined to be static address mapping, write the static address mapping relationship between virtual addresses and physical addresses into the page table corresponding to the physical device in the system memory management unit 130 through the inter-process communication interface provided by the microkernel.

[0057] For example, after processor core 110 obtains the address mapping method and address mapping information corresponding to the physical device, if the address mapping method corresponding to the physical device is a static address mapping method, then the address mapping information corresponding to the physical device includes the static address mapping relationship between the virtual address and the physical address. This static address mapping relationship can be represented as a one-to-one mapping relationship between the virtual address and the physical address. For example, VA1 PA1, VA2 PA2…VA 10 PA 10 Here, VA represents the virtual address and PA represents the physical address. This static address mapping relationship can also be represented as a mapping relationship between the starting address of the virtual address, the starting address of the physical address, and the address mapping size. For example, VA start = VA1, PA start = PA1, Add size =10, where VA start PA represents the starting address of the virtual address. start Indicates the starting address of the physical address, Add size This indicates the size of the address mapping. The virtual address and the physical address can be the same or different; this disclosure does not limit this.

[0058] Because the mapping relationship between virtual and physical addresses is fixed in static address mapping, processor core 110 can directly write the static address mapping relationship into the page table corresponding to the physical device in the system memory management unit 130 when initializing the address mapping configuration information corresponding to the physical device. At this time, the address mapping configuration information initialized by processor core 110 in the system memory management unit 130 is the page table corresponding to the physical device. Accordingly, processor core 110 can convert the static address mapping relationship between virtual and physical addresses into page table entries. Each page table entry includes a virtual address and a corresponding physical address. Then, processor core 110 can write the converted page table entries into the page table corresponding to the physical device through the inter-process communication interface provided by the microkernel.

[0059] In this embodiment, the device configuration file of the physical device can be flexibly configured with static address mapping methods and static address mapping relationships between virtual addresses and physical addresses. Subsequently, when the physical device driver initializes the address mapping of the system memory management unit 130, the physical device driver only needs to initiate an address mapping initialization instruction for the system memory management unit 130. The processor core 110 automatically obtains the static address mapping method and static address mapping relationship from the device configuration file of the physical device, and writes the static address mapping relationship into the page table corresponding to the physical device through the inter-process communication interface provided by the microkernel based on the static address mapping method. In this way, under the microkernel architecture, the system memory management unit 130 can support static address mapping methods.

[0060] In one optional implementation, the address mapping information includes a set of virtual addresses, and the address mapping configuration information includes a virtual address space manager corresponding to the physical device. The processor core 110 is specifically configured to: when the address mapping method is determined to be dynamic address mapping, create a virtual address space manager corresponding to the physical device in the system memory management unit 130 based on the virtual address set through the inter-process communication interface provided by the microkernel. The virtual address space manager is used to dynamically allocate virtual addresses to the physical device based on the virtual address set.

[0061] For example, after processor core 110 obtains the address mapping method and address mapping information corresponding to the physical device, if the address mapping method corresponding to the physical device is a dynamic address mapping method, then the address mapping information corresponding to the physical device includes a set of virtual addresses. This set of virtual addresses can be represented as several virtual addresses, either consecutively or non-consecutively. For example, VA1, VA2…VA… 10 This set of virtual addresses can also be represented as the starting address of the virtual address space and the size of the virtual address space. For example, VA start = VA1, Add size =10.

[0062] Because in dynamic address mapping, the virtual address set only includes virtual addresses and not the mapping relationship between virtual addresses and physical addresses, the processor core 110 can create a virtual address space manager for the physical device based on the virtual address set when initializing the address mapping configuration information corresponding to the physical device. The virtual address space manager is used to dynamically allocate virtual addresses to the physical device based on the virtual address set. At this time, the address mapping configuration information for the physical device initialized by the processor core 110 in the system memory management unit 130 is the virtual address space manager for the physical device. Correspondingly, the processor core 110 can create a virtual address space manager for the physical device in the system memory management unit 130 based on the virtual address set through the inter-process communication interface provided by the microkernel. The virtual addresses dynamically managed by this virtual address space manager are the virtual addresses in the virtual address set.

[0063] It should be noted that, under dynamic address mapping, the mapping relationship between virtual addresses and physical addresses changes dynamically. Therefore, the processor core 110 must determine the dynamic mapping relationship between virtual addresses and physical addresses before it can write the dynamic address mapping relationship into the page table corresponding to the physical device in the system memory management unit 130.

[0064] In this embodiment, the device configuration file of the physical device can be flexibly configured with dynamic address mapping and virtual address sets. Subsequently, when the physical device driver initializes the address mapping of the system memory management unit 130, the physical device driver only needs to issue an address mapping initialization instruction for the system memory management unit 130. The processor core 110 automatically obtains the dynamic address mapping and virtual address set from the device configuration file of the physical device, and based on the dynamic address mapping, through the inter-process communication interface provided by the microkernel, creates a virtual address space manager for dynamically allocating virtual addresses for the physical device based on the virtual address set. In this way, under the microkernel architecture, the system memory management unit 130 can support dynamic address mapping.

[0065] In one optional implementation, the address mapping information includes a static address mapping relationship between virtual addresses and physical addresses, and a set of virtual addresses. The address mapping configuration information includes a page table corresponding to the physical device and a virtual address space manager. The processor core 110 is specifically configured to: when the address mapping method is determined to be dynamic-static address mapping, construct a static address mapping relationship between virtual addresses and physical addresses in the page table corresponding to the physical device in the system memory management unit 130 through the inter-process communication interface provided by the microkernel; and create a virtual address space manager corresponding to the physical device in the system memory management unit 130 based on the virtual address set. The virtual address space manager is used to dynamically allocate virtual addresses to the physical device based on the virtual address set.

[0066] For example, after the processor core 110 obtains the address mapping method and address mapping information corresponding to the physical device, if the address mapping method corresponding to the physical device is a dynamic-static address mapping method, then the address mapping information corresponding to the physical device includes the static address mapping relationship between virtual addresses and physical addresses and the set of virtual addresses.

[0067] Because the mapping relationship between virtual addresses and physical addresses is fixed in static address mapping, while the virtual address set only includes virtual addresses and not the mapping relationship between virtual addresses and physical addresses, processor core 110 can directly write the static address mapping relationship into the page table of the physical device in the system memory management unit 130 when initializing the address mapping configuration information corresponding to the physical device, and create a virtual address space manager for the physical device based on the virtual address set. At this time, the address mapping configuration information for the physical device initialized by processor core 110 in the system memory management unit 130 consists of the page table and the virtual address space manager for the physical device. Correspondingly, for static address mapping, processor core 110 can convert the static address mapping relationship between virtual addresses and physical addresses into page table entries, and write the converted page table entries into the page table of the physical device through the inter-process communication interface provided by the microkernel. For virtual address sets, processor core 110 can create a virtual address space manager for the physical device in the system memory management unit 130 based on the virtual address set through the inter-process communication interface provided by the microkernel.

[0068] In this embodiment, the device configuration file of the physical device can be flexibly configured with dynamic and static address mapping methods, static address mapping relationships between virtual and physical addresses, and virtual address sets. Subsequently, when the physical device driver initializes the address mapping of the system memory management unit 130, the physical device driver only needs to initiate an address mapping initialization instruction for the system memory management unit 130. The processor core 110 automatically obtains the dynamic and static address mapping methods, static address mapping relationships, and virtual address sets from the physical device's device configuration file, and based on the dynamic and static address mapping methods, writes the static address mapping relationships into the page table corresponding to the physical device and creates a virtual address space manager for dynamically allocating virtual addresses for the physical device through the inter-process communication interface provided by the microkernel. In this way, under the microkernel architecture, the system memory management unit 130 can support dynamic and static address mapping methods.

[0069] In an optional implementation, the configuration instructions further include address mapping association instructions. The processor core 110 is also configured to: in response to an address mapping association instruction initiated by the driver corresponding to the physical device against the system memory management unit 130, determine the virtual address corresponding to the physical address based on the physical address carried in the address mapping association instruction and the address mapping method of the physical device; and transmit the virtual address to the physical device.

[0070] For example, after the physical device initializes its corresponding address mapping configuration information, the driver for the physical device can send an address mapping association instruction to the processor core 110 for the system memory management unit 130. This address mapping association instruction carries the physical address and the address mapping method of the physical device. The physical address is the hardware address of the physical device to be accessed in internal memory. After receiving the address mapping association instruction, the processor core 110 can determine the virtual address corresponding to the physical address based on the address mapping method and physical address carried in the instruction, and send the determined virtual address to the physical device. Subsequently, when the physical device needs to access memory, it can send a direct memory access request carrying the virtual address. After receiving the direct memory access request from the physical device, the system memory management unit 130 can complete the address translation from virtual address to physical address based on the address mapping relationship stored in the page table corresponding to the physical device, thereby realizing memory access control of the physical device. The process by which the processor core 110 determines the virtual address corresponding to the physical address differs depending on the address mapping method. The following embodiments of this disclosure will describe in detail the process of determining the virtual address corresponding to the physical address of the processor core 110 for different address mapping methods, which will not be repeated here.

[0071] In this embodiment of the disclosure, when a physical device needs to access memory through the system memory management unit 130, the physical device driver only needs to initiate an address mapping association instruction for the system memory management unit 130. The processor core 110 automatically obtains the physical address and address mapping method from the address mapping association instruction, determines the virtual address corresponding to the physical address based on the physical address and address mapping method through the inter-process communication interface provided by the microkernel, and sends the determined virtual address to the physical device. In this way, under the microkernel architecture, the system memory management unit 130 can support multiple address mapping methods.

[0072] In one optional implementation, the processor core 110 is specifically configured to: when the address mapping method is determined to be static address mapping, read the static address mapping relationship corresponding to the physical device in the page table corresponding to the physical device in the system memory management unit 130; determine the virtual address corresponding to the physical address based on the static address mapping relationship; and transmit the virtual address to the physical device.

[0073] For example, after the processor core 110 obtains the address mapping method corresponding to the physical device, if the address mapping method corresponding to the physical device is a static address mapping method, it means that the page table corresponding to the physical device in the system memory management unit 130 already stores the static address mapping relationship between the virtual address and the physical address. Accordingly, in response to the address mapping method being a static address mapping method, the processor core 110 can use the inter-process communication interface provided by the microkernel to query the virtual address corresponding to the physical address from the page table corresponding to the physical device based on the physical address, and send the queried virtual address to the physical device. Subsequently, when the physical device needs to access memory, the physical device can send a direct memory access request carrying the virtual address. After receiving the direct memory access request from the physical device, the system memory management unit 130 can complete the address translation from virtual address to physical address based on the static address mapping relationship stored in the page table corresponding to the physical device, thereby realizing memory access control of the physical device.

[0074] In this embodiment of the disclosure, when the physical device driver performs address mapping association with the system memory management unit 130, the physical device driver only needs to initiate an address mapping association instruction for the system memory management unit 130. The processor core 110 automatically obtains the static address mapping method and the physical address from the address mapping association instruction. Then, the processor core 110 can, based on the static address mapping method, query the virtual address corresponding to the physical address from the static address mapping relationship stored in the page table corresponding to the physical device through the inter-process communication interface provided by the microkernel, and transmit the virtual address to the physical device. In this way, under the microkernel architecture, the system memory management unit 130 can support the static address mapping method.

[0075] In one optional implementation, processor core 110 is specifically configured to: when the address mapping method is determined to be dynamic address mapping, determine the virtual address corresponding to the physical address based on the virtual address space manager corresponding to the physical device in system memory management unit 130; and transmit the virtual address to the physical device. Processor core 110 is also configured to: construct a dynamic address mapping relationship between the virtual address and the physical address in the page table corresponding to the physical device in system memory management unit 130 through the inter-process communication interface provided by the microkernel.

[0076] For example, after the processor core 110 obtains the address mapping method corresponding to the physical device, if the address mapping method corresponding to the physical device is a dynamic address mapping method, it means that the page table corresponding to the physical device in the system memory management unit 130 does not store a dynamic address mapping relationship between the virtual address and the physical address. Accordingly, in response to the address mapping method being a dynamic address mapping method, the processor core 110 needs to first dynamically allocate a virtual address for the physical address through the virtual address space manager corresponding to the physical device, and send the virtual address to the physical device. At this time, since a dynamic address mapping relationship is established between the virtual address and the physical address, the processor core 110 can further convert the dynamic address mapping relationship between the virtual address and the physical address into a page table entry, and write the converted page table entry into the page table corresponding to the physical device. Subsequently, when the physical device needs to access memory, the physical device can send a direct memory access request carrying the virtual address. After receiving the direct memory access request from the physical device, the system memory management unit 130 can complete the address translation from virtual address to physical address based on the dynamic address mapping relationship stored in the page table corresponding to the physical device, thereby realizing memory access control of the physical device.

[0077] In this embodiment, when the physical device driver performs address mapping association with the system memory management unit 130, the physical device driver only needs to initiate an address mapping association instruction for the system memory management unit 130. The processor core 110 automatically obtains the dynamic address mapping method and physical address from the address mapping association instruction. Then, the processor core 110 can dynamically allocate a virtual address for the physical address through the virtual address space manager corresponding to the physical device and send the virtual address to the physical device. Afterwards, the processor core 110 can further write the dynamic address mapping relationship between the virtual address and the physical address into the page table corresponding to the physical device of the system memory management unit 130 through the inter-process communication interface provided by the microkernel. In this way, under the microkernel architecture, the system memory management unit 130 can support dynamic address mapping.

[0078] In one optional implementation, processor core 110 is specifically configured to: when the address mapping method is determined to be dynamic-static address mapping, in response to determining that a physical address belongs to a physical address in the static address mapping relationship based on the static address mapping relationship, determine the virtual address corresponding to the physical address from the static address mapping relationship, and transmit the virtual address to the physical device; in response to determining that a physical address does not belong to a physical address in the static address mapping relationship based on the static address mapping relationship, determine the virtual address corresponding to the physical address based on the virtual address space manager corresponding to the physical device in the system memory management unit 130; and transmit the virtual address to the physical device. Processor core 110 is also configured to: construct a dynamic address mapping relationship between virtual addresses and physical addresses in the page table corresponding to the physical device in the system memory management unit 130 through the inter-process communication interface provided by the microkernel.

[0079] For example, after processor core 110 obtains the address mapping method corresponding to the physical device, if the address mapping method corresponding to the physical device is a dynamic-static address mapping method, it means that the page table corresponding to the physical device in the system memory management unit 130 stores a static address mapping relationship between virtual addresses and physical addresses, but does not store a dynamic address mapping relationship between virtual addresses and physical addresses. Since the physical address may or may not belong to the static address mapping relationship, in response to the address mapping method being a dynamic-static address mapping method, processor core 110 can first query the virtual address corresponding to the physical address from the page table corresponding to the physical device based on the physical address through the inter-process communication interface provided by the microkernel. If processor core 110 finds the virtual address corresponding to the physical address, it means that the physical address belongs to the physical address in the static address mapping relationship. At this time, processor core 110 can send the queried virtual address to the physical device. If processor core 110 does not find the virtual address corresponding to the physical address in the page table corresponding to the physical device, it means that the physical address does not belong to the physical address in the static address mapping relationship. At this point, processor core 110 can first dynamically allocate a virtual address for the physical address through the virtual address space manager corresponding to the physical device, and then send the virtual address to the physical device. Since a dynamic address mapping relationship is established between the virtual address and the physical address, processor core 110 can further write this dynamic address mapping relationship into the page table corresponding to the physical device. Subsequently, when the physical device needs to access memory, it can send a direct memory access request carrying the virtual address. After receiving the direct memory access request from the physical device, system memory management unit 130 can complete the address translation from virtual address to physical address based on the static or dynamic address mapping relationship stored in the page table corresponding to the physical device, thereby realizing memory access control of the physical device.

[0080] In this embodiment, when the physical device driver performs address mapping association with the system memory management unit 130, the physical device driver only needs to initiate an address mapping association instruction for the system memory management unit 130. The processor core 110 automatically obtains the dynamic / static address mapping method and the physical address from the address mapping association instruction. For physical addresses belonging to a static address mapping relationship, the processor core 110 queries the virtual address corresponding to the physical address from the static address mapping relationship stored in the page table corresponding to the physical device through the inter-process communication interface provided by the microkernel, and transmits the virtual address to the physical device. For physical addresses belonging to a dynamic address mapping relationship, the processor core 110 dynamically allocates a corresponding virtual address for the physical address through the virtual address space manager corresponding to the physical device, and sends the virtual address to the physical device. Then, the processor core 110 can further write the dynamic address mapping relationship between the virtual address and the physical address into the page table corresponding to the physical device of the system memory management unit 130 through the inter-process communication interface provided by the microkernel. Thus, under the microkernel architecture, the system memory management unit 130 can support both dynamic and static address mapping methods.

[0081] In an optional implementation, the configuration instructions further include an address mapping release instruction. The processor core 110 is also configured to: in response to an address mapping release instruction initiated by the driver corresponding to the physical device against the system memory management unit 130, based on the virtual address and the address mapping method corresponding to the physical device carried in the address mapping release instruction, delete the static address mapping relationship and / or dynamic address mapping relationship associated with the virtual address from the page table corresponding to the physical device in the system memory management unit 130 through the inter-process communication interface provided by the microkernel.

[0082] For example, when a physical device no longer needs to access memory through the system memory management unit 130, the driver corresponding to the physical device can send an address mapping release instruction to the processor core 110 for the system memory management unit 130. This address mapping release instruction carries the address mapping method of the virtual address and the physical device. The virtual address is the virtual address carried in the direct memory access request sent by the physical device. After receiving the address mapping release instruction, the processor core 110 can, based on the address mapping method and the virtual address, delete the static or dynamic address mapping relationship associated with the virtual address from the page table corresponding to the physical device through the inter-process communication interface provided by the microkernel. Subsequently, if the physical device sends a direct memory access request carrying this virtual address, since the page table corresponding to the physical device does not store the static or dynamic address mapping relationship associated with the virtual address, the system memory management unit 130 cannot perform address translation from virtual address to physical address, and the physical device cannot access the memory space corresponding to that physical address in its internal memory. The process by which processor core 110 deletes static or dynamic address mapping relationships associated with virtual addresses from the page table corresponding to the physical device differs depending on the address mapping method. This disclosure will subsequently describe in detail the process by which processor core 110 deletes static or dynamic address mapping relationships associated with virtual addresses from the page table corresponding to the physical device for different address mapping methods; these details will not be repeated here.

[0083] In this embodiment of the disclosure, when the physical device no longer needs to access memory through the system memory management unit 130, the physical device driver only needs to initiate an address mapping release instruction for the system memory management unit 130. The processor core 110 automatically obtains the virtual address and address mapping method from the address mapping release instruction, and through the inter-process communication interface provided by the microkernel, deletes the static address mapping relationship and / or dynamic address mapping relationship associated with the virtual address from the page table corresponding to the physical device based on the virtual address and address mapping method. In this way, under the microkernel architecture, the system memory management unit 130 can support the release of multiple address mapping methods.

[0084] In one alternative implementation, the processor core 110 is specifically configured to: when the address mapping method is determined to be static address mapping, delete the static address mapping relationship associated with the virtual address from the page table corresponding to the physical device in the system memory management unit 130 through the inter-process communication interface provided by the microkernel.

[0085] For example, after the processor core 110 obtains the address mapping method corresponding to the physical device, if the address mapping method corresponding to the physical device is a static address mapping method, it means that the page table corresponding to the physical device in the system memory management unit 130 already stores the static address mapping relationship between the virtual address and the physical address. Accordingly, in response to the address mapping method being a static address mapping method, the processor core 110 can directly delete the static address mapping relationship associated with the virtual address in the page table corresponding to the physical device through the inter-process communication interface provided by the microkernel. Subsequently, if the physical device sends a direct memory access request carrying the virtual address, since the page table corresponding to the physical device does not store the static address mapping relationship associated with the virtual address, the system memory management unit 130 cannot perform address translation from virtual address to physical address, and the physical device cannot access the memory space corresponding to the physical address in the internal memory.

[0086] In this embodiment of the disclosure, when the physical device driver unmaps the address of the system memory management unit 130, the physical device driver only needs to initiate an address mapping unmapping instruction for the system memory management unit 130. The processor core 110 automatically obtains the static address mapping method and the virtual address from the address mapping unmapping instruction. Then, the processor core 110 can, based on the static address mapping method, delete the static address mapping relationship associated with the virtual address from the static address mapping relationship stored in the page table corresponding to the physical device through the inter-process communication interface provided by the microkernel. In this way, under the microkernel architecture, the system memory management unit 130 can support the unmapping of the static address mapping method.

[0087] In one optional implementation, processor core 110 is specifically configured to: when the address mapping method is determined to be dynamic address mapping, delete the dynamic address mapping relationship associated with the virtual address from the page table corresponding to the physical device in the system memory management unit 130 through the inter-process communication interface provided by the microkernel. Processor core 110 is also configured to: reclaim the virtual address to the virtual address space manager corresponding to the physical device.

[0088] For example, after the processor core 110 obtains the address mapping method corresponding to the physical device, if the address mapping method corresponding to the physical device is a dynamic address mapping method, it means that the page table corresponding to the physical device in the system memory management unit 130 already stores the dynamic address mapping relationship between the virtual address and the physical address. Accordingly, in response to the address mapping method being a dynamic address mapping method, the processor core 110 can first directly delete the dynamic address mapping relationship associated with the virtual address in the page table corresponding to the physical device through the inter-process communication interface provided by the microkernel. In order to enable the virtual address to be dynamically reassigned to other physical addresses, the processor core 110 can further reclaim the virtual address through the virtual address space manager corresponding to the physical device. Subsequently, if the physical device sends a direct memory access request carrying the virtual address, since the page table corresponding to the physical device does not store the dynamic address mapping relationship associated with the virtual address, the system memory management unit 130 cannot directly perform address translation from virtual address to physical address, and the physical device cannot directly access the memory space corresponding to the physical address in the internal memory.

[0089] In this embodiment, when the physical device driver unmaps the address of the system memory management unit 130, the physical device driver only needs to initiate an address mapping unmapping instruction for the system memory management unit 130. The processor core 110 automatically obtains the dynamic address mapping method and the virtual address from the address mapping unmapping instruction. Then, based on the dynamic address mapping method, the processor core 110 can delete the dynamic address mapping relationship associated with the virtual address from the dynamic address mapping relationship stored in the page table corresponding to the physical device through the inter-process communication interface provided by the microkernel. Furthermore, the processor core 110 can further reclaim the virtual address through the virtual address space manager corresponding to the physical device. In this way, under the microkernel architecture, the system memory management unit 130 can support the unmapping of the dynamic address mapping method.

[0090] In one optional implementation, processor core 110 is specifically configured to: when the address mapping method is determined to be dynamic-static address mapping, in response to determining that a virtual address belongs to a virtual address in a static address mapping relationship based on the static address mapping relationship, delete the static address mapping relationship associated with the virtual address from the page table corresponding to the physical device of the system memory management unit 130 through the inter-process communication interface provided by the microkernel; and in response to determining that a virtual address does not belong to a virtual address in a static address mapping relationship based on the static address mapping relationship, delete the dynamic address mapping relationship associated with the virtual address from the page table corresponding to the physical device of the system memory management unit 130 through the inter-process communication interface provided by the microkernel. Processor core 110 is also configured to: reclaim the virtual address to the virtual address space manager corresponding to the physical device.

[0091] For example, after processor core 110 obtains the address mapping method corresponding to the physical device, if the address mapping method corresponding to the physical device is a dynamic-static address mapping method, it means that the page table corresponding to the physical device in the system memory management unit 130 already stores the static address mapping relationship and the dynamic address mapping relationship between the virtual address and the physical address. Since the virtual address may belong to the virtual address in the static address mapping relationship or may not belong to the virtual address in the static address mapping relationship, in response to the address mapping method being a dynamic-static address mapping method, processor core 110 can first query the static address mapping relationship associated with the virtual address from the page table corresponding to the physical device in the system memory management unit 130 through the inter-process communication interface provided by the microkernel. If processor core 110 finds that the virtual address is associated with a static address mapping relationship, it means that the virtual address belongs to the virtual address in the static address mapping relationship. At this time, processor core 110 can directly delete the static address mapping relationship associated with the virtual address in the page table corresponding to the physical device through the inter-process communication interface provided by the microkernel. If processor core 110 does not find a static address mapping associated with the virtual address, it means that the virtual address does not belong to the static address mapping. In this case, processor core 110 can first use the inter-process communication interface provided by the microkernel to directly delete the dynamic address mapping associated with the virtual address from the page table corresponding to the physical device. Simultaneously, to enable the virtual address to be dynamically reassigned to other physical addresses, processor core 110 can further reclaim the virtual address through the virtual address space manager corresponding to the physical device. Subsequently, if the physical device sends a direct memory access request carrying the virtual address, since the page table corresponding to the physical device does not store a static or dynamic address mapping associated with the virtual address, the system memory management unit 130 cannot directly perform address translation from virtual address to physical address, and the physical device cannot directly access the memory space corresponding to the physical address in the internal memory.

[0092] In this embodiment, when the physical device driver removes the address mapping of the system memory management unit 130, the physical device driver only needs to initiate an address mapping removal instruction for the system memory management unit 130. The processor core 110 automatically obtains the dynamic / static address mapping method and the virtual address from the address mapping removal instruction. For virtual addresses belonging to static address mapping relationships, the processor core 110 can directly delete the static address mapping relationship associated with the virtual address in the page table corresponding to the physical device through the inter-process communication interface provided by the microkernel. For virtual addresses belonging to dynamic address mapping relationships, the processor core 110 can directly delete the dynamic address mapping relationship associated with the virtual address in the page table corresponding to the physical device through the inter-process communication interface provided by the microkernel, and reclaim the virtual address through the virtual address space manager corresponding to the physical device. Thus, under the microkernel architecture, the system memory management unit 130 can support the removal of both dynamic and static address mapping methods.

[0093] Exemplary methods Figure 2 This is a flowchart illustrating a system-on-a-chip memory access control method provided in an exemplary embodiment of this disclosure. This embodiment can be applied to electronic devices, such as… Figure 2 As shown, it includes the following steps: Step 201: The processor core responds to the configuration instructions initiated by the driver corresponding to the physical device against the system memory management unit, and reads the device configuration file corresponding to the physical device from the internal memory.

[0094] Step 202: Based on the device configuration information for the system memory management unit included in the device configuration file, the processor core configures the memory access configuration information corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel.

[0095] Step 203: In response to the direct memory access request initiated by the physical device, the system memory management unit performs memory access control on the physical device based on the memory access configuration information corresponding to the physical device.

[0096] In one alternative implementation, the configuration instructions include binding instructions. For example... Figure 3 As shown above, in the above Figure 2 Based on the illustrated embodiment, step 202 may include the following steps: Step 301: The processor core responds to the binding instruction initiated by the driver corresponding to the physical device against the system memory management unit. Based on the device information of the physical device carried in the binding instruction, the device configuration file corresponding to the physical device is read from the internal memory, and the flow identifier and context descriptor of the physical device, which are included in the device configuration information, are obtained from the device configuration file.

[0097] Step 302: Based on the flow identifier, the processor core configures the binding relationship between the physical device and the system memory management unit (MMU) through the inter-process communication interface provided by the microkernel. It also configures the corresponding flow table entry and context descriptor for the physical device in the flow table of the MMU. The memory access configuration information includes the binding relationship between the physical device and the MMU, as well as the flow table entry and context descriptor for the physical device configured in the flow table of the MMU.

[0098] In one alternative implementation, the configuration instructions also include unbinding instructions. For example... Figure 4 As shown above, in the above Figure 2 Based on the illustrated embodiment, the system-on-chip memory access control method may further include the following steps: Step 401: In response to the unbinding instruction initiated by the driver corresponding to the physical device against the system memory management unit by the processor core, based on the flow identifier of the physical device carried in the unbinding instruction, the binding relationship between the physical device and the system memory management unit is released in the system memory management unit through the inter-process communication interface provided by the microkernel, and the flow table entry and context descriptor corresponding to the physical device are deleted in the flow table of the system memory management unit.

[0099] In one alternative implementation, the configuration instructions also include address mapping initialization instructions. For example... Figure 5 As shown above, in the above Figure 2 Based on the illustrated embodiment, step 202 may include the following steps: Step 501: The processor core responds to the address mapping initialization instruction initiated by the driver corresponding to the physical device against the system memory management unit. Based on the device information of the physical device carried in the address mapping initialization instruction, the device configuration file of the physical device is read from the internal memory, and the address mapping method and address mapping information corresponding to the physical device are obtained from the device configuration information, including the device configuration information.

[0100] Step 502: Based on the address mapping method and address mapping information, the processor core initializes the address mapping configuration information corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel. The address mapping information indicates the address mapping relationship between virtual addresses and physical addresses, and the memory access configuration information includes the address mapping configuration information.

[0101] In one optional implementation, the address mapping information includes a static address mapping relationship between virtual addresses and physical addresses, and the address mapping configuration information includes the page table corresponding to the physical device. For example... Figure 6 As shown above, in the above Figure 5 Based on the illustrated embodiment, step 502 may include the following steps: Step 601: When the processor core determines that the address mapping method is static address mapping, it writes the static address mapping relationship between the virtual address and the physical address into the page table corresponding to the physical device of the system memory management unit through the inter-process communication interface provided by the microkernel.

[0102] In one optional implementation, the address mapping information includes a set of virtual addresses, and the address mapping configuration information includes a virtual address space manager corresponding to the physical device. For example... Figure 7 As shown above, in the above Figure 5 Based on the illustrated embodiment, step 502 may include the following steps: Step 701: If the processor core determines that the address mapping method is dynamic address mapping, it creates a virtual address space manager for the physical device in the system memory management unit based on the virtual address set via the inter-process communication interface provided by the microkernel. The virtual address space manager is used to dynamically allocate virtual addresses to the physical device based on the virtual address set.

[0103] In one optional implementation, the address mapping information includes a static address mapping relationship between virtual addresses and physical addresses and a set of virtual addresses, while the address mapping configuration information includes the page table corresponding to the physical device and the virtual address space manager. For example... Figure 8 As shown above, in the above Figure 5 Based on the illustrated embodiment, step 502 may include the following steps: Step 801: If the processor core determines that the address mapping method is dynamic-static address mapping, it uses the inter-process communication interface provided by the microkernel to construct a static address mapping relationship between virtual addresses and physical addresses in the page table corresponding to the physical device in the system memory management unit. Based on the virtual address set, it also creates a virtual address space manager corresponding to the physical device in the system memory management unit. The virtual address space manager is used to dynamically allocate virtual addresses to the physical device based on the virtual address set.

[0104] In an alternative implementation, the configuration instructions also include address mapping association instructions. For example... Figure 9 As shown above, in the above Figure 2 Based on the illustrated embodiment, the system-on-chip memory access control method may further include the following steps: Step 901: The processor core responds to the address mapping association instruction initiated by the driver corresponding to the physical device against the system memory management unit, and determines the virtual address corresponding to the physical address based on the physical address carried in the address mapping association instruction and the address mapping method of the physical device.

[0105] Step 902: The virtual address is transmitted to the physical device via the processor core.

[0106] In one alternative implementation, such as Figure 10 As shown above, in the above Figure 9 Based on the illustrated embodiment, steps 901 and 902 may include the following steps: Step 1001: When the processor core determines that the address mapping method is static address mapping, it reads the static address mapping relationship corresponding to the physical device from the page table corresponding to the physical device in the system memory management unit.

[0107] Step 1002: Determine the virtual address corresponding to the physical address based on the static address mapping relationship through the processor core.

[0108] Step 1003: The virtual address is transmitted to the physical device through the processor core.

[0109] In one alternative implementation, such as Figure 11 As shown above, in the above Figure 9 Based on the illustrated embodiment, steps 901 and 902 may include the following steps: Step 1101: When the processor core determines that the address mapping method is dynamic address mapping, it determines the virtual address corresponding to the physical address based on the virtual address space manager corresponding to the physical device in the system memory management unit.

[0110] Step 1102: The virtual address is transmitted to the physical device through the processor core.

[0111] Step 1103: Through the inter-process communication interface provided by the microkernel, the processor core constructs a dynamic address mapping relationship between virtual addresses and physical addresses in the page table corresponding to the physical device in the system memory management unit.

[0112] In one alternative implementation, such as Figure 12 As shown above, in the above Figure 9Based on the illustrated embodiment, steps 901 and 902 may include the following steps: Step 1201: When the processor core determines that the address mapping method is dynamic-static address mapping, in response to the determination that the physical address belongs to the physical address in the static address mapping relationship based on the static address mapping relationship, the virtual address corresponding to the physical address is determined from the static address mapping relationship, and the virtual address is transmitted to the physical device.

[0113] Step 1202: The processor core responds to physical addresses that are not in the static address mapping relationship, and determines the virtual address corresponding to the physical address based on the virtual address space manager corresponding to the physical device in the system memory management unit.

[0114] Step 1203: The virtual address is transmitted to the physical device through the processor core.

[0115] Step 1204: Through the inter-process communication interface provided by the microkernel, the processor core constructs a dynamic address mapping relationship between virtual addresses and physical addresses in the page table corresponding to the physical device in the system memory management unit.

[0116] In an alternative implementation, the configuration instructions also include address mapping unmapping instructions. For example... Figure 13 As shown above, in the above Figure 2 Based on the illustrated embodiment, the system-on-chip memory access control method may further include the following steps: Step 1301: In response to the address mapping release instruction initiated by the driver corresponding to the physical device against the system memory management unit by the processor core, based on the address mapping method of the virtual address and the physical device carried in the address mapping release instruction, the static address mapping relationship and / or dynamic address mapping relationship associated with the virtual address is deleted from the page table corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel.

[0117] In one alternative implementation, such as Figure 14 As shown above, in the above Figure 13 Based on the illustrated embodiment, step 1301 may include the following steps: Step 1401: If the processor core determines that the address mapping method is static address mapping, it deletes the static address mapping relationship associated with the virtual address from the page table corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel.

[0118] In one alternative implementation, such as Figure 15 As shown above, in the above Figure 13Based on the illustrated embodiment, step 1301 may include the following steps: Step 1501: If the processor core determines that the address mapping method is dynamic address mapping, it deletes the dynamic address mapping relationship associated with the virtual address from the page table corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel.

[0119] Step 1502: The virtual address is recycled to the virtual address space manager corresponding to the physical device through the processor core.

[0120] In one alternative implementation, such as Figure 16 As shown above, in the above Figure 13 Based on the illustrated embodiment, step 1301 may include the following steps: Step 1601: When the processor core determines that the address mapping method is dynamic-static address mapping, in response to the virtual address being determined to belong to the virtual address in the static address mapping relationship based on the static address mapping relationship, the static address mapping relationship associated with the virtual address is deleted from the page table corresponding to the physical device of the system memory management unit through the inter-process communication interface provided by the microkernel.

[0121] Step 1602: In response to the virtual address that is determined not to be in the static address mapping relationship based on the static address mapping relationship, the processor core deletes the dynamic address mapping relationship associated with the virtual address from the page table corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel.

[0122] Step 1603: The virtual address is recycled to the virtual address space manager corresponding to the physical device through the processor core.

[0123] Regarding the memory access control method based on the system-on-a-chip in the above embodiments, the specific execution methods of each step and the corresponding beneficial effects have been described in detail in the corresponding embodiments of the system-on-a-chip part that supports memory access control. Please refer to the corresponding execution methods and beneficial technical effects of the above exemplary system part, which will not be repeated here.

[0124] Exemplary electronic devices Figure 17 A structural diagram of an electronic device provided in an embodiment of this disclosure includes at least one processor 11 and a memory 12.

[0125] The processor 11 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.

[0126] The memory 12 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 11 may execute one or more computer program instructions to implement the system-on-chip memory access control method and / or other desired functions of the various embodiments of this disclosure described above.

[0127] In one example, the electronic device 10 may also include an input device 13 and an output device 14, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0128] The input device 13 may also include, for example, a keyboard, a mouse, etc.

[0129] The output device 14 can output various information to the outside, including, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0130] Of course, for the sake of simplicity, Figure 17 Only some of the components of the electronic device 10 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 10 may include any other suitable components depending on the specific application.

[0131] Exemplary computer program products and computer-readable storage media In addition to the methods and apparatus described above, embodiments of this disclosure may also provide a computer program product, including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the system-on-chip memory access control methods of various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0132] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0133] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the system-on-chip memory access control methods of various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0134] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0135] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0136] Various modifications and variations can be made to this disclosure without departing from its spirit and scope. Therefore, this disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of this disclosure and their equivalents.

Claims

1. A system-on-chip supporting memory access control, comprising: The internal memory is configured to store device configuration files corresponding to the physical devices. The processor core is configured as follows: In response to a configuration instruction initiated by the driver corresponding to the physical device against the system memory management unit, the device configuration file corresponding to the physical device is read from the internal memory; Based on the device configuration information for the system memory management unit included in the device configuration file, the memory access configuration information corresponding to the physical device is configured in the system memory management unit through the inter-process communication interface provided by the microkernel; The system memory management unit is configured as follows: In response to a direct memory access request initiated by the physical device, memory access control is performed on the physical device based on the memory access configuration information corresponding to the physical device.

2. The system-on-a-chip according to claim 1, wherein, The configuration instructions include binding instructions; The processor core is specifically configured as follows: In response to the binding instruction initiated by the driver corresponding to the physical device against the system memory management unit, based on the device information of the physical device carried in the binding instruction, the device configuration file corresponding to the physical device is read from the internal memory, and the flow identifier and context descriptor of the physical device included in the device configuration information are obtained from the device configuration file; Based on the flow identifier, the binding relationship between the physical device and the system memory management unit is configured in the system memory management unit through the inter-process communication interface provided by the microkernel, and the flow table entry and context descriptor corresponding to the physical device are configured in the flow table of the system memory management unit; wherein, the memory access configuration information includes the binding relationship between the physical device and the system memory management unit, and the flow table entry and context descriptor corresponding to the physical device configured in the flow table of the system memory management unit.

3. The system-on-a-chip according to claim 2, wherein, The configuration instructions also include unbinding instructions; The processor core is also configured as follows: In response to the unbinding instruction initiated by the driver corresponding to the physical device against the system memory management unit, based on the flow identifier of the physical device carried in the unbinding instruction, the binding relationship between the physical device and the system memory management unit is released in the system memory management unit through the inter-process communication interface provided by the microkernel, and the flow table entry and the context descriptor corresponding to the physical device are deleted from the flow table of the system memory management unit.

4. The system-on-a-chip according to claim 1, wherein, The configuration instructions also include address mapping initialization instructions; The processor core is specifically configured as follows: In response to the address mapping initialization instruction initiated by the driver corresponding to the physical device for the system memory management unit, based on the device information of the physical device carried in the address mapping initialization instruction, the device configuration file of the physical device is read from the internal memory, and the address mapping method and address mapping information corresponding to the physical device, which are included in the device configuration information, are obtained from the device configuration file. Based on the address mapping method and the address mapping information, the address mapping configuration information corresponding to the physical device is initialized in the system memory management unit through the inter-process communication interface provided by the microkernel; wherein, the address mapping information is used to indicate the address mapping relationship between virtual addresses and physical addresses, and the memory access configuration information includes the address mapping configuration information.

5. The system-on-a-chip according to claim 4, wherein, The address mapping information includes the static address mapping relationship between virtual addresses and physical addresses, and the address mapping configuration information includes the page table corresponding to the physical device; The processor core is specifically configured as follows: If the address mapping method is determined to be a static address mapping method, the static address mapping relationship between the virtual address and the physical address is written into the page table corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel.

6. The system-on-a-chip according to claim 4, wherein, The address mapping information includes a set of virtual addresses, and the address mapping configuration information includes a virtual address space manager corresponding to the physical device. The processor core is specifically configured as follows: If the address mapping method is determined to be a dynamic address mapping method, a virtual address space manager corresponding to the physical device is created in the system memory management unit based on the virtual address set through the inter-process communication interface provided by the microkernel; wherein, the virtual address space manager is used to dynamically allocate virtual addresses to the physical device based on the virtual address set.

7. The system-on-a-chip according to claim 4, wherein, The address mapping information includes the static address mapping relationship between virtual addresses and physical addresses and the set of virtual addresses; the address mapping configuration information includes the page table and virtual address space manager corresponding to the physical device. The processor core is specifically configured as follows: When the address mapping method is determined to be a dynamic-static address mapping method, a static address mapping relationship between the virtual address and the physical address is constructed in the page table corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel, and a virtual address space manager corresponding to the physical device is created in the system memory management unit based on the virtual address set; wherein, the virtual address space manager is used to dynamically allocate virtual addresses for the physical device based on the virtual address set.

8. The system-on-a-chip according to claim 1, wherein, The configuration instructions also include address mapping association instructions; The processor core is also configured as follows: In response to the address mapping association instruction initiated by the driver corresponding to the physical device against the system memory management unit, the virtual address corresponding to the physical address is determined based on the physical address carried in the address mapping association instruction and the address mapping method of the physical device; The virtual address is transmitted to the physical device.

9. The system-on-a-chip according to claim 8, wherein, The processor core is specifically configured as follows: If the address mapping method is determined to be a static address mapping method, the static address mapping relationship corresponding to the physical device is read from the page table corresponding to the physical device in the system memory management unit. Based on the static address mapping relationship, determine the virtual address corresponding to the physical address; The virtual address is transmitted to the physical device.

10. The system-on-a-chip according to claim 8, wherein, The processor core is specifically configured as follows: If the address mapping method is determined to be a dynamic address mapping method, the virtual address corresponding to the physical address is determined based on the virtual address space manager corresponding to the physical device in the system memory management unit; Transmit the virtual address to the physical device; The processor core is also configured as follows: Through the inter-process communication interface provided by the microkernel, a dynamic address mapping relationship between the virtual address and the physical address is constructed in the page table corresponding to the physical device in the system memory management unit.

11. The system-on-a-chip according to claim 8, wherein, The processor core is specifically configured as follows: When it is determined that the address mapping method is a dynamic-static address mapping method, in response to determining that the physical address belongs to the physical address in the static address mapping relationship based on the static address mapping relationship, the virtual address corresponding to the physical address is determined from the static address mapping relationship, and the virtual address is transmitted to the physical device; In response to determining that the physical address does not belong to the physical address in the static address mapping relationship based on the static address mapping relationship, the virtual address corresponding to the physical address is determined based on the virtual address space manager corresponding to the physical device in the system memory management unit; Transmit the virtual address to the physical device; The processor core is also configured as follows: Through the inter-process communication interface provided by the microkernel, a dynamic address mapping relationship between the virtual address and the physical address is constructed in the page table corresponding to the physical device in the system memory management unit.

12. The system-on-a-chip according to claim 1, wherein, The configuration instructions also include address mapping removal instructions; The processor core is also configured as follows: In response to the address mapping release instruction initiated by the driver corresponding to the physical device against the system memory management unit, based on the virtual address carried in the address mapping release instruction and the address mapping method corresponding to the physical device, the static address mapping relationship and / or dynamic address mapping relationship associated with the virtual address is deleted from the page table corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel.

13. The system-on-a-chip according to claim 12, wherein, The processor core is specifically configured as follows: If the address mapping method is determined to be a static address mapping method, the static address mapping relationship associated with the virtual address is deleted from the page table corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel.

14. The system-on-a-chip according to claim 12, wherein, The processor core is specifically configured as follows: If the address mapping method is determined to be a dynamic address mapping method, the dynamic address mapping relationship associated with the virtual address is deleted from the page table corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel. The processor core is also configured as follows: The virtual address is recycled to the virtual address space manager corresponding to the physical device.

15. The system-on-a-chip according to claim 12, wherein, The processor core is specifically configured as follows: If the address mapping method is determined to be a dynamic-static address mapping method, in response to determining that the virtual address belongs to the virtual address in the static address mapping relationship based on the static address mapping relationship, the static address mapping relationship associated with the virtual address is deleted from the page table corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel; In response to determining that the virtual address does not belong to the static address mapping relationship based on the static address mapping relationship, the dynamic address mapping relationship associated with the virtual address is deleted from the page table corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel; The processor core is also configured as follows: The virtual address is recycled to the virtual address space manager corresponding to the physical device.

16. A memory access control method based on a system-on-a-chip, comprising: The processor core responds to the configuration instructions initiated by the driver corresponding to the physical device against the system memory management unit, and reads the device configuration file corresponding to the physical device from the internal memory; The processor core configures the memory access configuration information corresponding to the physical device in the system memory management unit through the inter-process communication interface provided by the microkernel, based on the device configuration information for the system memory management unit included in the device configuration file. In response to a direct memory access request initiated by the physical device, the system memory management unit performs memory access control on the physical device based on the memory access configuration information corresponding to the physical device.

17. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the system-on-chip memory access control method of claim 16.

18. A computer-readable storage medium storing a computer program that is executed by a processor to implement the system-on-a-chip memory access control method of claim 16.

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