A dual-redundancy timing control simulation verification method based on 1553B bus

Abstract

The application provides a kind of double redundancy timing control simulation verification method based on 1553B bus.The method takes BC master computer as core timing initiation end, integrates Simulink control system digital model (including double redundancy timing module) in real-time simulator, 1553B bus communication channel constructed by 1553 board card, and acts as RT end, realizes the full closed loop control of timing instruction issuing, execution, verification and feedback.The steps include:BC master generates full-process timing instruction and issues to RT end through 1553B bus;RT end receives instruction, drives corresponding simulation module to execute operation and generates reply signal;BC master verifies the validity of reply signal, and if verification is passed, triggers next timing process, and if verification fails, terminates timing and feeds back exception.The application realizes the cooperative control of multi-module timing such as servo and inertial unit, improves the real-time performance, reliability and authenticity of spacecraft simulation system, adapts to the linkage demand of spacecraft digital simulation and actual hardware test, and has wide application prospect.

Description

Technical Field

[0001] This invention belongs to the field of simulation control technology, specifically relating to a dual-redundant timing control simulation verification method based on a 1553B bus. Background Technology

[0002] Control system simulation requires the integration of multiple modules such as main control, servo, inertial navigation, timing, and power distribution. The stability and accuracy of timing control directly determine the reliability of the simulation results. Simulation systems often adopt a distributed timing control mode, where timing commands for each simulation module are initiated by itself or issued through a general bus, lacking a unified timing control core. At the same time, there is no effective response and verification mechanism after the commands are issued, which can easily lead to problems such as command loss and execution deviation, resulting in a disordered simulation process and poor consistency with the actual timing control logic.

[0003] The 1553B bus, a commonly used serial communication bus in the aerospace field, is characterized by high reliability and real-time performance, and is widely used for device communication in actual aircraft. However, its application in simulation is mostly limited to simple data transmission, failing to form a closed-loop timing control architecture of "command issuance - execution feedback - verification triggering". Furthermore, existing timing models are mostly single-redundant designs, lacking redundancy and fault-tolerance mechanisms. Once a logic fault or output deviation occurs, it is impossible to quickly locate the fault and switch to a valid channel, leading to simulation interruption or result distortion, further affecting the overall performance and reliability of the spacecraft simulation system.

[0004] To address the aforementioned technical shortcomings, there is an urgent need for a 1553B bus timing control method that can achieve unified timing management, closed-loop verification feedback, adapt to multi-module collaborative simulation, and has fault tolerance capabilities, thereby improving the stability and realism of the simulation system. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing spacecraft simulation timing control, such as dispersed timing control, lack of closed-loop verification, and lack of redundancy and fault tolerance. It provides a dual-redundant timing control simulation verification method based on the 1553B bus, which realizes timing process simulation verification and improves the real-time performance, reliability, and realism of the simulation system.

[0006] To achieve the above-mentioned objectives, the present invention provides the following technical solution: This invention provides a simulation verification method for dual-redundant timing control based on the 1553B bus. The application includes a main control computer (BC end), a real-time simulator (RT end), a 1553 board, and a Simulink control system digital model (including a dual-redundant timing model). The method includes the following steps: (1) Preset the timing process library, instruction verification standard and trigger threshold of each simulation module in the BC master computer; build a 1553B bus communication channel on the RT end through the 1553 board to complete the communication adaptation between the BC master and the RT end, set the communication baud rate, data frame format and data verification rules; import the Simulink control system digital model into VeriStand and complete the adaptation. (2) The BC master computer generates timing instructions for the target simulation module in sequence according to the preset timing process library, and sends the timing instructions to the RT end through the 1553B bus; The RT terminal receives timing instructions through the 1553B bus communication channel, parses the module identifier in the instructions, matches the corresponding simulation module, and drives the matched simulation module to perform operations. (3) After the simulation module is completed, the RT terminal collects the module execution data; generates a response signal according to the preset data format, and transmits the response signal back to the BC master computer through the 1553B bus.

[0007] After the execution of channels A and B in the timing module is completed, the module execution data is collected and output data is generated respectively. The outputs of the two channels are compared in real time, and a faultFlag is generated through Boolean operation. If faultFlag=0, the output data is merged and a response signal is generated. If faultFlag=1, deep fault verification is triggered. The outputs of the two channels are compared with the "standard timing output" port by port to generate a validity vector for each channel. Only the output data of the valid channels is retained and a response signal is generated. (4) The BC master computer receives the reply signal and verifies the validity of the reply signal according to the preset instruction verification standard. The verification content includes data integrity, execution result consistency, and parameter threshold compliance. If the verification passes, the generation and issuance of the next timing instruction are triggered, and the process returns to step (2). If the verification fails, the current timing process is terminated immediately, an abnormal feedback signal is generated and output. The timing process to be executed in this invention includes spacecraft power-on self-test, servo inertial navigation system on-ground testing, and parameter file loading.

[0008] In this invention, the data format transmitted by BC and RT via the 1553B bus is 30 hexadecimal numbers.

[0009] In this invention, the dual-redundant timing module uses a state machine to automatically switch between "dual-channel parallel operation" and "single-channel operation". In dual-channel mode, the two channels output in parallel and are compared in real time. When faultFlag=1, the faulty channel is located by combining the validity vector, and the system switches to the valid channel to enter the single-channel operation mode, which continuously monitors only the currently valid channel. In single-channel mode, the system continuously verifies the consistency between the output of the channel and the "standard timing output" to avoid secondary faults.

[0010] The advantages of this invention are: (1) This invention takes the BC main controller as the core and realizes unified timing control of multiple simulation modules such as servo and inertial navigation, which solves the technical problem of scattered timing in existing simulation systems. By constructing a closed-loop timing architecture and redundant configuration of "send-execute-respond-verify" through the 1553B bus, it can effectively avoid problems such as instruction loss and execution deviation, and improve the reliability of timing control. (2) This invention incorporates processes such as servo / inertial navigation system testing into closed-loop timing control, realizing synchronous linkage between the simulation of the control system and the real hardware, improving the consistency between the simulation system and the actual spacecraft working logic, providing accurate digital simulation support for the actual hardware testing of spacecraft, and reducing testing costs; (3) High timing synchronization accuracy: It adopts a dual-mode timing design of "clock-driven + condition-triggered" and is equipped with 1553B bus communication to achieve microsecond-level timing trigger accuracy in the verification process; (4) The dual redundancy fault-tolerant design, verification mechanism and abnormal feedback function of the present invention form a triple guarantee, which can detect data abnormalities and channel faults in the simulation process in real time, respond and process quickly, avoid simulation disorder, and improve the stability, maintainability and adaptability of the simulation system to large-scale applications. Attached Figure Description

[0011] Figure 1 This is the overall flowchart of the dual-redundant timing control simulation verification method based on the 1553B bus of the present invention; Figure 2 This is a schematic diagram of the architecture of the Simulink dual-redundant timing module of the present invention; Figure 3 This is a logic diagram of fault detection and mode switching of the dual-redundant timing module of the present invention; Detailed Implementation

[0012] This invention provides a simulation verification method for dual-redundant timing control based on a 1553B bus, comprising the following steps: (1) Preset the timing process library (including spacecraft power-on self-test, servo inertial navigation system on-the-ground test, parameter file loading, etc.), instruction verification standards and trigger thresholds of each simulation module in the BC main control computer; (2) A dual-redundant timing function module was built in MATLAB / Simulink, including channel A (main channel) and channel B (backup channel), with the two channels having completely identical functions. Simultaneously, dual-channel output comparison, error flag generation, standard value verification, and channel switching logic were embedded. Multiple MATLAB Function embedded code modules are established within each channel, each corresponding to a sub-address channel of the 1553B bus. Each module has an input / output port, named in the "address-sub-address" format.

[0013] The sequential logic adopts a dual-mode design of "clock-driven + condition-triggered" and forms a chain-like timing constraint network; (3) Develop a 1553 board channel in VeriStand to act as the RT end. Then, create sub-address channels under the channel, which are divided into send and receive modes. At the same time, it is also necessary to define the transmission type, refresh cycle, and data length parameters of each sub-address, which can be established according to the protocol. Next, create fields in the sub-address. For example, in this test, the data are all 30-bit hexadecimal arrays, so we set up 30 fields for each sub-address to achieve one-to-one correspondence.

[0014] (4) Compile the digital prototype model of the control system into a real-time code .so file using C code, import the .so file into VeriStand software, so that VeriStand software can recognize all input and output ports of the timing process module, and then use the mapping module to connect the sub-address channels and the input and output ports of the model one by one.

[0015] (5) After the simulation is started, the RT terminal simulated by the real-time simulator can interact with the ground BC terminal. That is, when the BC terminal sends data, the RT terminal can successfully receive and judge the data and then quickly send the data back. The BC terminal can also receive the information sent and judge it to proceed to the next step.

[0016] In summary, the verification method provided by this invention utilizes multiple embedded code modules within MATLAB Functions in Simulink to simulate the timing interaction process and corresponds to the data transmitted under timing instructions at different sub-addresses of the 1553B bus, thus completing signal transmission and reception. The design of the dual-redundant timing module ensures a certain degree of redundancy and fault tolerance. This invention successfully achieves closed-loop timing control of "BC command issuance - RT feedback - BC verification," which can smoothly execute processes such as power-on, system testing, and parameter file loading. This invention ensures the real-time performance, accuracy, and reliability of the simulation, effectively supporting simulation testing requirements.

[0017] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A simulation verification method for dual-redundant timing control based on a 1553B bus, comprising the following steps: (1) Includes a 1553 board packaged in the main control computer (BC end), a real-time simulator (RT end), and a Simulink control system digital model (including a dual-redundant timing model). (2) Multiple MATLAB Function embedded code modules are established in the timing module of the Simulink control system. Each MATLAB Function module corresponds to a different sub-address channel of the 1553B bus and undertakes a dedicated timing interaction process. The Simulink timing module digital model adopts a dual-redundancy structure and a "dual-channel parallel + hierarchical fault detection" scheme, which includes two timing logic channels (channel A and channel B) with completely identical functions. (3) A unified data format is preset on the BC end and the RT end. The data format is 30 hexadecimal numbers, which are used for signal transmission and parsing between the RT end and the BC end. (4) The control signals sent by the BC terminal are parsed by the MATLAB Function module of the corresponding sub-address through embedded code and the corresponding timing logic is executed to generate the data to be sent and then transmitted back to the BC terminal by the RT terminal.

2. The simulation verification method according to claim 1, characterized in that, The functions implemented by the embedded code in each MATLAB Function module include: receiving and parsing signals at the BC end, determining timing logic, generating 30 hexadecimal number format data, and sending data to the output port of the corresponding sub-address. The embedded code of the dual-redundant timing module additionally implements dual-channel output comparison, fault marker generation, standard value verification, and channel switching logic to ensure that the correct data is sent back to BC.

3. The method according to claim 1, characterized in that, The 30-hexadecimal data format includes a frame header identifier (2 hexadecimal numbers), an instruction type code (1 hexadecimal number), a data validity field (25 hexadecimal numbers), and a frame tail checksum (2 hexadecimal numbers).

4. The method according to claim 1, characterized in that, The dual-redundant timing module supports "dual-channel parallel" and "single-channel operation" modes, and achieves automatic switching through a state machine: in dual-channel mode, it outputs in parallel and monitors consistency; when faultFlag is set to 1, it switches to the effective channel and enters single-channel mode, continuously monitoring the consistency of the channel with the standard value.

5. The method according to claim 1, characterized in that, The fault detection of the dual-redundant timing module adopts a layered design: the first layer is to compare the outputs of channels A and B in real time, and generate a faultFlag flag through Boolean operation. If the comparison is inconsistent, the flag is set to 1. The second layer is deep fault verification, which compares the dual-channel output with the preset "standard timing output" port by port to generate a validity vector for each channel and determine the source of the fault.

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