Core particle interconnection system, resource scheduling method, electronic device, and vehicle

Abstract

The application relates to a core particle interconnection system, a resource scheduling method, electronic equipment and a vehicle, and relates to the chip technical field.The system comprises an interconnection core particle and a plurality of functional core particles;each functional core particle is configured with independent storage resources; the interconnection core particle is used for scheduling the storage resources of a second functional core particle for a first functional core particle in response to a resource sharing request of the first functional core particle; the first functional core particle is any one of the plurality of functional core particles, and the second functional core particle is any one of the plurality of functional core particles except the first functional core particle, so that the performance of the core particle interconnection system can be improved, and the efficient operation of the core particle interconnection system can be ensured.

Description

Technical Field

[0001] This application relates to the field of chip technology, specifically to a chip interconnect system, a resource scheduling method, an electronic device, and a vehicle. Background Technology

[0002] Chip integration technology is a silicon-level combination technology that connects multiple chips together through die-to-die (D2D) high-speed interface interconnects and advanced packaging processes to form a homogeneous or heterogeneous multi-core processor system.

[0003] Compared to traditional single-chip integration, chiplet integration technology has significant advantages in many aspects, but it still faces some challenges in practical applications. Specifically, in a chiplet system, all chips access double data rate (DDR) memory through a single bus. However, due to memory bandwidth limitations, when multiple chips access DDR memory simultaneously, access conflicts may occur, preventing the normal use of DDR memory and thus affecting the performance of the chiplet system. Summary of the Invention

[0004] One of the purposes of this application is to provide a chip interconnect system, resource scheduling method, electronic device and vehicle that can improve the performance of the chip interconnect system and ensure the efficient operation of the chip interconnect system.

[0005] To achieve the above objectives, the technical solution adopted in this application is as follows:

[0006] According to a first aspect of this application, a chip interconnect system is provided, comprising interconnect chips and a plurality of functional chips. Each functional chip is configured with independent storage resources. The interconnect chip is used to schedule storage resources of a second functional chip for the first functional chip in response to a resource sharing request from the first functional chip. The first functional chip is any one of the plurality of functional chips, and the second functional chip is any one of the plurality of functional chips other than the first functional chip.

[0007] Based on the aforementioned technical means, each functional chip in the chip interconnect system provided in this application can be configured with independent storage resources. This allows each functional chip to directly utilize its own storage resources, effectively avoiding access conflicts caused by multiple functional chips accessing the same storage resource, thereby ensuring the efficient operation of the chip interconnect system. Furthermore, when a functional chip's storage resources are insufficient, the interconnect chip can schedule storage resources from other functional chips for that functional chip, thus improving the overall performance of the chip interconnect system.

[0008] In one possible implementation, the interconnect chip is also used to release a first storage resource in response to a resource release notification from the first functional chip. The first storage resource is the storage resource of a second functional chip scheduled by the interconnect chip for the first functional chip.

[0009] Based on the above technical means, this application can release the first storage resource in a timely manner through the interconnect core. The first storage resource is the storage resource of the second functional core scheduled by the interconnect core for the first functional core, thereby reducing the idleness and waste of storage resources and improving the overall resource utilization rate of the core interconnect system.

[0010] In one possible approach, the interconnect core includes a configuration module and a storage address management module. The configuration module is used to configure the resource scheduling priority of each functional core and the accessibility between multiple functional cores. The storage address management module is used to manage the mapping relationship between the physical addresses and virtual addresses of the storage resources of each functional core.

[0011] Based on the aforementioned technical means, this application can configure resource scheduling priorities for each functional core, enabling interconnect cores to prioritize the scheduling of storage resources for functional cores with higher resource scheduling priorities. Simultaneously, by configuring accessibility among multiple functional cores, unauthorized access by functional cores can be prevented, thereby achieving resource isolation and security control.

[0012] In one possible approach, the interconnect chip also includes a caching module and a decoding module. The caching module caches access data for each functional chip. The decoding module decodes the physical and virtual addresses of the storage resources for each functional chip.

[0013] Based on the aforementioned technical means, this application can cache the access data of each functional core. When multiple functional cores need to access the same data, they can share the cached data, thereby avoiding data access conflicts and waiting time. Furthermore, the decoding module ensures accurate location and access to storage resources.

[0014] In one possible approach, each functional chip includes a processor cluster. The processor cluster is used to process data or perform computational tasks.

[0015] Based on the above-mentioned technical means, this application can process data or execute multiple computing tasks simultaneously and in parallel through a cluster of processors, thereby improving the efficiency of data processing and computing.

[0016] According to a second aspect of this application, a resource scheduling method is provided, applied to interconnecting cores in a core interconnection system of the first aspect. The method includes: receiving a resource sharing request sent by a first functional core; the resource sharing request is for requesting shared storage resources. In response to the resource sharing request, storage resources of a second functional core are scheduled for the first functional core; the second functional core is another functional core among a plurality of functional cores besides the first functional core.

[0017] Based on the above technical means, this application can schedule the storage resources of the second functional core for the first functional core after receiving the resource sharing request sent by the first functional core, so that the first functional core can access the storage resources of the second functional core, thereby improving the performance of the core interconnect system and ensuring the efficient operation of the core interconnect system.

[0018] In one possible approach, the second functional core must at least satisfy the following conditions: the second functional core allows the first functional core to access it; the remaining available storage resources of the second functional core are greater than or equal to the storage resources required by the first functional core; and the access priority of the second functional core is greater than a preset threshold.

[0019] Based on the above-mentioned technical means, this application can quickly and accurately determine the second functional core based on the above conditions.

[0020] In one possible approach, the access priority of the second functional core is determined by any of the following parameters: the transmission delay between the first and second functional cores; the configuration information of the second functional core; and the interface number of the second functional core.

[0021] Based on the above technical means, this application can determine the access priority of the second functional core based on the above parameters, so that the interconnect core can schedule storage resources for the first functional core based on the access priority of the second functional core, thereby improving the scheduling efficiency of the core interconnect system.

[0022] In one possible approach, the method further includes: sending a virtual address of the storage resources of the second functional core to the first functional core; the virtual address is used by the first functional core to access the storage resources of the second functional core.

[0023] Based on the above technical means, this application enables the first functional core to quickly access the storage resources of the second functional core based on the virtual address of the storage resources of the second functional core.

[0024] In one possible approach, the method further includes: receiving resource sharing requests from at least two functional cores; scheduling storage resources of other functional cores for each functional core according to the resource scheduling priority of each of the at least two functional cores; the other functional cores are functional cores other than the at least two functional cores among a plurality of functional cores.

[0025] Based on the above technical means, after receiving resource sharing requests from multiple functional cores, this application can, based on the resource scheduling priority of each functional core, first schedule storage resources for functional cores with high resource scheduling priority, and then schedule storage resources for functional cores with low resource scheduling priority. This improves the speed and efficiency of the core interconnection system in processing scheduling tasks and enhances the flexibility of the core interconnection system.

[0026] In one possible approach, the resource scheduling priority of each functional core is determined by any of the following parameters: the storage resources required by each functional core; the remaining available storage resources of each functional core; and the value of the register bits corresponding to each functional core.

[0027] Based on the above technical means, this application can determine the resource scheduling priority of each functional core, so that the interconnect core can reasonably allocate resources based on the resource scheduling priority of the functional core, thereby reducing the situation where system performance degrades due to resource contention.

[0028] According to a third aspect of this application, a resource scheduling method is provided, applied to a first functional core among a plurality of functional cores included in the core interconnect system of the first aspect. The method includes: sending a resource sharing request to the interconnect core; the resource sharing request is used to request shared storage resources; receiving a resource scheduling message sent by the interconnect core; the resource scheduling message is used to indicate storage resources of a second functional core; the second functional core is another functional core among the plurality of functional cores besides the first functional core; and using the storage resources of the second functional core for data storage.

[0029] In one possible approach, the second functional core must at least satisfy the following conditions: the second functional core allows the first functional core to access it; the remaining available storage resources of the second functional core are greater than or equal to the storage resources required by the first functional core; and the access priority of the second functional core is greater than a preset threshold.

[0030] In one possible approach, the access priority of the second functional core is determined by any of the following parameters: the transmission delay between the first and second functional cores; the configuration information of the second functional core; and the interface number of the second functional core.

[0031] In one possible approach, the method further includes: receiving a virtual address of the storage resources of a second functional core sent by the interconnect core; the virtual address is used by the first functional core to access the storage resources of the second functional core. The storage resources of the second functional core are accessed based on the virtual address.

[0032] According to the fourth aspect provided in this application, an electronic device is provided, which is configured with the chip interconnect system of the first aspect described above.

[0033] According to the fifth aspect provided in this application, a vehicle is provided, which is equipped with the electronic equipment described in the fourth aspect.

[0034] According to a sixth aspect provided in this application, a computer-readable storage medium is provided that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method of the second aspect and any possible implementation thereof, or to perform the method of the third aspect and any possible implementation thereof.

[0035] According to the seventh aspect provided in this application, a computer program product is provided, the computer program product including computer instructions, which, when executed on an electronic device, cause the electronic device to perform the method of the second aspect and any possible implementation thereof, or to perform the method of the third aspect and any possible implementation thereof.

[0036] Therefore, the above-mentioned technical features of this application have the following beneficial effects:

[0037] (1) Storage resources can be configured for each functional core in the core-core interconnect system, so that each functional core can directly use its own storage resources, effectively avoiding access conflicts caused by multiple functional cores accessing the same storage resources, thereby ensuring the efficient operation of the core-core interconnect system. In addition, when the storage resources of a certain functional core are insufficient, the interconnect core can schedule the storage resources of other functional cores for that functional core, thus improving the performance of the entire core-core interconnect system.

[0038] (2) The first storage resources can be released in a timely manner through the interconnected core, that is, the storage resources of the second functional core scheduled by the interconnected core for the first functional core, thereby reducing the idleness and waste of storage resources and improving the overall resource utilization rate of the core interconnection system.

[0039] (3) Resource scheduling priorities can be configured for each functional core, so that interconnect cores can prioritize scheduling storage resources for functional cores with higher resource scheduling priorities. At the same time, by configuring the accessibility between multiple functional cores, unauthorized access by functional cores can be prevented, thereby achieving resource isolation and security control.

[0040] (4) Access data for each functional core can be cached. When multiple functional cores need to access the same data, they can share the data in the cache, thereby avoiding data access conflicts and waiting time. In addition, the decoding module can ensure the accurate location and access of storage resources.

[0041] (5) Data processing and computation efficiency can be improved by processing data or executing multiple computational tasks simultaneously and in parallel through a cluster of processors.

[0042] (6) The second functional core can be quickly and accurately determined based on the conditions satisfied by the second functional core, such as the second functional core allowing the first functional core to access it, the remaining available storage resources of the second functional core being greater than or equal to the storage resources required by the first functional core, and the access priority of the second functional core being greater than a preset threshold.

[0043] (7) The access priority of the second functional core can be determined based on the transmission delay between the first functional core and the second functional core, the configuration information of the second functional core and / or the interface number of the second functional core, so that the interconnect core can schedule storage resources for the first functional core based on the access priority of the second functional core, thereby improving the scheduling efficiency of the core interconnect system.

[0044] (8) It enables the first functional core to quickly access the storage resources of the second functional core based on the virtual address of the storage resources of the second functional core.

[0045] (9) After receiving resource sharing requests from multiple functional cores, based on the resource scheduling priority of each functional core, storage resources can be scheduled first for functional cores with high resource scheduling priority, and then storage resources can be scheduled for functional cores with low resource scheduling priority, thereby improving the speed and efficiency of the core interconnection system in processing scheduling tasks and enhancing the flexibility of the core interconnection system.

[0046] (10) The resource scheduling priority of each functional core can be determined so that the interconnect core can allocate resources reasonably based on the resource scheduling priority of the functional core, thereby reducing the situation where system performance degrades due to resource contention.

[0047] It should be noted that the technical effects of any of the implementation methods in aspects four through seven can be found in the technical effects of the corresponding implementation methods in aspect one, aspect two, or aspect three, and will not be repeated here.

[0048] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0049] Figure 1 This is a schematic diagram illustrating a UMA-based SOC system according to an exemplary embodiment;

[0050] Figure 2 This is a schematic diagram illustrating a chip interconnect system based on a UMA architecture according to an exemplary embodiment;

[0051] Figure 3This is a schematic diagram of a chip interconnect system according to an exemplary embodiment;

[0052] Figure 4 This is a schematic diagram of another chip interconnect system according to an exemplary embodiment;

[0053] Figure 5 This is a schematic diagram of the structure of an interconnect chip according to an exemplary embodiment;

[0054] Figure 6 This is a schematic diagram illustrating a storage address management module in an interconnect chip according to an exemplary embodiment;

[0055] Figure 7 This is a schematic diagram illustrating the internal connection structure of an interconnect chip according to an exemplary embodiment;

[0056] Figure 8 This is a flowchart illustrating a resource scheduling method according to an exemplary embodiment;

[0057] Figure 9 This is a schematic diagram of a process for determining the access priority of a second functional chip according to an exemplary embodiment;

[0058] Figure 10 This is a flowchart illustrating another resource scheduling method according to an exemplary embodiment;

[0059] Figure 11 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation

[0060] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0061] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0062] In the embodiments of this application, the words "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a specific manner.

[0063] Furthermore, the terms "comprising" and "having," and any variations thereof, used in the description of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0064] First, the relevant technologies involved in this application will be explained to facilitate understanding by those skilled in the art.

[0065] With the rapid development of technology, emerging fields such as artificial intelligence, big data, and autonomous driving are placing increasing demands on chip computing power. Traditional systems-on-chips (SoCs) are struggling to meet the needs of these high-performance applications. To address this challenge, the integrated circuit industry is accelerating its development towards high integration, high performance, low cost, and low power consumption. However, as the feature size of integrated circuit digital chips continues to shrink and the complexity of intellectual property (IP) reuse continues to increase, traditional SoC designs are gradually pushing the limits of physics.

[0066] Against this backdrop, Chiplet integration technology emerged. Chiplet integration is a silicon-level combination technology that enables data identification and utilization of chips from different manufacturing processes through new connection technologies and data transmission methods. Chiplet integration breaks through the limitations of traditional SoC design, connecting multiple chips together through high-speed D2D interface interconnects and advanced packaging processes to form a homogeneous or heterogeneous multi-core processor system. This improves the integration density of the chip system and expands its performance and power consumption optimization capabilities.

[0067] Despite the significant advantages of Chiplet integration technology in many aspects, it still faces some challenges in practical applications. For example, related technologies have proposed a SOC system based on a uniform memory access (UMA) architecture. Figure 1 This is a schematic diagram illustrating a UMA-based SOC system according to an exemplary embodiment, the system comprising multiple processor clusters. Figure 1 As shown, in this system architecture, all processor clusters access DDR memory through a single bus. However, as the number of processor clusters increases, the bus becomes overloaded, limiting the scalability of the processor clusters. Furthermore, due to the limited bandwidth of memory, when multiple processor clusters access DDR memory simultaneously, it may cause the processor clusters to be unable to use DDR memory properly, impacting the performance of the SOC system.

[0068] Figure 2 This is a schematic diagram illustrating a chip interconnect system based on a UMA architecture according to an exemplary embodiment. Figure 2 As shown, the system includes multiple functional cores (also known as processing cluster cores) and an interconnect (ICN) core. The interconnect core connects to each functional core through multiple D2D interfaces. In this system architecture, although the chiplet integration technology can address the processor cluster size scaling limitation, all functional cores still access DDR memory through a single bus on the interconnect core. Due to memory bandwidth limitations, when multiple functional cores simultaneously initiate DDR memory access operations, access conflicts may occur, preventing the functional cores from using DDR memory correctly and thus affecting the performance of the core system.

[0069] To address the aforementioned technical problems, this application provides a chip-interconnect system in which each functional chip can be configured with independent storage resources. This allows each functional chip to directly utilize its own storage resources, effectively avoiding access conflicts caused by multiple functional chips accessing the same storage resource, thereby ensuring the efficient operation of the chip-interconnect system. Furthermore, when a functional chip's storage resources are insufficient, the interconnected chip can schedule storage resources from other functional chips for that functional chip, enabling it to utilize those resources and thus improving the overall performance of the chip-interconnect system.

[0070] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0071] Figure 3 This is a schematic diagram illustrating the structure of a chip interconnect system 300 according to an exemplary embodiment, such as... Figure 3 As shown, the system architecture includes an interconnect chip 301 and multiple functional chips 302. The interconnect chip 301 is communicatively connected to each functional chip 302. Each functional chip 302 is configured with independent storage resources. These storage resources can be memory, for example, DDR memory.

[0072] In one example, such as Figure 3 As shown, interconnect chip 301 may include multiple D2D interfaces, and each functional chip 302 may include one D2D interface. Interconnect chip 301 can be connected to each functional chip 302 through multiple D2D interfaces. For example, interconnect chip can be connected to functional chips A1, A2, A3, ..., An, B1, B2, B3, ..., Bm through multiple D2D interfaces.

[0073] The interconnect chip 301 can be used to schedule storage resources among functional chips 302. For example, the interconnect chip 301 can be used to schedule storage resources of the second functional chip for the first functional chip in response to a resource sharing request from the first functional chip. As another example, the interconnect chip 301 can also be used to release storage resources of the second functional chip scheduled for the first functional chip in response to a resource release notification from the first functional chip.

[0074] Each functional core 302 can use local storage resources to process tasks, and when local storage resources are insufficient, it can use the storage resources of other functional cores through interconnect core 301.

[0075] This application does not specify the number of each functional chip 302 in the chip interconnect system 300, and the number may include more than Figure 3 More or fewer functional cores 302.

[0076] Optional, such as Figure 4 As shown, each functional chip 302 may include a processor cluster. The processor cluster may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or an intelligence processing unit (IPU), and this application does not limit it.

[0077] Optional, such as Figure 4 As shown, each functional chip 302 can be connected to a memory (such as a DDR memory).

[0078] Optional, Figure 5 This is a schematic diagram illustrating the structure of an interconnect chip 301 according to an exemplary embodiment. For example... Figure 5 As shown, the interconnect chip 301 may include a configuration module, a storage address management module, a control module, a cache module, a decoding module, and multiple D2D interfaces.

[0079] The configuration module is used to configure the resource scheduling priority of each functional core 302. The configuration module is also used to configure the accessibility between each functional core 302.

[0080] The storage address management module is used to manage the mapping relationship between the physical address of the storage resource and the virtual address corresponding to the physical address of the storage resource in each functional core 302.

[0081] The control module is configured to schedule storage resources for each functional core 302 in response to a resource sharing request sent by each functional core 302. The control module is also configured to determine the access priority of each functional core 302. Furthermore, the control module is configured to release the storage resources scheduled for each functional core 302 in response to a resource release notification sent by each functional core 302. The resource release notification is used to instruct the interconnect core 301 to release the shared storage resources.

[0082] The caching module is used to cache access data between each functional core 302.

[0083] The decoding module is used to decode the physical address and virtual address of the storage resource of each functional core 302. That is, the decoding module can be used to decode the virtual address carried by the accessing functional core (such as the first functional core) when accessing the storage resource across functional cores to determine the physical address of the storage resource of the accessed functional core (such as the second functional core).

[0084] In one example, such as Figure 6 As shown, the storage address management module may include a shared address mapping unit and a shared address priority unit.

[0085] The shared address mapping unit can be used to store the virtual shared address table of the access-side functional core (such as the first functional core) and the physical shared address table of the accessed-side functional core (such as the second functional core).

[0086] The physical shared address table is used to store the interface number of the accessed functional core and the physical address range number of the storage resources of the accessed functional core.

[0087] The virtual shared address table stores the interface number of the accessing functional core and the virtual address range number of the storage resources of the accessed functional core, thereby realizing the mapping relationship between the virtual shared address of the accessing functional core and the physical shared address of the accessed functional core. The address range of the storage resource is the smallest address unit in the functional core where the storage resources can be shared.

[0088] The shared address priority unit is used to manage the access priority of multiple accessed side functional cores.

[0089] Optional, such as Figure 5 As shown, each D2D interface of interconnect chip 301 is used to connect to the corresponding functional chip. For example, D2D interface A1 is used to connect to functional chip A1, and D2D interface A2 is used to connect to functional chip A2. The functional chips connected to the D2D interfaces A3, ..., D2D interface An, D2D interface B1, D2D interface B2, D2D interface B3, ..., D2D interface Bm of interconnect chip 301 can be referred to the above description, and will not be repeated here.

[0090] Optional, Figure 7 This is a schematic diagram illustrating the internal connection structure of an interconnect chip 301 according to an exemplary embodiment. Figure 7 As shown, any two D2D interfaces can be bidirectionally connected, unidirectionally connected, or not connected. For example, bidirectional connectivity between D2D interface A1 (used to connect functional core A1) and D2D interface A2 (used to connect functional core A2) means that functional core A1 can access functional core A2, and functional core A2 can also access functional core A1. Unidirectional connectivity between D2D interface A1 and D2D interface A2 means that functional core A1 can access functional core A2, but functional core A2 cannot access functional core A1, or functional core A1 cannot access functional core A2, but functional core A2 can access functional core A1. Disconnectivity between D2D interface A1 and D2D interface A2 means that A1 cannot access functional core A2, and functional core A2 cannot access functional core A1.

[0091] Figure 7 The connectivity relationships between the D2D interfaces A3, ..., An, B1, B2, B3, ..., Bm of the Interconnect Core 301 can be referred to the above description and will not be repeated here.

[0092] The chip-particle interconnect system provided in this application embodiment can be configured in a vehicle. A vehicle can also be referred to as a vehicle, mobile carrier, electric vehicle (EV), hybrid electric vehicle (HEV), plug-in hybrid electric vehicle (PHEV), fuel cell vehicle (FCV), autonomous vehicle, intelligent and connected vehicle (ICV), driverless vehicle, etc.

[0093] In this embodiment, the vehicle can be a sedan, a sport utility vehicle (SUV), a truck, an electric vehicle, a motorcycle, a tricycle, a special vehicle (such as an ambulance, fire truck, police car, etc.), a driverless taxi, an intelligent connected bus, an autonomous logistics vehicle, an electric truck, etc. Furthermore, this method is also applicable to various special-purpose vehicles, such as agricultural vehicles, mining vehicles, forestry vehicles, airport vehicles, port vehicles, etc., and this application does not impose specific limitations on them.

[0094] The chip-to-chip interconnect system in this application embodiment can also be configured in an electronic device. The electronic device can be a terminal device, a server, or an in-vehicle terminal in a vehicle; this application embodiment does not limit this.

[0095] The terminal devices in this application embodiment can be mobile devices, such as mobile phones (or "cellular" phones) and computers with mobile terminal devices, or portable, pocket-sized, handheld, computer-embedded, or vehicle-mounted mobile devices that exchange voice and / or data with radio access network (RAN) nodes. For example, terminal devices can be: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminal devices in industrial control, self-driving, remote medical surgery, smart grids, transportation safety, smart cities, smart homes, etc.

[0096] The server in this application embodiment can be a single server, a server cluster, or a cloud server; this application embodiment does not limit the specific server configuration.

[0097] The vehicle-mounted terminal in this application embodiment may be a vehicle electronic control unit, a transmitter control unit, a transmission control unit, an automatic emergency brake control unit, a body control unit, an electronic stability program control unit, an airbag control unit, sensors (such as radar, cameras, lidar), an adaptive cruise control unit, a vehicle navigation system, a remote information processing terminal, etc.

[0098] For ease of understanding, the resource scheduling method provided in this application will be described in detail below with reference to the accompanying drawings.

[0099] Figure 8 This is a flowchart illustrating a resource scheduling method according to an exemplary embodiment, such as... Figure 8 As shown, this resource-based method is applied to interconnecting cores in a core interconnection system. The method includes: S801-S802.

[0100] S801, Receive resource sharing request sent by the first functional chip.

[0101] The resource sharing request is used to request shared storage resources. The first functional core can be any one of multiple functional cores in the core interconnect system.

[0102] Specifically, when the remaining available storage resources of the first functional core are less than or equal to the resource warning threshold, it can send a resource sharing request to the interconnect core. The resource sharing request may include the storage resources required by the first functional core. Correspondingly, the interconnect core can receive the resource sharing request.

[0103] Optionally, the resource warning threshold can be set according to actual needs. For example, the resource warning threshold can be 5% of the total storage resources of the first functional chip, or it can be 10% of the total storage resources of the first functional chip. This application does not make a specific limitation on this.

[0104] S802, In response to the resource sharing request, schedule the storage resources of the second functional core for the first functional core.

[0105] The second functional core is any functional core other than the first functional core among a plurality of functional cores.

[0106] Specifically, after receiving a resource sharing request from a first functional core, the interconnect core can determine a second functional core from among the other functional cores based on the accessibility between the first functional core and other functional cores, as well as the storage resources required by the first functional core. Then, the interconnect core can schedule storage resources for the second functional core for the first functional core.

[0107] The second functional core must meet at least the following conditions:

[0108] 1. The second functional core allows the first functional core to access it.

[0109] The second functional core allowing the first functional core to access it can mean that the second functional core and the first functional core are connected, or that the first functional core can access the storage resources of the second functional core (that is, the first functional core and the second functional core are unidirectionally connected).

[0110] 2. The remaining available storage resources of the second functional core are greater than or equal to the storage resources required by the first functional core.

[0111] The remaining available storage resources can also be referred to as the remaining shared resources. The remaining shared resources of the second functional core refer to those that can be shared with other functional cores in addition to being used by the second functional core.

[0112] 3. The access priority of the second functional core is greater than the preset threshold.

[0113] Access priority can be used to characterize the order in which the storage resources of a functional core are used. The higher the access priority of a functional core, the earlier its storage resources are used. For example, if the access priority of functional core 1 is higher than that of functional core 2, then if the storage resources of both functional core 1 and functional core 2 can be used by functional core 3, functional core 3 can preferentially use the storage resources of functional core 1.

[0114] Optionally, this application does not limit the way access priority is represented. For example, access priority can be level 1 to N, where N is a positive integer. Access priority can also be level A to Z.

[0115] Optionally, the preset threshold can be set according to actual needs. For example, the preset threshold can be level 3, level 4 or level 5, or level C or level D, and this application does not limit it in this regard.

[0116] Specifically, the access priority of functional cores can be determined in the following ways:

[0117] 3-1. Transmission delay between the first functional core and the second functional core.

[0118] The transmission delay between the first functional chip and the second functional chip can also refer to data transmission time or data transmission latency. The access priority of the second functional chip can be proportional to this transmission delay. For example, the smaller the transmission delay between the first and second functional chips, the higher the access priority of the second functional chip.

[0119] 3-2. Configuration information of the second functional core.

[0120] The configuration information of the second functional chip may include the total storage resource capacity or the storage bandwidth.

[0121] In some examples, the access priority of the second functional core can be determined based on the total storage resource capacity or storage bandwidth of the second functional core. For example, the larger the total storage resource capacity of the second functional core, the higher its access priority. Or, the larger the storage bandwidth of the second functional core, the higher its access priority.

[0122] 3-3. Interface number of the second functional core.

[0123] The interface number of the second functional core can be set according to actual needs. For example, the interface number of the second functional core can be A1, A2, or A3. Different functional cores have different interface numbers.

[0124] In some examples, the access priority of the second functional core can be determined according to its interface number. For example, the larger the interface number of the second functional core, the higher its access priority. Assuming that the interface number of functional core 1 is greater than that of functional core 2, and the interface number of functional core 1 is greater than that of functional core 3, and the numbering order of functional core 2 is greater than that of functional core 3, then the access priority order of functional core 1, functional core 2, and functional core 3 is: functional core 1 > functional core 2 > functional core 3.

[0125] Based on the aforementioned technical means, when the first functional core has insufficient local storage resources, it can send a resource sharing request to the interconnect core. Correspondingly, the interconnect core can respond to the resource sharing request by scheduling storage resources from the second functional core for the first functional core, enabling the first functional core to access the storage resources of the second functional core. This not only improves the performance of the core interconnect system but also solves the problem of shared storage resource usage across functional cores when the remaining available storage resources of functional cores are insufficient, thereby ensuring the efficient operation of the core interconnect system.

[0126] In some embodiments, the method provided in this application further includes: determining a second functional core.

[0127] In one possible implementation, the interconnect core can be equipped with multiple interface registers, with one interface register corresponding to each functional core. Each interface register can include multiple bits, and the value of each bit can indicate whether the functional core is allowed to be accessed by other functional cores. Each bit corresponds to a D2D interface, and each D2D interface is used to connect to the corresponding functional core.

[0128] Based on this, the interconnect chip can determine at least one target functional chip that the first functional chip is allowed to access by reading the values ​​of the bits used to connect the D2D interface in the interface registers of other functional chips. Then, the interconnect chip can send a remaining available storage resource listening signal to the at least one target functional chip and receive the remaining available storage resources sent by the at least one target functional chip. Next, the interconnect chip can determine the target functional chip whose remaining available storage resources are greater than or equal to the storage resources required by the first functional chip, and whose access priority is greater than a preset threshold, as the second functional chip.

[0129] Optionally, this application does not limit the type of D2D interface protocol. For example, the D2D interface protocol may include, but is not limited to: Universal Chiplet Interconnect Express (UCIE) protocol, Advanced Cost-Driven Chiplet Interface (ACC) protocol, or other custom protocols.

[0130] In some embodiments, if the remaining available storage resources of the target functional core are less than the storage resources required by the first functional core, the interconnect core may send a notification that no storage resources are available to the first functional core.

[0131] Based on the aforementioned technical means, the interconnect chip can quickly determine the target functional chip that the first functional chip is allowed to access by obtaining the value of the interface register bit corresponding to the first functional chip. Then, the interconnect chip can determine the second functional chip from the target functional chips based on the storage resources of the target functional chip and the access priority of the target functional chip.

[0132] In some embodiments, the above-described scheduling of storage resources of the second functional core by the first functional core may specifically include:

[0133] In one possible implementation, after determining the second functional core, the interconnect core can schedule the storage resources of the second functional core for the first functional core based on the storage resources required by the first functional core, and send a resource scheduling message to the first functional core so that the first functional core can use the storage resources of the second functional core for data storage based on the resource scheduling message.

[0134] Among them, the resource scheduling message is used to indicate the storage resources of the second functional core.

[0135] Specifically, after the interconnect core determines the second functional core, it can determine the virtual address of the storage resource based on the physical address of the storage resource of the second functional core. Then, the interconnect core can send the virtual address of the storage resource of the second functional core to the first functional core, so that the first functional core can access the storage resource of the second functional core based on the virtual address of the storage resource of the second functional core.

[0136] Based on the above technical means, the interconnecting core can schedule the storage resources of the second functional core for the first functional core, so that the first functional core can access the storage resources of the second functional core, thereby improving the performance of the core interconnecting system and ensuring the efficient operation of the core interconnecting system.

[0137] In some embodiments, the interconnect chip can configure the value of each bit of the interface register through a configuration module, that is, configure the connectivity between any two D2D interfaces in the interconnect chip. The connectivity between any two D2D interfaces can include bidirectional connectivity, unidirectional connectivity, or no connectivity between the two D2D interfaces, with each D2D interface used to connect to a corresponding functional chip.

[0138] For example, the interconnect chip can be equipped with n+m interface registers, such as interface register RA1, interface register RA2, ..., interface register RAn, ..., interface register RB1, interface register RB2, ..., interface register RBm. Each interface register includes n+m bits, such as {a1, a2, ..., an, b1, b2, ..., bm}. Each bit corresponds to interface A1 (used to connect to functional chip A1), interface A2 (used to connect to functional chip A2), ..., interface An (used to connect to functional chip An), interface B1 (used to connect to functional chip B1), interface B2 (used to connect to functional chip B2), ..., interface Bm (used to connect to functional chip Bm).

[0139] The value of each bit in the interface register can be configured through the configuration module. The an bit of the interface register RAn indicates whether interface An is allowed to access all other interfaces. For example, interface register RA1.a1 = 1 indicates that interface A1 is allowed to access all other interfaces, and interface register RA1.a1 = 0 indicates that interface A1 is not allowed to access all other interfaces. The other bits of the interface register RAn, excluding the an bit, are used to indicate whether interface An is allowed to access other interfaces. For example, interface register RA1.a2 = 1 indicates that interface A1 is allowed to access interface A2, and RA1.a2 = 0 indicates that interface A1 is not allowed to access interface A2.

[0140] Based on the above, assuming the first functional chip is A1, and the other functional chips include functional chips A2, A3, and A4. The interconnecting chips can read the values ​​of bit a1 in interface register RA2, interface register RA3, and interface register RA4 respectively to determine whether functional chips A2, A3, and A4 allow the first functional chip A1 to access them.

[0141] Based on the above technical means, interconnecting cores can be configured with registers to determine the connectivity between each functional core according to actual needs, thereby improving the scalability and flexibility of the system.

[0142] In some embodiments, the virtual shared address table and physical shared address table of the shared address mapping unit in the interconnect chip are empty by default. Based on this, during the process of determining the second functional chip in the interconnect chip, the information in the shared address mapping unit and the shared address priority unit can be adjusted synchronously.

[0143] Specifically, the interconnect chip can obtain the remaining available storage resources sent by at least one target functional chip in the manner described above. Then, the interconnect chip can identify the target functional chip whose remaining available storage resources are greater than or equal to the required storage resources of the first functional chip as the second functional chip.

[0144] When at least two second functional cores are determined, the shared address priority unit can sort the second functional cores according to their access priorities. Then, the interconnect core can store the interface numbers of the second functional cores in the physical shared address table according to their access priorities (e.g., from high to low priority), and correspondingly store the physical address range numbers of the storage resources of the second functional cores. Simultaneously, the interconnect core can store the interface numbers of the first functional cores and the virtual address range numbers of the storage resources of each second functional core in the virtual shared address table.

[0145] For example, taking the case where the access priority of the second functional core A is higher than that of the second functional core B, the interconnect core can first store the interface number of the second functional core A and the physical address segment number of the storage resource in the physical shared address table through the storage address management module, and then store the interface number of the second functional core B and the storage number of the physical address segment of the storage resource. Simultaneously, the interconnect core can also store the interface number of the first functional core, the virtual address of the storage resource of the second functional core A, and the virtual address of the storage resource of the second functional core B in the virtual shared address table through the storage address management module.

[0146] Optionally, if the storage resources of the second functional chip have multiple physical address ranges, the physical address range numbers of the storage resources of the second functional chip can be stored in the physical shared address table in descending order of physical address range numbers. For example, they can be stored in descending order of physical address range numbers, or in ascending order of physical address range numbers.

[0147] Based on the above technical means, the interconnect core can store the interface number and physical address of the accessed side's storage resources in the physical shared address table according to the access priority of the accessed side's functional core (such as the second functional core), and store the virtual address of the accessed side's storage resources in the virtual address shared table, thereby improving the management of storage resources and ensuring the reasonable allocation and use of storage resources.

[0148] The following section uses the interaction between the interconnect chip, the first functional chip, and the second functional chip as an example to explain in detail how the interconnect chip determines the access priority of the second functional chip based on the transmission delay between the first and second functional chips. Figure 9 As shown, the method may specifically include S901-S907:

[0149] S901, the interconnect chip sends a detection task notification to the first functional chip.

[0150] The detection task notification is used to instruct the first functional core to detect the transmission delay between the first functional core and the second functional core.

[0151] S902, the first functional core sends a detection signal to the second functional core.

[0152] The second functional core is a functional core that allows the first functional core to access it.

[0153] Specifically, the first functional core can send detection signals to the second functional cores in the order of their numbering. For example, the first functional core A1 can send detection signals to the second functional cores A2, ..., An, B1, B2, ..., Bm in sequence.

[0154] S903, the second functional core sends a response signal to the first functional core.

[0155] S904. The first functional chip determines the transmission delay between the first functional chip and the second functional chip based on the transmission time of the detection signal and the reception time of the response signal.

[0156] S905. The first functional core determines whether to send a detection signal to all second functional cores. If yes, execute S906-S907. If no, the first functional core sends a detection signal to the next second functional core that has not sent a detection signal.

[0157] S906, The first functional chip sends the transmission delay between the first functional chip and each second functional chip to the interconnecting chip.

[0158] S907, the interconnecting core determines the access priority of each second functional core based on the transmission delay between the first functional core and each second functional core.

[0159] Specifically, the access priority of each second functional core can be determined according to the transmission delay between the first functional core and each second functional core. That is, the second functional core with the smallest transmission delay has the highest access priority, and the second functional core with the largest transmission delay has the lowest access priority.

[0160] When the transmission delay is the same between the first functional core and multiple second functional cores, the interconnecting core can determine the access priority of the second functional core according to the number of the second functional core.

[0161] For example, assuming that the transmission delay of the first functional core A1 is the same as that of the second functional cores A2, A3, and A4, the interconnecting core can set the access priority of the above three second functional cores to the access priority of second functional core A2 > access priority of second functional core A3 > access priority of second functional core A4.

[0162] Based on the above technical means, this application can determine the access priority of the second functional core based on the transmission delay of the first functional core and the second functional core. This allows the first functional core to schedule the transmission delay of the second functional core with the lowest transmission delay, thereby reducing the delay of the scheduling task and improving the operating efficiency of the system.

[0163] In some embodiments, if it is determined that the first functional chip does not need to use the storage resources of the second functional chip, the interconnect chip may send resource release information to the second functional chip.

[0164] The resource release information can be used to indicate that the first functional core no longer uses the storage resources of the second functional core. That is, the storage resources of the second functional core can be used by other functional cores.

[0165] In one possible implementation, the first functional core can send a resource release notification to the interconnect core, indicating that the storage resources of the second functional core are no longer needed. Upon receiving the resource release notification from the first functional core, the interconnect core can respond by sending resource release information to the second functional core.

[0166] In another possible implementation, the interconnect chip can detect the storage resource usage and / or operating status of the first functional chip. When the remaining available storage resources of the first functional chip exceed a resource warning threshold, and / or when the first functional chip stops working or its operating status is abnormal, the interconnect chip can send resource release information to the second functional chip.

[0167] Furthermore, the interconnect core can also delete the interface number of the second functional core and the physical address segment number of the storage resource of the second functional core in the physical shared address table through the storage address management module, as well as delete the interface number of the first functional core and the virtual address segment number of the storage resource of the second functional core in the virtual shared address table.

[0168] Based on the above technical means, this application can release storage resources of other functional cores scheduled by the first functional core when there are sufficient remaining available storage resources of the first functional core, thereby reducing the waste of storage resources and improving the utilization rate of storage resources.

[0169] In some embodiments, when the interconnecting core receives shared resource requests from at least two functional cores, such as Figure 10 As shown, the resource scheduling method provided in this application embodiment may further include: S1001-S1002.

[0170] S1001, Receive resource sharing requests sent by at least two functional cores.

[0171] S1002. According to the resource scheduling priority of each of the at least two functional cores, schedule the storage resources of other functional cores for each functional core.

[0172] Other functional cores are functional cores other than at least two functional cores among a plurality of functional cores.

[0173] Specifically, after receiving resource sharing requests from at least two functional cores, the interconnect core can store the resource sharing requests of each functional core into a first-in-first-out (FIFO) cache queue according to the resource scheduling priority of each of the at least two functional cores. That is, resource sharing requests from functional cores with higher resource scheduling priority are stored first, followed by resource sharing requests from functional cores with lower resource scheduling priority. Afterwards, the interconnect core can schedule storage resources for each functional core sequentially according to the order of resource sharing requests in the FIFO cache queue. The method by which the interconnect core schedules storage resources for each functional core can be referred to the method in S802 above for the interconnect core to schedule storage resources for the second functional core for the first functional core, and will not be elaborated here.

[0174] After allocating storage resources for a functional core, the interconnect core can remove the resource sharing request for that functional core from the FIFO cache queue and respond to the first resource sharing request in the FIFO cache queue until there are no more resource sharing requests in the FIFO cache queue.

[0175] Based on the above technical means, after the interconnected core receives resource sharing requests from multiple functional cores, the interconnected core can allocate storage resources to functional cores with high resource allocation priorities first, and then allocate storage resources to functional cores with low resource allocation priorities, thereby solving the problem of disordered scheduling and improving the scheduling efficiency of the core interconnection system.

[0176] In one possible implementation, the resource scheduling priority of the first functional core can be determined by any of the following parameters:

[0177] 1. Storage resources required for the first functional chip.

[0178] In some examples, the interconnect core can determine the resource scheduling priority of the first functional core based on the amount of storage resources required by the functional core. For example, the more storage resources the first functional core requires, the higher its resource scheduling priority; or, the less storage resources the first functional core requires, the higher its resource scheduling priority.

[0179] 2. Remaining available storage resources of the first functional core.

[0180] In some examples, the interconnect chip can determine the resource scheduling priority of the first functional chip based on the amount of remaining available storage resources of the first functional chip. The resource scheduling priority of the first functional chip can be inversely proportional to the remaining available storage resources of the first functional chip. For example, the less remaining available storage resources the first functional chip has, the higher its resource scheduling priority; the more remaining available storage resources the first functional chip has, the lower its resource scheduling priority.

[0181] 3. The value of the register bit corresponding to the first functional chip.

[0182] In some examples, an interconnect chip may be deployed with a priority register, which may include multiple bits, each corresponding to a functional chip. Based on this, the interconnect chip can determine the resource scheduling priority of a first functional chip according to the value of the priority register bit corresponding to that first functional chip. For example, the smaller the value of the register bit corresponding to the first functional chip, the higher its resource scheduling priority. Alternatively, the larger the value of the register bit corresponding to the first functional chip, the higher its resource scheduling priority.

[0183] For example, assuming there are n+m functional cores, the register PR has (n+m)*k bits, with each functional core corresponding to k bits. Specifically, bits 0 to k-1 (RP[k-1:0]) correspond to functional core A1, bits k to 2k-1 (RP[2k-1:k]) correspond to functional core A2, ..., bits (n-1)*k to n*k-1 (RP[n*k-1:(n-1)*k]) correspond to functional core An, ..., bits (n+m-1)*k to (n+m)*k-1 (RP[(n+m)*k-1:(n+m-1)*k]) correspond to functional core Bm. Wherein, 2 k ≥n+m.

[0184] Assuming that the smaller the value of the register bit corresponding to a functional core, the higher the resource scheduling priority of that functional core. In this case, assuming that RP[k-1:0] = 0 for functional core A1 and RP[2k-1:k] = 1 for functional core A2, then the resource scheduling priority of functional core A1 is greater than that of functional core A2.

[0185] Based on the above technical means, the resource scheduling priority of each functional core can be determined, so that the interconnect core can allocate resources reasonably based on the resource scheduling priority of the functional core, thereby reducing the situation where system performance is degraded due to resource contention.

[0186] The foregoing primarily describes the solutions provided by the embodiments of the present invention from a methodological perspective. To achieve the above functions, the resource scheduling device or electronic device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the present invention can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0187] Figure 11 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Figure 11 As shown, the electronic device includes, but is not limited to, a processor 1101 and a memory 1102.

[0188] The memory 1102 described above is used to store the executable instructions of the processor 1101. It is understood that the processor 1101 is configured to execute instructions to implement the resource scheduling method in the above embodiments.

[0189] It should be noted that those skilled in the art will understand that Figure 11The electronic device structure shown does not constitute a limitation on the electronic device; the electronic device may include, but is not limited to, other electronic devices. Figure 11 This may indicate more or fewer components, or combinations of certain components, or different component arrangements.

[0190] Processor 1101 is the control center of the electronic device. It connects various parts of the electronic device via various interfaces and lines. By running or executing software programs and / or modules stored in memory 1102, and by calling data stored in memory 1102, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. Processor 1101 may include one or more processing units. Optionally, processor 1101 may integrate an application processor and a modem processor. The application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into processor 1101.

[0191] The memory 1102 can be used to store software programs and various data. The memory 1102 may primarily include a program storage area and a data storage area. The program storage area may store the operating system, application programs required by at least one functional module (such as a determination unit, processing unit, etc.), etc. Furthermore, the memory 1102 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0192] In an exemplary embodiment, a computer-readable storage medium including instructions is also provided, such as a memory 1102 including instructions, which can be executed by a processor 1101 of an electronic device to implement the methods in the above embodiments.

[0193] Optionally, the computer-readable storage medium may be a non-transitory computer-readable storage medium, such as a read-only memory (ROM), random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device.

[0194] In an exemplary embodiment, this application also provides a computer program product including one or more instructions, which can be executed by the processor 1101 of an electronic device to perform the methods described above.

[0195] It should be noted that when one or more instructions in the computer-readable storage medium or computer program product are executed by the processor of an electronic device, they implement the various processes of the above method embodiments and achieve the same technical effect as the above method. To avoid repetition, they will not be described again here.

[0196] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0197] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0198] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the classified units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0199] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0200] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, essentially, or the part that contributes to the prior art, or a complete or partial classification of the technical solution, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0201] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip-to-chip interconnect system, characterized in that, The interconnect system includes interconnected cores and multiple functional cores; each functional core is configured with independent storage resources; the interconnected core is used to schedule storage resources of a second functional core for the first functional core in response to a resource sharing request from the first functional core; the first functional core is any one of the multiple functional cores, and the second functional core is any one of the multiple functional cores other than the first functional core.

2. The system according to claim 1, characterized in that, The interconnect chip is also used to release a first storage resource in response to a resource release notification from the first functional chip; the first storage resource is the storage resource of the second functional chip scheduled by the first functional chip.

3. The system according to claim 1, characterized in that, The interconnect chip includes a configuration module and a storage address management module; The configuration module is used to configure the resource scheduling priority of each functional core and to configure the accessibility between multiple functional cores. The storage address management module is used to manage the mapping relationship between the physical address and virtual address of the storage resources of each functional chip.

4. The system according to any one of claims 1-3, characterized in that, The interconnect chip also includes a cache module and a decoding module; The caching module is used to cache the access data of each of the functional cores; The decoding module is used to decode the physical address and virtual address of the storage resources of each functional chip.

5. The system according to claim 1, characterized in that, Each of the functional cores includes a processor cluster; the processor cluster is used to process data or perform computational tasks.

6. A resource scheduling method, characterized in that, The method, applied to the interconnect chip in any one of claims 1-5, comprises: Receive a resource sharing request sent by the first functional chip; the resource sharing request is used to request shared storage resources; In response to the resource sharing request, storage resources of the second functional core are scheduled for the first functional core; the second functional core is one of the other functional cores besides the first functional core.

7. The method according to claim 6, characterized in that, The second functional core must at least meet the following conditions: The second functional core allows the first functional core to access it; The remaining available storage resources of the second functional chip are greater than or equal to the storage resources required by the first functional chip; The access priority of the second functional core is greater than a preset threshold.

8. The method according to claim 7, characterized in that, The access priority of the second functional chip is determined by any one of the following parameters: Transmission delay between the first functional chip and the second functional chip; Configuration information of the second functional core; The interface number of the second functional core.

9. The method according to any one of claims 6-8, characterized in that, The method further includes: Send the virtual address of the storage resource of the second functional core to the first functional core; the virtual address is used by the first functional core to access the storage resource of the second functional core.

10. The method according to claim 6, characterized in that, The method further includes: Receive resource sharing requests from at least two of the aforementioned functional cores; Storage resources of other functional cores are scheduled for each of the at least two functional cores according to the resource scheduling priority of each of the functional cores; the other functional cores are functional cores other than the at least two functional cores among the plurality of functional cores.

11. The method according to claim 10, characterized in that, The resource scheduling priority of each of the aforementioned functional cores is determined by any one of the following parameters: The required storage resources for each of the aforementioned functional cores; The remaining available storage resources for each of the aforementioned functional cores; The value of the register bit corresponding to each of the aforementioned functional cores.

12. A resource scheduling method, characterized in that, The method, applied to a first functional core among a plurality of functional cores in the core interconnect system according to any one of claims 1-5, comprises: Send a resource sharing request to the interconnect chip; the resource sharing request is used to request shared storage resources; The system receives a resource scheduling message sent by the interconnecting core; the resource scheduling message is used to indicate the storage resources of the second functional core; the second functional core is one of the functional cores other than the first functional core. Data storage is performed using the storage resources of the second functional chip.

13. The method according to claim 12, characterized in that, The second functional core must at least meet the following conditions: The second functional core allows the first functional core to access it; The remaining available storage resources of the second functional chip are greater than or equal to the storage resources required by the first functional chip; The access priority of the second functional core is greater than a preset threshold.

14. The method according to claim 13, characterized in that, The access priority of the second functional chip is determined by any one of the following parameters: Transmission delay between the first functional chip and the second functional chip; Configuration information of the second functional core; The interface number of the second functional core.

15. The method according to any one of claims 12-14, characterized in that, The method further includes: The first functional core receives a virtual address of the storage resource of the second functional core sent by the interconnect core; the virtual address is used by the first functional core to access the storage resource of the second functional core. Based on the virtual address, access the storage resources of the second functional core.

16. An electronic device, characterized in that, include: The electronic device is configured with the chip interconnect system as described in any one of claims 1-5.

17. A vehicle, characterized in that, The vehicle is equipped with the electronic equipment described in claim 16.

18. A computer-readable storage medium, characterized in that, When the computer-executable instructions stored in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device performs the resource scheduling method as described in any one of claims 6-11, or the resource scheduling method as described in any one of claims 12-15.

19. A computer program product, characterized in that, The computer program product includes the computer program, which is adapted to be loaded by a processor and executed by the resource scheduling method as described in any one of claims 6-11, or the resource scheduling method as described in any one of claims 12-15.

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