Crossbar circuit, chip, electronic device

Abstract

A crossbar circuit, a chip and an electronic device. The crossbar circuit comprises N first circuits corresponding to N source modules and N second circuits corresponding to N destination modules, N is a positive integer greater than 1, each first circuit comprises a first multiplexer and a second multiplexer, and each second circuit comprises a first demultiplexer and a second demultiplexer, the first multiplexer of each second circuit is electrically connected with a write address channel of the destination module coupled with the second circuit, and the received write address request is used as an arbitration candidate to participate in arbitration of the first multiplexer of the corresponding destination module coupled with the second circuit, wherein after data information of the write data request corresponding to the received write address request enters the corresponding second first-in-first-out buffer module of the corresponding destination module, the received write address request is used as an arbitration candidate to participate in arbitration. The crossbar circuit can effectively improve the data transmission performance and avoid deadlock.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of electrical digital data processing technology, and more specifically to a cross switch circuit, chip, and electronic device. Background Technology

[0002] In multi-core processor architectures, data, as the core input for computational tasks, needs to be transferred from memory units to each processor core via on-chip networks (NoC). Memory units include both near-end memory (such as on-chip cache) that is close to the processor cores and has low access latency, and far-end memory (such as off-chip DRAM) that has larger capacity but higher latency. Ultimately, the computational units of different processor cores, such as CPU cores and GPU cores, complete the computation and data processing. When directly using NoC to connect all memory and processor cores, the physical wiring of the NoC grows exponentially with the increase in the number of cores and memory. This not only occupies a large amount of chip silicon area but also leads to signal attenuation, increased transmission latency, and increased power consumption due to excessively long wiring, severely limiting the overall chip performance and integration density. Summary of the Invention

[0003] This invention provides at least one embodiment of a cross-connect circuit configured to transmit received write address requests from write address channels and write data requests from write data channels of source modules to a destination module for corresponding processing. The cross-connect circuit includes N first circuits coupled to N source modules in a one-to-one correspondence, and N second circuits coupled to N destination modules in a one-to-one correspondence, where N is a positive integer greater than 1. Each first circuit includes a first multiplexer and a second multiplexer. The first multiplexer is electrically connected to the write address channel of the source module coupled to the first circuit, and the second multiplexer is electrically connected to the write data channel of the source module coupled to the first circuit. Each second circuit includes a first multiplexer and a second multiplexer. The first multiplexer is electrically connected to the write address channel of the destination module coupled to the second circuit, and the second multiplexer is electrically connected to the write data channel of the destination module coupled to the second circuit. The outputs of the N first multiplexers and the inputs of the N first multiplexers are interconnected in a one-to-one correspondence. A first cross-connected data transmission path is formed for the write address request. The outputs of N second multiplexers and the inputs of N second multiplexers are interconnected one-to-one to form a second cross-connected data transmission path for the write data request. Each second multiplexer is provided with N second first-in-first-out (FIFO) buffer modules corresponding one-to-one with the N destination modules. Each second FIFO buffer module is configured to buffer the write data request data information transmitted by the write data channel coupled to the second multiplexer in the order of reception. In the cross-connected circuit, the received write address request participates in the arbitration of the first multiplexer coupled to the corresponding destination module as an arbitration candidate, and obtains arbitration in response to the received write address request. The write data request corresponding to the received write address request is sent to the second multiplexer coupled to the corresponding destination module. After the data information of the write data request corresponding to the received write address request enters the second FIFO buffer module corresponding to the corresponding destination module, the received write address request then participates in the arbitration as an arbitration candidate.

[0004] For example, in the cross-connect circuit provided in at least one embodiment of this invention application, each first multiplexer is coupled to N first first-in-first-out (FIFO) buffer modules corresponding one-to-one with the N destination modules. Each first FIFO buffer module is configured to buffer write address requests destined for the destination module corresponding to the first FIFO buffer module in the order of receipt. Each second FIFO buffer module is configured to send a first signal to the corresponding first FIFO buffer module in response to the second FIFO buffer module being non-empty, wherein the corresponding first FIFO buffer module and the second FIFO buffer module correspond to the same destination module. Each first FIFO buffer module is configured to send a participation arbitration request to the second circuit coupled to the destination module corresponding to the first FIFO buffer module in response to receiving the first signal.

[0005] For example, in the cross switch circuit provided in at least one embodiment of this invention application, the cross switch circuit is further provided with N shared buffers that are coupled one-to-one with the N first circuits; each shared buffer is configured to receive and buffer write data requests transmitted by the write data channel of the coupled source module, and return the storage address of the buffered write data request in the shared buffer as the data information of the buffered write data request, wherein the shared buffer supports non-contiguous storage among multiple write data requests.

[0006] For example, in the cross-switch circuit provided in at least one embodiment of this invention, each write address request corresponds to P write data requests, and the P write data requests are transmitted continuously, where P is a positive integer greater than or equal to 1. Each first circuit also provides a register, which is configured to delay the received write data request by one clock cycle. For two consecutive write address requests, the last write data request among the P write data requests corresponding to the first write address request is transmitted to the corresponding second first-in-first-out buffer module in the first clock cycle, and the second transmitted write address request is also transmitted to the corresponding first first-in-first-out buffer module in the first clock cycle.

[0007] For example, in the cross switch circuit provided in at least one embodiment of the present invention, the cross switch circuit is further provided with N shared buffers that are coupled one-to-one with the N first circuits; the register is coupled between the shared buffers coupled to the first circuits and the write data channels coupled to the first circuits, and the received write data request is written to the shared buffers coupled to the first circuits after being delayed by one clock cycle through the register.

[0008] For example, in the cross-switch circuit provided in at least one embodiment of this application, the second first-in-first-out cache module includes multiple storage slots, each storage slot being used to store a write data request. In response to the received write address request having been arbitrated, the precondition for the next write address request adjacent to the received write address request to participate in the arbitration includes: in the second first-in-first-out cache module corresponding to the corresponding destination module, more than one storage slot contains data.

[0009] For example, in the cross-switch circuit provided in at least one embodiment of this application, the second circuit includes an arbitration unit configured to receive participation arbitration requests sent by each of the first circuits, generate an arbitration result, and when the last write data request of the P write data requests is transmitted to the corresponding second circuit, the arbitration unit in the corresponding second circuit receives a second signal, wherein the second signal is used to indicate that the currently transmitted write data request is the last write data request among the P write data requests; each second first-in-first-out cache module is further configured to send a first number of storage slots currently storing data in the second first-in-first-out cache module to the arbitration unit in the coupled second circuit, and each arbitration unit is further configured to: upon receiving a participation arbitration request for any write address request: in response to not receiving the second signal, or receiving the second signal and the first number received being greater than 1, to include the any write address request as the arbitration candidate to participate in arbitration; in response to receiving the second signal and the first number received being equal to 1, to determine that the any write address request cannot be the arbitration candidate; wherein the second signal and the first number received by the arbitration unit correspond to the same source module as the any write address request.

[0010] For example, in the cross switch circuit provided in at least one embodiment of this application, each first circuit is provided with a third first-in-first-out (FIFO) cache module. The first circuit is configured to: after each write address request enters the first circuit, obtain index information for indicating the destination module of the write address request based on the write address request, store the write address request in the first FIFO cache module corresponding to the destination module, and store the index information in the third FIFO cache module.

[0011] For example, in the cross switch circuit provided in at least one embodiment of this application, the cross switch circuit is further provided with N shared buffers that are coupled one-to-one with the N second multiplexers; the first circuit is further configured to, after the write data request corresponding to the received write address request enters the first circuit, extract the index information from the third first-in-first-out buffer module, and store the data information of the write data request corresponding to the received write address request into the second first-in-first-out buffer module indicated by the index information according to the index information.

[0012] For example, in the cross-connect circuit provided in at least one embodiment of this application, each second circuit is further provided with a fourth first-in-first-out (FIFO) buffer module and an arbitration unit. The arbitration unit is configured to receive arbitration participation requests sent by each first circuit and generate an arbitration result. The first multiplexer in the second circuit is configured to select and output a corresponding write address request according to the arbitration result, so as to transmit it to the destination module coupled to the second circuit. The fourth FIFO buffer module is configured to buffer the arbitration result. The second multiplexer in the second circuit is further configured to read the arbitration result from the fourth FIFO buffer module, select and output a corresponding write data request according to the arbitration result, so as to transmit it to the destination module coupled to the second circuit.

[0013] This application provides at least one embodiment of a chip, including the cross switch circuit as described in any embodiment of this application.

[0014] This application provides at least one embodiment of an electronic device, including a chip as described in any embodiment of this application.

[0015] In the cross-connect circuit provided in at least one embodiment of this invention, to prevent deadlock, the write address request can only participate in arbitration after the data information of the write data request corresponding to the received write address request enters the second first-in-first-out buffer module corresponding to the corresponding destination module. This prevents the situation where the write data corresponding to the write address request occupying the arbitration cannot be transmitted even after the write address request has occupied the arbitration, for example, when the resources of the write data channel are occupied by other requests. This eliminates the loop waiting conditions that lead to deadlock, fundamentally preventing the occurrence of deadlock and effectively improving data transmission performance; it also eliminates the need to expand the input buffer, reducing resource overhead and area occupation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0017] Figure 1 A schematic diagram illustrating data writing from a multi-master device to a multi-slave device. Figure 2 This is a schematic diagram of the structure of a cross switch circuit provided in at least one embodiment of the present disclosure; Figure 3 A schematic structural diagram of a first circuit provided for at least one embodiment of this disclosure; Figure 4 A schematic structural diagram of a second circuit provided in an embodiment of this disclosure; Figure 5 This is a timing diagram showing the continuous transmission of write requests to the crossbar switch circuit under a Burst transmission mode. Figure 6 This is a timing diagram of a write request entering the crossbar switch circuit. Figure 7 A timing diagram of a write request provided for at least one embodiment of this disclosure; Figure 8 A schematic structural diagram of a first circuit provided for another embodiment of this disclosure; Figure 9 A schematic structural diagram of a second circuit provided for at least one embodiment of this disclosure; Figure 10 A schematic diagram of a cross switch circuit provided in an embodiment of this disclosure; Figure 11 A schematic structural diagram of a chip provided for at least one embodiment of this disclosure; Figure 12 This is a schematic diagram of the architecture of a general-purpose graphics processing unit (GPGPU). Figure 13 A schematic structural diagram of an electronic device provided for at least one embodiment of this disclosure; Figure 14 This is a schematic diagram of the specific structure of an electronic device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0019] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0020] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and known components have been omitted.

[0021] In multi-core processors, data is often loaded from near-end / far-end memory units to different processor cores for computation / processing via an on-chip network bus. As mentioned above, directly connecting all memory units and processor cores using an on-chip network would result in an exponential increase in physical wiring.

[0022] The crossbar architecture is a hardware interconnect scheme that employs a matrix switching structure. This architecture establishes a fully connected topology between multiple input and output ports, enabling dynamic connections from any input to output through crossbar switches. Its core characteristics lie in supporting concurrent communication between multiple sets of input and output ports, providing non-blocking communication capabilities, high parallelism, and reconfigurable connection flexibility. Within multi-core processors, the crossbar architecture is often used as a high-speed data path between the processor's internal computing units and the memory system, with data flowing between multiple master ports and multiple slave ports via the crossbar switches.

[0023] Figure 1 This is a schematic diagram illustrating the process of writing data from a multi-master device to a multi-slave device.

[0024] like Figure 1As shown, there are three slave devices (device 0 to slave 2) and three master devices (master devices 0 to master 2). When data is transmitted from a master device to a slave device, master device 0 returns data packets of varying sizes to different slave devices, such as slave device 0, slave device 1, etc., according to the source index of the write request. Master device 1 also returns data packets of varying sizes to different slave devices according to the source index of the write request. In one clock cycle, a slave device will only receive data packets sent by one master device. If slave device 0 receives data packets returned by two master devices (e.g., master device 0 and master device 1) simultaneously, arbitration is required between these two data packets from different sources. The data packet that wins the arbitration (is selected) can continue to be returned to the corresponding slave device.

[0025] The AXI (Advanced Extensible Interface) protocol is a bus protocol designed specifically for high-performance on-chip systems. This protocol achieves high-bandwidth data transmission and low-latency access by employing a separate read / write channel structure, supporting burst transmission modes and out-of-order completion mechanisms. Its standardized interface design ensures broad compatibility with various IP (Intellectual Property) cores and provides excellent system scalability. The crossbar interconnect architecture based on the AXI protocol, with its high concurrency and configurability, has become the preferred solution for achieving efficient communication between multiple modules in complex on-chip systems.

[0026] The AXI protocol decomposes the bus communication link into five independent unidirectional transmission channels: Write Address (AW), Write Data (W), Write Response (B), Read Address (RW), and Read Data (R), achieving complete decoupling between read and write operations. Each channel has its own independent handshake timing and transmission path, without consuming resources or blocking timing, supporting the synchronous parallel execution of read and write transactions. Simultaneously, address and data transmission within a single transaction can be pipelined, initiating subsequent requests without waiting for the complete completion of a single transaction. This significantly improves the parallel transmission capabilities of on-chip interconnects at the architectural level, adapting to concurrent interaction scenarios with multiple inputs and multiple outputs in crossbar switching circuits.

[0027] In current high-performance processor architectures, the AXI bus, as an on-chip interconnect protocol designed for high bandwidth and low latency, has become a core infrastructure for data transmission between multiple master and slave devices. To meet the needs of concurrent data interaction between multiple master and slave devices, crossbar switch architectures based on the AXI bus are widely used.

[0028] In a Crossbar architecture based on the AXI bus, deadlocks may occur in certain scenarios due to the "Collins 4 conditions," causing the system to stagnate and malfunction. A typical example is multicast deadlock. Figure 1 For example, write address request AW1 issued by master device 0 occupies the arbitration of slave device 1 and waits for write data WD1; write address request AW0 issued by master device 0 waits for arbitration on slave device 0, and write data WD0 fills the input buffer, blocking write data WD1; write address request AW3 issued by master device 1 occupies the arbitration of slave device 0 and waits for write data WD3; write address request AW2 issued by master device 1 waits for arbitration on slave device 1, and write data WD2 fills the input buffer, blocking write data WD3. In this scenario, the two master devices cross-occupy the slave device arbitration resources, and their respective write data channels fill the input buffer, causing reverse blocking, forming a circular waiting loop, which satisfies the Collins deadlock four conditions and triggers deadlock.

[0029] Traditional solutions to this problem typically consider the input buffer as insufficient, increasing its size to resolve write channel blocking. However, this approach still fails to address situations like multiple consecutive write requests within a single channel, where the input buffer can become full, leading to deadlock. In other words, simply increasing the input buffer only alleviates the probability of blocking; it cannot fundamentally prevent deadlock by filling the buffer in scenarios with continuous batch writes. This creates a loop of mutual waiting within the system, resulting in deadlock.

[0030] This disclosure provides at least one embodiment of a cross switch circuit, chip, and electronic device. In at least one embodiment of the cross-connect circuit provided in this disclosure, the cross-connect circuit is configured to transmit received write address requests from write address channels and write data requests from write data channels of source modules to destination modules for corresponding processing. The cross-connect circuit includes N first circuits coupled one-to-one with N source modules and N second circuits coupled one-to-one with N destination modules. Each first circuit includes a first multiplexer and a second multiplexer. The first multiplexer is electrically connected to the write address channel of the source module coupled to the first circuit, and the second multiplexer is electrically connected to the write data channel of the source module coupled to the first circuit. Each second circuit includes a first multiplexer and a second multiplexer. The first multiplexer and the second multiplexer are electrically connected to the write address channel of the destination module coupled to the second circuit, and the second multiplexer and the second multiplexer are electrically connected to the write data channel of the destination module coupled to the second circuit. The output terminals of the N first multiplexers and the input terminals of the N first multiplexers are interconnected one-to-one to form a first cross-connect data for write address requests. The transmission path consists of N second multiplexers, each with its output and input, interconnected to form a second cross-connected data transmission path for write data requests. Each second multiplexer has N second first-in-first-out (FIFO) buffer modules corresponding to N destination modules. Each FIFO buffer module is configured to buffer the write data request data transmitted via the write data channel coupled to the second multiplexer in the order of reception. In the cross-connected circuit, the received write address request participates in the arbitration of the first multiplexer coupled to the corresponding destination module as an arbitration candidate and obtains arbitration in response to the received write address request. The write data request corresponding to the received write address request is sent to the second multiplexer coupled to the corresponding destination module. The prerequisite for the received write address request to participate in the arbitration of the first multiplexer coupled to the corresponding destination module includes at least the following: after the data information of the write data request corresponding to the received write address request enters the second FIFO buffer module corresponding to the corresponding destination module, N is a positive integer greater than 1.

[0031] In the cross-connect circuit provided in at least one embodiment of this disclosure, to prevent deadlock, the write address request can only participate in arbitration after the data information of the write data request corresponding to the received write address request enters the second first-in-first-out buffer module corresponding to the corresponding destination module. This prevents the situation where the write data corresponding to the write address request occupying the arbitration cannot be transmitted even after the write address request has occupied the arbitration, for example, when the resources of the write data channel are occupied by other requests. This eliminates the loop waiting conditions that lead to deadlock, fundamentally preventing the occurrence of deadlock and effectively improving data transmission performance; it also eliminates the need to expand the input buffer, reducing resource overhead and area occupation.

[0032] The circuit structure of the cross switch circuit provided in at least one embodiment of this disclosure will be described in detail below with reference to the accompanying drawings.

[0033] Figure 2 This is a schematic diagram of the structure of a cross switch circuit provided in at least one embodiment of the present disclosure.

[0034] The cross switch circuit 100 is coupled to N source modules and N destination modules, where N is a positive integer greater than 1. Figure 2 For convenience, source module a1 and source module a2, as well as destination module b1 and destination module b2 are shown in the diagram. However, it should be noted that there may also be source module a3, destination module b3, etc., which will not be elaborated here.

[0035] For example, depending on actual needs, the source module and the destination module can be different hardware components. For example, in one embodiment, the source module can be multiple storage units in a storage component, and the destination module can be multiple processing cores; in another embodiment, the source module can be a processing core, and the destination module can be a storage unit. Of course, in other examples, the source module and the destination module can also have other structural forms, and this disclosure does not impose specific limitations on them.

[0036] For example, storage components are configured to store data. For example, storage components can be memory (e.g., high-bandwidth memory HBM), cache (e.g., L2 cache), etc., and this disclosure does not impose any specific limitations on them.

[0037] For example, memory can be divided into multiple memory blocks, each of which can independently respond to read and write requests. Multiple memory blocks can work in parallel, improving overall throughput. For example, each memory block can serve as a destination module or a source module.

[0038] For example, the processing core can be a GPU core, a CPU core, or a multiprocessor core; or, the processing core can be a computing core in a GPU core, etc. This disclosure does not impose specific restrictions on this. The processing core can be a component that needs to use data in the storage component for processing and calculation, and its structure and function can be set as needed.

[0039] For example, a crossbar switch circuit can transmit data to the processing core via a bus, such as an on-chip network bus.

[0040] The cross switch circuit 100 is configured to transmit the write address request received from the write address channel and the write data request received from the write data channel of the source module to the destination module for corresponding processing.

[0041] For example, a crossbar switch circuit can send the write data request from the source module to the corresponding destination module among N destination modules based on the destination address (source index) in the write address request, so as to perform subsequent calculations or processing.

[0042] The cross switch circuit 100 includes N first circuits 101, each corresponding to one of the N source modules, and N second circuits 102, each corresponding to one of the N destination modules. For example... Figure 2 As shown, a first circuit 101_1 coupled to source module a1, a first circuit 101_2 coupled to source module a2, and a second circuit 102_1 coupled to destination module b1 and a second circuit 102_2 coupled to destination module b2 are illustrated. The structure and connection relationships of the other first and second circuits are similar to those shown. Figure 2 The first and second circuits shown are similar and will not be shown again here.

[0043] It should be noted that, in Figure 2 In the example, to distinguish between the first circuit coupled to different source modules and the second circuit coupled to different destination modules, the first circuit is represented as 101_1, 101_2, and the second circuit is represented as 102_1, 102_2, etc. The same applies to other cases, such as the first multiplexer, where different suffixes are used to describe the coupling to different source or destination modules, which will not be elaborated further here.

[0044] Each first circuit 101 includes a first multiplexer 103 and a second multiplexer 104. The first multiplexer 103 is electrically connected to the write address channel of the source module coupled to the first circuit 101, and the second multiplexer 104 is electrically connected to the write data channel of the source module coupled to the first circuit 101.

[0045] like Figure 2 As shown, taking source module a1 as an example, the first circuit 101_1 is coupled to source module a1. The first multiplexer (DMUX) 103_1 in the first circuit 101_1 is electrically connected to the write address channel of source module a1 and is used to receive the write address request AW_REQ transmitted from source module a1. The second multiplexer 104_1 in the first circuit 101_1 is electrically connected to the write data channel of source module a1 and is used to receive the write data request W_REQ transmitted from source module a1.

[0046] In this disclosure, write data requests may include variable-length data packets, such as a single data packet to be sent. Taking Burst transmission as an example, in a single transaction, the source module sends only one write address request, which corresponds to multiple write data requests. For subsequent write data requests, their data addresses are automatically generated by the hardware, thereby enabling the continuous transmission of a batch of data packets, achieving one address and batch transmission.

[0047] For example, the data length of a data packet is the bandwidth of the data bus from the source module to the second multiplexer.

[0048] Each second circuit includes a first multiplexer and a second multiplexer, the first multiplexer and the second circuit being electrically connected to the write address channel of the destination module coupled to the destination module, and the second multiplexer and the second circuit being electrically connected to the write data channel of the destination module coupled to the destination module.

[0049] like Figure 2 As shown, taking destination module b1 as an example, the second circuit 102_1 is coupled to destination module b1. The first multiplexer (MUX) 105_1 in the second circuit 102_1 is electrically connected to the write address channel of destination module b1 and is used to send the arbitrated write address request AW_REQ to the corresponding destination module. The second multiplexer 106_1 in the second circuit 102_1 is electrically connected to the write data channel of destination module b1 and is used to send the arbitrated write data request W_REQ to the corresponding destination module.

[0050] The outputs of N first multiplexers and the inputs of N first multiplexers are interconnected one-to-one to form a first crossbar data transmission path for write address requests. The outputs of N second multiplexers and the inputs of N second multiplexers are interconnected one-to-one to form a second crossbar data transmission path for write data requests.

[0051] Specifically, the inputs of N first multiplexers are coupled one-to-one with the write address channels of N source modules, and the outputs of N first multiplexers are coupled one-to-one with the write address channels of N destination modules; the N outputs of each first multiplexer are coupled to one input of each of the N first multiplexers; the inputs of N second multiplexers are coupled one-to-one with the write data channels of N source modules; the outputs of N second multiplexers are coupled one-to-one with the write data channels of N destination modules, and the N outputs of each second multiplexer are coupled to one input of each of the N second multiplexers.

[0052] like Figure 2 As shown, multiple outputs of the first multiplexer are coupled to one input of each of the multiple first multiplexers. For example, the two outputs of the first multiplexer 103_1 are coupled to one input of the first multiplexer 105_1 and one input of the first multiplexer 105_2, respectively. The other multiplexers are handled similarly. Thus, data from the source module can be transmitted to any destination module connected via a crossbar switch circuit.

[0053] Each second multiplexer has N second first-in-first-out (FIFO) buffer modules corresponding one-to-one with N destination modules. Each second FIFO buffer module is configured to buffer the write data request data transmitted by the write data channel coupled to the second multiplexer in the order of receipt.

[0054] Figure 2 This illustrates multiple second first-in-first-out (FIFO) buffer modules coupled to the second multiplexer 104_1, namely... Figure 2 The multiplexers include FIFO_21, FIFO_22, etc., where FIFO_21 corresponds to destination module b1, FIFO_22 corresponds to destination module b2, and so on. For example, FIFO_21 is coupled to the second multiplexer 106_1, and FIFO_22 is coupled to the second multiplexer 106_2.

[0055] The second FIFO (First-In-First-Out) cache module FIFO_21 is configured to cache write data requests sent by source module a1 in the order of reception, and FIFO_21 also caches write data requests destined for destination module b1 (e.g., indicated by the source index). Similarly, FIFO_22 is configured to cache data packets sent by source module a1 in the order of reception, and FIFO_22 also caches write data requests destined for destination module b2. Other second FIFO cache modules are configured similarly and will not be described further here.

[0056] In the cross switch circuit, the received write address request participates in the arbitration of the first multiplexer coupled to the corresponding destination module as an arbitration candidate, and obtains arbitration in response to the received write address request. The write data request corresponding to the received write address request is sent to the second multiplexer coupled to the corresponding destination module.

[0057] In this disclosure, after the data information of the write data request corresponding to the received write address request enters the second first-in-first-out (FIFO) cache module corresponding to the corresponding destination module, the received write address request then participates in arbitration as an arbitration candidate. That is, the prerequisite for the received write address request to participate in the arbitration of the first multiplexer coupled to the corresponding destination module in this disclosure includes at least the following: after the data information of the write data request corresponding to the received write address request enters the second FIFO cache module corresponding to the corresponding destination module.

[0058] In this disclosure, for a write request, the write address request in the write request is used as an arbitration candidate to participate in arbitration. After obtaining arbitration, the write data request and the write address request in the write request are sent to the second multiplexer coupled to the corresponding destination module, and then transmitted to the corresponding destination module.

[0059] For the AXI bus, its write address channel and write data channel are not guaranteed to be synchronized. Therefore, a write data request may not arrive at the first circuit simultaneously with the corresponding write address request. Thus, unlike current methods that immediately participate in arbitration upon the arrival of a write address request, in this disclosure, the prerequisite for a received write address request to participate in the arbitration of the first multiplexer coupled to the corresponding destination module includes at least the following: after the data information of the write data request corresponding to the received write address request enters the second first-in-first-out buffer module corresponding to the corresponding destination module.

[0060] For example, a write request includes a write data request transmitted via the write data channel and a write address request transmitted via the write address channel. For a write request, it is necessary to ensure that its write data request has passed through the second data distributor and is ready to enter the second multiplexer before the write address request is allowed to participate in the arbitration of the first multiplexer. This prevents a write address request from occupying the write data channel resources after arbitration while waiting for those resources to be used by other requests, thus eliminating the loop waiting conditions that lead to deadlock and fundamentally preventing deadlock from occurring, effectively improving data transmission performance; it also eliminates the need to expand the input buffer, reducing resource overhead and area usage.

[0061] For example, with Figure 2 For example, suppose that for write request wq1, its write address request AW1 has reached the first circuit, but its write data request W1 has not yet passed through the second multiplexer 104_1. At this time, write address request AW1 cannot participate in arbitration. Only after write data request W1 passes through the second multiplexer 104_1 and enters a second first-in-first-out buffer module (e.g., FIFO_21) can write address request AW1 participate in the arbitration of the first multiplexer 105_1.

[0062] Figure 3 A schematic structural diagram of a first circuit provided for at least one embodiment of this disclosure.

[0063] exist Figure 3 In the example, the first circuit 101_1 is used as an example for description. The structure of other first circuits can be referred to the first circuit 101_1, and will not be repeated here.

[0064] For example, each first multiplexer is coupled to N first first-in-first-out (FIFO) cache modules, which correspond one-to-one with N destination modules. Each first FIFO cache module is configured to cache write address requests destined for the destination module corresponding to that first FIFO cache module in the order of receipt.

[0065] For example, such as Figure 3 As shown, the first multiplexer 103_1 is coupled to multiple first first-in-first-out (FIFO) buffer modules, for example, it could be... Figure 3The FIFOs are FIFO_11, FIFO_12, and FIFO_13. For example, FIFO_11 corresponds to and can be coupled to destination module b1; FIFO_12 corresponds to and can be coupled to destination module b2, and so on. For example, FIFO_11 is configured to buffer write address channels from source module a1 and write address requests destined for destination module b1 in the order of reception; FIFO_12 is configured to buffer write address channels from source module a1 and write address requests destined for destination module b2 in the order of reception, and so on.

[0066] For example, FIFO_11 is configured to buffer write address requests transmitted via the write address channel of source module a1 coupled to the first multiplexer 103_1 in the order of reception, and FIFO_12 is configured to buffer write address requests transmitted via the write address channel of source module a2 coupled to the first multiplexer 103_2 in the order of reception.

[0067] After completing a new arbitration, the first multiplexer locks the arbitration result until all write data requests in a burst transmission have been sent to the destination module before starting a new round of arbitration. Since both the write data channel and the write address channel are in order-preserving transmissions, and the same first-in-first-out (FIFO) buffer module only submits the next write address request after the previous one is completed, when a write address request enters the first FIFO buffer module and is ready to participate in arbitration, it is only necessary to ensure that data exists in the second FIFO buffer module for the write data request and the write address request to be considered to have completed synchronously.

[0068] Each second FIFO buffer module is configured to: in response to the second FIFO buffer module being non-empty, send a first signal to the corresponding first FIFO buffer module, wherein the corresponding first FIFO buffer module and the second FIFO buffer module correspond to the same destination module.

[0069] Each first-in-first-out (FIFO) buffer module is configured to: in response to receiving a first signal, send a request to participate in arbitration to the second circuit coupled to the destination module corresponding to the first FIFO buffer module.

[0070] For example, a signal line can be set between the second FIFO buffer module and the corresponding first FIFO buffer module to transmit the first signal. Here, "corresponding" means that the second FIFO buffer module and the corresponding first FIFO buffer module are both coupled to the same second circuit and correspond to the same destination module.

[0071] For example, when the second FIFO cache module is empty, an empty flag signal is sent to the corresponding first FIFO cache module. At this time, even if a write address request enters the first FIFO cache module, no arbitration request will be sent. When the second FIFO cache module is not empty, a first signal is sent to the corresponding first FIFO cache module, and the first FIFO cache module sends an arbitration request to the coupled second circuit.

[0072] exist Figure 3 The diagram shows the signal lines between FIFO_21 and FIFO_11. Signal lines are also provided between FIFO_22 and FIFO_12, and between FIFO_23 and FIFO_13, but are not shown in the diagram.

[0073] For example, a request to participate in arbitration can be a valid signal sent to the multiplexer. After receiving the request, the second circuit determines which path to select based on the arbitration mechanism and other conditions. Then, it returns an indication signal (e.g., a ready signal) to the first FIFO buffer module coupled to that path. At this time, the first FIFO buffer module completes a valid+ready handshake. Then, the first FIFO buffer module can read out the first write address request (POP) and send it to the corresponding second circuit.

[0074] For example, since a write address request also needs to go through processes such as index information retrieval, storage in the third FIFO cache module, and reading (see below), the write address request can first enter the corresponding first FIFO cache module. For example, suppose write address request AW1 enters FIFO_11, and at this time, the first signal has not been received, so no valid signal is sent to participate in arbitration; when write data request W1 corresponding to write address request AW1 enters FIFO_21, FIFO_21 is not empty, and at this time, the first signal is sent to the first FIFO cache module FIFO_11; after receiving the first signal, FIFO_11 sends a valid signal for the write address request AW1 to the first multiplexer 105_1 to participate in arbitration.

[0075] The crossbar switch circuit also has N shared buffers coupled one-to-one with the N first circuits. Each shared buffer is configured to receive and buffer write data requests transmitted from the write data channel of the coupled source module, and return the storage address of the buffered write data request in the shared buffer as the data information of the buffered write data request. The shared buffer supports non-contiguous storage among multiple write data requests.

[0076] For example, a shared cache can reuse a shared cache in a graphics processor or a general-purpose graphics processor.

[0077] For example, Figure 2The first circuit 101_1 can be coupled to a shared buffer 1, the first circuit 101_2 can be coupled to a shared buffer 2, and so on. (See reference) Figure 3 This shows that the write data channel of source module a1 is coupled to shared buffer 1.

[0078] Unlike the FIFO (First-In, First-Out) cache module, the shared buffer supports non-contiguous storage of multiple returned data packets. For example, write data requests returned sequentially can be stored in the shared buffer in the order they were received, or they can be stored non-contiguously. When accessing the shared buffer, data packets at any position can be retrieved by reading their addresses.

[0079] For example, shared cache 1 is configured to cache write data requests returned by cache source module a1, shared cache 2 is configured to cache write data requests returned by cache source module a2, and so on.

[0080] For example, in some embodiments, the first circuit is configured to store the write data request received from the coupled source module into a shared buffer area coupled to the first circuit, and store the storage address of the received write data request in the shared buffer area as the data information of the write data request into the second first-in-first-out buffer module corresponding to the destination module of the received data packet.

[0081] In this embodiment, data is stored in a shared cache area. Only the storage address of the write data request in the shared cache area is stored as data information in the second first-in-first-out cache module. The storage capacity of the second first-in-first-out cache module can be set to be relatively small, especially for large bit-width write data. This method can ensure the data transmission order while flexibly allocating buffer resources, saving buffer space, and effectively saving chip area.

[0082] For example, in some other embodiments, the data information is the data in the write data request, that is, the data in the write data request is stored in the second first-in-first-out cache module.

[0083] For example, each first circuit is equipped with a third first-in-first-out (FIFO) cache module. The first circuit is configured such that after each write address request enters the first circuit, it obtains index information indicating the destination module of the write address request based on the write address request, stores the write address request in the first FIFO cache module corresponding to the destination module, and stores the index information in the third FIFO cache module.

[0084] For example, refer to Figure 3 After a write address request enters the first circuit, a hash operation is performed on the write address request to obtain the index information indicating the destination module corresponding to the write address request. Based on the index information, the write address request is then cached in the corresponding first-in-first-out cache module.

[0085] In addition, the index information is also stored in the third first-in-first-out cache module FIFO3 for caching the corresponding write data requests.

[0086] For example, in some other embodiments, when the cross switch circuit is further provided with N shared buffers that are coupled one-to-one with N second multiplexers, the first circuit is further configured to, after the write data request corresponding to the received write address request enters the first circuit, extract index information from the third first-in-first-out buffer module, and store the data information of the write data request corresponding to the received write address request into the second first-in-first-out buffer module indicated by the index information according to the index information.

[0087] For example, in this disclosure, a write data request corresponding to a write address request refers to a write data request being transmitted to a specified location of the destination module according to the write address request.

[0088] For example, as mentioned above, the index information corresponding to the write address request has been stored in the third first-in-first-out cache module FIFO3; then, when the write data request corresponding to the write address request enters the first circuit, the write data request is stored in the shared buffer, and the storage address of the returned write data request in the shared buffer is used as data information and stored in the corresponding second first-in-first-out cache module according to the index information.

[0089] For example, in a specific example, refer to Figure 3 When the current write address request AW1 enters the first circuit 101_1, the aforementioned hash operation is first performed to obtain the index information corresponding to the write address request AW1. Then, based on the index information, the write address request AW1 is stored in the corresponding first first-in-first-out cache module, such as FIFO_11, and the index information is stored in FIFO3. When the write data request W1 corresponding to the write address request AW1 enters the first circuit, the write data request W1 is first stored in the shared buffer 1, and the storage address of the write data request W1 in the shared buffer 1 is used as data information. The aforementioned index information is read from the third first-in-first-out cache module FIFO3, and through the second multiplexer 104_1, the data information (i.e., the storage address) is stored in FIFO_21 based on the index information.

[0090] Based on the above, before write data request W1 enters FIFO_21, although write address request AW1 has entered FIFO_11, no valid signal is sent. Only after write data request W1 enters FIFO_21 does FIFO_21 send the first signal to FIFO_11. After receiving the first signal, FIFO_11 sends a valid signal for write address request AW1 as a request to participate in arbitration to the first multiplexer 105_1 to participate in arbitration.

[0091] For example, each second circuit also includes a fourth FIFO buffer module and an arbitration unit. The arbitration unit is configured to receive arbitration requests from each first circuit and generate an arbitration result. The first multiplexer in the second circuit is configured to select the corresponding path based on the arbitration result and output the corresponding write address request for transmission to the destination module coupled to the second circuit. The fourth FIFO buffer module is configured to buffer the arbitration result.

[0092] The second multiplexer in the second circuit is also configured to read the arbitration result from the fourth first-in-first-out buffer module, select the corresponding path according to the arbitration result, and output the corresponding write data request to transmit it to the destination module coupled to the second circuit.

[0093] Figure 4 This is a schematic structural diagram of a second circuit provided in an embodiment of the present disclosure.

[0094] exist Figure 4 In the example, the second circuit 102_1 is used as an example for description. The structure of other second circuits can be referred to the structure of the second circuit 102_1, and will not be described in detail here.

[0095] like Figure 4 As shown, the second circuit 102_1 includes a fourth first-in-first-out buffer module FIFO4 and an arbitration unit.

[0096] The arbitration unit is configured to receive arbitration participation requests sent by each of the first circuits and generate an arbitration result according to the arbitration mechanism. For example, an arbitration participation request can be a valid signal. When the arbitration unit receives a valid signal, it will arbitrate the source module that sent the valid signal as an arbitration candidate.

[0097] For example, arbitration mechanisms can be set up according to predetermined rules, such as priority, order of requests, etc., and this disclosure does not impose specific restrictions on them.

[0098] For example, after receiving a request to participate in arbitration, the second circuit determines which path to select (i.e., the arbitration result) based on the arbitration mechanism and other conditions. Then, it returns an indication signal (e.g., a ready signal) to the first first-in-first-out (FIFO) buffer module corresponding to that path. At this time, the first FIFO buffer module completes a valid+ready handshake. Then, the first FIFO buffer module can read out the first write address request (POP) and send it to the corresponding second circuit.

[0099] Simultaneously, after generating the arbitration result, the arbitration unit sends it to the first multiplexer 105_1 to select the corresponding path and output the write address request for that path. Furthermore, the arbitration result is cached in the fourth FIFO buffer module 4. Based on the arbitration result, the second circuit returns an indication signal (e.g., a ready signal) to the second FIFO buffer module indicated by the arbitration result. At this point, the second FIFO buffer module completes a valid+ready handshake. Then, the second FIFO buffer module can read the data information of the first P write data requests (POP), find the data at the corresponding storage location in the shared buffer, and send it to the second multiplexer. This data is then output from the corresponding path selected by the second multiplexer.

[0100] In the AXI bus protocol, for a given write request, the write data channel does not carry address information; it needs to obtain the address information from the write address channel. However, the AXI bus does not guarantee synchronization between the write address channel and the write data channel. Therefore, the write address AW and write data W of a given write request may not necessarily enter the crossbar switch circuit simultaneously. In the crossbar switch circuit, a FIFO (First In First Out) is commonly used to store the index information generated after the write address has been processed, and this information is output to the write data channel to help it determine which slave device port to forward the request to.

[0101] Burst transmission mode is a common data transmission mode in which the master device only needs to initiate an address and configuration information handshake once to continuously complete the batch transmission of multiple sets of data.

[0102] Figure 5 This is a timing diagram showing the continuous transmission of write requests to the crossbar switch circuit under a Burst transmission mode.

[0103] Figure 5 The diagram illustrates two write requests. The first write request includes a write address request AW1 transmitted via the write address channel and four write data requests W1 transmitted via the write data channel. Thus, a single write address request AW1 can complete the batch transmission of four write data requests W1. Similarly, the second write request includes a write address request AW2 transmitted via the write address channel and four write data requests W2 transmitted via the write data channel. Thus, a single write address request AW2 can complete the batch transmission of four write data requests W2.

[0104] like Figure 5As shown, the first write address request AW1 and the first write data request W1 of its corresponding write data request W1 enter the cross switch circuit in the same cycle, with the four write data requests W1 connected end to end. After the last write data request W1, the second write address request AW2 and the first write data request W2 of its corresponding write data request W2 also enter the cross switch circuit in the same cycle, with the four write data requests W2 connected end to end.

[0105] Figure 6 This is a timing diagram of a write request entering the crossbar switch circuit.

[0106] Currently, after receiving a write address request, the crossbar switch circuit still needs to determine the index information, and then read the index information into the FIFO. This process takes at least one clock cycle. Therefore, even if the write data request and the write address request enter the crossbar switch circuit simultaneously, the lack of index information causes the write data request to be reverse-biased. Continuous write data requests at input create bubbles, resulting in bandwidth loss. The timing at this time is as follows: Figure 6 As shown. Figure 6 As shown, on the write data channel, data requests that should flow continuously in the timing process have an idle window period of one clock cycle between write data request W1 and write data request W2, during which there are no valid tasks and no valid transmissions. This blank time is called the bubble, which will reduce the overall throughput and lengthen the total time.

[0107] For example, in at least one embodiment of this disclosure, each write address request corresponds to P write data requests, and the P write data requests are transmitted consecutively. For example, when P is greater than 1, it can be understood as burst transmission. Each first circuit also provides a register configured to delay the received write data request by one clock cycle. For two consecutive write address requests, the last write data request among the P write data requests corresponding to the first write address request is transmitted to the corresponding second first-in-first-out (FIFO) buffer module in the first clock cycle, and the second transmitted write address request is also transmitted to the corresponding first FIFO buffer module in the first clock cycle.

[0108] To address the issue of writing data request bubbles, this disclosure introduces a register slice into the writing data path after the write data request enters the crossbar switch circuit. This causes the first write data request to be delayed by one clock cycle relative to the write address request, providing time for the index information to be stored in the third FIFO cache module and then read out. Simultaneously, the next write address request is transmitted while the last of the multiple write data requests corresponding to the previous write address request is being transmitted, thus eliminating bubbles in the write data request.

[0109] Figure 7 A timing diagram of a write request provided for at least one embodiment of this disclosure.

[0110] like Figure 7 As shown, after entering the crossbar switch circuit, the first write data request W1 is delayed by one clock cycle relative to the write address request AW1. Write data requests W1 and W2 are transmitted continuously, while the second write address request AW2 and the last write data request W1 are transmitted in the same clock cycle. Therefore, this scheme can completely eliminate bubbles in the write data requests, fill bus transmission gaps, compress invalid idle cycles, improve the continuity of the write data stream, reduce transmission timing gaps, reduce waiting, pauses, and idle cycles within the channel, improve the actual throughput of the channel, and enhance bandwidth utilization.

[0111] Figure 8 A schematic structural diagram of a first circuit provided for another embodiment of this disclosure.

[0112] For example, the cross switch circuit also has N shared buffers, each coupled to one of the N first circuits. Figure 8 As shown, the register is coupled between the shared buffer 1 coupled to the first circuit 101_1 and the write data channel of the source module a1 coupled to the first circuit 101_1.

[0113] The received write data request is written to the shared buffer of the first circuit after a one-clock-cycle delay via the register.

[0114] For example, in an embodiment where registers are set in the first circuit to eliminate bubbles, when a first multiplexer grants the same source module twice in a row, since the second arbitration is performed at the same time as the last write data request in the previous write request, the second cache module still contains the write data request of the previous write request. Therefore, a non-empty signal as a sign of synchronization completion may not be accurate enough. It is necessary to ensure that there is more than one storage slot in the second first-in-first-out cache module containing data at this time.

[0115] For example, the second first-in-first-out cache module includes multiple storage slots, each of which stores a write data request. In response to the arbitration of a received write address request, the prerequisite for the next write address request adjacent to the received write address request to participate in the arbitration includes: in the second first-in-first-out cache module corresponding to the corresponding destination module, more than one storage slot contains data.

[0116] For example, when the second write address request arrives at the first FIFO cache module, its corresponding write data request may not have yet arrived at the second FIFO cache module, but the first write address request has already been arbitrated, and its data has not yet been completely transmitted. To avoid bubbles, the second write address request needs to participate in the arbitration when the last write address request of the first write request is being transmitted. At this time, the last write address request of the first write request is still stored in the second FIFO cache module, so the second FIFO cache module is not empty. However, the second write data request may not have entered the second FIFO cache module yet. If the second write address request directly participates in the arbitration, a deadlock may still occur.

[0117] Therefore, in this disclosure, for the next write address request that has already been arbitrated, the prerequisite for it to participate in the arbitration includes that more than one storage slot in the second first-in-first-out cache module where the write address request is located contains data. When more than one storage slot contains data, it means that the write data request of the write address request has arrived at the second first-in-first-out cache module and can participate in the arbitration.

[0118] Figure 9 A schematic structural diagram of a second circuit provided for at least one embodiment of this disclosure.

[0119] like Figure 9 As shown, the second circuit also includes an arbitration unit. The arbitration unit is configured to receive arbitration requests from each of the first circuits and generate an arbitration result according to the arbitration mechanism. The arbitration result may include, for example, the index number of the selected path, through which the first multiplexer 105_1 and the second multiplexer 106_1 can select the corresponding path.

[0120] When the last write data request of P write data requests is transmitted to the corresponding second circuit, the arbitration unit in the corresponding second circuit receives a second signal. This second signal is used to indicate that the currently transmitted write data request is the last write data request among write data requests corresponding to the same write address request.

[0121] For example, the arbitration unit can be configured to receive the w_last signal. The w_last signal is transmitted at the same time as the write address request. The w_last signal is 1 when the last write data request of P write data requests corresponding to the same write address request is transmitted to the corresponding second circuit, and 0 in other cases. For example, the w_last signal can be equal to 1 as the second signal.

[0122] In addition, the second first-in-first-out cache module also sends the first number of storage slots currently storing data in the second first-in-first-out cache module to the arbitration unit in the coupled second circuit.

[0123] It should be noted that, in Figure 9 The diagram illustrates a first quantity and a second signal. In reality, multiple coupled second FIFO cache modules each send their own first quantity to the arbitration unit, and different write data requests also correspond to their own second signals. Figure 9 They will not be shown one by one in the text.

[0124] Each arbitration unit is further configured to, upon receiving any write address request for participation in arbitration: in response to not receiving a second signal, or in response to receiving a second signal and the first number of received signals being greater than 1, to accept any write address request as an arbitration candidate for participation in arbitration; and in response to receiving a second signal and the first number of received signals being equal to 1, to determine that any write address request cannot be an arbitration candidate.

[0125] Here, the second signal and the first quantity received by the arbitration unit correspond to the same source module as any write address request. For example, assuming that any write address request received by the arbitration unit in the second circuit 102_1 comes from FIFO_11, the second signal and the first quantity used to determine whether any write address request is the source module a1 corresponding to the arbitration candidate are as follows: for example, the second signal indicates that the write data request currently transmitted from FIFO_21 to the second multiplexer 106_1 is the last write data request in a set of write data requests transmitted by FIFO_21, and the write address request corresponding to this set of write data requests is the previous write address request of any write address request. The first quantity indicates the number of storage slots in FIFO_21 that currently store data.

[0126] In other words, for example, the first FIFO cache module, after receiving a non-empty signal from the second FIFO cache module, will still directly send a request to participate in arbitration to the arbitration unit. Simultaneously, the second FIFO cache module, which corresponds to the same destination module as the first FIFO cache module, will also send a second signal corresponding to the P write data requests transmitted in the previous group, as well as the first number of storage slots currently storing data in the second FIFO cache module.

[0127] For example, taking the arbitration unit in the second circuit 102_1 receiving an arbitration request from the source module a1 as an example, the arbitration unit will determine whether the first quantity of the second first-in-first-out (FIFO) cache module FIFO_21 is greater than 1 if the second signal received from the source module a1 is, for example, the signal w_last corresponding to the previous group of P write requests sent by the source module a1 is 1. If the first quantity is greater than 1, it means that the write data request corresponding to the write address request participating in the arbitration has entered the corresponding second first-in-first-out (FIFO) cache module FIFO_21, and the write address request can be used as an arbitration candidate for arbitration. If the first quantity is equal to 1, it means that the write data request corresponding to the write address request participating in the arbitration has not yet entered the second first-in-first-out (FIFO) cache module FIFO_21, and the write address request cannot be used as an arbitration candidate for arbitration.

[0128] If no second signal is received from the first circuit at present, for example, if the w_last signal from the first circuit is 0 at this time, the write address request can be directly used as an arbitration candidate for arbitration.

[0129] Afterwards, refer to Figure 4 The relevant description states that, based on the arbitration result, the appropriate path is selected to output the selected write address request and write data request.

[0130] For example, in other embodiments, other feasible methods may be used to determine the "preconditions for the next write address request adjacent to the received write address request to participate in arbitration", which will not be elaborated here.

[0131] For example, to ensure that multiple source modules have a fair chance to transmit data, arbitration can be conducted using a round-robin method. The arbitration result of the write address channel will be written into the fourth first-in-first-out buffer module and output to the write data channel.

[0132] For example, in some embodiments, N first circuits are first coupled one-to-one with N ports of the on-chip network bus, and then coupled to N processing cores through the on-chip network bus. The on-chip network bus is used to transmit data from the processing cores to the corresponding destination modules via a crossbar switch circuit. That is, in this embodiment, the first circuits are coupled to the ports of the on-chip network bus, the data lines are buffered in the buffer area corresponding to the processing core, and then transmitted to the crossbar switch circuit via the on-chip network.

[0133] For example, in some embodiments, the first-in-first-out cache module stores the data in the write data request, so a write data request can be read out one at a time (POP operation) through a read operation.

[0134] For example, in some other embodiments, when the cross switch circuit is provided with N shared buffers corresponding one-to-one with N multiplexers, when a write data request needs to be sent to the second circuit, performing a read operation includes performing the following operations: when an indication signal (e.g., a ready signal) sent by the second circuit is received, the first P read addresses are read from the second first-in-first-out buffer module (POP operation); according to the read addresses, P write data requests are read from the shared buffer coupled to the second first-in-first-out buffer module, and these write data requests are sent to the second circuit.

[0135] Figure 10 This is a schematic diagram of a cross switch circuit provided in an embodiment of the present disclosure.

[0136] The following is combined with Figure 10 This fully describes the overall structure and function of the cross switch circuit provided in at least one embodiment of the present disclosure. Figure 10 In the example provided, for convenience, N=3 is used as an example for illustration, but this disclosure is not limited to this.

[0137] For example, the destination module can act as a slave device, such as a storage unit. The source module can be called a master device, such as a processing core / on-chip network port. The crossbar switch circuit is an AXI bus-based crossbar switch circuit that meets the needs of data interaction or transmission between multiple master and slave devices.

[0138] like Figure 10 As shown, the three source modules are source module a1, source module a2, and source module a3, and the source modules are, for example, the processing core. The three destination modules are destination module b1, destination module b2, and destination module b3, and the destination modules are, for example, memory blocks in memory (memory banks).

[0139] The crossbar switch circuit 100 is configured to transmit write address requests received from the write address channel and write data requests from the write data channel of the source module to the destination module for processing. For example, the crossbar switch circuit 100 uses routing scheduling to allocate the output data of multiple processing cores to the target transmission path as needed to send them to the corresponding storage units.

[0140] like Figure 10 As shown, the crossbar switch circuit 100 includes three first circuits: first circuit 101_1, first circuit 101_2, and first circuit 101_3. Each first circuit includes a first multiplexer and a second multiplexer. The input terminals of the three first multiplexers are coupled one-to-one with the write address channels of the three source modules, and the input terminals of the three second multiplexers are coupled one-to-one with the write data channels of the three source modules.

[0141] For example, taking the first circuit 101_1 as an example, it includes a first multiplexer 103_1 and a second multiplexer 104_1.

[0142] like Figure 10 As shown, the cross switch circuit 100 also includes three second circuits: second circuit 102_1, second circuit 102_2, and second circuit 102_3. Each second circuit includes a first multiplexer and a second multiplexer. The outputs of the three first multiplexers are coupled one-to-one with the write address channels of the three destination modules, and the outputs of the three second multiplexers are coupled one-to-one with the write data channels of the three destination modules.

[0143] For example, taking the second circuit 102_1 as an example, it includes a first multiplexer 105_1 and a second multiplexer 106_1.

[0144] Each of the three outputs of the first multiplexer is coupled to one input of each of the three first multiplexers, for example, as shown in the diagram. Figure 10 The black solid line in the diagram represents the three outputs of each secondary multiplexer, which are each coupled to one input of one of the three secondary multiplexers. For example, it is illustrated as follows: Figure 10 The black dashed line in the middle.

[0145] The source module and the destination module use buses with independent write address channels and write data channels, such as the AXI bus. The AXI bus is an on-chip bus designed for high performance, high bandwidth and low latency. The cross switch circuit 100 is a cross switch circuit based on the AXI bus.

[0146] about Figure 10 For details regarding the internal structure of the first and second circuits, please refer to the relevant descriptions in the foregoing embodiments; they will not be repeated here.

[0147] It should be noted that, for the sake of simplifying the accompanying drawings, in Figure 10 The signal line for transmitting the first signal between the first FIFO buffer module and the corresponding second FIFO buffer module is not shown, nor are the arbitration request, first quantity, second signal, etc. received by the arbitration unit shown. For details, please refer to the description of the foregoing embodiments.

[0148] like Figure 10 As shown, the cross switch circuit also includes three shared buffers corresponding one-to-one with the three first circuits. The shared buffers are coupled to the source module through the first circuits. For example, the shared buffers can be shared buffers in a graphics processor or a general-purpose graphics processor. They are not limited to a first-in-first-out (FIFO) mode, and write data requests can be stored in the shared buffers in any order.

[0149] The following is combined with Figure 7 The timing example illustrates the operation of the cross switch circuit.

[0150] Assumption Figure 7 When the first write address request AW1 is transmitted into the cross switch circuit, all first-in-first-out buffer modules are empty.

[0151] For example, assuming the write address channel of source module a1 receives the first write address request AW1, the first circuit 101_1 performs a hash operation on the write address request AW1 to obtain the destination module as index information. Based on this index information, the write address request is input to the corresponding first first-in-first-out (FIFO) cache module. For example, assuming the destination module of the write address request AW1 is destination module b1, it is stored in the first FIFO cache module FIFO_11. Simultaneously, the index information is stored in the third FIFO cache module FIFO3.

[0152] When write data request W1 enters the first circuit 101_1, it is first delayed by one clock cycle in the register, and then stored in a free location in the shared buffer. The shared buffer returns the storage address of write data request W1 in the shared buffer, and uses the stored location pointer as data information. According to the index information, the data information is stored in the corresponding second first-in-first-out buffer module FIFO_21. Therefore, especially when dealing with write data requests with large bit widths, this approach can ensure the data transmission order while flexibly allocating buffer resources and saving buffer space.

[0153] After the data is stored in FIFO_21, FIFO_21 is not empty and sends a first signal to FIFO_11. After receiving the first signal, FIFO_11 sends a request to participate in arbitration to the arbitration unit of the second circuit. For example, at this time, the valid signal sent by FIFO_11 to the arbitration unit is pulled high.

[0154] After receiving a valid signal from FIFO_11, the arbitration unit first determines whether the source module that sent the arbitration request can be an arbitration candidate. At this time, the w_last signal received by the arbitration unit is low, meaning that the second signal has not been received. Therefore, source module a1 can be considered an arbitration candidate and arbitrated together with other arbitration candidates. Afterwards, arbitration can be performed according to various preset arbitration mechanisms to obtain the arbitration result.

[0155] Assuming that source module a1 is selected through arbitration, the second circuit 102_1 sends an indication signal (ready signal) to FIFO_11. After receiving the indication signal, FIFO_11 reads the write address request AW1 from FIFO_11 and transmits it to the first multiplexer 105_1. At the same time, the arbitration unit outputs the arbitration result to the first multiplexer 105_1. The first multiplexer 105_1 selects the first path and outputs the write address request AW1.

[0156] The arbitration unit also caches the arbitration result in the fourth FIFO buffer module 4. The second multiplexer 106_1 reads the arbitration result from the fourth FIFO buffer module 4 and sends an indication signal to FIFO_21. After receiving the indication signal, FIFO_21 reads the data information of the four write data requests W1 corresponding to write address request AW1 from FIFO_21 in sequence, reads the write data requests of the corresponding storage locations from the shared buffer, and transmits them to the second multiplexer 106_1. The first multiplexer 106_1 selects the first path according to the read arbitration result and outputs the write data request W1.

[0157] refer to Figure 7 Simultaneously with the transmission of the last write address request AW1, write address request AW2 is input into the write address channel. Similarly, the first circuit 101_1 performs a hash operation on write address request AW2 to obtain the destination module as index information. Based on this index information, the write address request is input into the corresponding first first-in-first-out (FIFO) buffer module. For example, assuming the destination module of write address request AW1 is destination module b1, it is stored in the first FIFO buffer module FIFO_11. At the same time, the index information is stored in the third FIFO buffer module FIFO3.

[0158] At this time, regardless of whether write data request W2 has entered FIFO_21, there is still write data request W1 in FIFO_21. Therefore, FIFO_21 is not empty and sends the first signal to FIFO_11. After receiving the first signal, FIFO_11 sends a request to participate in arbitration to the arbitration unit of the second circuit. For example, at this time, the valid signal sent to the arbitration unit is pulled high.

[0159] After receiving a valid signal, the arbitration unit first determines whether the arbitration request can be used as an arbitration candidate. At this time, the last write data request W1 is being transmitted, so w_last is high. That is, the arbitration unit receives the second signal. The arbitration unit determines whether the first quantity sent by FIFO_21 is greater than 1. If it is greater than 1, the source module a1 can be used as an arbitration candidate for arbitration. If it is equal to 1, the source module a1 cannot be used as an arbitration candidate for arbitration.

[0160] For example, assuming the first quantity is greater than 1, source module a1 can participate in arbitration as an arbitration candidate. Assuming source module a1 continues to be selected for arbitration, the second circuit 102_1 sends an indication signal (ready signal) to FIFO_11; after receiving the indication signal, FIFO_11 reads the write address request AW2 from FIFO_11 and transmits it to the first multiplexer 105_1. At the same time, the arbitration unit outputs the arbitration result to the first multiplexer 105_1, and the first multiplexer 105_1 selects the first path and outputs the write address request AW2.

[0161] The arbitration unit also caches the arbitration result in the fourth FIFO buffer module 4. The second multiplexer 106_1 reads the arbitration result from the fourth FIFO buffer module 4 and sends an indication signal to FIFO_21. After receiving the indication signal, FIFO_21 reads the data information of the four write data requests W2 corresponding to write address request AW2 from FIFO_21 in sequence, reads the write data request W2 of the corresponding storage location from the shared buffer, and transmits it to the second multiplexer 106_1. The first multiplexer 106_1 selects the first path according to the read arbitration result and outputs the write data request W2.

[0162] For example, assuming the first quantity is 1 at this point, meaning write data request W2 has not yet entered FIFO_21, then write address request AW1 will not participate in arbitration during the current clock cycle. In the next clock cycle or a subsequent clock cycle, when write data request W2 enters FIFO_21, write address request AW1 can participate in arbitration. At this time, w_last equals 0, and FIFO_21 is not empty. The specific process is similar to that of write data request W1 described above, and will not be repeated here.

[0163] In the above embodiments, to prevent deadlock, the write address request can only participate in arbitration after the data information of the write data request corresponding to the received write address request has entered the second first-in-first-out cache module of the corresponding destination module. This prevents the write address request from occupying the resources of the write data channel after arbitration while waiting for the write data channel resources are occupied by other requests, thus eliminating the loop waiting conditions that lead to deadlock and fundamentally preventing deadlock from occurring, effectively improving data transmission performance; it also eliminates the need to expand the input buffer, reducing resource overhead and area occupation.

[0164] Furthermore, in the above embodiments, after the write data request of the write data channel enters the crossbar switch circuit, a register slice is added to the write data path, causing the write data request to be delayed by one clock cycle relative to the write address request, providing time for the index information to be stored in the third first-in-first-out cache module and then read out. Simultaneously, the next write address request is input while the last write data request of the multiple write data requests corresponding to the previous write address request is being transmitted, eliminating bubbles in the write data request, filling bus transmission gaps, compressing invalid idle cycles, improving the continuity of the write data stream, reducing transmission timing gaps, reducing waiting, pauses, and idle cycles within the channel, improving the actual throughput of the channel, and increasing bandwidth utilization.

[0165] Furthermore, in this embodiment, data is stored in a shared cache area, and only the storage address of the write data request in the shared cache area is stored as data information in the second first-in-first-out cache module. The storage capacity of the second first-in-first-out cache module can be set to be relatively small, especially for large bit-width write data. This method can ensure the data transmission order while flexibly allocating buffer resources, saving buffer space, and effectively saving chip area.

[0166] This disclosure also provides a chip in at least one embodiment. Figure 11 This is a schematic structural diagram of a chip provided for at least one embodiment of the present disclosure.

[0167] like Figure 11 As shown, the chip 200 is provided with a cross switch circuit 100 as described in at least one embodiment of this disclosure. Further details regarding the cross switch circuit 100 can be found in the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0168] For example, chips can include system-on-chip (SoC) forms. SoC can integrate modules such as crossbar switch circuits, processor cores, memory, and peripheral interfaces (such as UART, SPI, and GPIO interfaces) into a single chip, forming a highly integrated hardware architecture.

[0169] For example, the chip may include a central processing unit, a graphics processing unit, a tensor processor, or other large-scale integrated circuits with data processing and / or instruction execution capabilities. Alternatively, the chip may include digital circuits or digital circuit units that implement specific functions, such as field-programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs).

[0170] In addition, the chip may also include auxiliary circuit modules to ensure the stable operation of the cross switch circuit. These may include a power management module to provide a stable operating voltage for the cross switch circuit; a clock module to provide a precise clock signal for the cross switch circuit; and a reset module that generates a reset signal. Upon receiving the reset signal, the cross switch circuit can first clear its internal cache and configuration parameters, and then work with the processor to complete the device reset and restart.

[0171] This disclosure does not limit the function, form or use of the chip, and the electronic device may include the cross switch circuit described in any embodiment of this disclosure.

[0172] For example, the chip provided in at least one embodiment of this disclosure may specifically be a Graphic Processing Unit (GPU), a General-Purpose Graphic Processing Unit (GPGPU), a Tensor Processing Unit (TPU), a Data Processing Unit (DPU), a Neural Processing Unit (NPU), etc., and this disclosure does not impose any specific limitations on it.

[0173] The following is based on Figure 12 For example, this illustrates the structure when the chip is a graphics processor or a general-purpose graphics processor.

[0174] Figure 12 This is a schematic diagram of a general-purpose graphics processing unit (GPGPU).

[0175] like Figure 12 As shown, a general-purpose graphics processor is actually an array of programmable multiprocessors. For example, a programmable multiprocessor can be a streaming processor cluster (SPC), such as including... Figure 12 The diagram shows multiple streaming processor clusters. In a general-purpose graphics processor, one streaming processor cluster handles one computational task, or multiple streaming processor clusters handle one computational task. Multiple streaming processor clusters share data through a global cache or global memory.

[0176] like Figure 12 As shown, a streaming processor cluster includes multiple computing units (CUs). Each computing unit (CU) is used to perform arithmetic and logical operations, such as accumulation, reduction, and regular addition, subtraction, multiplication, and division.

[0177] A computing unit comprises multiple cores (also called computing kernels or computing cores). Each computing core includes an arithmetic logic unit (ALU), a floating-point unit, etc., and is used to execute specific computational tasks. In addition, the computing unit also includes registers (e.g., ... Figure 12 The register file and shared memory in a computing unit are used to store source and destination data related to computing tasks in a hierarchical manner. The shared memory in a computing unit is used to share data between the cores of that computing unit.

[0178] like Figure 12 As shown, each computing unit also provides a tensor core for performing tensor-related computations, such as tensor shrinking operations. Tensor cores can accelerate tensor operations such as matrix multiplication. Tensor cores in multiple computing units can be scheduled and controlled uniformly.

[0179] In parallel computing, computational tasks are typically executed by multiple threads. These threads are divided into multiple thread blocks before execution in the graphics processing unit (or parallel computing processor), and then dispatched via a thread block distribution module. Figure 12 (Not shown in the image) Multiple thread blocks are distributed to various computation units. All threads in a thread block must be assigned to the same computation unit for execution. Simultaneously, thread blocks are broken down into minimum execution thread bundles (or simply warps), each containing a fixed number (or less than this fixed number) of threads, for example, 32 threads. Multiple thread blocks can execute in the same computation unit or in different computation units.

[0180] In each computing unit, the thread beam scheduling / distribution module ( Figure 12 (Not shown in the diagram) Thread bundles are scheduled and allocated so that multiple computing cores within the computing unit can run thread bundles. Depending on the number of computing cores in the computing unit, multiple thread bundles within a thread block can execute concurrently or in a time-sharing manner. Multiple threads within each thread bundle execute the same instructions. Memory-executed instructions are issued to shared memory within the computing unit or further issued to intermediate-level caches, global caches, or global memory (e.g., [example cache]). Figure 12 High Bandwidth Memory (HBM) is used for read and write operations.

[0181] For example, the source module of a cross switch circuit can be a computing core, tensor core, or other component in a general-purpose graphics processor that processes or calculates data, while the destination module can be the memory or L2 cache in a general-purpose graphics processor.

[0182] For example, if the cross switch circuit also has N shared buffers corresponding one-to-one with N multiplexers, the shared buffers can be used Figure 12 Shared memory implementation in [the context of the project].

[0183] At least one embodiment of this disclosure also provides an electronic device. Figure 13 A schematic structural diagram of an electronic device provided for at least one embodiment of this disclosure.

[0184] like Figure 13 As shown, the electronic device 300 includes a chip 200. Further description of the chip 200 can be found in the relevant descriptions of the foregoing embodiments, and will not be repeated here.

[0185] For example, the electronic device could be a multi-GPU system, which integrates multiple GPU cards and works together to complete large-scale parallel computing tasks. This architecture is commonly used for tasks such as artificial intelligence training, scientific computing, and high-performance graphics rendering.

[0186] For example, in some embodiments, the electronic device 300 provided in at least one embodiment of this disclosure can be a single-machine multi-card form, where multiple GPU cards are integrated in a single server or workstation, and inter-card communication is achieved through a bus (such as PCIe bus, AMD bus, etc.). For example, the electronic device 500 can also be a multi-machine multi-card form, where multiple single-machine multi-card servers are interconnected through a high-speed network to form a cluster, and each card can not only communicate with other cards in its own machine, but also interact with cards in other groups through the network.

[0187] For example, electronic device 300 can also be a TPU cluster, a multi-FPGA accelerator card system, etc., and this disclosure does not impose specific limitations on it.

[0188] For example, this electronic device 300 overcomes the limitations of single-card computing power or memory through parallel computing, and is therefore widely used in scenarios requiring large-scale data processing, high-throughput computing, or low-latency parallel tasks. Examples include deep learning and large model training, high-performance computing, large-scale data processing and AI inference, real-time rendering and visualization, and it can be applied to fields such as large model training, scientific computing, high-concurrency AI services, and real-time rendering.

[0189] Figure 14 This is a schematic diagram of the specific structure of an electronic device provided in at least one embodiment of the present disclosure.

[0190] The following is for reference. Figure 14 It shows a specific structural schematic diagram of an electronic device (e.g., a terminal device or a server) 400 suitable for implementing a data loading device including embodiments of the present disclosure.

[0191] The electronic devices in this disclosure can include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. For example, the electronic device can be in the form of a server, used for various application scenarios such as deep learning and artificial intelligence, scientific computing, graphics rendering and video editing, virtual reality and game development, and cloud services. For example, the electronic device can be a dedicated server such as a data center or cloud computing center that is deployed for tasks such as deep learning training, large-scale data analysis, and high-performance computing.

[0192] Figure 14 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0193] like Figure 14 As shown, the electronic device 400 may include a processing unit 401, which may include, for example, the aforementioned chip 200. This processing unit can execute various appropriate actions and processes based on non-transitory computer-readable instructions stored in memory to achieve various functions. The processing unit 401 may also include devices with instruction optimization capabilities and / or program execution capabilities, such as a central processing unit (CPU) or a tensor processor (TPU). The CPU may be based on x86, ARM, or RISC-V architectures. The GPU may be directly integrated into the SOC, directly integrated onto the motherboard, or built into the northbridge chip of the motherboard.

[0194] like Figure 14 As shown, for example, the memory may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) 403 and / or cache memory, etc., for example, computer-readable instructions may be loaded from storage device 408 into RAM 403 to execute computer-readable instructions. Non-volatile memory may include, for example, read-only memory (ROM) 402, hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. Various applications and various data, such as style images, and various data used and / or generated by the applications, may also be stored in the computer-readable storage medium.

[0195] For example, the processing device 401, the read-only memory (ROM) 402, and the random access memory (RAM) 403 are interconnected via bus 404. The input / output (I / O) interface 405 is also connected to bus 404.

[0196] Typically, the following devices can be connected to the input / output (I / O) interface 405: input devices 406 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 407 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 408 including, for example, magnetic tape, hard disk, flash memory, etc.; and communication devices 409. Communication device 409 allows electronic device 400 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although Figure 14 An electronic device 400 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 400 may alternatively implement or have more or fewer devices. For example, the processing device 401 may control other components in the electronic device 400 to perform desired functions.

[0197] The following points should be noted regarding this disclosure: The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0198] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0199] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0200] The following points should be noted regarding this disclosure: (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0201] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0202] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A cross switch circuit, characterized in that, The system is configured to transmit the received write address request from the write address channel and write data request from the write data channel from the source module to the destination module for processing. The cross-switch circuit includes N first circuits coupled one-to-one with N source modules, and N second circuits coupled one-to-one with N destination modules, where N is a positive integer greater than 1. Each first circuit includes a first multiplexer and a second multiplexer, the first multiplexer being electrically connected to a write address channel of a source module coupled to the first circuit, and the second multiplexer being electrically connected to a write data channel of the source module coupled to the first circuit. Each second circuit includes a first multiplexer and a second multiplexer. The first multiplexer is electrically connected to a write address channel of a destination module coupled to the second circuit, and the second multiplexer is electrically connected to a write data channel of the destination module coupled to the second circuit. The outputs of N first multiplexers and the inputs of N first multiplexers are interconnected one-to-one to form a first crossbar data transmission path for the write address request. The outputs of N second multiplexers and the inputs of N second multiplexers are interconnected one-to-one to form a second cross-connect data transmission path for the write data request. Each second multiplexer is equipped with N second first-in-first-out (FIFO) buffer modules, each corresponding to one of the N destination modules. Each second FIFO buffer module is configured to buffer the write data request data information transmitted by the write data channel coupled to the second multiplexer in the order of reception. In the cross switch circuit, the received write address request participates in the arbitration of the first multiplexer coupled to the corresponding destination module as an arbitration candidate, and obtains arbitration in response to the received write address request. The write data request corresponding to the received write address request is sent to the second multiplexer coupled to the corresponding destination module. After the data information of the write data request corresponding to the received write address request enters the second first-in-first-out buffer module corresponding to the corresponding destination module, the received write address request then participates in the arbitration as an arbitration candidate.

2. The cross switch circuit according to claim 1, characterized in that, Each first multiplexer is coupled to N first first-in-first-out (FIFO) buffer modules, each corresponding to one of the N destination modules. Each first FIFO buffer module is configured to buffer write address requests destined for the destination module corresponding to the first FIFO buffer module in the order of receipt. Each second-first-out cache module is configured as follows: In response to the second first-in-first-out (FIFO) buffer module being non-empty, a first signal is sent to the corresponding first FIFO buffer module, wherein the corresponding first FIFO buffer module and the second FIFO buffer module correspond to the same destination module; Each first-in-first-out cache module is configured as follows: In response to receiving the first signal, a request to participate in arbitration is sent to the second circuit coupled to the destination module corresponding to the first first-in-first-out buffer module.

3. The cross switch circuit according to claim 1, characterized in that, The cross switch circuit is also provided with N shared buffer areas that are coupled one-to-one with the N first circuits; Each shared buffer is configured to receive and cache write data requests transmitted via the write data channel of the coupled source module, and return the storage address of the cached write data request in the shared buffer as the data information of the cached write data request, wherein the shared buffer supports non-contiguous storage among multiple write data requests.

4. The cross switch circuit according to claim 1, characterized in that, Each write address request corresponds to P write data requests, which are transmitted consecutively, where P is a positive integer greater than or equal to 1. Each first circuit also provides a register configured to delay received write data requests by one clock cycle. For two consecutive write address requests, the last write data request among the P write data requests corresponding to the first write address request is transmitted to the corresponding second first-in-first-out cache module in the first clock cycle, and the second transmitted write address request is also transmitted to the corresponding first first-in-first-out cache module in the first clock cycle.

5. The cross switch circuit according to claim 4, characterized in that, The cross switch circuit is also provided with N shared buffer areas that are coupled one-to-one with the N first circuits; The register is coupled between the shared buffer coupled to the first circuit and the write data channel coupled to the first circuit. The received write data request is written to the shared buffer area coupled to the first circuit after a one-clock-cycle delay through the register.

6. The cross switch circuit according to claim 4, characterized in that, The second first-in-first-out cache module includes multiple storage slots, each used to store a write data request. In response to the arbitration of the received write address request, the prerequisite for the next write address request adjacent to the received write address request to participate in the arbitration includes: in the second first-in-first-out cache module corresponding to the corresponding destination module, more than one storage slot contains data.

7. The cross switch circuit according to claim 4, characterized in that, The second circuit includes an arbitration unit configured to receive arbitration requests from each of the first circuits and generate an arbitration result. When the last write data request of the P write data requests is transmitted to the corresponding second circuit, the arbitration unit in the corresponding second circuit receives a second signal, wherein the second signal is used to indicate that the currently transmitted write data request is the last write data request of the P write data requests. Each second FIFO cache module is further configured to send a first number of storage slots currently storing data in the second FIFO cache module to an arbitration unit in a coupled second circuit. Each arbitration unit is also configured as follows: Upon receiving a request to participate in arbitration for any write address request: In response to the failure to receive the second signal, or in response to the receipt of the second signal and the first number of receipts being greater than 1, any write address request is considered as an arbitration candidate to participate in arbitration; In response to receiving the second signal and the first number received being equal to 1, it is determined that any write address request cannot be used as an arbitration candidate; The second signal and the first quantity received by the arbitration unit correspond to the same source module as any write address request.

8. The cross switch circuit according to claim 1, characterized in that, Each first circuit is equipped with a third first-in-first-out buffer module. The first circuit is configured as follows: After each write address request enters the first circuit, index information indicating the destination module of the write address request is obtained based on the write address request. The write address request is then stored in the first first-in-first-out cache module corresponding to the destination module, and the index information is stored in the third first-in-first-out cache module.

9. The cross switch circuit according to claim 8, characterized in that, The cross switch circuit is also provided with N shared buffers that are coupled one-to-one with the N second multiplexers; The first circuit is further configured to, after the write data request corresponding to the received write address request enters the first circuit, extract the index information from the third first-in-first-out cache module, and store the data information of the write data request corresponding to the received write address request into the second first-in-first-out cache module indicated by the index information according to the index information.

10. The cross switch circuit according to claim 1, characterized in that, Each second circuit is also equipped with a fourth first-in-first-out buffer module and an arbitration unit. The arbitration unit is configured to receive arbitration participation requests sent by each of the first circuits and generate arbitration results; The first multiplexer in the second circuit is configured to select and output a corresponding write address request based on the arbitration result, so as to transmit it to the destination module coupled to the second circuit; The fourth first-in-first-out cache module is configured to cache the arbitration result. The second multiplexer in the second circuit is further configured to read the arbitration result from the fourth first-in-first-out buffer module, select and output a corresponding write data request based on the arbitration result, and transmit it to the destination module coupled to the second circuit.

11. A chip, characterized in that, Includes the cross switch circuit as described in any one of claims 1-10.

12. An electronic device, characterized in that, Including the chip as described in claim 11.

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