Routing decoding detection apparatus and method, storage medium and electronic device

Abstract

A routing decoding detection device and method, a storage medium and an electronic device are disclosed, and relate to the technical field of security. The routing decoding detection device comprises a first hardware circuit, a routing decoding circuit and a decoding detection circuit. In the embodiment of the present disclosure, after the first hardware circuit sends a first bus command and the routing decoding circuit decodes the first bus command to obtain a second bus command, the decoding detection circuit determines a decoding detection result based on a first bus address in the first bus command and / or a second bus address in the second bus command. In this way, whether the routing decoding of the bus command is correct in the transmission process can be detected based on the first access address sent by the first hardware circuit and / or the second access address obtained after decoding. Furthermore, compared with the traditional redundancy protection scheme, the scheme in the embodiment of the present disclosure can reduce the chip area overhead while ensuring that the protection of the routing decoding logic reaches the corresponding functional safety level.

Description

Technical Field

[0001] This disclosure relates to the field of security technology, and in particular to a routing decoding detection device and detection method, storage medium and electronic device. Background Technology

[0002] Routing and decoding logic is a crucial function in chip bus design. Its primary responsibility is to parse bus address signals and, based on the parsing results, locate the target device and select the transmission path. If the routing and decoding logic on the chip bus malfunctions, accurate data transmission cannot be guaranteed, potentially leading to the device executing incorrect instructions.

[0003] Currently, the main technology for protecting routing decoding logic is to replicate multiple identical routing decoding circuits. However, this approach consumes a significant amount of chip area. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a routing decoding detection device and method, a storage medium, and an electronic device to detect routing decoding results with minimal hardware overhead.

[0005] A first aspect of this disclosure provides a routing decoding and detection apparatus, comprising: a first hardware circuit configured to generate a first bus command for sending to a second hardware circuit; wherein the first bus command includes a first access address; a routing decoding circuit configured to acquire a target bus command, decode the target bus command to obtain a second bus command; wherein the target bus command is determined based on the first bus command; and a decoding and detection circuit configured to acquire the second bus command, parse the second bus command to obtain a second access address corresponding to the second bus command; and determine a decoding and detection result based on the first access address and / or the second access address.

[0006] A second aspect of this disclosure provides a routing decoding detection method, comprising: generating a first bus command for sending to a second hardware circuit; wherein the first bus command includes a first access address; obtaining a target bus command, decoding the target bus command to obtain a second bus command; wherein the target bus command is determined based on the first bus command; obtaining the second bus command, parsing the second bus command to obtain a second access address corresponding to the second bus command; and determining a decoding detection result based on the first access address and / or the second access address.

[0007] A third aspect of this disclosure provides a computer-readable storage medium storing a computer program that, when executed by a processor, is used to implement the routing decoding detection method provided in the second aspect above.

[0008] A fourth aspect of this disclosure provides an electronic device comprising: a processor; a memory for storing executable instructions of the processor; the processor being configured to read executable instructions from the memory and execute the instructions to implement the routing decoding detection method provided in the second aspect above.

[0009] A fifth aspect of this disclosure provides a computer program product that, when instructions in the computer program product are executed by a processor, performs the routing decoding and detection method provided in the second aspect of this disclosure.

[0010] A sixth aspect of this disclosure provides a chip that includes the routing decoding and detection device provided in the first aspect above.

[0011] In the technical solution provided by this disclosure, after a first bus command is issued by a first hardware circuit and a routing decoding circuit decodes the target bus command determined based on the first bus command to obtain a second bus command, a decoding detection circuit parses the second bus command to obtain a second access address corresponding to the second bus command. Then, based on the first access address included in the first bus command and / or the decoded second access address, a decoding detection result is determined. Thus, based on the first access address issued by the first hardware circuit and / or the decoded second access address, it is possible to detect whether the routing decoding of the first access address in the first bus command is correct during transmission. Furthermore, compared to traditional redundancy protection schemes, the solution in this disclosure can ensure that the protection of the routing decoding logic reaches the corresponding functional safety level while reducing chip area overhead. Attached Figure Description

[0012] Figure 1A This is a schematic diagram of the structure of a routing decoding and detection device provided in an exemplary embodiment of this disclosure.

[0013] Figure 1B This is a schematic diagram of the structure of a routing decoding and detection device provided in another exemplary embodiment of this disclosure.

[0014] Figure 2 This is a schematic diagram of the structure of a routing decoding and detection device provided in another exemplary embodiment of this disclosure.

[0015] Figure 3 This is a schematic diagram of the structure of a routing decoding and detection device provided in yet another exemplary embodiment of this disclosure.

[0016] Figure 4 This is a schematic diagram of the structure of a security detection circuit for a data linked list provided in yet another exemplary embodiment of this disclosure.

[0017] Figure 5This is a schematic diagram of the structure of a routing decoding and detection device provided in yet another exemplary embodiment of this disclosure.

[0018] Figure 6 This is a flowchart illustrating a routing decoding and detection method provided in an exemplary embodiment of this disclosure.

[0019] Figure 7 This is a flowchart illustrating a route decoding and detection method provided in another exemplary embodiment of this disclosure.

[0020] Figure 8 This is a flowchart illustrating a routing decoding and detection method provided in yet another exemplary embodiment of this disclosure.

[0021] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of this disclosure.

[0022] Figure 10 This is a schematic diagram of the structure of a chip provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0023] Application Overview Routing decoding logic is very common in chip bus design. Its main function is to parse bus address signals, locate the target device, and select the transmission path. If the routing decoding logic on the chip bus fails, accurate data transmission cannot be guaranteed, which may lead to the device executing incorrect instructions. Therefore, it is crucial to adopt a cost-effective security detection scheme to protect the routing decoding logic on the bus.

[0024] The solution in related technologies is to redundantly protect the routing decoding logic, but this approach consumes a significant amount of chip area. Alternatively, some chips do not protect the routing decoding logic on the bus, resulting in a loss of coverage for this part of the logic.

[0025] To address the aforementioned problems, this disclosure provides a routing decoding and detection device and a routing decoding and detection method. After a first hardware circuit issues a first bus command, and a routing decoding circuit decodes the target bus command determined based on the first bus command to obtain a second bus command, a decoding and detection circuit parses the second bus command to obtain a second access address corresponding to the second bus command. Then, based on the first access address included in the first bus command and / or the decoded second access address, a decoding and detection result is determined. Thus, based on the first access address issued by the first hardware circuit and / or the decoded second access address, it is possible to detect whether the routing decoding of the first access address in the first bus command is correct during transmission. Furthermore, compared to traditional redundancy protection schemes, the solution in this disclosure can ensure that the protection of the routing decoding logic reaches the corresponding functional safety level while reducing chip area overhead.

[0026] The routing decoding detection transpose and routing decoding detection method can be applied to a chip, which can be an automotive chip or a chip used in drones or robots. This disclosure does not limit the type of chip or the specific application scenario.

[0027] Exemplary device Figure 1A This is a schematic diagram of the structure of a routing decoding and detection apparatus provided in an exemplary embodiment of this disclosure, as shown below. Figure 1A As shown, the routing decoding and detection device 100 includes at least a first hardware circuit 101, a routing decoding circuit 102, and a decoding and detection circuit 103.

[0028] A first hardware circuit 101 is configured to generate a first bus command for sending to a second hardware circuit; wherein the first bus command includes a first access address.

[0029] For example, the first hardware circuit 101 in this embodiment of the present disclosure may be a master device controller IP (Intellectual Property, chip core) that actively initiates and manages bus transactions within a system-on-a-chip, also referred to as a master IP, source node, or source device. The first hardware circuit 101 can issue commands that satisfy multiple bus protocols, including but not limited to read and write commands. Among them, the multiple bus protocols may be AXI (Advanced eXtensible Interface), APB (Advanced Peripheral Bus), AHB (Advanced High-performance Bus), or CHI (Coherent Hub Interface), etc.

[0030] For example, the first hardware circuit 101 may include a CPU (Central Processing Unit) core, a DMA (Direct Memory Access) controller, a GPU (Graphics Processing Unit), a peripheral host control IP, a bus bridge, and / or a high-speed interface controller, etc.

[0031] Correspondingly, the second hardware circuit in this embodiment of the present disclosure may be a functional module IP within the system-on-a-chip that passively responds to the master device control signal sent by the first hardware circuit 101. The second hardware circuit may also be referred to as a slave IP, a destination node, or a destination device. The second hardware circuit includes, but is not limited to, RAM (Random Access Memory), ROM (Read Only Memory), registers, memory controllers, interrupt controllers, and / or various types of peripherals. Among them, various types of peripherals include, for example, UART (Universal Asynchronous Receiver Transmitter), SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit), GPIO (General-Purpose Input Output), and / or timers.

[0032] It should be noted that the specific types of the first hardware circuit and the second hardware circuit are not limited in this embodiment; and the actual content of the first bus command generated by the first hardware circuit 101 for sending to the second hardware circuit is also not limited.

[0033] In some examples, the first bus command generated by the first hardware circuit 101 in this embodiment includes a first access address, which can uniquely identify the second hardware circuit, thereby enabling the control signals (read / write) and / or related data in the first bus command to be transmitted to the second hardware circuit corresponding to the first access address.

[0034] The routing decoding circuit 102 is configured to acquire a target bus command, decode the target bus command, and obtain a second bus command; wherein the target bus command is determined based on the first bus command.

[0035] For example, in this embodiment of the present disclosure, the routing decoding circuit 102 can first obtain the target bus command determined based on the first bus command, and then perform routing decoding on the target bus command to obtain the second bus command. That is, the routing decoding circuit 102 can listen to the first bus command issued by the first hardware circuit 101, or the target bus command determined based on the first bus command, and determine the access target through address decoding, complete the path selection and command distribution, and accurately send the first bus command or the target bus command to the corresponding slave IP (i.e., the second hardware circuit).

[0036] For example, the routing decoding circuit 102 can directly determine the first bus command as the target bus command. Alternatively, it can provide checksum generation protection for the first access address field in the first bus command, thus determining the first bus command carrying the checksum as the target bus command. The methods for providing checksum generation protection include, but are not limited to, parity check, cyclic redundancy check, and error correcting code protection. Furthermore, the routing decoding circuit 102 can perform routing decoding on the target bus command to obtain the second bus command.

[0037] In some examples, the chip contains different types of buses, such as a primary bus (i.e., a high-speed bus) and a secondary bus (i.e., a peripheral bus). The primary bus can be a high-speed system bus, primarily used to connect high-performance IPs such as the CPU, GPU, NPU (Neural Processing Unit), and DDR (Double Data Rate) controller; the secondary bus can be a low-speed peripheral bus, primarily used to connect low-speed peripheral IPs such as UART, I2C, GPIO, and timers. Therefore, the first bus command sent by the first hardware circuit 101 can be delivered to the second hardware circuit via a single-level or multi-level bus link. For example, when the CPU initiates a first bus command, this command can be transmitted to the DDR controller via the primary bus. Alternatively, when the CPU initiates a first bus command, this command can first pass through the primary bus, then through the secondary bus, and finally be transmitted to the UART peripheral.

[0038] Furthermore, the routing decoding circuit 102 in this embodiment may include routing decoding modules corresponding to each level of the bus in the bus path between the first hardware circuit 101 and the second hardware circuit. That is, the routing decoding circuit 102 may include multiple routing decoding modules, and these multiple routing decoding modules may be of the same or different types. For example, the first hardware circuit 101 on the secondary bus initiates a first bus command. The routing decoding module A of the secondary bus performs routing decoding on the first bus command, generates a first intermediate command, and forwards the first intermediate command to the primary bus according to the address information in the first intermediate command. After receiving the first intermediate command, the routing decoding module B corresponding to the primary bus decodes the first intermediate command again to generate a second intermediate command, and forwards the second intermediate command to the secondary bus according to the address information in the second intermediate command. After receiving the second intermediate command, the routing decoding module C of the secondary bus decodes the second intermediate command to output a second bus command, and sends the second bus command to the bus where the second hardware circuit is located, so that the second hardware circuit can parse and execute the control information in the second bus command. At this time, routing decoding module A, routing decoding module B and routing decoding module C together constitute the routing decoding circuit 102 in this embodiment of the present disclosure.

[0039] In other words, this disclosure does not limit the type or number of routing decoding modules included in the routing decoding circuit 102.

[0040] The decoding detection circuit 103 is configured to acquire a second bus command, parse the second bus command to obtain a second access address corresponding to the second bus command, and determine the decoding detection result based on the first access address and / or the second access address.

[0041] For example, in this embodiment of the present disclosure, a decoding detection circuit 103 may be provided between the routing decoding circuit 102 and the second hardware circuit. This decoding detection circuit 103 can parse the acquired second bus command to obtain the corresponding second access address. Then, based on the first access address included in the first bus and the decoded second access address, a decoding detection result is determined; and / or, based on the decoded second access address, the decoding detection result is determined. Thus, based on the first access address issued by the first hardware circuit and / or the decoded second access address, it is possible to detect whether the routing decoding of the first access address in the first bus command is correct during transmission. Furthermore, compared to traditional redundancy protection schemes, the scheme in this embodiment of the present disclosure can ensure that the protection of the routing decoding logic reaches the corresponding functional safety level while reducing chip area overhead.

[0042] In some examples, such as Figure 1AAs shown, the output of the first hardware circuit 101 is coupled to the input of the routing decoding circuit 102 via a bus. After the first hardware circuit 101 initiates a first bus command, it outputs the first bus command to the bus so that the routing decoding circuit 102 can obtain the target bus command determined based on the first bus command. The output of the routing decoding circuit 102 is coupled to the input of the decoding detection circuit 103. After the routing decoding circuit 102 performs routing decoding on the target bus command determined based on the first bus command to obtain a second bus command, it outputs the second bus command to the decoding detection circuit 103 so that the decoding detection circuit 103 can parse the second bus command to obtain the second access address corresponding to the second bus command, and determine the decoding detection result based on the first access address and / or the second access address.

[0043] In some embodiments, such as Figure 1B As shown, in Figure 1A Based on this, another exemplary embodiment of the present disclosure further provides a route decoding and detection device 100, which further includes a second hardware circuit 106, the second hardware circuit 106 being the destination IP corresponding to the first access address.

[0044] The second hardware circuit 106 is configured to receive and respond to a second bus command.

[0045] like Figure 1B As shown, the output of the routing decoding circuit 102 is also coupled to the input of the second hardware circuit 106. After the routing decoding circuit 102 performs routing decoding on the target bus command determined based on the first bus command to obtain the second bus command, if the routing decoding circuit 102 decodes correctly, the second bus command can be forwarded to the bus where the second hardware circuit 106 is located through the output of the routing decoding circuit 102, so that the second hardware circuit 106 can respond to the second bus command accordingly, such as executing the control information included in the second bus command.

[0046] Thus, since the output of the routing decoding circuit 102 can be coupled to the input of the decoding detection circuit 103, or directly coupled to the input of the second hardware circuit 106, this bypass detection structure does not increase the transmission delay of bus data. Figure 1B The routing decoding and detection device in the system can ensure that there is no loss of data transmission efficiency while implementing routing decoding logic protection.

[0047] Of course, those skilled in the art can also couple the output of the routing decoding circuit 102 to the input of the decoding detection circuit 103, and then couple the output of the decoding detection circuit 103 to the input of the second hardware circuit 106, so that if the decoding detection result of the decoding detection circuit 103 is successful, the second bus command is sent to the second hardware circuit 106. This disclosure does not limit this approach, and such a structure also falls within the protection scope of this disclosure. In this way, problems such as main IP freezing and business logic crashes caused by problems in the routing decoding logic of the routing decoding circuit 102 can be avoided.

[0048] In some embodiments of this disclosure, such as Figure 2 As shown, in Figure 1A Based on this, the decoding detection circuit 103 includes a first detection sub-circuit 1031.

[0049] The first detection sub-circuit 1031 is configured to determine the preset address range corresponding to the second hardware circuit in the memory mapping table, match the second access address with the preset address range to obtain a matching result, and determine the first detection result based on the matching result. The decoding detection results include the first detection result.

[0050] Optionally, the memory map, also known as the address map, in this embodiment is a hardware routing and address allocation rule within the chip where the routing decoding and detection device 100 is located. It defines the correspondence between the unified physical address space and on-chip / off-chip hardware resources. The memory map is an address allocation rule fixed in hardware circuitry (bus matrix + address decoding) during chip design. The memory map is determined by the bus matrix and address decoding hardware and is fixed at the factory.

[0051] Furthermore, the address range corresponding to the second hardware circuit, i.e. the address division of the entire memory mapping table of the chip on the second hardware circuit, can be pre-stored in the first detection sub-circuit 1031.

[0052] Furthermore, the first detection sub-circuit 1031 can match the decoded second access address with the pre-stored address range to obtain a matching result; and, based on the matching result, determine the first detection result.

[0053] For example, let's take a UART as the second hardware circuit, with the UART peripheral address range being 0x40004400 ~ 0x400047FF. If the second access address in the second bus command is 0x70001000, since 0x70001000 is not within the preset address range of 0x40004400 ~ 0x400047FF, the matching result is a failure, thus determining that the first detection result is a decoding logic error in the routing decoding circuit. If the second access address in the second bus command is 0x40004520, since 0x40004520 is within the preset address range of 0x40004400 ~ 0x400047FF, the matching result is a successful match, thus determining that the first detection result is a correct decoding logic in the routing decoding circuit.

[0054] In this way, the decoding detection result of the routing decoding circuit can be determined by using the decoded address information (i.e., the second access address), thereby realizing end-to-end routing decoding logic protection on the chip bus, thus ensuring that the protection of these logics reaches the corresponding functional safety level while reducing chip area overhead.

[0055] In some examples, such as Figure 2 As shown, the output of the first hardware circuit 101 is coupled to the input of the routing decoding circuit 102 via a bus. After the first hardware circuit 101 initiates a first bus command, it outputs the first bus command to the bus so that the routing decoding circuit 102 can obtain the target bus command determined based on the first bus command. The output of the routing decoding circuit 102 is coupled to the input of the first detection sub-circuit 1031. After the routing decoding circuit 102 performs routing decoding on the target bus command determined based on the first bus command to obtain a second bus command, it outputs the second bus command to the first detection sub-circuit 1031 so that the first detection sub-circuit 1031 can parse the second bus command to obtain the second access address corresponding to the second bus command and determine the preset address range corresponding to the second hardware circuit in the memory mapping table. Then, it matches the second access address with the preset address range to obtain a matching result, and determines the first detection result based on the matching result.

[0056] In some embodiments, the first detection sub-circuit 1031 is specifically configured as follows: In response to the matching result indicating that the preset address range includes the second access address, the first detection result is determined to indicate that the decoding logic of the routing decoding circuit is correct; or, In response to the matching result indicating that the preset address range does not include the second access address, the first detection result is determined to represent a decoding logic error in the routing decoding circuit.

[0057] For example, in this embodiment of the disclosure, if the matching result indicates that the preset address range includes the second access address, that is, the second access address is within the preset address range, then the first detection result indicates that the decoding logic of the routing decoding circuit 102 is correct. If the matching result indicates that the preset address range does not include the second access address, that is, the second access address is outside the preset address range, then the first detection result indicates that the decoding logic of the routing decoding circuit 102 is incorrect. In this way, the verification and detection of the routing decoding process can be completed from the perspective of decoding logic compliance.

[0058] In some embodiments of this disclosure, such as Figure 3 As shown, in Figure 1A Based on this, the routing decoding and detection device 100 also includes a check code generation circuit 104 and a command processing circuit 105.

[0059] The verification code generation circuit 104 is configured to obtain the first access address included in the first bus command from the first hardware circuit 101, and determine the first verification information corresponding to the first access address based on the first access address. The command processing circuit 105 is configured to determine the target bus command based on the acquired first bus command and first verification information.

[0060] For example, the checksum generation circuit 104 in this embodiment can obtain a first bus command initiated by the first hardware circuit 101, and determine the first check information corresponding to the first access address based on the first access address included in the first bus command. This first check information is the protection information of the first access address. For example, a specific algorithm can be used to encode the first access address to obtain the encoded result, which is the first check information. This specific algorithm includes, but is not limited to, parity check algorithms or cyclic redundancy check algorithms.

[0061] In some examples, the command processing circuit 105 is mainly used to fill the first verification information into the user field (user-defined field) of the original bus command after receiving the original bus command (i.e. the first bus command) issued by the first hardware circuit 101 and the first verification information output by the verification code generation circuit 104, to form the target bus command, and then send the target bus command to the bus corresponding to the first hardware circuit.

[0062] For example, the command processing circuit 105 can be implemented by a bus protocol layer module on the side of the first hardware circuit 101. The bus protocol layer module monitors the command transmission timing of the first hardware circuit 101. When the first hardware circuit 101 outputs the original bus command, the bus protocol layer module simultaneously receives the first verification information output by the checksum generation circuit 104. After the two signals arrive synchronously, the bus protocol layer module automatically "embeds" the first verification information into the user field of the original bus command and then outputs the complete command. This process can be implemented through timing-synchronized hardware control logic. Of course, the command processing circuit 105 can also be implemented by other modules, such as a bus interface module. This embodiment of the present disclosure does not limit this.

[0063] In some examples, such as Figure 3 As shown, in the routing decoding and detection device 100, the output terminal of the first hardware circuit 101 is coupled to the input terminal of the checksum generation circuit 104 and the input terminal of the command processing circuit 105, respectively. The output terminal of the checksum generation circuit 104 is coupled to the input terminal of the command processing circuit 105, the output terminal of the command processing circuit 105 is coupled to the input terminal of the routing decoding circuit 102, and the output terminal of the routing decoding circuit 102 is coupled to the input terminal of the decoding and detection circuit 103. The input and output terminals of the checksum generation circuit 104 share the same port; similarly, the input and output terminals of the command processing circuit 105 share the same port. After the first hardware circuit 101 initiates a first bus command, the checksum generation circuit 104 obtains the first access address included in the first bus command, determines the corresponding first verification information based on the first access address, and then outputs the first verification information to the command processing circuit 105. The command processing circuit 105 generates a target bus command based on the obtained first bus command and first verification information, and outputs the target bus command to the routing decoding circuit 102. The routing decoding circuit 102 performs routing decoding on the target bus command, obtains the second bus command, and outputs the second bus command to the decoding detection circuit 103 through its output terminal; the decoding detection circuit 103 parses the second bus command, obtains the second access address corresponding to the second bus command, and determines the decoding detection result based on the first access address and / or the second access address.

[0064] In some embodiments of this disclosure, such as Figure 4 As shown, in Figure 3 Based on this, the decoding detection circuit 103 includes a second detection sub-circuit 1032.

[0065] The second detection sub-circuit 1032 is configured to obtain the second bus command from the routing decoding circuit, parse the second bus command, and obtain the second access address and the first verification information. Based on the second access address, determine the second verification information corresponding to the second access address; The first verification information and the second verification information are compared to obtain the comparison result; Based on the comparison results, the second detection result is determined; The decoding detection results include the second detection results.

[0066] For example, in this embodiment of the present disclosure, the second detection sub-circuit 1032 can acquire a second bus command and parse it to obtain a decoded second access address and the carried first verification information. Further, the second access address can be encoded using the same algorithm as when determining the first verification information to obtain an encoded result, which is the second verification information. The value of the first verification information is then compared with the value of the second verification information to obtain a comparison result. For example, if the values ​​of the first and second verification information are the same, the comparison result is successful, thus determining that the second detection result indicates the routing decoding process is correct. Conversely, if the values ​​of the first and second verification information are different, the comparison result is unsuccessful, thus determining that the second detection result indicates an error in the routing decoding process.

[0067] For example, when determining the first verification information, a parity check algorithm was used to encode the first access address to obtain the first verification information. Then, the second detection sub-circuit 1032 continues to use the parity check algorithm to encode the second access address to obtain the second verification information. That is, the second detection sub-circuit 1032 can reprocess the second access address according to the same algorithm in the checksum generation circuit 104 to obtain new verification information, which is the second verification information.

[0068] In some examples, such as Figure 4As shown, in the routing decoding and detection device 100, the output terminal of the first hardware circuit 101 is coupled to the input terminal of the checksum generation circuit 104 and the input terminal of the command processing circuit 105, respectively. The output terminal of the checksum generation circuit 104 is coupled to the input terminal of the command processing circuit 105, the output terminal of the command processing circuit 105 is coupled to the input terminal of the routing decoding circuit 102, and the output terminal of the routing decoding circuit 102 is coupled to the input terminal of the second detection sub-circuit 1032. The input and output terminals of the checksum generation circuit 104 share the same port; similarly, the input and output terminals of the command processing circuit 105 share the same port. After the first hardware circuit 101 initiates a first bus command, the checksum generation circuit 104 obtains the first access address included in the first bus command, determines the corresponding first verification information based on the first access address, and then outputs the first verification information to the command processing circuit 105. The command processing circuit 105 generates a target bus command based on the obtained first bus command and first verification information, and outputs the target bus command to the routing decoding circuit 102. The routing decoding circuit 102 performs routing decoding on the target bus command to obtain the second bus command, and then outputs the second bus command to the second detection sub-circuit 1032 through its output terminal. The second detection sub-circuit 1032 parses the second bus command to obtain the second access address and the first verification information, and determines the second verification information corresponding to the second access address based on the second access address. Then, it compares the first verification information with the second verification information to obtain the comparison result, and determines the second detection result based on the comparison result.

[0069] In some embodiments, the second detection sub-circuit 1032 is specifically configured as follows: In response to the comparison result indicating that the first verification information and the second verification information are the same, it is determined that the second detection result indicates that the integrity verification of the first access address has passed during the decoding and transmission process; or, In response to the verification result indicating that the first verification information is different from the second verification information, it is determined that the second detection result indicates that the integrity verification of the first access address failed during the decoding and transmission process.

[0070] For example, in this embodiment of the disclosure, if the comparison result indicates that the values ​​of the first verification information and the second verification information are the same, then the second detection result indicates that the integrity verification of the first access address in the first bus command initiated by the first hardware circuit 101 has passed during the decoding and transmission process. If the comparison result indicates that the values ​​of the first verification information and the second verification information are different, then the second detection result indicates that the first access address may have been damaged, lost, or tampered with during the decoding and transmission process. In this way, the verification and detection of the routing decoding process can be completed from the perspective of data transmission integrity.

[0071] It should be noted that the decoding detection circuit 103 in this embodiment may simultaneously include a first detection sub-circuit 1031 and a second detection sub-circuit 1032. For example, the second detection sub-circuit 1032 can be used to first verify whether the first access address will be damaged, lost, or tampered with during the decoding and transmission process. Further, this can be divided into the following three cases: In the first case, if the detection result of the second detection sub-circuit 1032 is "pass", the first detection sub-circuit 1031 is then used to detect the decoding logic in the routing decoding process. If the result after detection indicates that the decoding logic is also correct, then the final result of the routing decoding detection is "pass".

[0072] The second approach is that if the detection result of the second detection sub-circuit 1032 is "fail", then the final result of the routing decoding detection can be directly determined to be "fail".

[0073] Thirdly, if the detection result of the second detection sub-circuit 1032 is passed, the first detection sub-circuit 1031 can be used to detect the decoding logic in the routing decoding process. If the result after detection indicates that the decoding logic is wrong, it means that the final result of the routing decoding detection is still not passed.

[0074] Of course, the decoding detection circuit 103 in this embodiment may also include only the first detection sub-circuit 1031 or the second detection sub-circuit 1032, and this embodiment does not limit this. Those skilled in the art can flexibly choose the specific implementation of the decoding detection circuit 103 according to the functional safety level requirements and actual business types in the actual chip design, so as to minimize the hardware resource overhead of the chip while meeting the functional safety requirements and actual business needs.

[0075] In some embodiments of this disclosure, the routing decoding and detection device 100 further includes an error handling module, which is configured to: In response to a first detection result from the first detection sub-circuit 1031 indicating a decoding logic error in the routing decoding circuit 102, and / or a second detection result from the second detection sub-circuit 1032 indicating that the integrity check of the first access address failed during the decoding transmission process, a preset security processing operation is performed; wherein, the decoding detection circuit 103 includes the first detection sub-circuit 1031 and the second detection sub-circuit 1032.

[0076] For example, in this embodiment of the present disclosure, after the decoding detection circuit 103 determines the decoding detection result, if the decoding detection result is that the integrity verification fails or the routing decoding logic is incorrect, the decoding detection circuit 103 generates an error interrupt signal to the chip's error handling module to trigger the corresponding security processing procedure. The security processing procedure includes, for example, resetting the bus, reporting error information to the security management unit, setting the abnormal status register flag, restarting the chip, and printing the error log, thereby reducing chip functional abnormalities caused by incorrect routing and further improving the security and reliability of chip operation.

[0077] It should be noted that the error handling module in the embodiments of this disclosure can be implemented as a hardware circuit or a software program, and the embodiments of this disclosure do not limit it in this way.

[0078] In some embodiments, function switches can also be provided for the routing decoding and detection device 100 in this disclosure. Specifically, enable switches can be provided for the checksum generation circuit 104, command processing circuit 105, and decoding and detection circuit 103 in the routing decoding and detection device 100. When the chip is powered on, the enable switch can be configured to be in the on state, thereby activating the relevant functions of the routing decoding and detection device 100. For example, when the chip is powered on, only the enable switch of the decoding and detection circuit 103 can be configured to be in the on state, thereby activating the relevant functions of routing decoding logic detection. Alternatively, when the chip is powered on, the enable switches of the decoding and detection circuit 103, checksum generation circuit 104, and command processing circuit 105 can all be configured to be in the on state, thereby activating the relevant functions of routing decoding logic detection and integrity detection during data decoding and transmission.

[0079] In some embodiments of this disclosure, such as Figure 5 As shown, in Figure 1A Based on this, the routing decoding circuit 102 includes a first decoding sub-circuit 1021 and a second decoding sub-circuit 1022.

[0080] The first decoding sub-circuit 1021 is configured to decode the target bus command to obtain the intermediate bus command; based on the address information in the intermediate bus command, the intermediate bus command is routed and forwarded between the first-level bus and the second-level bus. The second decoding sub-circuit 1022 is configured to acquire intermediate bus commands, decode the intermediate bus commands to obtain second bus commands, and send the second bus commands to the second hardware circuit if the first access address is the same as the second access address corresponding to the second bus command.

[0081] For example, the routing decoding circuit 102 in this embodiment may include: a first decoding sub-circuit 1021 that forwards a target bus command determined based on a first bus command between different buses; and a second decoding sub-circuit 1022 that sends the decoded second bus command to a second hardware circuit.

[0082] For example, the first hardware circuit 101 on the secondary bus initiates a first bus command. The routing decoding module A of the secondary bus performs routing decoding on the target bus command determined based on the first bus command, generates a first intermediate command, and forwards the first intermediate command to the primary bus according to the address information included in the first intermediate command. After receiving the first intermediate command, the routing decoding module B of the primary bus decodes the first intermediate command to generate a second intermediate command, and forwards the second intermediate command to the secondary bus according to the address information included in the second intermediate command. After receiving the second intermediate command, the routing decoding module C of the secondary bus decodes the second intermediate command to output a second bus command, and sends the second bus command to the bus where the second hardware circuit is located, so that the second hardware circuit can parse and execute the control information within the second bus command. In this decoding and routing process, routing decoding module A and routing decoding module B constitute the first decoding sub-circuit 1021, routing decoding module C constitutes the second decoding sub-circuit 1022, and the first and second intermediate commands constitute the intermediate bus command.

[0083] In some examples, such as Figure 5 As shown, the output terminal of the first hardware circuit 101 is coupled to the input terminal of the first decoding sub-circuit 1021 via a bus. After the first hardware circuit 101 initiates the first bus command, the first bus command is output to the bus through the output terminal of the first hardware circuit 101, so that the first decoding sub-circuit 1021 can obtain the target bus command determined based on the first bus command. The output of the first decoding sub-circuit 1021 is coupled to the input of the second decoding sub-circuit 1022. The first decoding sub-circuit 1021 decodes the target bus command to obtain an intermediate bus command. Based on the address information in the intermediate bus command, the intermediate bus command is routed and forwarded between the first-level bus and the second-level bus. The intermediate bus command is then output to the second decoding sub-circuit 1022 through the output of the first decoding sub-circuit 1021. The output of the second decoding sub-circuit 1022 is coupled to the input of the decoding detection circuit 103. The second decoding sub-circuit 1022 decodes the intermediate bus command to obtain a second bus command. The second bus command is then output to the decoding detection circuit 103 through the output of the second decoding sub-circuit 1022. The decoding detection circuit 103 then parses the second bus command to obtain the second access address corresponding to the second bus command. Based on the first access address and / or the second access address, the decoding detection result is determined.

[0084] Exemplary methods Corresponding to the device embodiments provided above, this disclosure also provides a route decoding detection method.

[0085] Figure 6 This is a flowchart illustrating a route decoding and detection method provided in an exemplary embodiment of this disclosure. Figure 6 As shown, this routing decoding detection method can be applied to SOC (System on Chip) and may include the following steps 601 to 604.

[0086] Step 601: Generate a first bus command for sending to the second hardware circuit; wherein the first bus command includes a first access address; Step 602: Obtain the target bus command, decode the target bus command to obtain the second bus command; wherein, the target bus command is determined based on the first bus command; Step 603: Obtain the second bus command, parse the second bus command, and obtain the second access address corresponding to the second bus command; Step 604: Determine the decoding detection result based on the first access address and / or the second access address.

[0087] In some embodiments of this disclosure, such as Figure 7 As shown above, in the above Figure 6 Based on the illustrated embodiment, step 604 may include steps 6041a-6043a.

[0088] Step 6041a: Determine the preset address range corresponding to the second hardware circuit in the memory mapping table; Step 6042a: Match the second access address with the preset address range to obtain the matching result; Step 6043a: Based on the matching results, determine the first detection result; wherein, the decoding detection result includes the first detection result.

[0089] In some embodiments of this disclosure, step 6043a, determining the first detection result based on the matching result, includes: in response to the matching result indicating that the preset address range includes the second access address, determining that the first detection result indicates that the decoding logic of the routing decoding circuit is correct; or, in response to the matching result indicating that the preset address range does not include the second access address, determining that the first detection result indicates that the decoding logic of the routing decoding circuit is incorrect.

[0090] In some embodiments of this disclosure, the routing decoding detection method further includes: obtaining a first access address included in a first bus command from a first hardware circuit, and determining first verification information corresponding to the first access address based on the first access address; and determining a target bus command based on the obtained first bus command and the first verification information.

[0091] In some embodiments of this disclosure, such as Figure 8 As shown above, in the above Figure 6 Based on the illustrated embodiment, step 604 may include steps 6041b-6044b.

[0092] Step 6041b: Obtain the second bus command from the routing decoding circuit, parse the second bus command to obtain the second access address and the first verification information; Step 6042b: Based on the second access address, determine the second verification information corresponding to the second access address; Step 6043b: Compare the first verification information with the second verification information to obtain the comparison result; Step 6044b: Based on the comparison results, determine the second detection result; wherein, the decoding detection result includes the second detection result.

[0093] In some embodiments of this disclosure, step 6044b, determining the second detection result based on the comparison result, includes: in response to the comparison result indicating that the first verification information and the second verification information are the same, determining the second detection result to indicate that the integrity verification of the first access address in the decoding and transmission process has passed; or, in response to the verification result indicating that the first verification information and the second verification information are different, determining the second detection result to indicate that the integrity verification of the first access address in the decoding and transmission process has failed.

[0094] In some embodiments of this disclosure, the routing decoding detection method further includes: in response to a first detection result from a first detection sub-circuit indicating a decoding logic error in the routing decoding circuit, and / or a second detection result from a second detection sub-circuit indicating that the integrity check of the first access address failed during the decoding transmission process, performing a preset security processing operation; wherein the decoding detection circuit includes a first detection sub-circuit and a second detection sub-circuit.

[0095] In some embodiments of this disclosure, step 602, obtaining a target bus command and decoding the target bus command to obtain a second bus command, includes: decoding the target bus command to obtain an intermediate bus command; routing and forwarding the intermediate bus command between the first-level bus and the second-level bus based on the address information in the intermediate bus command; obtaining the intermediate bus command and decoding the intermediate bus command to obtain a second bus command; and sending the second bus command to the second hardware circuit if the first access address is the same as the second access address corresponding to the second bus command.

[0096] It is understood that the specific execution methods and corresponding beneficial effects of each step in the routing decoding and detection method in the above embodiments have been described in detail in the embodiments corresponding to the routing decoding and detection device mentioned above. Please refer to the corresponding execution methods and beneficial technical effects in the exemplary device section above, and they will not be repeated here.

[0097] Exemplary electronic devices Figure 9 A structural diagram of an electronic device 900 provided for an exemplary embodiment of the present disclosure includes at least one processor 901 and a memory 902.

[0098] The processor 901 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 900 to perform desired functions.

[0099] The memory 902 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 901 may execute one or more computer program instructions to implement the routing decoding detection method and / or other desired functions of the various embodiments of this disclosure described above.

[0100] In one example, the electronic device 900 may also include an input device 903 and an output device 904, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0101] The input device 903 may also include, for example, a keyboard, a mouse, etc.

[0102] The output device 904 can output various information to the outside, including, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0103] Of course, for the sake of simplicity, Figure 9 Only some of the components of the electronic device 900 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 900 may include any other suitable components depending on the specific application.

[0104] Exemplary chip Figure 10 This is a schematic diagram of a chip structure provided for an exemplary embodiment of this disclosure. For example... Figure 10 As shown, the chip 10 integrates at least a routing decoding detection device 11 for detecting routing decoding logic and a memory 12.

[0105] The routing decoding and detection device 11 is mainly used to protect the address information in the bus command during the transmission of the bus command, ensuring that the address information is correct before it is transmitted to the second hardware circuit. Furthermore, it determines whether the bus command has been routed to the correct destination IP, i.e., the second hardware circuit, based on the position of the address information in the chip's memory mapping table.

[0106] The memory 12 can be used to store the routing decoding and detection results output by the routing decoding and detection device 11.

[0107] In this way, routing decoding logic protection can be achieved while reducing hardware footprint. For example, the specific security level could be ASILB (Automotive Safety Integrity Level B).

[0108] The routing decoding and detection device 11 can be the above Figures 1A to 5 In any of the routing decoding and detection devices shown, chip 10 can be a SOC (System on Chip) chip or other types of chips, and this disclosure does not limit this.

[0109] In some embodiments of this disclosure, a chip is further provided, which includes at least a routing decoding and detection device and a memory. The routing decoding and detection device includes: A first hardware circuit is configured to generate a first bus command for sending to a second hardware circuit; wherein the first bus command includes a first access address.

[0110] The routing decoding circuit is configured to acquire the target bus command, decode the target bus command, and obtain the second bus command; wherein the target bus command is determined based on the first bus command.

[0111] The decoding detection circuit is configured to acquire a second bus command, parse the second bus command to obtain a second access address corresponding to the second bus command, and determine the decoding detection result based on the first access address and / or the second access address.

[0112] The second hardware circuit is configured to receive and respond to the second bus command.

[0113] It should be noted that the specific implementations of the first hardware circuit, the routing decoding circuit, the decoding detection circuit, and the second hardware circuit can be referred to the corresponding contents in the foregoing embodiments, and will not be repeated here.

[0114] Exemplary computer program products and computer-readable storage media In addition to the methods and apparatus described above, embodiments of this disclosure may also provide a computer program product, including computer program instructions, which, when executed by a processor, cause the processor to perform the steps in the routing decoding detection methods of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0115] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0116] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the routing decoding detection method of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0117] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0118] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0119] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, this disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of this disclosure and their equivalents.

Claims

1. A routing decoding and detection device, comprising: A first hardware circuit is configured to generate a first bus command for sending to a second hardware circuit; wherein the first bus command includes a first access address; The routing decoding circuit is configured to acquire a target bus command, decode the target bus command to obtain a second bus command; wherein the target bus command is determined based on the first bus command. The decoding detection circuit is configured to acquire the second bus command, parse the second bus command to obtain the second access address corresponding to the second bus command, and determine the decoding detection result based on the first access address and / or the second access address.

2. The apparatus according to claim 1, wherein, The decoding detection circuit includes a first detection sub-circuit, which is configured to: A preset address range corresponding to the second hardware circuit in the memory mapping table is determined, and the second access address is matched with the preset address range to obtain a matching result; based on the matching result, a first detection result is determined; The decoding detection result includes the first detection result.

3. The apparatus according to claim 2, wherein, The first detection sub-circuit is specifically configured as follows: In response to the matching result indicating that the preset address range includes the second access address, it is determined that the first detection result indicates that the decoding logic of the routing decoding circuit is correct; or, In response to the matching result indicating that the preset address range does not include the second access address, the first detection result is determined to characterize a decoding logic error in the routing decoding circuit.

4. The apparatus according to any one of claims 1-3, wherein the routing decoding and detection apparatus further comprises: The verification code generation circuit is configured to obtain the first access address included in the first bus command from the first hardware circuit, and determine the first verification information corresponding to the first access address based on the first access address. The command processing circuit is configured to determine the target bus command based on the acquired first bus command and the first verification information.

5. The apparatus according to claim 4, wherein, The decoding detection circuit includes a second detection sub-circuit, which is configured as follows: Obtain the second bus command from the routing decoding circuit, parse the second bus command to obtain the second access address and the first verification information; Based on the second access address, determine the second verification information corresponding to the second access address; The first verification information and the second verification information are compared to obtain the comparison result; Based on the comparison results, a second detection result is determined; The decoding detection result includes the second detection result.

6. The apparatus according to claim 5, wherein, The second detection sub-circuit is specifically configured as follows: In response to the comparison result indicating that the first verification information and the second verification information are the same, it is determined that the second detection result indicates that the integrity verification of the first access address in the decoding and transmission process has passed; or, In response to the verification result indicating that the first verification information is different from the second verification information, it is determined that the second detection result indicates that the integrity verification of the first access address failed during the decoding and transmission process.

7. The apparatus according to claim 1, wherein the routing decoding and detection apparatus further comprises: An error handling module is configured to perform a preset security processing operation in response to a first detection result from a first detection sub-circuit indicating a decoding logic error in the routing decoding circuit, and / or a second detection result from a second detection sub-circuit indicating that the integrity check of the first access address failed during the decoding transmission process; wherein the decoding detection circuit includes the first detection sub-circuit and the second detection sub-circuit.

8. The apparatus according to claim 1, wherein, The routing decoding circuit includes a first decoding sub-circuit and a second decoding sub-circuit: The first decoding sub-circuit is configured to decode the target bus command to obtain an intermediate bus command; Based on the address information in the intermediate bus command, the intermediate bus command is routed and forwarded between the first-level bus and the second-level bus; The second decoding sub-circuit is configured to acquire the intermediate bus command, decode the intermediate bus command, and obtain the second bus command; If the first access address is the same as the second access address corresponding to the second bus command, the second bus command is sent to the second hardware circuit.

9. A routing decoding detection method, comprising: Generate a first bus command for sending to a second hardware circuit; wherein the first bus command includes a first access address; Obtain the target bus command, decode the target bus command to obtain the second bus command; wherein the target bus command is determined based on the first bus command; Obtain the second bus command, parse the second bus command, and obtain the second access address corresponding to the second bus command; Determine the decoding detection result based on the first access address and / or the second access address.

10. A computer-readable storage medium storing a computer program that is executed by a processor to perform the routing decoding detection method of claim 9.

11. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the routing decoding detection method of claim 9.

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