Big data based chip defect online detection traceability method

Abstract

The application relates to the technical field of big data analysis, in particular to a chip defect online detection traceability method based on big data, which comprises the following steps: preprocessing a chip image to obtain a chip defect image, extracting features of the chip defect image to obtain chip defect features, and judging whether the extraction effectiveness of the chip defect features meets the requirements according to the coverage rate of the chip defect features; constructing a machine learning model based on the chip defect features, identifying chip images at the output ends of the several processing procedures according to the machine learning model to obtain an identification result, determining the positions of the chips with defects, and determining whether to supplement and connect the broken defect segments in the chip defect image according to the identification accuracy of the identification result; and checking the defect source according to the traceability success rate of the traceability report to determine whether to re-execute the traceability analysis. The application improves the traceability accuracy of chip defect detection.

Description

Technical Field

[0001] This invention relates to the field of big data analytics, and in particular to a method for tracing the source of chip defects through online detection based on big data. Background Technology

[0002] In existing technologies, during the process of tracing the source of chip defects in online detection using big data, lighting conditions, background complexity, and image distortion and noise introduced by hardware devices can directly interfere with defect feature extraction. Insufficient number of defect samples, single type, or incomplete data annotation can prevent the model from fully learning defect features. Furthermore, as device geometry continues to shrink and the number of wafer layers increases, tiny defects are easily masked by multiple complex backgrounds. The dual requirements of real-time detection for algorithm efficiency and accuracy further exacerbate the difficulty of tracing the source and affect the accuracy of chip defect detection.

[0003] Chinese Patent Publication No. CN113299572A discloses a chip defect detection method, comprising: S1, providing a wafer with multiple identical chips fabricated on its surface, wherein the multiple identical chips are arranged in a matrix on the wafer; S2, selecting a chip to be tested, and establishing a virtual Cartesian coordinate system with the geometric center of the chip to be tested as the origin, wherein the X-axis of the Cartesian coordinate system is perpendicular to the opening direction of the wafer alignment mark, and the Y-axis is parallel to the opening direction of the wafer alignment mark, and selecting chips on the angle bisectors of the four quadrants of the Cartesian coordinate system as comparison chips, wherein at least two comparison chips are selected; S3, acquiring data images of the chip to be tested and the comparison chips; S4, comparing the data image of each comparison chip with the data image of the chip to be tested one by one, and if an anomaly is found, the chip to be tested is defective.

[0004] Therefore, the chip defect detection method only compares the image differences between the chip under test and a small number of comparison chips at fixed positions. The detection basis is too singular and cannot fully reflect the true spatial distribution and process-related characteristics of wafer defects, which can easily lead to false detections or missed detections. Summary of the Invention

[0005] To address this, the present invention provides a traceability method for online detection of chip defects based on big data, which overcomes the problem that existing technologies rely solely on image differences between the chip under test and a small number of comparison chips at fixed locations. This results in overly simplistic detection criteria, which fail to fully reflect the true spatial distribution and process-related characteristics of wafer defects, and are prone to false detections or missed detections.

[0006] To achieve the above objectives, this invention provides a method for tracing the source of chip defects through online detection based on big data, comprising: Acquire chip images from several processing flow outputs, preprocess the chip images to obtain chip defect images, extract features from the chip defect images to obtain chip defect features, and determine whether the effectiveness of chip defect feature extraction meets the requirements based on the coverage of chip defect features. A machine learning model is constructed based on the chip defect features, and the chip images at the output of the several processing steps are identified according to the machine learning model to obtain the identification results, so as to determine the location of the chip with defects, and to determine whether to repair the broken defect segments in the chip defect image according to the identification accuracy of the identification results. A traceability report is generated based on the identification results, and defective chips are located and removed according to the traceability report. The source of the defect is then checked back based on the traceability success rate of the traceability report to determine whether to re-execute the traceability analysis. Chip defect images include wafer surface images, chip cell area images, and defect candidate area images; Chip defect characteristics include defect location characteristics, chip array location characteristics, and process parameter correlation characteristics.

[0007] Furthermore, the coverage of chip defect features is used to determine whether the effectiveness of chip defect feature extraction meets the requirements, including: If the coverage of chip defect features is greater than or equal to the preset coverage, then the effectiveness of chip defect feature extraction is determined to meet the requirements. If the coverage of the chip defect features is less than the preset coverage, then the effectiveness of the chip defect feature extraction is determined to be unsatisfactory.

[0008] Furthermore, if the effectiveness of chip defect feature extraction does not meet the requirements, it is preliminarily determined that the analytical capability of the machine learning model does not meet the requirements, and the analytical capability of the machine learning model is determined based on the recognition accuracy of the recognition results.

[0009] Furthermore, the analytical capabilities of the machine learning model are determined based on the recognition accuracy of the recognition results, including: If the recognition accuracy of the recognition result is greater than or equal to the preset second accuracy, then the analytical capability of the machine learning model is determined to meet the requirements. If the recognition accuracy of the recognition result is less than the preset second accuracy, then it is determined that the analytical capability of the machine learning model does not meet the requirements.

[0010] Further, determine whether it is necessary to repair broken defect segments in the chip defect image, including: If the recognition accuracy of the recognition result is greater than or equal to the preset first accuracy and less than the preset second accuracy, then it is determined that the broken defect segments in the chip defect image need to be repaired. If the recognition accuracy of the recognition result is less than the preset first accuracy, it is determined that it is not necessary to repair the broken defect segments in the chip defect image.

[0011] Furthermore, the process of repairing broken defect segments in the chip defect image involves filtering out noise isolated points that do not participate in the repair based on the chip array position relationship, repairing broken defect segments that conform to the chip array continuity relationship, and then removing the remaining segments a second time after repair.

[0012] Furthermore, if the recognition accuracy of the recognition result is less than the preset first accuracy, it is preliminarily determined that the analysis accuracy of the traceability report does not meet the requirements, and the analysis accuracy of the traceability report is determined based on the traceability success rate of the traceability report.

[0013] Furthermore, the accuracy of the source tracing report's analysis is determined based on the success rate of the source tracing report, including: If the traceability success rate of the traceability report is greater than or equal to the preset success rate, then the accuracy of the traceability report analysis is determined to meet the requirements. If the success rate of the source tracing report is less than the preset success rate, it is determined that the accuracy of the source tracing report does not meet the requirements, and the source of the defect is investigated to determine whether to re-execute the source tracing analysis.

[0014] Furthermore, the traceability success rate of the traceability report is determined based on the ratio of the number of successful traceability attempts to the total number of traceability attempts.

[0015] Furthermore, the process of retracing the source of defects to determine whether to re-execute the source analysis involves using the continuous defect patches obtained after patching as input, retracing the source of defects according to the production process records at the tank level, adjusting the patching and isolated point removal conditions, and re-executing the source analysis after adjustment.

[0016] Compared with existing technologies, the beneficial effects of this invention are as follows: The method of this invention determines the effectiveness of chip defect feature extraction based on the coverage of chip defect features, identifies abnormal data loss caused by incomplete sampling areas or excessively high defect trigger thresholds, and avoids incomplete defect feature representation caused by ineffective collection of minute defects and edge region defects from the source, ensuring consistency between chip defect features and the actual distribution and severity of chip defects; based on the recognition accuracy of the recognition results, the analytical capability of the machine learning model is determined, and broken defect segments in the chip defect image are repaired and connected, improving the continuity and integrity of the defect image and restoring the true spatial distribution of the defects. The layout enhances the identifiability and consistency of defect patterns, thereby improving the machine learning model's ability to analyze chip defect patterns. The accuracy of the traceability report is determined by its success rate. The continuous defect patches obtained after patching are used as the traceability input. The defect source is traced back according to the slot records and slot-level process parameter fluctuation records of the corresponding batch of wafers. When the traceability fails, the patching distance conditions, the participation of isolated points in patching conditions, or the cavity mapping range of the same group of chips are adjusted according to the failure type feedback. The continuous defect patches are regenerated and the traceability analysis is re-executed. This reduces the situation where the same defect event is incorrectly mapped to multiple process nodes, thereby improving the traceability accuracy of chip defect detection.

[0017] Furthermore, the method described in this invention determines the effectiveness of chip defect feature extraction by setting a preset coverage rate. Since different defect types present significant differences in features in the image during online chip defect detection, if the feature extraction only includes a small number of grayscale, area, or position features without covering key features such as morphology, spatial distribution, array position, and process correlation, it will be difficult to effectively distinguish different defect patterns, affecting the accuracy of analysis and tracing. By determining the coverage rate of chip defect features, it can be determined whether the currently extracted defect features cover the main defect types and their key representation dimensions, which helps to more comprehensively characterize the type, morphology, location, distribution, and process correlation of chip defects, further improving the accuracy of chip defect detection and tracing.

[0018] Furthermore, the method of the present invention, by setting a preset first accuracy rate and a second accuracy rate, reconnects broken defect segments in the chip defect image. During chip defect detection, issues such as cross-dices scratches and cavity airflow banded particles typically present a continuous or corresponding distribution along the same row of chips or the same cavity-mapped group of chips. When the preprocessing process excessively smooths weak response anomalies or eliminates isolated points, patches belonging to the same defect event may be cut off. By first filtering out measurement noise-like isolated points that do not correspond to the chip array position, random anomalies can be avoided from being mistakenly incorporated into the real defect patch. Then, using the array topology relationship between chips in the same row, in the same column, adjacent chips in the dices, and chips in the same group of cavity mappings as the primary basis, the broken defect segments are reconnected, which can restore the cross-chip scratches, banded particles, and process offset defects that were cut off during preprocessing. After reconnection, residual segments that still do not meet the chip array continuity relationship or batch repetition relationship are removed a second time, thereby obtaining a defect feature map that better matches the true spatial distribution of wafer defects, further improving the traceability accuracy of chip defect detection.

[0019] Furthermore, the method described in this invention sets a success rate to determine whether to re-execute the source tracing analysis by reviewing the defect source. During chip manufacturing, different slots within the same process and equipment cavity may be affected by temperature gradients, airflow distribution, etc., causing different edge chipping and granular banding distributions to form on different slots of the same batch of wafers. This can cause continuous scratches or bridging defects that originally belong to the same defect event to be identified as multiple scattered clusters, leading the source tracing model to incorrectly map the same defect event to multiple process nodes. By using the continuous defect pattern as the source tracing input, continuous spatial information such as the defect morphology can be preserved. The continuous defect pattern is then compared with the slot records and slot-level process parameter fluctuation records of the corresponding batch of wafers to determine the candidate process source corresponding to the repeated continuous defect pattern. When source tracing fails, the second-layer patching distance condition, isolated point participation patching condition, or cavity mapping range of the same chip group is adjusted according to the source failure type feedback, and the continuous defect pattern is regenerated for source tracing analysis, further improving the source tracing accuracy of chip defect detection. Attached Figure Description

[0020] Figure 1 This is an overall flowchart of the chip defect online detection and tracing method based on big data according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating the process of determining whether the extraction of chip defect features meets the requirements in the traceability method for online chip defect detection based on big data, as described in this embodiment of the invention. Figure 3This is a flowchart illustrating the process of repairing broken defect segments in a chip defect image to determine the source tracing method for online chip defect detection based on big data, as described in this embodiment of the invention. Figure 4 This is a flowchart illustrating the logical process of a big data-based online chip defect detection tracing method in this invention, which involves retrospectively investigating the source of defects to determine whether the tracing analysis process should be re-executed. Detailed Implementation

[0021] To make the objectives and advantages of the present invention clearer, the present invention will be further described below with reference to embodiments; it should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0022] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0023] Please see Figure 1 The diagram shown is an overall flowchart of the chip defect online detection and tracing method based on big data according to an embodiment of the present invention. The method described in this embodiment includes... Step S1: Obtain chip images from several processing flow outputs, preprocess the chip images to obtain chip defect images, extract features from the chip defect images to obtain chip defect features, and determine whether the effectiveness of chip defect feature extraction meets the requirements based on the coverage of chip defect features. Step S2: Construct a machine learning model based on the chip defect features, and use the machine learning model to identify the chip images at the output of the several processing steps to obtain identification results, so as to determine the location of the chip with defects, and determine whether to repair the broken defect segments in the chip defect image based on the identification accuracy of the identification results. Step S3: Generate a traceability report based on the identification results, locate and remove defective chips according to the traceability report, and check the source of defects based on the traceability success rate of the traceability report to determine whether to re-execute the traceability analysis.

[0024] Specifically, chip defect images include wafer surface images, chip cell area images, and defect candidate area images.

[0025] Specifically, chip defect characteristics include defect location characteristics, chip array location characteristics, and process parameter correlation characteristics.

[0026] Specifically, preprocessing includes image denoising, brightness correction, and wafer coordinate registration.

[0027] Specifically, the process of building a machine learning model based on the chip defect features is as follows: a training sample set is established based on the chip defect features; the training samples are labeled with defect categories and process sources; the defect image features, chip array position features, and process parameter correlation features are input into the machine learning model for training; and the model output results are verified by validation samples to obtain a machine learning model for chip defect analysis and source tracing.

[0028] Specifically, the machine learning models include image feature extraction models for extracting spatial features of defect images, defect classification models for identifying defect types, and defect grading models for judging the severity of defects.

[0029] Specifically, the process of identifying chip images at the output ends of several processing steps using the machine learning model to obtain identification results involves inputting a preprocessed chip defect image into the machine learning model to extract grayscale, shape, boundary, spatial distribution, chip array position, and processing step-related features; identifying the defect type, region, severity, and chip location based on these features; and mapping the defect region to the corresponding chip row and column number, wafer region position, and processing step output end to obtain the identification result; wherein, the identification result includes the defect chip location, defect type, defect confidence, defect severity, defect distribution region, and corresponding processing step output end information.

[0030] Specifically, the identification results include defect category, defect location, and defect severity.

[0031] Specifically, the source tracing report includes defect analysis results, continuous defect patch characteristics, and candidate defect sources.

[0032] In this embodiment, the method determines the effectiveness of chip defect feature extraction based on the coverage of chip defect features. This allows the method to determine whether the currently extracted defect features cover the main defect types and their key representation dimensions, which helps to more comprehensively characterize the type, shape, location, distribution, and process correlation of chip defects. The method also determines the analytical capability of the machine learning model based on the recognition accuracy of the identification results. Broken defect segments in the chip defect image are repaired and connected to improve the continuity and integrity of the defect image, restore the true spatial distribution of defects, and enhance the identifiability and consistency of defect patterns, thereby improving the machine learning model's ability to analyze chip defect patterns. Furthermore, the method determines the analytical accuracy of the traceability report based on its traceability success rate. The continuous defect patches obtained after repair are used as traceability input. The defect source is traced back according to the slot records and slot-level process parameter fluctuation records of the corresponding batch of wafers. When traceability fails, the repair distance conditions, isolated point participation repair conditions, or cavity mapping within the same chip group are adjusted based on the failure type feedback. Continuous defect patches are regenerated and traceability analysis is re-executed, reducing the possibility of the same defect event being incorrectly mapped to multiple process nodes and improving the traceability accuracy of chip defect detection.

[0033] Please see Figure 2 The diagram shown is a logical flowchart illustrating the process of determining whether the extraction validity of chip defect features meets the requirements according to an embodiment of the present invention. In this embodiment, the coverage rate of chip defect features is obtained to determine the extraction validity of chip defect features. The coverage of chip defect features is determined by the ratio of the actual amount of abnormal data collected to the theoretical total amount of abnormal data that should be collected.

[0034] Specifically, the coverage of chip defect features determines whether the effectiveness of chip defect feature extraction meets the requirements, including: If the coverage of chip defect features is greater than or equal to the preset coverage, then the effectiveness of chip defect feature extraction is determined to meet the requirements. If the coverage of the chip defect features is less than the preset coverage, then the effectiveness of the chip defect feature extraction is determined to be unsatisfactory.

[0035] It is understandable that the preset coverage rate is a value determined by those skilled in the art based on the historical statistical distribution of chip defect feature coverage within multiple defect detection cycles in a chip defect detection scenario, combined with the effectiveness of chip defect feature extraction corresponding to different defect feature coverage levels. The coverage rate of chip defect features is positively correlated with the effectiveness of chip defect feature extraction. The preset coverage rate is the coverage rate of chip defect features corresponding to the requirement that the effectiveness of chip defect feature extraction meets the requirements in the historical statistical distribution. When the chip defect feature coverage rate is greater than or equal to the preset coverage rate, it means that the currently extracted defect features can cover the main defect types and their key characterization dimensions. The morphological features, spatial distribution features, chip array position features, and process correlation features of the defects can meet the requirements of subsequent defect analysis and source tracing. Therefore, it is determined that the effectiveness of chip defect feature extraction meets the requirements. When the chip defect feature coverage rate is less than the preset coverage rate, it means that the currently extracted defect features are insufficient. Some defect types or key feature dimensions have not been effectively extracted, making it difficult for the defect features to fully characterize the true type, morphology, location, distribution, and process correlation of chip defects. Therefore, it is determined that the effectiveness of chip defect feature extraction does not meet the requirements.

[0036] The specific value of the preset coverage rate can be set according to the chip process complexity of the historical defect detection task, the sensitivity of business defects, and the requirements of those skilled in the art for the effectiveness of chip defect feature extraction, and will not be elaborated here.

[0037] Specifically, chip manufacturing process complexity includes the number of process steps, the number of structural layers, and the level of process refinement.

[0038] Specifically, business defect sensitivity refers to the degree to which chip application scenarios tolerate missed defects, false defects, or deviations in tracing the source of defects.

[0039] In this embodiment, the method determines the effectiveness of chip defect feature extraction by setting a preset coverage rate. Since different defect types present significant differences in features in the image during online chip defect detection, if the feature extraction only includes a small number of grayscale, area, or position features without covering key features such as morphology, spatial distribution, array position, and process correlation, it will be difficult to effectively distinguish different defect patterns, affecting the accuracy of analysis and tracing. By determining the coverage rate of chip defect features, it can be determined whether the currently extracted defect features cover the main defect types and their key representation dimensions, which helps to more comprehensively characterize the type, morphology, location, distribution, and process correlation of chip defects, further improving the accuracy of chip defect detection and tracing.

[0040] Please see Figure 3 The diagram shown is a flowchart illustrating the process of repairing broken defect segments in a chip defect image according to an embodiment of the present invention. In this embodiment, the recognition accuracy of the recognition result is obtained to determine whether the analytical capability of the machine learning model meets the requirements. The recognition accuracy rate is determined by the ratio of the number of correct results to the total number of verification results.

[0041] Specifically, if the effectiveness of extracting chip defect features does not meet the requirements, it is initially determined that the analytical capability of the machine learning model does not meet the requirements, and the analytical capability of the machine learning model is determined based on the recognition accuracy of the recognition results.

[0042] Specifically, the analytical capabilities of the machine learning model are determined based on the recognition accuracy of the recognition results, including: If the recognition accuracy of the recognition result is greater than or equal to the preset second accuracy, then the analytical capability of the machine learning model is determined to meet the requirements. If the recognition accuracy of the recognition result is less than the preset second accuracy, then it is determined that the analytical capability of the machine learning model does not meet the requirements.

[0043] Specifically, determining whether it is necessary to repair broken defect segments in the chip defect image includes: If the recognition accuracy of the recognition result is greater than or equal to the preset first accuracy and less than the preset second accuracy, then it is determined that the broken defect segments in the chip defect image need to be repaired. If the recognition accuracy of the recognition result is less than the preset first accuracy, it is determined that it is not necessary to repair the broken defect segments in the chip defect image.

[0044] In this embodiment, the preset first accuracy rate is less than the preset second accuracy rate, wherein... If the recognition accuracy of the recognition result is less than the preset first accuracy, the corresponding situation is as follows: During the chip manufacturing process, different slots in the same process and the same equipment cavity may be affected by temperature gradient, airflow distribution and other issues, causing different edge defects and particle band distributions to form on different slots of the same batch of wafers. This may cause continuous scratches or bridging defects that originally belong to the same defect event to be identified as multiple scattered clusters, resulting in the traceability model incorrectly mapping the same defect event to multiple process nodes. If the recognition accuracy rate of the recognition result is greater than or equal to the preset first accuracy rate and less than the preset second accuracy rate, the corresponding situation is as follows: In the chip defect detection process, problems such as cross-scribing scratches and cavity airflow band particles usually appear as continuous or corresponding distributions along the same row of chips or the same cavity mapped group of chips; when the preprocessing process excessively smooths weak response abnormal points or eliminates isolated points, the patches belonging to the same defect event may be cut off. If the recognition accuracy rate of the recognition result is greater than or equal to the preset second accuracy rate, the corresponding situation is: the analytical capability of the machine learning model is determined to meet the requirements.

[0045] It is understandable that the preset first accuracy rate and preset second accuracy rate are values ​​determined by those skilled in the art based on the historical statistical distribution of the recognition accuracy rate of the identification results in chip defect detection scenarios, combined with the analytical capabilities of the machine learning model corresponding to different verification accuracy rates. The recognition accuracy rate of the identification result is positively correlated with the analytical capabilities of the machine learning model. The preset first accuracy rate is the recognition accuracy rate of the recognition results when the analytical ability of the machine learning model is seriously inadequate in the historical statistical distribution. When the recognition accuracy rate of the recognition results is less than this value, it indicates that there is a significant deviation between the defect category, defect patch morphology and candidate process source output by the model. Continuous scratches, bridging defects or edge band defects that originally belong to the same defect event may be identified as multiple scattered clusters, causing the subsequent source tracing model to incorrectly map the same defect event to multiple process nodes. Therefore, the analytical ability of the machine learning model is seriously inadequate. The second preset accuracy rate is the recognition accuracy rate of the recognition results when the analytical ability of the machine learning model in the historical statistical distribution meets the requirements. When the recognition accuracy rate of the recognition results is greater than or equal to this value, it means that the model can accurately identify the chip defect type, defect spatial morphology and defect array distribution relationship, and can meet the requirements of subsequent traceability analysis for defect feature integrity and stability. Therefore, it is determined that the analytical ability of the machine learning model meets the requirements. When the recognition accuracy of the recognition result is greater than or equal to the preset first accuracy and less than the preset second accuracy, it indicates that the machine learning model can recognize some defects and anomalies, but it is insufficient in representing the continuous spatial morphology of cross-scribing scratches, cavity airflow banded particles, continuous edge defects and process offset defects. It is easily affected by the excessive smoothing of weak response anomaly points, the mistaken removal of isolated points or the failure to reconnect broken patches, which leads to the same defect event being split into multiple discontinuous segments. Therefore, the analytical ability of the machine learning model does not meet the requirements.

[0046] The preset accuracy rate can be set according to the complexity of chip defect types, chip array distribution density, and the requirements of those skilled in the art for the analytical capabilities of machine learning models, and will not be elaborated here.

[0047] Specifically, chip defect type complexity refers to the number of defect types involved in chip defect detection, such as scratches, particulate contamination, and bridging, their similarity, and the degree of morphological overlap between different defect types.

[0048] Specifically, chip array distribution density refers to the density of the arrangement of chip rows and columns on the same wafer, as well as the density of spatial relationships formed between adjacent chips, chips adjacent to the dicing track, and chips in the same group of cavity mapping.

[0049] Specifically, the process of repairing broken defect segments in the chip defect image involves filtering out noise isolated points that do not participate in the repair based on the chip array position relationship, repairing broken defect segments that conform to the chip array continuity relationship, and then removing the remaining segments a second time after repair.

[0050] Specifically, the process of repairing broken defect segments in a chip defect image includes: The preprocessed chip defect image is acquired, and the defect patches, broken defect fragments and candidate isolated anomalies in the chip defect image are identified based on the abnormal pixel position, abnormal response intensity, defect contour and chip array coordinates. The chip array position relationship is established based on the row and column numbering of chips on the wafer, the positions of adjacent chips, the adjacency relationship of scribe lines, and the mapping relationship of the device cavity; wherein, the chip array position relationship includes the continuous relationship of chips in the same row, the continuous relationship of chips in the same column, the adjacency relationship of chips on both sides of the scribe line, and the correspondence between the grouped chips mapped in the same device cavity; The candidate isolated anomalies are initially screened. If the candidate isolated anomalies do not correspond to the abnormal distribution in the same group of chips, chips in the same column, chips adjacent to the dicing channel, or chips mapped to the device cavity, and do not recur in the same batch of wafers, the candidate isolated anomalies are marked as noise isolated points that do not participate in the patching, so as to avoid random measurement noise being mistakenly spliced ​​into the real defect patch. After eliminating isolated noise points, the remaining broken defect segments are reconnected. Specifically, it is determined whether two broken defect segments are located within the corresponding regions of chips in the same row, in the same column, adjacent chips in the dicing channel, or in the same group of chips mapped by the device cavity. If the two broken defect segments satisfy the above chip array continuity relationship, further auxiliary verification is performed based on the distance between the endpoints of the two broken defect segments, the main extension direction, the continuity of grayscale response, and the presence of weak abnormal response regions. If two fracture defect segments satisfy the chip array continuity relationship and the endpoint distance, main extension direction and grayscale response continuity meet the requirements for patching, the two fracture defect segments are patched into the same defect patch, and the weak abnormal response area between the two fracture defect segments is included in the defect patch to restore the continuous spatial morphology of cross-die scratches, cavity airflow banded particles, edge continuous defects or process offset defects. After completing the repair of the broken defect segments, the repaired defect patch is reviewed, and it is re-evaluated whether the abnormal points previously marked as noise isolated points fall into the extended path of the repaired defect patch, the continuous path of the same row of chips, the continuous path of the same column of chips, the adjacent path of the dicing track, or the defect path of the same group of chips mapped by the device cavity; if so, the corresponding abnormal point is restored from the noise isolated point set and re-included into the corresponding defect patch. After completing the patching and anomaly point recovery, residual fragments that still do not form a chip array continuity relationship, dicing track adjacency relationship, equipment cavity mapping relationship or batch repetition relationship with any patched defect patch are further eliminated or have their input weight reduced in order to obtain a continuous defect patch after patching.

[0051] In this embodiment, the method reconnects broken defect segments in a chip defect image by setting a preset first accuracy rate and a second accuracy rate. During chip defect detection, issues such as cross-dices scratches and cavity airflow banded particles typically present a continuous or corresponding distribution along the same row of chips or the same cavity-mapped group of chips. When the preprocessing process excessively smooths weak response anomalies or eliminates isolated points, patches belonging to the same defect event may be cut off. By first filtering out measurement noise-like isolated points that do not correspond to the chip array position, random anomalies can be avoided from being mistakenly incorporated into the real defect patch. Then, using the array topology relationship between chips in the same row, in the same column, adjacent chips in the dices, and chips in the same cavity-mapped group as the primary basis, the broken defect segments are reconnected, restoring the cross-chip scratches, banded particles, and process offset defects that were cut off during preprocessing. After reconnection, residual segments that still do not meet the chip array continuity or batch repetition relationship are further removed, thereby obtaining a defect feature map that better matches the true spatial distribution of wafer defects, further improving the accuracy of chip defect detection.

[0052] Specifically, if the recognition accuracy of the recognition result is less than the preset first accuracy, it is initially determined that the analysis accuracy of the traceability report does not meet the requirements, and the analysis accuracy of the traceability report is determined based on the traceability success rate of the traceability report.

[0053] Please see Figure 4 The diagram shown illustrates the logical flowchart of an embodiment of the present invention for retrospectively investigating the source of defects to determine whether the source tracing analysis process should be re-executed. In this embodiment, the source tracing success rate of the source tracing report is obtained to determine whether the accuracy of the source tracing report's analysis meets the requirements. The traceability success rate of the traceability report is determined based on the ratio of the number of successful traceability attempts to the total number of traceability attempts.

[0054] Successful source tracing means that the source of the candidate defect in the source tracing report is consistent with the source of the defect confirmed by the review.

[0055] Specifically, the accuracy of the source tracing report's analysis is determined based on the success rate of the source tracing report, including: If the traceability success rate of the traceability report is greater than or equal to the preset success rate, then the accuracy of the traceability report analysis is determined to meet the requirements. If the success rate of the source tracing report is less than the preset success rate, it is determined that the accuracy of the source tracing report does not meet the requirements, and the source of the defect is investigated to determine whether to re-execute the source tracing analysis.

[0056] It is understandable that the preset success rate is a value determined by those skilled in the art based on the historical statistical distribution of the success rate of traceability reports in chip defect detection and traceability scenarios, combined with the accuracy of traceability report analysis corresponding to different success rates. The success rate of traceability reports is positively correlated with the accuracy of traceability report analysis. The preset success rate is the traceability success rate of the traceability report corresponding to the required accuracy of the analysis of the traceability report in the historical statistical distribution. When the traceability success rate of the traceability report is greater than or equal to this value, it means that a stable correspondence can be formed between the candidate defect source in the traceability report and the results of manual review, equipment alarm records, slot-level process parameter fluctuation records, or the repeated distribution of defects in the same batch of wafers. The traceability report can accurately point to the target process, target equipment, target cavity, target slot, or target slot group. Therefore, it is determined that the analysis accuracy of the traceability report meets the requirements. When the traceability success rate of the traceability report is less than this value, it indicates that the correspondence between continuous defect patches and production process records is unstable. There may be situations where the same continuous defect event is mapped to multiple inconsistent candidate process nodes, the source of candidate defects cannot be supported by the fluctuation records of process parameters at the slot level, or random isolated anomalies are mistakenly included in the traceability judgment. This makes it difficult for the traceability report to accurately determine the true source of defects. Therefore, the analysis accuracy of the traceability report is determined to be unsatisfactory, and the defect source is checked back to determine whether the traceability analysis should be re-executed.

[0057] The specific value of the preset success rate can be set according to the verification base of chip defect sources, the spatial stability of continuous defect patches, and the requirements of those skilled in the art for the accuracy of source tracing report analysis, and will not be elaborated here.

[0058] Specifically, the chip defect source verification base is the number of reference data used to verify whether the traceability report is successful. It can be determined by the number of manual review results, equipment alarm records, slot-level process parameter fluctuation records, records of repeated defect distribution in the same batch of wafers, and subsequent re-inspection results.

[0059] Specifically, the spatial stability of continuous defect patches refers to the degree of consistency among the continuous defect patches obtained after patching in terms of morphology, main extension direction, wafer region location, cross-chip distribution range, and failure chip location. It is used to determine whether the current continuous defect patches can serve as a stable source tracing input.

[0060] Specifically, the process of retracing the source of defects to determine whether to re-execute the source analysis involves taking the continuous defect patches obtained after patching as input, retracing the source of defects according to the production process records at the slot level, adjusting the patching and isolated point removal conditions, and re-executing the source analysis after adjustment.

[0061] Specifically, determining whether to re-perform the source tracing analysis includes: If the continuous defect patches after the patching can form a stable correspondence with the slot-level production process record, and the traceability report can clearly point to the target process, equipment, cavity or slot, then it is not necessary to re-execute the traceability analysis. If the traceability report cannot consistently point to the target process, equipment, cavity, or slot, and the failure is due to defect patch breakage, random isolated point entry, excessive patch merging, or real isolated point being mistakenly removed, the traceability analysis needs to be re-executed.

[0062] Specifically, the process of tracing the source of defects to determine whether to re-perform source tracing analysis includes: The continuous defect patch obtained after patching is obtained. The continuous defect patch is a defect patch formed by patching broken defect segments in the chip defect image, filtering out noise isolated points, and removing residual segments a second time. The continuous defect patch retains the defect morphology type, wafer location, main extension direction, number of chips spanned, location of failed chips, defect density, and wafer area distribution information. Source tracing features are extracted based on the continuous defect patches. The source tracing features include the linear, band-like, cluster-like, edge-continuous, or locally diffused morphology of the continuous defect patches, the radial position, angular position, edge distance, main extension direction, cross-chip distribution range, corresponding chip row and column numbers, and the distribution of failed chips on the wafer. Retrieve the production process records of the batch of wafers corresponding to the continuous defect patches. The production process records include process name, equipment number, cavity number, formula number, processing time, wafer processing sequence, slot number, slot group number, and slot-level process parameter fluctuation records. Among them, the slot-level process parameter fluctuation records include temperature changes, airflow changes, liquid flow state, pressure changes, deposition rate, etching rate, cleaning status, mechanical clamping position, and equipment alarm information corresponding to the same slot or the same slot group. The traceability characteristics of the continuous defect patches are compared with the slot-level production process records to determine whether the continuous defect patches correspond to the target process, target equipment, target cavity, target slot, or target slot group. Among them, if the continuous defect patches are concentrated in the wafer corresponding to the same slot or the same slot group, and their morphology, main extension direction, or wafer area distribution matches the fluctuation of the corresponding slot-level process parameters, the corresponding process, equipment, cavity, slot, or slot group is identified as a candidate defect source. Candidate defect sources are ranked according to the degree of correspondence between candidate defect sources and continuous defect patches. The degree of correspondence is determined based on the recurrence of continuous defect patches in the same slot or the same slot group, the consistency between continuous defect patches and the fluctuation of slot-level process parameters, the consistency between continuous defect patches and equipment alarm records, and the consistency between continuous defect patches and the defect distribution of wafers in the same batch. If the candidate defect source can stably point to the target process, target equipment, target cavity, target slot or target slot group, and the candidate defect source corresponds to at least one of the verification criteria such as manual review results, equipment alarm records, slot-level process parameter fluctuation records or the distribution of repeated defects in the same batch of wafers, the current source tracing analysis is determined to be valid and the source tracing analysis is not re-executed. If the candidate defect source cannot stably point to the target process, target equipment, target cavity, target slot or target slot group, or if the same continuous defect patch is mapped to multiple inconsistent candidate defect sources, the current source tracing analysis is determined to be unsatisfactory, and the supplementary connection and isolated point removal conditions of the second layer are adjusted according to the source tracing failure type feedback.

[0063] When the same defect event is split into multiple candidate defect sources, it is determined that the reinforcement of broken defect segments is insufficient, and the reinforcement conditions under the relationship of adjacent chips in the same row, in the same column, or in the dicing channel are relaxed; when multiple random isolated points are mistakenly assigned to the same candidate defect source, it is determined that the removal of isolated points is insufficient, and the conditions for isolated points to participate in reinforcement are tightened; when a continuous defect patch crosses multiple chip regions that do not have a slot correspondence and causes a conflict of candidate defect sources, it is determined that the reinforcement is excessive, and the reinforcement range of the same group of chips in the cavity mapping is narrowed; when an abnormal point marked as a noise isolated point falls into the defect path of a stable slot group, the corresponding abnormal point is restored from the noise isolated point set and re-included in the continuous defect patch; Based on the feedback-adjusted patching and isolated point removal conditions, the broken defect segments in the chip defect image are patched again to generate an updated continuous defect patch. The traceability features are then extracted again based on the updated continuous defect patch and compared with the slot-level production process records to generate a new traceability report.

[0064] In this embodiment, the method sets a preset success rate to determine whether to re-execute the source tracing analysis by checking the defect source. During chip manufacturing, different slots in the same process and equipment cavity may be affected by temperature gradients, airflow distribution, etc., causing different edge chipping and particle banding distributions to form on different slots of the same batch of wafers. This can cause continuous scratches or bridging defects that originally belong to the same defect event to be identified as multiple scattered clusters, resulting in the source tracing model incorrectly mapping the same defect event to multiple process nodes. By using the continuous defect patch as the source tracing input, the continuous spatial information such as the morphology of the defect can be preserved. Then, the continuous defect patch is compared with the slot record and slot-level process parameter fluctuation record of the corresponding batch of wafers to determine the candidate process source corresponding to the repeated continuous defect patch. When the source tracing fails, the second-layer reinforcement distance condition, isolated point participation reinforcement condition, or cavity mapping of the same group of chips is adjusted according to the source tracing failure type feedback, and the continuous defect patch is regenerated for source tracing analysis, which further improves the source tracing accuracy of chip defect detection.

[0065] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of the present invention.

Claims

1. A method for tracing the source of chip defects through online detection based on big data, characterized in that, include: Acquire chip images from several processing flow outputs, preprocess the chip images to obtain chip defect images, extract features from the chip defect images to obtain chip defect features, and determine whether the effectiveness of chip defect feature extraction meets the requirements based on the coverage of chip defect features. A machine learning model is constructed based on the chip defect features, and the chip images at the output of the several processing steps are identified according to the machine learning model to obtain the identification results, so as to determine the location of the chip with defects, and to determine whether to repair the broken defect segments in the chip defect image according to the identification accuracy of the identification results. A traceability report is generated based on the identification results, and defective chips are located and removed according to the traceability report. The source of the defect is then checked back based on the traceability success rate of the traceability report to determine whether to re-execute the traceability analysis. Chip defect images include wafer surface images, chip cell area images, and defect candidate area images; Chip defect characteristics include defect location characteristics, chip array location characteristics, and process parameter correlation characteristics; Determine whether it is necessary to repair broken defect segments in the chip defect image, including: If the recognition accuracy of the recognition result is greater than or equal to a preset first accuracy and less than a preset second accuracy, then it is determined that the broken defect segments in the chip defect image need to be repaired. If the recognition accuracy of the recognition result is less than the preset first accuracy, then it is determined that it is not necessary to repair the broken defect segments in the chip defect image. The process of repairing broken defect segments in chip defect images involves filtering out noise isolated points that do not participate in the repair based on the chip array positional relationship, repairing broken defect segments that conform to the chip array continuity relationship, and then removing residual segments a second time after repair.

2. The method for tracing the source of chip defects based on big data online detection according to claim 1, characterized in that, The coverage of chip defect features determines whether the effectiveness of chip defect feature extraction meets the requirements, including: If the coverage of chip defect features is greater than or equal to the preset coverage, then the effectiveness of chip defect feature extraction is determined to meet the requirements. If the coverage of the chip defect features is less than the preset coverage, then the effectiveness of the chip defect feature extraction is determined to be unsatisfactory.

3. The method for tracing the source of chip defects based on big data online detection according to claim 2, characterized in that, If the effectiveness of chip defect feature extraction does not meet the requirements, it is initially determined that the analytical capability of the machine learning model does not meet the requirements, and the analytical capability of the machine learning model is determined based on the recognition accuracy of the recognition results.

4. The method for tracing the source of chip defects based on big data online detection according to claim 3, characterized in that, The accuracy of the recognition results determines whether the analytical capability of the machine learning model meets the requirements, including: If the recognition accuracy of the recognition result is greater than or equal to the preset second accuracy, then the analytical capability of the machine learning model is determined to meet the requirements. If the recognition accuracy of the recognition result is less than the preset second accuracy, then it is determined that the analytical capability of the machine learning model does not meet the requirements.

5. The method for tracing the source of chip defects based on big data online detection according to claim 4, characterized in that, If the recognition accuracy of the recognition result is less than the preset first accuracy, it is initially determined that the analysis accuracy of the traceability report does not meet the requirements, and the analysis accuracy of the traceability report is determined based on the traceability success rate of the traceability report.

6. The method for tracing the source of chip defects based on big data online detection according to claim 5, characterized in that, The success rate of the source tracing report is used to determine whether the accuracy of the source tracing report's analysis meets the requirements, including: If the traceability success rate of the traceability report is greater than or equal to the preset success rate, then the accuracy of the traceability report analysis is determined to meet the requirements. If the success rate of the source tracing report is less than the preset success rate, it is determined that the accuracy of the source tracing report does not meet the requirements, and the source of the defect is investigated to determine whether to re-execute the source tracing analysis.

7. The method for tracing the source of chip defects based on big data online detection according to claim 6, characterized in that, The traceability success rate of the traceability report is determined based on the ratio of the number of successful traceability attempts to the total number of traceability attempts.

8. The method for tracing the source of chip defects based on big data online detection according to claim 7, characterized in that, The process of re-checking the source of defects to determine whether to re-execute the source analysis involves taking the continuous defect patches obtained after patching as input, checking the source of defects according to the production process records at the tank level, adjusting the patching and isolated point removal conditions, and re-executing the source analysis after adjustment.

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