Data compensation method and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a data compensation method and a display panel, which comprises the following steps: a timing controller determines at least one compensation node in a vertical blanking area of a current frame according to a preset row interval, and sends a step pulse to a gamma chip at a corresponding moment of each compensation node; the gamma chip accumulates a step value corresponding to a number of the step pulse on the basis of a reference gamma value, generates a corresponding compensation gamma voltage, and outputs the compensation gamma voltage to a source driving circuit according to the number of the step pulse; and the source driving circuit compensates a data voltage of a next frame according to the last received compensation gamma voltage. The application solves the top partial screen problem caused by data transmission delay in the related art through the cooperative work of the fixed row interval triggered compensation node and the single-pulse step transmission mode, and realizes accurate compensation under different refresh rates.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a data compensation method and a display panel. Background Technology

[0002] LCD displays use progressive scan driving, and thin-film transistors (TFTs) experience leakage current when off. The lower the refresh rate, the longer the pixel voltage is held, resulting in more leakage current. This causes the brightness of a low refresh rate image to be lower than that of a high refresh rate image at the same grayscale, and flickering occurs when the refresh rate dynamically switches.

[0003] To compensate for this brightness difference, related technologies propose a vertical blanking region gamma compensation method, which involves setting up multiple compensation nodes in the vertical blanking region. At each node, the timing controller sends 16-bit complete register data to the programmable gamma chip via the I²C bus, gradually increasing the gamma voltage.

[0004] However, the I²C bus takes a long time to transmit 16 bits of data. When the compensation node is too close to the start signal of the next frame, the compensation gamma voltage cannot be transmitted within the blanking zone, causing the gamma voltage to switch during the display of the image, resulting in a horizontal brightness dividing line at the top of the frame, i.e., a top split screen defect.

[0005] Therefore, how to improve the top screen defect caused by the compensation for gamma voltage transmission delay in related technologies is an urgent problem to be solved. Summary of the Invention

[0006] This application provides a data compensation method and a display panel. By using the coordinated operation of a compensation node triggered at a fixed row interval and a single-pulse step transmission method, this application solves the top screen splitting problem caused by data transmission delay in related technologies and achieves accurate compensation at different refresh rates.

[0007] In a first aspect, this application provides a data compensation method applied to a display panel, the display panel including a timing controller, a gamma chip, and a source drive circuit. The data compensation method includes: the timing controller determining at least one compensation node in the vertical blanking region of the current frame according to a preset row number interval, and sending step pulses to the gamma chip at the corresponding time of each compensation node; the gamma chip accumulating a corresponding number of step values ​​based on a reference gamma value according to the number of step pulses, generating a corresponding compensation gamma voltage and outputting it to the source drive circuit; and the source drive circuit compensating the data voltage of the next frame according to the last received compensation gamma voltage.

[0008] Optionally, the gamma chip includes a control unit, a memory, and a register; before sending a step pulse to the gamma chip at the corresponding time of each compensation node, the data compensation method further includes: the timing controller sending a reset pulse to the gamma chip within the vertical blanking region; wherein the reset pulse has a first pulse width, the step pulse has a second pulse width, and the first pulse width is different from the second pulse width; the control unit performs pulse width detection on the received current pulse, and when the current pulse is detected to be the first pulse width, controls the reference gamma value stored in the memory to be written into the register to reset the gamma voltage value stored in the register.

[0009] Optionally, the gamma chip accumulates a corresponding number of step values ​​based on the reference gamma value according to the number of step pulses, generates a corresponding compensation gamma voltage, and outputs it to the source drive circuit. This includes: when the control unit detects that the current pulse is the second pulse width, generating a step instruction and sending it to the register; the register accumulates a fixed step voltage on the currently stored gamma voltage value according to the received step instruction to obtain a corresponding compensation gamma voltage, and sends the compensation gamma voltage to the source drive circuit.

[0010] Optionally, the register accumulates a fixed step voltage on the currently stored gamma voltage value according to the received step instruction to obtain a corresponding compensated gamma voltage, and sends the compensated gamma voltage to the source drive circuit, including: in the vertical blanking region of the current frame, when the register receives the first step instruction, the register adds a fixed step voltage to the currently stored reference gamma value to generate a first compensated gamma voltage, and outputs the first compensated gamma voltage to the source drive circuit; when the register receives a second step instruction after receiving the first step instruction, the register adds another fixed step voltage to the currently stored first compensated gamma voltage to generate a second compensated gamma voltage, and outputs the second compensated gamma voltage to the source drive circuit.

[0011] Optionally, the register is a 16-bit register used to store a 16-bit binary gamma voltage value; the fixed step voltage corresponds to the voltage increment generated by adding 1 to the least significant bit of the 16-bit binary gamma voltage value.

[0012] Optionally, the source drive circuit compensates the data voltage of the next frame based on the last received compensation gamma voltage, including: within the vertical blanking region of the current frame, the source drive circuit updates the locally stored gamma voltage value with the currently received compensation gamma voltage each time it receives a compensation gamma voltage; when the vertical blanking region of the current frame ends, the timing controller generates a frame start signal for the next frame; in response to the frame start signal, the source drive circuit determines the locally stored gamma voltage value as the last received compensation gamma voltage; the source drive circuit uses the last received compensation gamma voltage as a reference voltage to perform digital-to-analog conversion on the image data of the next frame to generate the corresponding data voltage.

[0013] Optionally, the timing controller includes a clock counter. The timing controller determines at least one compensation node within the vertical blanking region of the current frame according to a preset row number interval, and sends a step pulse to the gamma chip at the corresponding time of each compensation node. This includes: at the beginning of the vertical blanking region of the current frame, the clock counter accumulates the row scan clock within the vertical blanking region; when the current count value of the clock counter reaches the preset row number interval, the timing controller determines the current time as a compensation node and sends a step pulse to the gamma chip at the current time; after sending the step pulse, the timing controller resets the clock counter to zero and restarts the accumulation count to determine the next compensation node; when the vertical blanking region ends, the timing controller resets the clock counter to zero again.

[0014] Secondly, this application provides a display panel, including a display area and a non-display area. The display area includes multiple pixel units arranged in an array and multiple data lines. The non-display area includes: a timing controller, configured to determine at least one compensation node in the vertical blanking region of the current frame according to a preset row number interval, and send a step pulse at the corresponding time of each compensation node; a gamma chip, connected to the timing controller, configured to accumulate a corresponding number of step values ​​on the basis of a reference gamma value according to the number of step pulses, and generate a corresponding compensation gamma voltage; and a source drive circuit, connected to the gamma chip and the multiple data lines, configured to compensate the data voltage of the next frame according to the last received compensation gamma voltage, and send the compensated data voltage to the data lines.

[0015] Optionally, the timing controller is connected to the gamma chip via a TTL signal line.

[0016] Optionally, the gamma chip includes: a control unit connected to the timing controller, configured to perform pulse width detection on the received pulse, output a reset command when the detected pulse is a first pulse width, and output a step command when the detected pulse is a second pulse width; a memory connected to the control unit, configured to store the reference gamma value and output the reference gamma value in response to the reset command; and a register connected to the control unit, the memory, and the source drive circuit, configured to write the received reference gamma value to reset the current stored voltage in response to the reset command, and to accumulate a fixed step voltage on the currently stored gamma voltage value in response to the step command to obtain a corresponding compensated gamma voltage, and send the compensated gamma voltage to the source drive circuit.

[0017] The technical solution provided in this application has at least the following beneficial effects:

[0018] (1) This application triggers compensation nodes and sends step pulses within the vertical blanking zone at fixed row intervals using a timing controller. This allows the number of compensation nodes to automatically adapt to the actual length of the blanking zone. The longer the blanking zone, the more step pulses are sent, and the shorter the blanking zone, the fewer step pulses are sent, thus making the compensation amplitude proportional to the leakage time. Therefore, this application does not require the timing controller to know the refresh rate or the total number of rows in the blanking zone in advance to achieve a precise match between the compensation intensity and the leakage time, avoiding insufficient or over-compensation caused by inaccurate node prediction.

[0019] (2) The gamma chip in this application accumulates a fixed step value sequentially based on the number of step pulses. Each time a pulse is received, the compensation voltage is increased by one level. No data content needs to be transmitted; the final compensation value can be determined solely by the number of pulses. Compared to the traditional I²C bus, which requires several microseconds or even longer to transmit 16-bit complete data, the width of one step pulse in this application only requires one line of scanning time or less, and there is no need to wait for the serial transmission to complete. Therefore, the transmission and response of the pulse are completed in a very short time. Even if the compensation node is close to the frame start signal, all accumulation can be completed before the effective display area begins, thereby avoiding the gamma voltage switching caused by transmission delay from intruding into the display area and eliminating the top split screen problem.

[0020] (3) This application uses the last received compensation voltage to compensate the next frame after the blanking region ends by using the source drive circuit, ensuring that the whole frame uses the same stable reference voltage, thus eliminating the possibility of brightness boundary lines appearing in the same frame. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0022] Figure 1 The diagram shown is a schematic representation of the duration of the vertical blanking region under different refresh modes provided in an embodiment of this application.

[0023] Figure 2 The diagram shows a compensation architecture in related technologies.

[0024] Figure 3 The diagram shows the equidistant stepping of multiple compensation nodes in related technologies.

[0025] Figure 4 The diagram shown is a flowchart of a data compensation method provided in an embodiment of this application.

[0026] Figure 5 As shown Figure 4 An exemplary process diagram of step S100.

[0027] Figure 6 The diagram shown is a structural schematic of a display panel provided in an embodiment of this application.

[0028] Figure 7 The diagram shown is a timing logic diagram provided in an embodiment of this application.

[0029] Figure 8 As shown Figure 4 An exemplary process diagram of step S200.

[0030] Figure 9 As shown Figure 4 An exemplary process diagram of step S300.

[0031] Explanation of reference numerals in the attached figures: 110. Timing controller; 120. Gamma chip; 130. Source drive circuit; 121. Control unit; 122. Memory; 123. Register. Detailed Implementation

[0032] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0033] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0034] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0035] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) employ a progressive scan driving method. When the gate drive signal for the Nth row is high, all TFTs in that row are turned on, and the source data lines in the column direction can write grayscale voltages to the corresponding pixel electrodes. When the gate drive signal for the Nth row is low, all TFTs in that row are turned off, and the pixel electrodes maintain their voltage using liquid crystal capacitors and storage capacitors until the next frame is refreshed.

[0036] In practical circuits, TFTs are not ideal switches and experience off-state leakage current during the off period. The pixel voltage needs to be held for a certain time between the completion of a data update and the next data update; the length of this holding time directly determines the amount of leakage current. A higher refresh rate results in a shorter time interval between two adjacent data updates and less leakage current; a lower refresh rate results in a longer holding time and more leakage current.

[0037] Taking a display panel with a resolution of 1920×1080 (Full HD, FHD) and a maximum refresh rate of 240Hz as an example, in order to ensure that the charging time of each row of pixels is consistent at different refresh rates, the timing controller (TCON) will dynamically adjust the total number of vertical rows (V total): In low refresh rate mode (48Hz): as shown in the attached image. Figure 1 As shown in 1a, to extend the total time per frame, the vertical blanking area is significantly lengthened to 4470 lines, while the effective display area remains at 1080 lines. This results in a longer pixel voltage holding time and a significant increase in leakage current.

[0038] In high refresh rate mode (240Hz): as shown in the attached image. Figure 1 As shown in 2a, the active area remains 1080 lines, while the vertical blanking area (V-blanking) contains only 30 lines. This results in a short charging cycle per line, fast frame refresh, and minimal impact from leakage.

[0039] Therefore, for the same grayscale voltage, the actual pixel voltage at a high refresh rate is higher than that at a low refresh rate, resulting in a higher display brightness at a high refresh rate and noticeable flickering when the refresh rate is dynamically switched.

[0040] To address the aforementioned problems, the inventors of this application propose a vertical blanking region gamma compensation algorithm (V-blanking Gamma Compensation, VGC). The core idea of ​​this algorithm is attached. Figure 2 As shown: The system on chip (SOC) sends a high / low level signal to the TCON to indicate the current refresh rate change. After the TCON automatically detects the change, it sets multiple compensation nodes in the vertical blanking area of ​​each frame.

[0041] It's important to note that the compensation node here isn't a specific row or column of pixels on the screen, but rather a trigger point on the timeline. Specifically, the TCON counts the line scan clock within the vertical blanking area. When the count reaches a preset number of lines (e.g., 1000 lines, 2000 lines, etc.), it's considered to have reached a node. At each node, the TCON sends different data to the programmable gamma IC (P-gamma IC) via the I²C bus (Inter-Integrated Circuit Bus) to dynamically change the gamma voltage or common electrode voltage (VCOM), thereby compensating for brightness attenuation caused by leakage current at low refresh rates.

[0042] The purpose of setting multiple compensation nodes here is that, because the monitor's refresh rate changes dynamically (e.g., supporting FreeSync or VRR technology), the length of the vertical blanking region for each frame cannot be predicted in advance. For example, in 240Hz mode, the vertical blanking region is only 30 lines, leaving almost no compensation time; while in 48Hz mode, the vertical blanking region is as long as 4470 lines, providing ample time for multi-level compensation. Therefore, the VGC algorithm adopts a strategy of setting nodes at preset line intervals: after the TCON enters the vertical blanking region, it counts the number of lines and triggers a node every fixed number of lines (e.g., every 1000 lines), increasing the gamma voltage by one level. In this way, the number of compensations automatically adapts to the length of the vertical blanking region: the longer the blanking region, the more nodes are triggered, and the greater the compensation magnitude; when the blanking region is extremely short, no nodes may be triggered, and no compensation is performed. This adaptive mechanism does not require the TCON to know the refresh rate of the current frame in advance; it is entirely determined by the actual number of lines in the blanking region.

[0043] Furthermore, as shown in the appendix Figure 3 As shown, the compensation details of the VGC algorithm proposed by the inventors of this application typically employ an equal-interval stepping method: assuming the initial gamma value is A (the uncompensated reference value), the gamma value becomes A+X after the first node N1 is triggered, A+2X after the second node N2 is triggered, and so on. Here, X is typically taken as the minimum adjustable level of the gamma chip to ensure the precision of voltage adjustment. For example, if the initial binary value of the gamma register is 00000101, then with each triggered node, the register value increments by 1, successively becoming 00000110, 00000111, 00001000, etc. That is, with each additional triggered node, the gamma voltage increases by one minimum step level.

[0044] However, further analysis by the inventors of this application revealed a key flaw in the VGC algorithm in practical applications: the TCON sends instructions to the gamma chip via the I²C bus, and the entire process, from transmission to response (typically on the order of microseconds), requires a certain amount of transmission and response time. If a compensation node (especially the last node) is set too close to the start of frame signal (STV) of the next frame, the I²C instruction may not be able to complete transmission and take effect within the current vertical blanking area, but will instead be delayed until the active area of ​​the next frame. In this case, the gamma voltage switching occurs precisely during screen display, leading to a top split-screen problem.

[0045] For example, taking a 240Hz FHD resolution product as an example: In 240Hz mode, the total number of vertical lines is 1110, and the number of vertical blanking lines is 1110. 1080 = 30 lines. In 48Hz mode, the total number of vertical lines expands to 5550, and the number of vertical blanking lines is 5550. 1080 = 4470 rows.

[0046] Assuming the VGC algorithm sets nodes at intervals of 1000 lines, in 48Hz mode, the vertical blanking region will sequentially trigger four nodes: lines 1000, 2000, 3000, and 4000, with the gamma value gradually increasing by four levels from the initial value. It's worth noting that these node positions correspond to different theoretical time frequencies (assuming a scan time of 4 microseconds per line): the blanking region frequency corresponding to the line 1000 node is approximately 1 / (4μs×2080)≈120Hz; the line 2000 node corresponds to approximately 81Hz; the line 3000 node corresponds to approximately 61Hz; and the line 4000 node corresponds to approximately 48Hz. These frequency points happen to be intermediate states during the dynamic refresh rate switching process. In 48Hz mode, the last node (line 4000) is only 470 lines (approximately 1.88 milliseconds) away from the STV signal, making the timing extremely tight.

[0047] If TCON sends a complete 16-bit register data (e.g., from 00000111 to 00001000) via the I²C bus at this time, due to the limited I²C transmission rate (typically 100kbps~400kbps), the instruction will take several microseconds or even longer to complete transmission and take effect. If the STV signal arrives before the instruction completes, the effective display area of ​​the next frame has already begun scanning. At this time, the gamma voltage has not yet completed switching, and the first few rows of pixels can only use the old gamma value (e.g., 00000111). Only after the I²C instruction finally takes effect will the gamma voltage suddenly jump to the new value (00001000), and subsequent rows will use the new gamma value. After the STV signal arrives, data transmission still occurs on the I²C bus data line (SDA), which means that the gamma voltage update has already intruded into the effective display area. Specifically, in terms of image display, in the top area of ​​the screen, some pixel rows use the old gamma value (Gamma A, lower brightness), while other pixel rows use the new gamma value (Gamma B, normal brightness). The boundary between these two uses a horizontal brightness dividing line that is clearly perceptible to the human eye, resulting in a top-screen split or top-screen flickering phenomenon. This problem is particularly pronounced in applications with high resolution, high refresh rates, and densely distributed pixels, severely impacting display quality.

[0048] Therefore, in order to improve the top-screening problem caused by I²C bus transmission delay in the above VGC algorithm, this application provides a data compensation method, specifically including the following embodiments: Figure 4 The diagram shown is a flowchart illustrating a data compensation method provided in an embodiment of this application; as follows: Figure 4As shown, the data compensation method of this embodiment is applied to a display panel including a timing controller, a gamma chip, and a source drive circuit, and includes the following steps: Step S100: The timing controller determines at least one compensation node in the vertical blanking region of the current frame according to a preset row number interval, and sends a step pulse to the gamma chip at the corresponding time of each compensation node.

[0049] It's important to note that in an LCD panel, a single frame of image consists of an active area and a vertical blanking area (V-blanking). The active area is used to write image data line by line, while the V-blanking area is the idle period between the end of one frame and the beginning of the next, during which no new image data is written. To ensure consistent pixel charging time across different refresh rates, the timing controller dynamically adjusts the length of the V-blanking area based on the refresh rate. For example, in a 240Hz high refresh rate mode, the V-blanking area has only 30 lines; while in a 48Hz low refresh rate mode, it can be as long as 4470 lines.

[0050] In this embodiment, the timing controller determines compensation nodes in the vertical blanking region according to a fixed and preset row number interval (e.g., every 1000 rows), and immediately sends a step pulse to the gamma chip at the corresponding time of each compensation node; in addition, if the preset row number interval is not met at the end of the vertical blanking region, no compensation node is generated.

[0051] It is worth noting that the compensation nodes in this embodiment do not correspond to a specific row of pixels on the screen, but rather to time points within the vertical blanking region, triggered by a count reaching a preset threshold. The step pulse in this embodiment is an electrical pulse signal, such as a high-level pulse signal. The number of compensation nodes in this embodiment automatically adapts to the blanking region length; that is, the longer the blanking region, the more compensation nodes are needed, and the more step pulses are sent. When the blanking region is extremely short, such as 30 rows, there may be no compensation nodes, and therefore no step pulses are sent. Therefore, this embodiment triggers step pulses at fixed row intervals, eliminating the need for the timing controller to know the refresh rate or total blanking region length of the current frame in advance, and automatically matches the leakage current level at different refresh rates.

[0052] Step S200: The gamma chip accumulates the corresponding number of step values ​​based on the reference gamma value according to the number of step pulses, generates the corresponding compensation gamma voltage, and outputs it to the source drive circuit.

[0053] It's important to note that the gamma chip internally stores a reference gamma value, which is the initial gamma voltage before compensation, corresponding to the standard brightness at a normal refresh rate. Additionally, the gamma chip contains a register to store the current gamma voltage value. Before the start of each frame, this register is set to the reference gamma value. When the gamma chip receives a step pulse from the timing controller, it increments the current register value by a fixed step voltage. After the accumulation operation is complete, the value stored in the register becomes the new compensated gamma voltage, which the gamma chip outputs to the source driver circuit.

[0054] For example, in 48Hz mode, four step pulses are generated sequentially in the vertical blanking region: (1) Upon receiving the first step pulse: the register value increases from the reference value A to A+X, and the first compensated gamma voltage is output; (2) Upon receiving the second step pulse: the register value increases from A+X to A+2X, and the second compensated gamma voltage is output; (3) Upon receiving the third step pulse: the register value increases to A+3X, and the third compensated gamma voltage is output; (4) Upon receiving the fourth step pulse: the register value increases to A+4X, and the fourth (final) compensated gamma voltage is output.

[0055] It is worth noting that the number of step pulses in this embodiment directly determines the number of accumulations, and thus also determines the magnitude of the final compensation voltage. The fixed step value in this embodiment is a preset voltage increment that matches the leakage current accumulation over time. In addition, the result after each accumulation is immediately output to the source drive circuit so that the source drive circuit can continuously track the latest compensation voltage.

[0056] Step S300: The source drive circuit compensates the data voltage of the next frame based on the compensation gamma voltage received last time.

[0057] It should be noted that within the vertical blanking region, the gamma chip sends a compensation gamma voltage to the source drive circuit after each accumulation. Therefore, the source drive circuit may receive multiple compensation gamma voltages during the blanking period, but the last compensation gamma voltage to arrive is the target voltage that is actually needed to compensate for the next frame.

[0058] Furthermore, after the vertical blanking period ends and before the start of the next frame's effective display area, the source driver circuit uses the most recently received compensated gamma voltage as a reference voltage; that is, the source driver circuit ignores the intermediate compensated voltage and only uses the highest voltage that finally stabilizes. When the next frame's effective display area begins, the source driver circuit receives the grayscale values ​​of each pixel from the display controller. Using the final compensated gamma voltage as the reference voltage for digital-to-analog conversion, the source driver circuit converts each grayscale value into a corresponding analog pixel voltage and outputs it to the corresponding pixel unit via the data line. Because this reference voltage has been appropriately increased, even if a pixel maintains its voltage for a long time at a low refresh rate and experiences leakage, its final brightness can still reach the expected standard, thereby eliminating the top splitting phenomenon caused by compensation delay and ensuring the brightness consistency of the entire frame.

[0059] In summary, this application has the following technical effects: (1) This application triggers compensation nodes and sends step pulses within the vertical blanking zone at fixed row intervals using a timing controller. This allows the number of compensation nodes to automatically adapt to the actual length of the blanking zone. The longer the blanking zone, the more step pulses are sent, and the shorter the blanking zone, the fewer step pulses are sent, thus making the compensation amplitude proportional to the leakage time. Therefore, this application does not require the timing controller to know the refresh rate or the total number of rows in the blanking zone in advance to achieve a precise match between the compensation intensity and the leakage time, avoiding insufficient or over-compensation caused by inaccurate node prediction.

[0060] (2) The gamma chip in this application accumulates a fixed step value sequentially based on the number of step pulses. Each time a pulse is received, the compensation voltage is increased by one level. No data content needs to be transmitted; the final compensation value can be determined solely by the number of pulses. Compared to the traditional I²C bus, which requires several microseconds or even longer to transmit 16-bit complete data, the width of one step pulse in this application only requires one line of scanning time or less, and there is no need to wait for the serial transmission to complete. Therefore, the transmission and response of the pulse are completed in a very short time. Even if the compensation node is close to the frame start signal, all accumulation can be completed before the effective display area begins, thereby avoiding the gamma voltage switching caused by transmission delay from intruding into the display area and eliminating the top split screen problem.

[0061] (3) This application uses the last received compensation voltage to compensate the next frame after the blanking region ends by using the source drive circuit, ensuring that the whole frame uses the same stable reference voltage, thus eliminating the possibility of brightness boundary lines appearing in the same frame.

[0062] Therefore, this application solves the top-screen splitting problem caused by data transmission delay in related technologies by using the coordinated operation of fixed-row interval trigger compensation nodes and single-pulse step transmission mode, and achieves accurate compensation at different refresh rates.

[0063] Figure 5 As shown Figure 4 An exemplary process diagram of step S100; as shown Figure 5 As shown, the timing controller includes a clock counter. The timing controller determines at least one compensation node within the vertical blanking region of the current frame according to a preset line interval, and sends a step pulse to the gamma chip at the corresponding time of each compensation node. Specifically, the timing controller includes the following steps: Step S110: At the beginning of the vertical blanking region of the current frame, the clock counter accumulates the row scan clock within the vertical blanking region.

[0064] Step S120: When the current count value of the clock counter reaches the preset row interval, the timing controller determines the current moment as a compensation node and sends a step pulse to the gamma chip at the current moment.

[0065] Step S130: After sending the step pulse, the timing controller clears the clock counter to zero and restarts the accumulation count to determine the next compensation node.

[0066] Step S140: When the vertical blanking region ends, the timing controller resets the clock counter to zero again.

[0067] It should be noted that in an LCD panel, the line scan clock is the reference clock signal used in the driving circuit for line-by-line scanning. Each time a line of pixels is scanned, the line scan clock generates a pulse. The timing controller uses this clock signal to accurately count the number of lines within the vertical blanking area. Specifically: (1) After the effective display area of ​​the current frame ends, the display panel enters the vertical blanking area. At the moment the vertical blanking area begins, the timing controller starts its internal clock counter and begins to accumulate the count of the line scan clock. At this time, the counter starts from zero, and the count value is incremented by 1 for each line scan clock pulse received.

[0068] (2) The timing controller has a fixed row interval threshold pre-stored inside, such as 1000 rows. When the current count value of the clock counter reaches the preset threshold, the timing controller immediately determines the current moment as a compensation node and sends a step pulse to the gamma chip at this moment. The step pulse is sent instantaneously. After the step pulse is sent, the timing controller clears the clock counter to zero and then starts accumulating the count again to find the next compensation node.

[0069] (3) When the vertical blanking region ends, the timing controller resets the clock counter to zero again, thereby clearing the count value that may remain at the end of the vertical blanking region and is less than the preset row interval, so as to avoid the residual value interfering with the counting start point of the next frame.

[0070] Therefore, through the clock counter counting and clearing mechanism of this embodiment, the timing controller does not need to know the refresh rate of the current frame or the total number of rows in the vertical blanking region in advance. It can passively and adaptively determine the position and number of compensation nodes simply by accumulating and comparing the hardware counter. The triggering time of each compensation node is completely determined by the accumulated number of row scan clocks and is independent of the refresh rate, thereby ensuring the uniformity and predictability of node distribution under different refresh rates.

[0071] In one embodiment, before sending a step pulse to the gamma chip at the corresponding time of each compensation node, the data compensation method further includes: a timing controller sending a reset pulse to the gamma chip within the vertical blanking region; wherein the reset pulse has a first pulse width, the step pulse has a second pulse width, and the first pulse width is different from the second pulse width; the control unit performs pulse width detection on the received current pulse, and when the current pulse is detected to be the first pulse width, the control unit writes the reference gamma value stored in the memory into the register to reset the gamma voltage value stored in the register.

[0072] It should be noted that, as Figure 6 As shown, the gamma chip 120 in this embodiment integrates a control unit 121, a memory 122, and a register 123. The control unit 121 is connected to the timing controller 110 via a single TTL signal line. The memory 122 stores the uncompensated reference gamma value, and the register 123 stores the currently active gamma voltage value. The control unit 121 is responsible for pulse width detection of the received pulses. In this embodiment... Figure 1 Based on the above, the reset operation of the gamma chip 120 is further defined, specifically: (1) such as Figure 7 As shown, at the very beginning of the vertical blanking region of each frame, the timing controller 110 first sends a reset pulse to the gamma chip 120; this reset pulse has a first pulse width, for example, 2T, where T is the scan time of one line; subsequently, at each compensation node position, the timing controller 110 sends a step pulse, which has a second pulse width, for example, T; obviously, the width of the reset pulse is significantly larger than the width of the step pulse, making them easy to distinguish. Figure 7 In this context, DE represents the data enable signal, used to distinguish between the valid display area and the vertical blanking area. A high level of DE corresponds to the valid display area, and a low level of DE corresponds to the vertical blanking area. VGC represents the compensation operation pulse, which specifically includes a reset pulse and multiple step pulses.

[0073] (2) When the control unit 121 detects that the width of the current pulse is the width of the first pulse, it determines that the pulse is a reset pulse. Then the control memory 122 writes the reference gamma value stored therein into the register 123, thereby resetting the gamma voltage value stored in the register 123 to the reference gamma value, ensuring that each frame starts from the same reference gamma value for step accumulation, thus avoiding inter-frame accumulation error.

[0074] (3) When the control unit 121 detects that the width of the current pulse is the width of the second pulse, it determines that it is a step pulse. At this time, the control unit 121 generates a step instruction, so that the register 123 accumulates a fixed step voltage based on the current value.

[0075] from Figure 7 As can be seen from the timing logic, the reset pulse is located at the beginning of the vertical blanking region, followed by multiple step pulses at preset row intervals. All pulses are transmitted within the vertical blanking region, and the reset and accumulation have ended when the frame start signal arrives, thus ensuring that the effective display area of ​​the next frame can directly use the finally compensated gamma voltage. This embodiment distinguishes between reset and step commands through pulse width, eliminating the need for additional signal lines. Only a single TTL signal line is needed to transmit both types of control information simultaneously, simplifying the hardware interface while ensuring the determinism of the compensation start point for each frame.

[0076] Figure 8 As shown Figure 4 An exemplary flowchart of step S200; as shown Figure 8 As shown, the gamma chip accumulates a corresponding number of step values ​​based on the reference gamma value according to the number of step pulses, generates a corresponding compensated gamma voltage, and outputs it to the source drive circuit. Specifically, this includes the following steps: Step S210: When the control unit detects that the current pulse is the second pulse width, it generates a step instruction and sends it to the register.

[0077] Step S220: The register adds a fixed step voltage to the currently stored gamma voltage value according to the received step instruction to obtain the corresponding compensated gamma voltage, and sends the compensated gamma voltage to the source drive circuit.

[0078] Specifically, within the vertical blanking region of the current frame, when the register receives the first step instruction, the register increases the currently stored reference gamma value by a fixed step voltage to generate a first compensated gamma voltage, and outputs the first compensated gamma voltage to the source drive circuit; when the register receives a second step instruction after receiving the first step instruction, the register increases the currently stored first compensated gamma voltage by another fixed step voltage to generate a second compensated gamma voltage, and outputs the second compensated gamma voltage to the source drive circuit.

[0079] It should be noted that, as Figure 7 The timing logic shown involves the timing controller sending step pulses sequentially at preset row intervals after the reset pulse is sent. The control unit inside the gamma chip continuously detects the pulse width of the received pulses. Specifically, when the control unit detects that the width of the current pulse is the second pulse width, it identifies it as a step pulse and sends a step instruction to the register. After receiving the step instruction, the register adds a fixed step voltage to the currently stored gamma voltage value to obtain a new compensated gamma voltage, which is then output to the source drive circuit.

[0080] For example, in a 48Hz low refresh rate mode, four step pulses appear sequentially within the vertical blanking region. Before the first step pulse arrives, the voltage value in the register has been reset to the reference gamma value A. When the first step pulse is detected, the register increases the current value A by a fixed step voltage X, generating a first compensated gamma voltage A+X, which is immediately output to the source drive circuit. When the second step pulse arrives, the register adds X to the current value A+X, generating a second compensated gamma voltage A+2X, which is then output. This process continues, with the register incrementing X for each received step pulse and outputting the new value.

[0081] It should be noted that the register uses a 16-bit binary storage format to store the adjusted gamma voltage value. The fixed step voltage X corresponds to the voltage increment resulting from adding 1 to the least significant bit of this 16-bit register value. That is, each accumulation operation only changes the least significant bit of the register, while the higher-order bits remain unchanged. For example, if the current register value is 0101010100000101, adding 1 results in 0101010100000110, with only the last two bits changing and the higher-order bits completely repeating. Since each step instruction only needs to inform the gamma chip to perform the increment operation without transmitting the complete 16-bit value, the actual data transmitted per step instruction is only 1 bit, significantly reducing communication time compared to the traditional I²C bus transmission of 16-bit data. This embodiment controls the number of accumulations by the number of step pulses, achieving fine voltage adjustment by successively incrementing the least significant bit of the 16-bit register, ensuring compensation accuracy while avoiding the delay caused by transmitting complete data.

[0082] Figure 9 As shown Figure 4 An exemplary process diagram of step S300; as shown Figure 9 As shown, the source drive circuit compensates the data voltage of the next frame based on the compensation gamma voltage received last time, specifically including the following steps: Step S310: In the vertical blanking region of the current frame, the source drive circuit updates the locally stored gamma voltage value with the currently received compensation gamma voltage each time it receives a compensation gamma voltage.

[0083] Step S320: When the vertical blanking region of the current frame ends, the timing controller generates the frame start signal for the next frame.

[0084] Step S330: In response to the frame start signal, the source drive circuit determines the locally stored gamma voltage value as the last received compensated gamma voltage.

[0085] Step S340: The source drive circuit uses the last received compensation gamma voltage as a reference voltage to perform digital-to-analog conversion on the image data of the next frame, generating the corresponding data voltage.

[0086] It should be noted that within the vertical blanking region, the gamma chip sends a compensation gamma voltage to the source driver circuit after each accumulation. Since the number of step pulses varies at different refresh rates, the source driver circuit may receive one, two, or more compensation gamma voltages within the blanking region, and these voltage values ​​increase sequentially. The source driver circuit has an internal local buffer to temporarily store the most recently received compensation gamma voltage. Whenever a compensation gamma voltage is received from the gamma chip, the source driver circuit updates the gamma voltage value stored in the local buffer with that voltage value. In other words, the local buffer always stores the most recently received voltage value, while previous voltage values ​​are overwritten.

[0087] Furthermore, when the vertical blanking region ends, the timing controller generates a frame start signal for the next frame. Upon detecting this signal, the source drive circuit locks the voltage value currently stored in the local buffer and confirms it as the last received compensated gamma voltage. Since all step pulses have been transmitted within the blanking region, the voltage value stored in the local buffer is now the final value after complete accumulation, such as A+4X in 48Hz mode.

[0088] Subsequently, the source driver circuit uses this final voltage value as the reference voltage for digital-to-analog conversion. When the next frame of image data arrives, the source driver circuit uses this reference voltage to convert each grayscale value into the corresponding analog pixel voltage and outputs it to each pixel unit of the display panel via the data line. Since the reference voltage remains constant throughout the entire effective display area, all pixel rows undergo digital-to-analog conversion based on the same reference, resulting in consistent brightness across the entire frame. This embodiment, through continuous updating within the blanking region and frame start signal-triggered latching, eliminates the need for the source driver circuit to actively determine which is the last time; it accurately obtains the final compensation voltage solely based on timing relationships, achieving simplicity and reliability.

[0089] This application provides a display panel, specifically including the following embodiments: Figure 6 The diagram shown is a structural schematic of a display panel provided in an embodiment of this application; as follows: Figure 6 As shown, the display panel of this embodiment includes a display area and a non-display area. The display area includes multiple pixel units arranged in an array and multiple data lines. The non-display area includes a timing controller 110, a gamma chip 120 and a source drive circuit 130.

[0090] Specifically, the timing controller 110 is used to determine at least one compensation node in the vertical blanking region of the current frame according to a preset line interval, and send a step pulse at the corresponding time of each compensation node; the gamma chip 120 is connected to the timing controller 110 and is used to accumulate the corresponding number of step values ​​on the basis of the reference gamma value according to the number of step pulses to generate a corresponding compensation gamma voltage; the source drive circuit 130 is connected to the gamma chip 120 and multiple data lines and is used to compensate the data voltage of the next frame according to the compensation gamma voltage received last time, and send the compensated data voltage to the data lines.

[0091] In one embodiment, the timing controller 110 is connected to the gamma chip 120 via a TTL signal line.

[0092] In one embodiment, such as Figure 6 As shown, the gamma chip 120 includes a control unit 121, a memory 122, and a register 123. Specifically, the control unit 121 is connected to the timing controller 110 and is used to detect the pulse width of the received pulse. When the detected pulse width is the first pulse width, a reset command is output, and when the detected pulse width is the second pulse width, a step command is output. The memory 122 is connected to the control unit 121 and is used to store the reference gamma value and output the reference gamma value in response to the reset command. The register 123 is connected to the control unit 121, the memory 122, and the source drive circuit 130, respectively. In response to the reset command, the received reference gamma value is written to reset the current stored voltage, and in response to the step command, a fixed step voltage is added to the currently stored gamma voltage value to obtain the corresponding compensated gamma voltage, and the compensated gamma voltage is sent to the source drive circuit 130.

[0093] It should be noted that the working principle of the timing controller 110, the gamma chip 120 and the source drive circuit 130 in this embodiment is the same as the working principle of the data compensation method described above, and will not be repeated here.

[0094] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0095] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0096] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A data compensation method, characterized in that, Applied to a display panel, the display panel includes a timing controller, a gamma chip, and a source drive circuit, wherein the timing controller includes a clock counter, and the data compensation method includes: The timing controller determines at least one compensation node within the vertical blanking region of the current frame according to a preset row number interval, and sends a step pulse to the gamma chip at the corresponding time of each compensation node. Specifically, this includes: at the beginning of the vertical blanking region of the current frame, the clock counter accumulates the row scan clock within the vertical blanking region; when the current count value of the clock counter reaches the preset row number interval, the timing controller determines the current time as a compensation node and sends a step pulse to the gamma chip at the current time; after sending the step pulse, the timing controller resets the clock counter to zero and restarts the accumulation count to determine the next compensation node; when the vertical blanking region ends, the timing controller resets the clock counter to zero again. The gamma chip accumulates a corresponding number of step values ​​on the basis of the reference gamma value according to the number of step pulses, generates a corresponding compensation gamma voltage, and outputs it to the source drive circuit. The source drive circuit compensates the data voltage of the next frame based on the compensation gamma voltage received last time.

2. The data compensation method according to claim 1, characterized in that, The gamma chip includes a control unit, a memory, and registers; the data compensation method further includes: The timing controller sends a reset pulse to the gamma chip at the beginning of the vertical blanking region; The control unit performs pulse width detection on the received current pulse. When the current pulse is detected to be the first pulse width, it controls the reference gamma value stored in the memory to be written into the register to reset the gamma voltage value stored in the register.

3. The data compensation method according to claim 2, characterized in that, The gamma chip, based on the number of step pulses, accumulates a corresponding number of step values ​​on top of a reference gamma value to generate a corresponding compensated gamma voltage and outputs it to the source drive circuit, including: When the control unit detects that the current pulse is the second pulse width, it generates a step instruction and sends it to the register. The register adds a fixed step voltage to the currently stored gamma voltage value according to the received step instruction to obtain a corresponding compensated gamma voltage, and sends the compensated gamma voltage to the source drive circuit.

4. The data compensation method according to claim 3, characterized in that, The register, based on the received step instruction, increments the currently stored gamma voltage value by a fixed step voltage to obtain a corresponding compensated gamma voltage, and sends the compensated gamma voltage to the source drive circuit, including: Within the vertical blanking region of the current frame, when the register receives the first step instruction, the register increases the currently stored reference gamma value by a fixed step voltage to generate a first compensation gamma voltage, and outputs the first compensation gamma voltage to the source drive circuit. When the register receives a second step instruction after receiving the first step instruction, the register adds a fixed step voltage to the currently stored first compensated gamma voltage to generate a second compensated gamma voltage, and outputs the second compensated gamma voltage to the source drive circuit.

5. The data compensation method according to claim 4, characterized in that, The register is a 16-bit register used to store a 16-bit binary gamma voltage value; the fixed step voltage corresponds to the voltage increment generated by adding 1 to the least significant bit of the 16-bit binary gamma voltage value.

6. The data compensation method according to claim 1, characterized in that, The source drive circuit compensates the data voltage of the next frame based on the last received compensation gamma voltage, including: Within the vertical blanking region of the current frame, the source drive circuit updates the locally stored gamma voltage value with the currently received compensation gamma voltage each time it receives a compensation gamma voltage. When the vertical blanking region of the current frame ends, the timing controller generates the frame start signal for the next frame; The source drive circuit responds to the frame start signal by determining the locally stored gamma voltage value as the last received compensated gamma voltage. The source drive circuit uses the last received compensation gamma voltage as a reference voltage to perform digital-to-analog conversion on the image data of the next frame, generating the corresponding data voltage.

7. The data compensation method according to claim 2, characterized in that, The reset pulse has a first pulse width, the step pulse has a second pulse width, and the first pulse width is different from the second pulse width.

8. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of pixel units arranged in an array and a plurality of data lines, characterized in that, The non-display area includes: A timing controller is used to determine at least one compensation node within the vertical blanking region of the current frame according to a preset row number interval, and to send a step pulse at the corresponding time of each compensation node; specifically, it includes: at the beginning of the vertical blanking region of the current frame, a clock counter accumulates the row scan clock within the vertical blanking region; when the current count value of the clock counter reaches the preset row number interval, the timing controller determines the current time as a compensation node and sends a step pulse to the gamma chip at the current time; after sending the step pulse, the timing controller clears the clock counter to zero and restarts the accumulation count to determine the next compensation node; when the vertical blanking region ends, the timing controller clears the clock counter to zero again; A gamma chip, connected to the timing controller, is used to accumulate a corresponding number of step values ​​on the basis of the reference gamma value according to the number of step pulses, and generate a corresponding compensation gamma voltage. The source drive circuit, connected to the gamma chip and the multiple data lines, is used to compensate the data voltage of the next frame based on the compensation gamma voltage received last time, and send the compensated data voltage to the data lines.

9. The display panel according to claim 8, characterized in that, The timing controller is connected to the gamma chip via a TTL signal line.

10. The display panel according to claim 8 or 9, characterized in that, The gamma chip includes: The control unit, connected to the timing controller, is used to detect the pulse width of the received pulse. When the pulse is detected to be of the first pulse width, it outputs a reset command; when the pulse is detected to be of the second pulse width, it outputs a step command. A memory, connected to the control unit, is used to store the reference gamma value and output the reference gamma value in response to the reset command; The registers are connected to the control unit, the memory, and the source drive circuit, respectively. They are used to write the received reference gamma value to reset the current stored voltage in response to the reset instruction, and to accumulate a fixed step voltage on the currently stored gamma voltage value in response to the step instruction to obtain a corresponding compensated gamma voltage, and to send the compensated gamma voltage to the source drive circuit.

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