A cascaded battery pack fault bypass and phase-shifted pwm control method and system

Abstract

The application discloses a kind of cascade battery pack fault bypass and phase shift PWM control method and system, first acquisition each package terminal voltage, SOC, bus current and fault signal, according to overcharge and overdischarge threshold and energy flow direction identification abnormal package and execute bypass;According to the range of healthy battery pack SOC selects unified duty cycle mode or SOC priority mode, the number of candidate package is dynamically determined according to priority, and the duty cycle is corrected according to target bus voltage;Subsequently, the same frequency PWM of soft start and equal interval phase shift generates main, bypass gate logic instruction, and gate drive module can also set non-overlapping dead zone and hardware interlock, to improve the safety of main bypass switching.The application can maintain the current path of cascade system when single package is abnormal or SOC is inconsistent, and consider fault isolation, SOC regulation, output voltage maintenance, and make the switching edge of multiple battery packs staggered distribution in the same PWM period.

Description

Technical Field

[0001] This invention belongs to the field of battery management and reconfigurable energy storage system control technology, and more specifically, relates to a method and system for fault bypass, SOC directional regulation, target bus voltage correction and phase shift synchronous PWM coordinated control for series-cascaded battery packs. Background Technology

[0002] Large-capacity energy storage devices typically consist of battery packs composed of multiple cells, which are then connected in series to form a high-voltage DC power supply. Due to factors such as manufacturing variations, operating temperature, cycle life, and aging, the capacity, internal resistance, terminal voltage, and state of charge of each battery pack are difficult to maintain consistently over a long period. In a fixed series system, all battery packs flow with the same current; the weaker battery pack is more likely to reach overcharge or over-discharge limits first, forcing the entire system to shut down, thus limiting the usable capacity and continuous power supply capability of the energy storage system.

[0003] To prevent a single battery pack malfunction from causing the entire series system to fail, existing technologies can install bypass branches at both ends of the battery pack. When an anomaly is detected, the corresponding battery pack is isolated from the series link via a bypass switch. However, simple fault bypass only solves the problem of current path interruption; the SOC difference between healthy battery packs may still continue to widen. Furthermore, changes in the number of bypasses can alter the series output voltage, increasing the regulation pressure on subsequent power converters.

[0004] Existing equalization schemes employ dissipative resistors or energy transfer circuits to transfer energy between battery packs, resulting in high circuit complexity and cost. Other modular battery control methods select a fixed number of battery packs for deployment based on voltage or SOC, but fail to simultaneously consider fault level, charging / discharging direction, target bus voltage, continuous duty cycle adjustment, and carrier phase relationships between multiple switching channels. Furthermore, when different battery packs use different switching frequencies, beat frequencies and dispersed spectra are easily generated, which is detrimental to bus ripple control.

[0005] Furthermore, fixed-quantity deployment strategies typically pre-set the number of battery packs involved in operation, without adjusting them in real time based on the healthy battery pack terminal voltage and the target bus voltage. When battery packs are bypassed, terminal voltages change with SOC, or the number of available modules decreases, fixed configurations are prone to insufficient output voltage or insufficient duty cycle margin, causing subsequent converters to experience significant input voltage fluctuations.

[0006] Some reconfigurable battery systems have independent switching frequencies for different battery packs or lack a unified phase arrangement. The switching edges of multiple channels may appear in clusters, or beat frequency and broadband interference may occur. At the same time, if only ideal complementary gates are given without specifying default bypass and data failure handling, uncertain switching states may occur during sampling anomalies or controller reset.

[0007] For example, Chinese patent CN115378102A discloses a method for full current balancing of the state of charge (SOC) of an energy storage system. However, it uses a coarse sorting of SOC states without considering battery faults and health to control a fixed number of "full activation / full deactivation" cycles. The activated battery packs are all on (approximately square wave), and the current command is simply linked to the balancing quantity. The current is finely adjusted only by the duty cycle of a single intermediate module, and the output voltage is dynamically generated by a PI regulator. The control is simple, but the voltage ripple is large and the dynamic response is slow. Furthermore, it ignores the synchronization problem of multiple hard switching edges in the switching sequence, which easily generates current spikes. Therefore, this control method has obvious shortcomings in terms of voltage regulation accuracy, ripple suppression, SOC balancing efficiency, system safety, and fault tolerance granularity.

[0008] Therefore, the improved control scheme required by this invention should not only complete the isolation of abnormal battery packs, but also simultaneously complete the energy state sorting, candidate number determination, equivalent output voltage correction, soft start, and phase coordination under a unified frequency in the remaining healthy battery packs, and provide an identifiable derating operating state when the target voltage cannot be reached, thereby improving the fault-tolerant operation capability and energy utilization level of the series system. Summary of the Invention

[0009] (a) Technical problems to be solved

[0010] This invention discloses a fault bypass and phase-shift PWM control method and system for cascaded battery packs. It aims to solve problems in existing series battery systems, such as single-pack failure leading to entire string failure, inconsistent SOC ranges of healthy battery packs causing reduced usable capacity, dynamic bypass causing output voltage platform fluctuations, and lack of unified phase coordination among multiple switching channels. The method deeply couples dynamic selection of healthy battery packs, SOC direction priority, hardware dead-time interlocking, and soft-start, employing refined continuous PWM control. In near-equal SOC mode, all healthy battery packs participate in unified duty cycle modulation; in unbalanced SOC mode, candidate packs are dynamically selected from healthy battery packs according to priority for modulation. Precise voltage regulation is achieved through global scaling correction of the target voltage, and all modules are phase-shifted at equal intervals with the same frequency. This approach balances fault tolerance, active balancing, and ripple suppression to deliver high-quality DC output, improving the fault-tolerant operation capability and battery pack life of the series system.

[0011] (II) Technical Solution

[0012] This invention discloses a fault bypass and phase-shift PWM control method for cascaded battery packs. The cascaded battery system includes N battery pack modules connected in series. Each battery pack module includes a battery pack, a main circuit switch disposed in the main power supply path of the battery pack, and a bypass switch connected across both ends of the main power supply path. The control method includes the following steps:

[0013] Step S100: Data Acquisition; Acquire the terminal voltage of each battery pack. State of charge Bus current Current time and external fault signals Among them, it is stipulated that This indicates that the system is discharging to the load. This indicates that the system is in a charging state.

[0014] Step S200: Fault identification and bypass; Based on the external fault signal, the secondary overcharge and over-discharge threshold of the battery pack, and the primary protection threshold adapted to the charging and discharging direction, the faulty battery pack is identified, and the faulty battery pack is removed from the main series circuit, and the current path is maintained by the bypass branch.

[0015] Step S300: Health statistics and mode judgment; calculate the number of healthy battery packs, average SOC, SOC range and total voltage of healthy battery packs based on health indicators; when the SOC range is not greater than the balancing threshold, enter the near-balancing mode; otherwise, enter the SOC priority dynamic combination mode.

[0016] Step S400: Dynamic selection of healthy battery packs; calculate the SOC priority of healthy battery packs according to the direction of bus current, and select battery packs one by one from high to low priority until the cumulative equivalent voltage of the candidate packs at the maximum duty cycle reaches the target bus voltage.

[0017] Step S500: Duty cycle correction and soft start; allocate a pre-duty cycle to the candidate packet, perform a uniform proportional correction on the pre-duty cycle according to the target bus voltage, implement minimum and maximum duty cycle limits, and multiply by a soft start coefficient that increases over time.

[0018] Step S600: Phase-shifted synchronous PWM and gate output; each battery pack uses the same PWM cycle. The phase is set at equal intervals according to the battery pack number; the phase-shifted carrier is compared with the duty cycle after soft start to obtain the complementary logic instructions for the main circuit switch and the bypass switch; in the actual hardware implementation, the gate drive module can add non-overlapping dead zone and hardware interlock on the basis of the complementary logic instructions to form the actual main circuit gate and bypass gate signals; at the same time, the fault flag, duty cycle command, achievable voltage and status code are output.

[0019] Furthermore, for details regarding steps S200 to S600, please refer to the specific implementation method described below; they will not be repeated here.

[0020] In addition, the present invention also claims a cascaded battery pack fault bypass and phase-shift PWM control system, comprising: at least one processor; and at least one memory communicatively connected to the processor, wherein: the memory stores program instructions executable by the processor, and the processor can execute the cascaded battery pack fault bypass and phase-shift PWM control method described above by calling the program instructions.

[0021] (III) Beneficial Effects

[0022] 1. This invention maps external faults, secondary overcharge and over-discharge, and direction-dependent primary protection into a unified fault flag, and achieves single-pack-level isolation through main circuit switches and bypass switches, avoiding direct interruption of the entire series system by a single abnormal battery pack.

[0023] 2. This invention automatically switches between near-equilibrium mode and SOC priority mode based on the SOC range. When the SOCs are close, it avoids meaningless frequent sorting. When the SOCs are significantly different, it adjusts the current flow time of each packet according to the charging and discharging direction.

[0024] 3. This invention adopts a dynamic selection strategy for health packs based on the target voltage instead of a fixed number of packs, which can automatically change the number of battery packs participating in modulation according to the number of health packs, terminal voltage and target bus voltage.

[0025] 4. This invention combines discrete candidate selection and continuous duty cycle adjustment through target voltage proportional correction, and can still automatically correct the equivalent output voltage when the number of candidate packets or the terminal voltage changes.

[0026] 5. This invention uses a common PWM cycle. The equal-interval phase shifts allow the turn-on and turn-off edges of multiple battery packs to be staggered within the same PWM cycle, avoiding beat frequencies caused by different frequencies and helping to reduce bus ripple concentration.

[0027] 6. This invention sets soft start, upper and lower limits of duty cycle, default bypass state, and running status code; in actual hardware implementation, the gate driver module can also set non-overlapping dead zone and hardware interlock to improve the safety of master-bypass switching.

[0028] 7. This invention sets clear safety and derating states for sampling failure, unreachable target voltage, fault recovery, and main / bypass switching, so that the control algorithm can not only provide the duty cycle under normal operating conditions, but also cover boundary conditions such as controller initialization, module exit, and insufficient capacity. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below:

[0030] Figure 1 This is a flowchart illustrating the cascaded battery pack fault bypass and phase-shift PWM control method of the present invention.

[0031] Figure 2 This is a schematic diagram of the main circuit topology of the present invention, in which multiple dual-channel battery pack modules are connected in series. The main circuit in the figure is an example of 8 battery pack modules.

[0032] Figure 3 This is a functional block diagram of the dynamic reconfiguration control system of the present invention;

[0033] Figure 4 This diagram illustrates the gate waveforms of multiple battery packs using equal-interval phase-shifted PWM at the same frequency according to the present invention. Each battery pack is illustrated with equal-interval phase shifts of 1 / N periods within the same PWM cycle. Take 24 The corresponding carrier frequency f pwm At approximately 41.67 kHz, when the main circuit pulse is 1, the bypass gate takes a complementary state.

[0034] The above figures are used to illustrate the control flow, main circuit connection relationship, functional module relationship and phase shift PWM timing in the embodiments of the present invention. The number of modules, proportional relationship and waveform width in the figures should not be construed as a limitation on the scope of protection of the present invention.

[0035] The reference numerals in the attached diagrams are as follows: 100, Dynamic Reconfiguration Controller; 110, Acquisition Module; 120, Fault Identification Module; 130, Health Statistics Module; 140, SOC Priority Module; 150, Dynamic Combination Module; 160, Voltage Correction Module; 170, Phase-Shift Synchronous PWM Module; 180, Gate Driver Module; 190, Status Output Module; 200, Battery Pack Module; 201, Battery Pack; 202 (QM), Main Circuit Switch; 203 (QB), Bypass Switch; 300, PCS or DC Load. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0037] To facilitate understanding of the control method of the present invention, the structure of the cascaded battery pack system and the functional modules of the dynamic reconfiguration control system of the present invention will be introduced first.

[0038] like Figure 2As shown, embodiments of the present invention are illustrated using... Taking a cascaded battery pack system as an example, the system consists of eight battery pack modules 200 connected in series. In other embodiments, the number N of battery pack modules 200 can be adjusted according to the target voltage level, system capacity, and input range of the subsequent converter. Each battery pack module 200 includes a battery pack 201, a main circuit switch 202, and a bypass switch 203. The main circuit switch 202 and the battery pack 201 are connected in series to form the main power supply path, and the bypass switch 203 is connected across the two ends of the main power supply path. When the main circuit switch 202 is on and the bypass switch 203 is off, the terminal voltage of the battery pack 201 is connected to the cascaded system; when the main circuit switch 202 is off and the bypass switch 203 is on, the series current flows through the branch where the bypass switch 203 is located, and the battery pack 201 is disconnected from the main power supply path. The main circuit switch 202 and the bypass switch 203 are controlled by complementary gate logic instructions output by the dynamic reconfiguration controller 100. In the actual hardware implementation, non-overlapping dead zones and interlocks can be further added to prevent the main power supply path and the bypass branch from being turned on at the same time.

[0039] Figure 3 This is a functional block diagram of the dynamic reconfiguration control system of the present invention. In this embodiment, the acquisition module 110 is used to obtain the terminal voltage vector, SOC vector, bus current, time, and external fault signals; the fault identification module 120 is used to perform hard fault and directional protection; the health statistics module 130 is used to calculate the SOC mean, SOC range, and health voltage sum; the SOC priority module 140 is used to determine the priority according to the charging and discharging direction; the dynamic combination module 150 is used to determine the candidate battery pack; the voltage correction module 160 is used to complete the target voltage scaling, duty cycle limiting, and soft start; the phase-shift synchronous PWM module 170 is used to generate synchronous, equally spaced phase-shifted PWM logic signals; the gate drive module 180 is used to output the main circuit gate and bypass gate according to the PWM logic signals; and the status output module 190 is used to output the fault flag, duty cycle command Duty_Command, and diagnostic status code PackStatus. Modules 110-170 correspond to the various steps in the control method of the present invention described below.

[0040] To address the technical challenges in series battery pack systems, such as single-pack anomalies leading to entire string failure, inconsistent SOC causing reduced usable capacity, and dynamic bypass causing output voltage fluctuations, in... Figure 2 Based on the cascaded battery pack system, this invention provides a cascaded battery pack fault bypass and phase-shift PWM control method, such as... Figure 1 As shown, the control process of the method includes the following steps.

[0041] Step S100: Data Acquisition. The controller acquires the terminal voltage of each battery pack. State of charge Bus current Current time and external fault signals .Regulation Indicates the direction of discharge. Indicates the charging direction.

[0042] Step S200: Fault Identification and Bypass. The controller first converts the individual cell protection threshold to the battery pack-level protection threshold. Assume a single battery pack consists of... The battery is composed of several cells connected in series. The overcharge, overcharge, over-discharge, and over-discharge thresholds for a single cell are denoted as follows: Then the corresponding battery pack protection threshold is calculated according to formula (1).

[0043]

[0044] In a preferred embodiment, each battery pack consists of 8 strings of 280 Ah cells, with a single cell having a primary overcharge threshold of 3.69 V, a secondary overcharge threshold of 3.80 V, a primary over-discharge threshold of 2.70 V, and a secondary over-discharge threshold of 2.20 V, corresponding to battery pack thresholds of 29.52 V, 30.40 V, 21.60 V, and 17.60 V, respectively.

[0045] The hard fault flag for the k-th battery pack is determined according to equation (2). External fault signals, secondary over-discharge, and secondary overcharge are independent of the direction of the bus current. As long as any one of these conditions is met, the battery pack will be judged as having a hard fault.

[0046]

[0047] In a preferred embodiment, setting the external fault signal threshold to 0.5 is standard logic used to distinguish between "valid fault" (1) and "invalid / normal" (0), while also considering noise immunity (avoiding noise glitches). If the signal is normalized or after analog-to-digital conversion (ADC)... >0.5, logically considered "high level" or "true" (indicating an external fault, such as an unrecoverable fault reported by the BMS, excessive temperature, etc.); if ≤0.5 is considered "low level" or "false" (no external fault).

[0048] The primary protection flag, which is adapted to the charging and discharging direction, is determined according to formula (3). Thus, in the discharging state, it mainly prevents the battery pack from being over-discharged, and in the charging state, it mainly prevents the battery pack from being over-charged.

[0049]

[0050] Comprehensive Fault Flags and health symbols Determine according to equations (4) and (5) respectively.

[0051]

[0052]

[0053] when When the main circuit switch of the battery pack is turned off and the bypass switch is turned on, the controller will directly cut off the main circuit switch and turn on the bypass switch when the terminal voltage or SOC sampling data is invalid, communication times out, or exceeds the reasonable range. This prevents the battery pack from entering subsequent sorting and duty cycle calculations, and maintains a bypass safety state.

[0054] Step S300: Health Statistics and Pattern Judgment. The controller calculates the number of healthy battery packs based on the health indicators. and the average SOC of healthy battery packs The calculation formulas are shown in equation (6) and equation (7) respectively.

[0055]

[0056]

[0057] Equation (7) in Used when; At this time, the controller will no longer perform combination selection, all battery packs will remain bypassed, and the system will output an unavailable status. The average SOC is mainly used for operational status statistics, upper-level energy management, and fault diagnosis.

[0058] Healthy battery pack SOC range and the total voltage of the health battery pack Calculate according to Equation (8) and Equation (9) respectively.

[0059]

[0060]

[0061] in, and These represent the maximum and minimum SOC of a healthy battery pack. When the load factor is not greater than the preset equalization threshold, all healthy battery packs use the same base duty cycle. Calculate according to formula (10).

[0062]

[0063] Equation (10) in Used at that time The target bus voltage; when When the allowable range is exceeded, the corresponding duty cycle boundary shall be used.

[0064] The physical meaning of this formula is: In the "near-equilibrium mode" where the SOC range is small, the controller ensures that all healthy battery packs use the same base duty cycle. This duty cycle equals the "target bus voltage" divided by the "current total voltage of the healthy battery pack," meaning that through proportional chopping, the average total voltage of the healthy battery pack is adjusted to the target value. When the calculated... When the duty cycle exceeds the minimum / maximum range allowed by the system (e.g., 0.02~0.95), the boundary value will be directly used for amplitude limiting.

[0065] when When the SOC priority is greater than the preset equalization threshold, the SOC priority under the discharge condition is calculated according to formula (11), and the SOC priority under the charging condition is calculated according to formula (12).

[0066]

[0067]

[0068] Priority is limited to between 0 and 1. As can be seen from equations (11) and (12), battery packs with higher SOC during discharge receive higher priority, while battery packs with lower SOC during charging receive higher priority, so that the SOC of each healthy battery pack gradually converges.

[0069] The physical meaning of this formula: In formula (11), "whoever has higher charge has priority in discharging," this formula calculates the relative position of the current battery pack's SOC within the overall health group. The higher the SOC, the better. The closer to 1; the lower the SOC (closest to the minimum value). ), The closer to 0. In formula (12), "whoever has the lowest charge level takes priority in charging," this formula completely reverses the logic. The lower the SOC, the more the molecule... The larger, The closer to 1, the higher the SOC. The closer to 0, the better. This differentiated principle of "prioritizing increasing SOC during discharge and prioritizing decreasing SOC during charging" enables priority-based charging. By allocating duty cycles, the system continuously reduces the ΔSOC (range) during charge and discharge cycles, eventually causing the SOC of all healthy battery packs to gradually converge, thereby maximizing the usable capacity of the entire series-connected battery pack. When the range... Once the value is reduced to within the preset equilibrium threshold (e.g., 0.02), the system will automatically switch back to the "near equilibrium mode" of formula (10), stop differentiated scheduling, and avoid frequent sorting.

[0070] Step S400: Dynamic m selects n. The controller selects healthy battery packs according to priority. Sort from highest to lowest, and record the sorted numbers as follows: The maximum equivalent output voltage when selecting the first m battery packs. Calculate according to formula (13).

[0071]

[0072] To determine the terminal voltage of the j-th battery pack among the first m battery packs after sorting, the controller adds each battery pack to the candidate set one by one, starting from the battery pack with the highest priority, until equation (14) is satisfied.

[0073]

[0074] Choose the smallest integer m that satisfies equation (14); when all healthy battery packs are at maximum duty cycle If the target voltage still cannot be reached, select all healthy battery packs and output the derating status and the achievable upper voltage limit. The selection flag for the k-th battery pack... Determined according to formula (15).

[0075]

[0076] in, , representing the candidate set consisting of the first m high-priority healthy battery packs.

[0077] Step S500: Duty cycle correction and soft start.

[0078] Pre-duty cycle generation (determines "weight" allocation): In unbalanced mode, the pre-duty cycle of the k-th battery pack. Calculate according to formula (16).

[0079]

[0080] in, The base duty cycle for candidate packets. For SOC priority gain; unselected battery packs due to Maintaining a zero duty cycle is an open-loop weighted allocation strategy that prioritizes energy throughput towards the target packet while ensuring that all candidate packets have outputs.

[0081] In near-equilibrium mode, the pre-duty cycle of the kth battery pack is calculated according to equation (17).

[0082]

[0083] Equation (17) is a flow sharing strategy where all modules output power proportionally, avoiding frequent switching and calculation jitter.

[0084] Voltage closed-loop correction (ensuring target accuracy): Equivalent output voltage corresponding to the pre-duty cycle. Calculate according to formula (18); when At that time, the target bus voltage scaling factor is calculated according to equation (19), and the final duty cycle is... Calculate according to formula (20).

[0085]

[0086]

[0087]

[0088] when When the duty cycle is greater than the maximum duty cycle, the maximum duty cycle is used; when 0 < When the duty cycle is less than the minimum, the minimum duty cycle is used; when... At that time, keep Through the above proportional correction, the "relative output ratio (weight) of each package" determined in steps S400 and S500 (first layer) is fully preserved. At the same time, through overall translation, the bus voltage is forcibly pulled to the target bus voltage value. This solves the problem of continuous and precise voltage regulation that cannot be achieved by simply using discrete combinations of "m select n". It can make the system's equivalent output voltage approach the target bus voltage while maintaining the relative duty cycle relationship of the candidate packets.

[0089] Safety limiting (physical boundary constraints): To reduce the voltage and current surges during startup, a soft-start coefficient is set, expressed as shown in equation (21); the duty cycle after soft start. As shown in equation (22).

[0090]

[0091]

[0092] For the set soft-start duration (such as 0.05 seconds in the example), when Seasonal soft start coefficient The soft-start timer can be reset to zero when the system is re-enabled, a fault is recovered, or the target voltage experiences a jump exceeding a preset amplitude.

[0093] Duty cycle after soft start It acts as a "soft starter" for voltage and current. At the moment of startup (t=0), the duty cycle is 0; as time progresses, the duty cycle gradually rises to the target value. This prevents the duty cycle from jumping directly from 0 to 0.95 when the controller is first enabled or a fault is recovered, thus avoiding the generation of huge inrush current (surge) that could damage power devices or cause violent charging and discharging of the bus capacitor.

[0094] Therefore, the duty cycle setting principle of step S500 is as follows: first, allocate weights as needed according to different modes (Equation 16 / 17); then, uniformly calibrate the accuracy according to the target bus voltage (Equation 18 / 19 / 20); and finally, apply the physical safety constraint of "limiting + soft start" (Equation 21 / 22). It decouples "SOC balancing demand" (differentiated weights) and "bus voltage stability demand" (global scaling), which can actively adjust battery consistency and ensure that downstream loads or PCS inverters obtain stable DC input.

[0095] Step S600: Phase-shifted synchronous PWM and gate output. All battery packs use the same PWM cycle. The normalized phase offset of the kth battery pack is calculated according to equation (23), and the phase-shifted carrier is calculated according to equation (24).

[0096]

[0097]

[0098] Here, mod represents the modulo operation with respect to 1, therefore The periodic variation is between 0 and 1. Equation (23) is used to arrange the carrier start point of the k-th battery pack at (k−1) / N of the period. Equation (24) is a sawtooth wave (or equivalent triangular wave count) that grows linearly and periodically between 0 and 1, corresponding to an ever-accumulating counter in the controller for phase-shift carrier generation. By superimposing equation (23) Each battery pack has its own independent, but completely consistent, counting reference.

[0099] The carrier comparison result is determined according to equation (25).

[0100]

[0101] Physical meaning: This is the core "comparator" principle of PWM. When the instantaneous value of the sawtooth wave (carrier) is less than the duty cycle command... When the output is high (1), the corresponding main circuit switch is turned on; when the sawtooth wave rises and exceeds the duty cycle command... When the output is low (0), the corresponding main circuit switch is turned off.

[0102] The main circuit gate and the bypass gate generate ideal complementary logic instructions according to equations (26) and (27), respectively.

[0103]

[0104]

[0105] in, The gate is at a high level. Faulty battery pack forced. Thus, the main circuit logic instruction is low and the bypass logic instruction is high. In actual hardware applications, a non-overlapping dead zone and hardware interlock can be added by the gate drive module based on the logic instruction. The PWM switching frequency is calculated according to equation (28).

[0106]

[0107] Therefore, the specific execution path of step S600 is as follows: numerical instructions Multiply by the common PWM cycle Obtain the conduction duration t on → In the phase shift slot assigned to itself Internal comparison → Output high / low level → Drive main / side switch transistors after dead-time compensation → Battery connects or disconnects from bus as expected. Step S600 can divide the numerical duty cycle into non-overlapping pulses by comparing staggered phase sawtooth waves, and convert them into complementary high and low voltage drive signals with safety interlock, ultimately accurately controlling the connection and disconnection of the battery pack.

[0108] Furthermore, the present invention provides numerical examples of the control process and its effects for each step based on the following embodiments.

[0109] In a preferred embodiment Take 24 This corresponds to a carrier frequency of approximately 41.667 kHz. When At that time, the theoretical phase difference between adjacent channels is 3. .like Figure 4 As shown, phase shift only changes the position of the pulses in each channel within the common period, without changing the switching frequency of each channel. Its function is to stagger the turn-on and turn-off edges of different battery packs.

[0110] In one simulation implementation, the system comprises eight battery packs, each consisting of eight cells with a rated capacity of 280 Ah. The initial State of Charge (SOC) of the eight battery packs are set sequentially to 0.90, 0.85, 0.80, 0.70, 0.65, 0.60, 0.55, and 0.50 to construct an inconsistent SOC operating condition. The system target bus voltage is set to 122 V, the duty cycle range is set to 0.02 to 0.95, the SOC equalization threshold is set to 0.02, the candidate pack base duty cycle is set to 0.55, the priority gain is set to 0.40, and the soft-start time is set to 0.05 s.

[0111] For example, when the voltage of the fourth battery pack is set to 21.45 V, its voltage is lower than the first-level over-discharge threshold of 8 × 2.70 V = 21.60 V. Under discharge conditions, the controller sets the direction protection flag of the fourth battery pack to 1, outputs 0V at the main circuit gate and 15V at the bypass gate, and re-executes SOC statistics, dynamic m-to-n selection, and duty cycle correction in the remaining healthy battery packs.

[0112] As an example of dynamic m-to-n selection, if the terminal voltages of all eight healthy battery packs are approximately 25.6 V, the maximum duty cycle is 0.95, and the target bus voltage is 122 V, then the maximum equivalent contribution of a single pack is approximately 24.32 V. When five battery packs are selected, the cumulative maximum equivalent voltage is approximately 121.60 V, which is less than the target value; when six battery packs are selected, the cumulative maximum equivalent voltage is approximately 145.92 V, which meets the target value. Therefore, the controller determines n=6. This calculation is only used to illustrate the process of determining the minimum number of candidates.

[0113] In this embodiment, the relationship between the diagnostic status code PackStatus and the gate is shown in Table 1.

[0114] Table 1. Relationship between Battery Pack Operating Status Diagnosis and Gate Pole Correspondence

[0115]

[0116] The gate threshold value in Table 1 can be 7.5 V, while the actual high-level drive is 15 V. The status code can be determined by a combination of control commands or actual gate feedback, and is used for host computer diagnosis and fault recording.

[0117] The control method described in this invention can be implemented by a microcontroller, digital signal processor, field-programmable gate array, system-on-a-chip, or industrial control computer. For modular energy storage systems with N greater than 8, the following method can continue to be used. The phase shift can also be achieved by dividing the battery pack into several phase groups and performing equal-interval phase shifts within each group. The target bus voltage can be dynamically given by the upper-level energy management system; if the target value changes rapidly, a slope limit can be set; if the maximum achievable voltage of the health pack is less than the target value, the output can realize the upper voltage limit and derating flag, which are then used by the power conversion system (PCS) to adjust the power.

[0118] It is worth mentioning that this invention employs a three-stage strategy: "first, continuous pressurization (λ); then, dynamic replenishment (m selects n); and finally, declaring the limit." Compared to the "step-by-step" derating in existing technologies, this invention's derating occurs later, is shallower, and the derating process is smoother. It doesn't sacrifice derating itself, but rather uses an algorithm to sacrifice "brutal full-power hardware" in exchange for "high system availability and continuity"—a more valuable metric in energy storage scenarios than simply pursuing rated power.

[0119] In the embodiments provided by this invention, the control method can also be implemented as a software program, which can be stored in a computer-readable storage medium. The storage medium includes various media capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory, random access memory, magnetic disk, or optical disk.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fault bypass and phase-shift PWM control of a cascaded battery pack, characterized in that, The cascaded battery system includes N battery pack modules connected in series. Each battery pack module includes a battery pack, a main circuit switch located in the main power supply path of the battery pack, and a bypass switch connected across both ends of the main power supply path. The control method includes the following steps: Step S100: Collect the terminal voltage of each battery pack State of charge Bus current Current time and external fault signals; Step S200: Determine the overcharge and over-discharge protection threshold of the battery pack based on the individual cell protection threshold and the number of cells connected in series in a single battery pack. Combine the primary protection threshold, secondary overcharge and over-discharge threshold adapted to the charging and discharging direction, and external fault signals to generate a fault flag, so that the main circuit switch of the faulty battery pack is cut off, the bypass switch is turned on, and a healthy battery pack set is formed. Step S300: Calculate the number of healthy battery packs, average SOC, SOC range, and total voltage of the healthy battery packs; When the SOC range is not greater than the preset equalization threshold, all healthy battery packs adopt a uniform basic duty cycle; when the SOC range is greater than the equalization threshold, the SOC priority is calculated according to the direction of the bus current. Step S400: Calculate the SOC priority of the healthy battery pack according to the direction of the bus current, select healthy battery packs in descending order of SOC priority, and determine the minimum number n of candidates that meet the target bus voltage in the set of healthy battery packs; Step S500: Calculate the pre-duty cycle of the candidate battery pack, and uniformly scale and constrain the pre-duty cycle according to the target bus voltage, implement minimum and maximum duty cycle limits, and multiply by the soft-start coefficient that increases over time. Step S600: According to the same PWM cycle Equally spaced phase-shifted carriers are generated for each battery pack. The phase-shifted carriers are compared with the duty cycle after soft start to obtain complementary logic instructions for the main circuit switch and the bypass switch.

2. The cascaded battery pack fault bypass and phase-shift PWM control method according to claim 1, characterized in that, In step S200, the protection threshold for a single cell is multiplied by the number of cells connected in series within a single battery pack to obtain the corresponding battery pack protection threshold, the expression of which is: in, The number of cells connected in series within a single battery pack; This refers to the protection threshold for a single battery cell. The battery pack protection threshold is denoted as follows: The first-level overcharge, second-level overcharge, first-level over-discharge, and second-level over-discharge thresholds for a single cell are denoted as follows: The subscripts oc1, oc2, od1, and od2 represent first-stage overcharge, second-stage overcharge, first-stage over-discharge, and second-stage over-discharge, respectively, and are the hard fault flags for the k-th battery pack. Directional protection signs Comprehensive fault indicators and health indicators Determine them according to the following formulas respectively: in, This represents an external fault signal for the k-th battery pack. Indicates the direction of discharge. Indicates the charging direction; , and These are the hard fault flag, direction protection flag, and comprehensive fault flag for the k-th battery pack, respectively. This indicates that the battery pack has triggered a fault or protection mechanism. As a health indicator, when the terminal voltage or SOC sampling data is invalid, let .

3. The cascaded battery pack fault bypass and phase-shift PWM control method according to claim 2, characterized in that, Number of healthy battery packs in step S300 Average SOC of healthy battery pack , Healthy battery pack SOC extremely poor Total voltage of the healthy battery pack and a unified basic duty cycle Calculate according to the following formulas respectively: in, This represents the total number of cascaded battery packs. For the first Health indicators for each battery pack For the number of healthy battery packs, For the first SOC of a battery pack The average SOC of a healthy battery pack. and These are the maximum and minimum SOC of a healthy battery pack. The battery pack has extremely poor SOC (State of Charge). For the first Battery pack terminal voltage, The total voltage of a healthy battery pack. For the target bus voltage, To unify the basic duty cycle; Formula (7) in When used, formula (10) is in Used at that time; When the duty cycle exceeds the preset range, the corresponding boundary value is used.

4. The cascaded battery pack fault bypass and phase-shift PWM control method according to claim 3, characterized in that, In step S300, when When the SOC exceeds the preset equalization threshold, the SOC priority of the kth healthy battery pack in the discharge state and the charging state are respectively: Among them, priority Limited to between 0 and 1; when When the value is not greater than the preset equalization threshold, formulas (11) and (12) are not executed, and all healthy battery packs participate in modulation according to the uniform basic duty cycle calculated by formula (10).

5. The cascaded battery pack fault bypass and phase-shift PWM control method according to claim 4, characterized in that, In step S400, the healthy battery packs are prioritized according to their SOC (State of Charge). Sort from highest to lowest, and record the sorted numbers as follows: The maximum equivalent output voltage when selecting the first m battery packs after sorting. for: This represents the terminal voltage of the j-th battery pack among the first m battery packs after sorting. To maximize the duty cycle, select the smallest integer n that satisfies formula (14); If formula (14) is still not satisfied after all healthy battery packs have been selected, then all healthy battery packs are selected, and the selection flag for the k-th battery pack is set. for: in, ={π(1), π(2), ..., π(n)} represents the candidate set consisting of the first n high-priority healthy battery packs, where N is the total number of cascaded battery packs. Let n be the number of healthy battery packs, and n be the number of candidate battery packs selected from the set of healthy battery packs.

6. The cascaded battery pack fault bypass and phase-shift PWM control method according to claim 5, characterized in that, In step S500, the pre-duty cycle in unbalanced mode and near-balanced mode Equivalent output voltage corresponding to the pre-duty cycle Target voltage scaling factor and final duty cycle They are respectively: Formula (16) is used in the unbalanced mode, and formula (17) is used in the near-balanced mode. When the SOC range is not greater than the preset balance threshold, the near-balanced mode is entered; otherwise, the unbalanced mode with priority dynamic combination of SOC is entered. The base duty cycle for candidate packets. For SOC priority gain; when Formulas (19) and (20) are not executed when... When the duty cycle is greater than the maximum duty cycle, the maximum duty cycle is used; when 0 < When the minimum duty cycle is less than the minimum duty cycle, the minimum duty cycle is used; when the pre-duty cycle is less than the minimum duty cycle, the minimum duty cycle is used. Keep .

7. The cascaded battery pack fault bypass and phase-shift PWM control method according to claim 6, characterized in that, Soft start coefficients in steps S500 and S600 Soft start duty cycle Phase shift Phase-shifted carrier PWM activation status Gate logic instructions for main circuit / bypass switches / and PWM frequency They are respectively: Among them, when season When the first When a battery pack is determined to be a faulty battery pack, a mandatory order is issued. For the first The main circuit gate logic instructions for each battery pack. For the first Bypass gate logic instructions for a battery pack The gate is at a high level; dead time and interlocking are set between the main circuit switch and the bypass switch in the actual hardware implementation.

8. The cascaded battery pack fault bypass and phase-shift PWM control method according to any one of claims 1 to 7, characterized in that, When the terminal voltage or SOC data of any battery pack is invalid, communication times out, or exceeds the preset reasonable range, the battery pack is determined to be in an unschedulable state and kept in bypass mode; after the fault is cleared, the battery pack must pass the data validity, terminal voltage threshold, and direction protection checks again before it can enter the healthy set.

9. The cascaded battery pack fault bypass and phase-shift PWM control method according to any one of claims 1 to 7, characterized in that, The cascaded battery system comprises eight battery packs, each containing eight cells in series; the target bus voltage is 122V, the minimum duty cycle is 0.02, the maximum duty cycle is 0.95, the SOC equalization threshold is 0.02, the soft-start time is 0.05 s, and the PWM cycle is... The parameter is 24 The gate high level is 15 V.

10. A cascaded battery pack fault bypass and phase-shift PWM control system, characterized in that, include: At least one processor; And at least one memory communicatively connected to the processor, wherein: the memory stores program instructions executable by the processor, and the processor invokes the program instructions to execute the cascaded battery pack fault bypass and phase-shift PWM control method according to any one of claims 1-9.

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