High-reliability inverter drive dual backup control system and switching method thereof

Abstract

The application relates to a high-reliability inverter driving double-backup control system and a switching method thereof, which comprises a first control unit, a second control unit and a switching unit. Each control unit comprises a CPU control circuit, a locking circuit, a state detection circuit and a driving control circuit; the switching unit comprises a CPU master control circuit and a double-backup interlocking circuit. The system and the method adopt two control units to form a double-backup control structure which is mutually backed up and autonomously competes for output; when a group of control units fails, the system can immediately switch to output of another group of control units, thereby greatly improving the reliability of system operation. Meanwhile, the switching adopts double interlocking control composed of circuit interlocking control of the first control unit and the second control unit and circuit interlocking control of the switching unit, thereby ensuring the reliable stability of inverter driving.

Description

Technical Field

[0001] This invention relates to the field of inverter drive control technology, specifically to a highly reliable inverter drive dual-backup control system and its switching method. Background Technology

[0002] With the development of technology, the reliability and stability of power supply have become increasingly important. Critical locations such as data centers, communication equipment rooms, and hospitals have increasingly stringent power supply requirements; power outages can result in enormous losses. Therefore, uninterruptible power supplies (UPS) have been widely adopted to improve the stability of power supply systems. However, traditional UPS systems use a single control unit. When this control unit malfunctions, the UPS system cannot function properly, affecting the normal operation of the entire power supply system. This results in low reliability and inconvenient on-site maintenance. Summary of the Invention

[0003] In view of this, a highly reliable inverter drive dual-backup control system with automatic switching and dual-backup control, and its switching method are provided.

[0004] A highly reliable inverter drive dual-backup control system includes a first control unit, a second control unit, and a switching unit. The first control unit and the second control unit serve as backups for each other and can output inverter drive signals when in operation. The switching unit can switch between the two control units based on their operating states. The first control unit includes a first CPU control circuit, a first locking circuit, a first state detection circuit, and a first drive control circuit, wherein the first drive control circuit has a first switching element; the second control unit includes a second CPU control circuit, a second locking circuit, a second state detection circuit, and a second drive control circuit, wherein the second drive control circuit has a second switching element; the switching unit includes a CPU main control circuit and a first interlock circuit and a second interlock circuit that are backups of each other. The first CPU control circuit is connected to the output terminal of the inverter drive signal through a first switching element. The first switching element is switched on and off under the control of the first drive control circuit. The first locking circuit has a first locking signal input terminal to receive a first locking signal from the switching unit and a second locking signal input terminal to receive a second locking signal from the second locking circuit. The output terminal of the first locking circuit is connected to the first state detection circuit and the first drive control circuit. The first state detection circuit outputs a first running signal to the CPU main control circuit based on the first output signal of the first locking circuit. The first drive control circuit outputs a first drive signal based on the first output signal of the first locking circuit to control the switching on and off of the first switching element. The second CPU control circuit is connected to the output terminal of the inverter drive signal via a second switching element. The second switching element is switched on and off under the control of the second drive control circuit. The second locking circuit has a first locking signal input terminal to receive a first locking signal from the switching unit or the first locking circuit. The output terminal of the second locking circuit is connected to the second state detection circuit and the second drive control circuit. The second state detection circuit outputs a second running signal to the CPU main control circuit based on the second output terminal signal of the second locking circuit. The second drive control circuit outputs a second drive signal based on the second output terminal signal of the second locking circuit to control the switching on and off of the second switching element. When the first CPU control circuit is working normally, it outputs a first normal signal. When the second CPU control circuit is working normally, it outputs a second normal signal. The CPU main control circuit receives the first normal signal and the first running signal and outputs a first working signal to the first interlock circuit. The CPU main control circuit receives the second normal signal and the second running signal and outputs a second working signal to the second interlock circuit. When one of the two working signals is working normally, the corresponding interlock circuit is turned on and outputs the first locking signal, while locking the other interlock circuit so that the other interlock circuit is not turned on. When the first locking signal output by the switching unit is a locking signal, the first control unit is locked and the second control unit is unlocked. When the first locking signal output by the switching unit is an unlocking signal, the second control unit is locked and the first control unit is unlocked. When the first locking signal output by the switching unit is an unlocking signal or the system is in the default initial state, the first locking circuit is in the unlocked state and provides a first drive signal to the first drive control circuit to turn on the first drive control circuit, provides a trigger signal to the first state detection circuit to output a first running signal, and provides a locking signal to the second locking circuit. Simultaneously, the second locking circuit is in the unlocked state and provides a second drive signal to the second drive control circuit to turn on the second drive control circuit, provides a trigger signal to the second state detection circuit to output a second running signal, and provides a locking signal to the first locking circuit, so that the output of the first control unit and the output of the second control unit are interlocked and compete autonomously, and one of the control units outputs the inverter drive signal. When the first locking signal output by the switching unit is a locking signal, the first locking circuit is in a locked state and the first drive control circuit is not turned on, the first state detection circuit does not output the first running signal, and the second locking circuit receives the unlocking signal. Simultaneously, the second locking circuit is in an unlocked state and provides a second drive signal to the second drive control circuit to turn on the second drive control circuit, provides a trigger signal to the second state detection circuit to output the second running signal, and provides a locking signal to the first locking circuit, so that the system outputs the inverter drive signal by the second control unit.

[0005] Specifically, when the first control unit malfunctions or fails to operate, it outputs a signal to the CPU main control circuit and / or the first state detection circuit does not output a first operating signal. The switching unit outputs a first locking signal to the first locking circuit and locks the first locking circuit, and outputs a first locking signal to the second locking circuit and unlocks the second locking circuit, so that the system outputs an inverter drive signal from the second control unit. When the second control unit malfunctions or fails to operate, it outputs a signal to the CPU main control circuit and / or the second state detection circuit does not output a second operating signal. The switching unit outputs a first locking signal to the first locking circuit and unlocks the first locking circuit, and outputs a first locking signal to the second locking circuit and locks the second locking circuit, so that the system outputs an inverter drive signal from the first control unit.

[0006] Furthermore, the first locking signal is either high or low. When the first locking signal is high, the first locking circuit is unlocked and the second locking circuit is locked. When the first locking signal is low, the second locking circuit is unlocked and the first locking circuit is locked. When the second locking signal is high, it is used to lock the first locking circuit and make the first locking signal low. When the second locking signal is low, the first locking circuit is unlocked and the second locking circuit is locked.

[0007] Further, each of the first and second locking circuits includes a power supply and a switching device. The power supply is connected to a corresponding state detection circuit and a drive control circuit. The input terminal of the switching device receives a corresponding locking signal, the second terminal is connected to the power supply, and the third terminal is grounded. When the locking signal received by the input terminal of the switching device in one of the locking circuits is high, the switching device in that locking circuit is in a conducting state, causing the power supply to be directly grounded and pulling down the voltage, thus locking the locking circuit with the switching device and providing the low level to the input terminal of the switching device in another locking circuit to unlock the other locking circuit. When the locking signal received by the input terminal of the switching device in one of the locking circuits is low, the switching device in that locking circuit is in a disconnected state, preventing the power supply from being pulled down and maintaining a high level, thus unlocking the locking circuit with the switching device and providing the high level to the input terminal of the switching device in another locking circuit to lock the other locking circuit.

[0008] Furthermore, each state detection circuit in the first and second state detection circuits includes an operational amplifier and a detection Zener diode. The first lock signal is connected to the non-inverting input of the operational amplifier, and the inverting input of the operational amplifier is connected to a predetermined voltage power supply, such as the power supply VCC or other preset voltage power supply. The output of the operational amplifier is connected to one end of the cathode of the detection Zener diode, and the anode of the detection Zener diode is connected to the control ground GND. The cathode of the detection Zener diode serves as the output of the first operating signal of the first state detection circuit.

[0009] Furthermore, the first CPU control circuit has a first switching output terminal to output a first switching signal. The first switching output terminal is connected to the input terminal of the first state detection circuit and the input terminal of the first drive control circuit through a first switching switch. The second CPU control circuit has a second switching output terminal to output a second switching signal. The second switching output terminal is connected to the input terminal of the second state detection circuit and the input terminal of the second drive control circuit through a second switching switch. After the first CPU control circuit or the second CPU control circuit operates, it outputs a first normal signal or a second normal signal to the switching unit accordingly, and outputs a high-level first switching signal or a second switching signal to the corresponding switching switch via the first switching output terminal and the second switching output terminal. The first switching switch and the second switching switch are both manual switches.

[0010] Furthermore, both the first drive control circuit and the second drive control circuit include a drive transistor, a drive Zener diode, and a relay; the corresponding lock signal passes through the cathode of the drive Zener diode and is connected from the anode of the drive Zener diode to the base of the drive transistor; the emitter of the drive transistor is connected to control ground GND; the collector of the drive transistor is connected to one end of the relay coil; the other end of the relay coil is connected to a preset power supply; one contact of the relay is connected to the corresponding CPU control circuit; and the normally open contact of the relay is the drive signal output terminal of the corresponding drive control circuit and outputs an inverter drive signal during operation.

[0011] Furthermore, the switching unit includes a CPU main control circuit and a first interlock circuit and a second interlock circuit that are backups of each other. In the switching unit, the CPU main control circuit outputs a first working signal WORK1 based on the first normal signal and the first running signal of the first control unit, and outputs a second working signal WORK2 based on the second normal signal and the second running signal of the second control unit. The first interlock circuit includes a first NAND gate chip U1A, a second NOT gate chip U1B, a first interlock switch element, and a non-inverting drive circuit; the second interlock circuit includes a third NAND gate chip U1C, a fourth NAND gate chip U1D, a second interlock switch element, and an inverting drive circuit. The first NAND gate chip U1A and the third NAND gate chip U1C are respectively configured such that a high-level input results in a low-level output and a low-level input results in a cutoff signal; the second NOT gate chip U1B and the fourth NAND gate chip U1D are respectively configured such that a low-level input results in a high-level output and a high-level input results in a cutoff signal; the input terminal of the first interlock switch element is connected to the first NAND gate chip U1A and its output terminal is connected to the fourth NAND gate chip U1D; the input terminal of the second interlock switch element is connected to the third NAND gate chip U1C and its output terminal is connected to the second NAND gate chip U1B; the output terminal of the first NAND gate chip U1A is connected to the input terminal of the second NOT gate chip U1B; the output terminal of the third NAND gate chip U1C is connected to the input terminal of the fourth NOT gate chip U1D; the output terminal of the second NOT gate chip U1B is connected to the input terminal of the non-inverting drive circuit; and the output terminal of the fourth NOT gate chip U1D is connected to the input terminal of the inverting drive circuit; the signals output by the output terminals of the non-inverting drive circuit and the inverting drive circuit are respectively the first locking signal. The output signal of the first NAND gate chip U1A is connected to the input terminal of the first interlock switch element. The first interlock switch element is cut off when the input terminal is high and turns on when the input terminal is low, and inputs a high level to the fourth NAND gate chip U1D to turn off the fourth NAND gate chip U1D. The output signal of the third NAND gate chip U1C is connected to the input terminal of the second interlock switch element. The second interlock switch element is cut off when the input terminal is high and turns on when the input terminal is low, and inputs a high level to the second NAND gate chip U1B to turn off the second NAND gate chip U1B. The first working signal WORK1 is connected to the input terminal of the first NAND gate chip U1A; when the first working signal WORK1 is high, the first NAND gate chip U1A outputs a low level and turns off the second switching element, turns on the second NAND gate U1B and outputs a high level, and outputs a high level through the non-inverting drive circuit. At this time, the first locking signal is high. The second working signal WORK2 is connected to the input terminal of the third NAND gate chip U1C. When the second working signal WORK2 is high, the third NAND gate chip U1C outputs a low level and turns off the first switching element, turns on the fourth NAND gate U1D and outputs a high level, and outputs a low level through the inverting drive circuit. At this time, the first locking signal is low.

[0012] Furthermore, the first interlocking switching element is a first interlocking transistor Q1, the second interlocking switching element is a second interlocking transistor Q2, both interlocking MOSFETs are PNP transistors, the input terminal of the first interlocking switching element and the input terminal of the second interlocking switching element are both bases, the output terminal of the first interlocking switching element and the output terminal of the second interlocking switching element are both collectors, the emitter of the first interlocking switching element and the emitter of the second interlocking switching element are respectively connected to their respective interlocking power supplies; the non-inverting drive circuit includes a third transistor Q3 and a fifth transistor Q5, the inverting drive circuit includes a fourth transistor Q4, a sixth transistor Q6, and a seventh transistor Q7, the third transistor Q3, the fourth transistor Q4 and the seventh transistor Q7 are all NPN transistors, and the fifth transistor Q5 and the sixth transistor Q6 are both PNP transistors; The output of the second NAND gate U1B is connected to the base of the third transistor Q3 via the seventh resistor R7. The emitter of the third transistor Q3 is connected to the control ground GND. The collector of the third transistor Q3 is connected to the base of the fifth transistor Q5 via the ninth resistor R9. The base of the fifth transistor Q5 is connected to the auxiliary power supply via the tenth pull-up resistor R10. The emitter of the fifth transistor Q5 is connected to the auxiliary power supply. The collector of the fifth transistor Q5 is connected to the output of the first lock signal of the switching unit via the thirteenth resistor R13. The output of the fourth NAND gate U1D is connected to the base of the fourth transistor Q4 via the eighth resistor R8. The emitter of the fourth transistor Q4 is connected to the control ground GND. The collector of the fourth transistor Q4 is connected to the base of the sixth transistor Q6 via the eleventh resistor R11; the base of the sixth transistor Q6 is connected to the auxiliary power supply via the twelfth pull-up resistor R12; the emitter of the sixth transistor Q6 is connected to the auxiliary power supply; the collector of the sixth transistor Q6 is connected to the base of the seventh transistor Q7 via the fourteenth resistor R14; the base of the seventh transistor Q7 is connected to the control ground GND via the fifteenth pull-down resistor R15; the emitter of the seventh transistor Q7 is connected to the control ground GND; and the collector of the seventh transistor Q7 is connected to the output terminal of the first lock signal of the switching unit via the sixteenth resistor R16.

[0013] Furthermore, a switching method for a reliable inverter-driven dual-backup control system, applicable to the high-reliability inverter-driven dual-backup control system described above, the method comprising the following steps: In the initial state or when powered on, the first locking circuit can output a locking signal to the second locking circuit, and at the same time, the second locking circuit can output a locking signal to the first locking circuit. The outputs of the first control unit and the second control unit are interlocked and compete autonomously, with one of the control units outputting the inverter drive signal. The first locking circuit provides an on or off signal to the first drive control circuit based on the second locking signal to determine whether the first CPU control circuit outputs an inverter drive signal. The first state detection circuit outputs a first running signal to the CPU main control circuit based on the first output signal of the first locking circuit. The first CPU control circuit sends a first normal signal to the CPU main control circuit based on the working state. The second locking circuit provides an on or off signal to the second drive control circuit based on the first locking signal to determine whether the second CPU control circuit outputs an inverter drive signal. The second state detection circuit outputs a second running signal to the CPU main control circuit based on the second output signal of the second locking circuit. The second CPU control circuit sends a second normal signal to the CPU main control circuit based on the working state. The switching unit outputs a first locking signal based on the received first normal signal, first running signal, second normal signal, and second running signal. When the first locking signal output by the switching unit is a locking signal, the first control unit is locked and the second control unit is unlocked. When the first locking signal output by the switching unit is an unlocking signal, the second control unit is locked and the second control unit is locked. The locking signal is a low-level signal, and the unlocking signal is a high-level signal. When the CPU main control circuit receives the first normal signal and the first running signal as normal operation or running signal, it outputs the first working signal to the first interlock circuit. The first interlock circuit is turned on and outputs the first locking signal, while simultaneously turning off the second interlock circuit. At this time, the first locking signal output is a high-level signal. When the CPU main control circuit receives the second normal signal and the second running signal as normal operation or running signal, it outputs the second working signal to the second interlock circuit. The second interlock circuit is turned on and outputs the first locking signal while simultaneously turning off the first interlock circuit. At this time, the first locking signal output is a low-level signal. When the CPU main control circuit receives a signal indicating that one of the two control units is not working or is malfunctioning, the corresponding working signal will be at a low level to prevent the corresponding interlock circuit from conducting and automatically turn on the other interlock circuit, thereby achieving automatic switching of the inverter drive signal output.

[0014] In the aforementioned highly reliable inverter drive dual-backup control system and its switching method, a dual-backup control structure is adopted, consisting of a first control unit and a second control unit that serve as backups for each other. This allows for autonomous competition for output, and also enables immediate switching to the output of the other control unit in the event of a failure in one set of control units, significantly improving the system's reliability and stability. Furthermore, the switching mechanism employs a dual interlocking control system, consisting of circuit interlocking between the first and second control units and circuit interlocking control of the switching unit, ensuring the reliable and stable operation of the inverter drive. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall circuit structure of the high-reliability inverter drive dual backup control system provided in this embodiment of the invention.

[0016] Figure 2 yes Figure 1 A schematic diagram of the circuit principle of the first control unit of the high-reliability inverter drive dual backup control system.

[0017] Figure 3 yes Figure 1 A schematic diagram of the circuit principle of the second control unit of the high-reliability inverter drive dual backup control system.

[0018] Figure 4 yes Figure 1 A schematic diagram of the switching unit of a high-reliability inverter-driven dual-backup control system. Detailed Implementation

[0019] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0020] Please see Figure 1 , Figure 2 , Figure 3 and Figure 4 This invention illustrates a highly reliable inverter drive dual backup control system and its components provided by an embodiment of the present invention. The system includes a first control unit, a second control unit, and a switching unit. The first control unit and the second control unit serve as backups for each other and can output inverter drive signals when in operation. The switching unit can switch based on the operating states of the two control units. The first control unit includes a first CPU control circuit, a first locking circuit, a first state detection circuit, and a first drive control circuit, wherein the first drive control circuit has a first switching element; the second control unit includes a second CPU control circuit, a second locking circuit, a second state detection circuit, and a second drive control circuit, wherein the second drive control circuit has a second switching element; the switching unit includes a CPU main control circuit and a first interlock circuit and a second interlock circuit that are backups of each other. The first CPU control circuit is connected to the output terminal of the inverter drive signal through a first switching element. The first switching element is switched on and off under the control of the first drive control circuit. The first locking circuit has a first locking signal input terminal to receive a first locking signal from the switching unit and a second locking signal input terminal to receive a second locking signal from the second locking circuit. The output terminal of the first locking circuit is connected to the first state detection circuit and the first drive control circuit. The first state detection circuit outputs a first running signal to the CPU main control circuit based on the first output signal of the first locking circuit. The first drive control circuit outputs a first drive signal based on the first output signal of the first locking circuit to control the switching on and off of the first switching element. The second CPU control circuit is connected to the output terminal of the inverter drive signal via a second switching element. The second switching element is switched on and off under the control of the second drive control circuit. The second locking circuit has a first locking signal input terminal to receive a first locking signal from the switching unit or the first locking circuit. The output terminal of the second locking circuit is connected to the second state detection circuit and the second drive control circuit. The second state detection circuit outputs a second running signal to the CPU main control circuit based on the second output terminal signal of the second locking circuit. The second drive control circuit outputs a second drive signal based on the second output terminal signal of the second locking circuit to control the switching on and off of the second switching element. When the first CPU control circuit is working normally, it outputs a first normal signal. When the second CPU control circuit is working normally, it outputs a second normal signal. The CPU main control circuit receives the first normal signal and the first running signal and outputs a first working signal to the first interlock circuit. The CPU main control circuit receives the second normal signal and the second running signal and outputs a second working signal to the second interlock circuit. When one of the two working signals is working normally, the corresponding interlock circuit is turned on and outputs the first locking signal, while locking the other interlock circuit so that the other interlock circuit is not turned on. When the first locking signal output by the switching unit is a locking signal, the first control unit is locked and the second control unit is unlocked. When the first locking signal output by the switching unit is an unlocking signal, the second control unit is locked and the first control unit is unlocked. When the first locking signal output by the switching unit is an unlocking signal or the system is in the default initial state, the first locking circuit is in the unlocked state and provides a first drive signal to the first drive control circuit to turn on the first drive control circuit, provides a trigger signal to the first state detection circuit to output a first running signal, and provides a locking signal to the second locking circuit. Simultaneously, the second locking circuit is in the unlocked state and provides a second drive signal to the second drive control circuit to turn on the second drive control circuit, provides a trigger signal to the second state detection circuit to output a second running signal, and provides a locking signal to the first locking circuit, so that the output of the first control unit and the output of the second control unit are interlocked and compete autonomously, and one of the control units outputs the inverter drive signal. When the first locking signal output by the switching unit is a locking signal, the first locking circuit is in a locked state and the first drive control circuit is not turned on, the first state detection circuit does not output the first running signal, and the second locking circuit receives the unlocking signal. Simultaneously, the second locking circuit is in an unlocked state and provides a second drive signal to the second drive control circuit to turn on the second drive control circuit, provides a trigger signal to the second state detection circuit to output the second running signal, and provides a locking signal to the first locking circuit, so that the system outputs the inverter drive signal by the second control unit.

[0021] Specifically, when the first control unit malfunctions or fails to operate, it outputs a signal to the CPU main control circuit and / or the first state detection circuit does not output a first operating signal. The switching unit outputs a first locking signal to the first locking circuit and locks the first locking circuit, and outputs a first locking signal to the second locking circuit and unlocks the second locking circuit, so that the system outputs an inverter drive signal from the second control unit. When the second control unit malfunctions or fails to operate, it outputs a signal to the CPU main control circuit and / or the second state detection circuit does not output a second operating signal. The switching unit outputs a first locking signal to the first locking circuit and unlocks the first locking circuit, and outputs a first locking signal to the second locking circuit and locks the second locking circuit, so that the system outputs an inverter drive signal from the first control unit.

[0022] Furthermore, the first locking signal is either high or low. When the first locking signal is high, the first locking circuit is unlocked and the second locking circuit is locked. When the first locking signal is low, the second locking circuit is unlocked and the first locking circuit is locked. When the second locking signal is high, it is used to lock the first locking circuit and make the first locking signal low. When the second locking signal is low, the first locking circuit is unlocked and the second locking circuit is locked.

[0023] Further, each of the first and second locking circuits includes a power supply and a switching device. The power supply is connected to a corresponding state detection circuit and a drive control circuit. The input terminal of the switching device receives a corresponding locking signal, the second terminal is connected to the power supply, and the third terminal is grounded. When the locking signal received by the input terminal of the switching device in one of the locking circuits is high, the switching device in that locking circuit is in a conducting state, causing the power supply to be directly grounded and pulling down the voltage, thus locking the locking circuit with the switching device and providing the low level to the input terminal of the switching device in another locking circuit to unlock the other locking circuit. When the locking signal received by the input terminal of the switching device in one of the locking circuits is low, the switching device in that locking circuit is in a disconnected state, preventing the power supply from being pulled down and maintaining a high level, thus unlocking the locking circuit with the switching device and providing the high level to the input terminal of the switching device in another locking circuit to lock the other locking circuit.

[0024] Furthermore, each state detection circuit in the first state detection circuit and the second state detection circuit includes an operational amplifier and a detection Zener diode. The first lock signal is connected to the non-inverting input terminal of the operational amplifier, the inverting input terminal of the operational amplifier is connected to a predetermined voltage power supply, the output terminal of the operational amplifier is connected to one end of the cathode of the detection Zener diode, and the anode of the detection Zener diode is connected to the control ground GND. The cathode of the detection Zener diode serves as the output terminal of the first operating signal of the first state detection circuit.

[0025] Furthermore, the first CPU control circuit has a first switching output terminal to output a first switching signal. The first switching output terminal is connected to the input terminal of the first state detection circuit and the input terminal of the first drive control circuit via a first switching switch. The second CPU control circuit has a second switching output terminal to output a second switching signal. The second switching output terminal is connected to the input terminal of the second state detection circuit and the input terminal of the second drive control circuit via a second switching switch. After the first CPU control circuit or the second CPU control circuit operates, it outputs a first normal signal or a second normal signal to the switching unit accordingly, and outputs a high-level first switching signal or a second switching signal to the corresponding switching switch via the first switching output terminal and the second switching output terminal. The first switching switch and the second switching switch are preferably manual switches. Figures 1 to 3As shown, the first switching output terminal is LOCK1, the second switching output terminal is LOCK2, the first switching switch is SW1, and the second switching switch is SW2. Both switches also act as reset switches. When the system restarts or one of the active control units malfunctions, the switch of the other control unit is closed to directly input a high-level signal to the corresponding drive control circuit, thereby activating the corresponding CPU control circuit and outputting an inverter drive signal. Preferably, the two switches are manual switches. In the first control unit, the first CPU control circuit acquires DC and inverter signals, and based on the operating status and detection signals of the first CPU control circuit, outputs a first manual switching signal to the manual switching signal input terminal of the first locking circuit. This sets the first switching output terminal LOCK1 to a high level and resets and opens the first switching switch SW1, for example, manually. Similarly, in the second control unit, the second CPU control circuit acquires DC and inverter signals, and outputs a second manual switching signal to the manual switching signal input terminal of the second locking circuit based on the operating status and detection signals of the second CPU control circuit. This means setting the second switching output terminal LOCK2 to a high level and resetting and opening the second switching switch SW2, for example, manually opening it. By setting two manual switching switches, the main and backup order can be manually selected during normal operation of the control system. Specifically, when the first control unit is working normally, the first switching output terminal LOCK1 constantly outputs a high level; similarly, when the second control unit is working normally, the second switching output terminal LOCK2 constantly outputs a high level.

[0026] Furthermore, both the first drive control circuit and the second drive control circuit include a drive transistor, a drive Zener diode, and a relay; the corresponding lock signal passes through the cathode of the drive Zener diode and is connected from the anode of the drive Zener diode to the base of the drive transistor; the emitter of the drive transistor is connected to control ground GND; the collector of the drive transistor is connected to one end of the relay coil; the other end of the relay coil is connected to a preset power supply; one contact of the relay is connected to the corresponding CPU control circuit; and the normally open contact of the relay is the drive signal output terminal of the corresponding drive control circuit and outputs an inverter drive signal during operation.

[0027] Specifically, the two locking circuits preferably each have their own independent power supply. As shown in the figure, the switching device of the first locking circuit is the eleventh transistor 1Q1. The connection method of the first locking circuit is as follows: one end of the twelfth resistor 1R2, the thirteenth resistor 1R3 and the eleventh capacitor 1C1 is connected to the input terminal of the second locking signal of the first control unit; the other end of the thirteenth resistor 1R3 and the eleventh capacitor 1C1 is connected to the control ground GND; the other end of the twelfth resistor 1R2 is connected to the base of the eleventh transistor 1Q1; the emitter of the eleventh transistor 1Q1 is connected to the control ground GND; the collector of the eleventh transistor 1Q1 is connected to the auxiliary power supply VCC, i.e., the first power supply, through the eleventh resistor 1R1; and the collector of the eleventh transistor 1Q1 serves as the input terminal of the first locking signal. The connection method of the first drive control circuit is as follows: the first lock signal passes through the cathode of the Zener diode 1Z1 and is connected from the anode of the Zener diode 1Z1 to the base of the twelfth transistor 1Q2. The base of the twelfth transistor 1Q2 is connected to the control ground GND through the eighteenth resistor 1R8. The emitter of the twelfth transistor 1Q2 is connected to the control ground GND. The collector of the twelfth transistor 1Q2 is connected to one end of the coil of the first relay K1 and the anode of the eleventh diode 1D1. The other end of the coil of the first relay K1 and the cathode of the eleventh diode 1D1 are connected to the auxiliary power supply VCC. The normally open contact of the first relay K1 is the drive signal output terminal of the first drive control circuit, that is, the output terminal of the inverter drive signal of the first control unit. The connection method of the first state detection circuit is as follows: the first lock signal is connected to the non-inverting input terminal of the second operational amplifier U2. The non-inverting input terminal of the second operational amplifier U2 is connected to the output terminal of the second operational amplifier U2 through resistor 1R5. The inverting input terminal of the second operational amplifier U2 is connected to the auxiliary power supply VCC through resistor 1R4. The inverting input terminal of the second operational amplifier U2 is connected to the control ground GND through the sixteenth resistor 1R6 and the twelfth capacitor 1C2. The output terminal of the second operational amplifier U2 is connected to the cathode of the Zener diode 1Z2 and one end of the thirteenth capacitor 1C3 through the seventeenth resistor 1R7, and the other end of the Zener diode 1Z2 and the thirteenth capacitor 1C3 are connected to the anode of the Zener diode 1Z2 and the other end of the thirteenth capacitor 1C3. Connected to control ground GND, the cathode of Zener diode 1Z2 serves as the output terminal of the first state detection circuit, i.e., the first operating signal output terminal of the first control unit. In the first control unit, after the first CPU control circuit is working normally, it outputs the first normal signal M-1 to the switching unit and outputs a high-level switching control signal to the first switching switch SW1 of the first locking circuit. The other end of the first switching switch SW1 is connected to the output terminal of the first locking signal. The first CPU control circuit outputs the first inverter drive signal to one end of the normally open contact of the first relay K1 of the first drive control circuit. The normally open contact of the first relay K1 is the output terminal of the inverter drive signal of the first control unit.

[0028] As shown in the figure, in the second control unit, the switching device of the second locking circuit is the 21st transistor 2Q1. The connection method of the second locking circuit is as follows: one end of the 22nd resistor 2R2, the 23rd resistor 2R3, and the 21st capacitor 2C1 is connected to the first locking signal input terminal of the second control unit; the other end of the 23rd resistor 2R3 and the capacitor 2C1 is connected to the control ground GND terminal; the other end of the 22nd resistor 2R2 is connected to the base of the 21st transistor 2Q1; the emitter of the 21st transistor 2Q1 is connected to the control ground GND; the collector of the 21st transistor 2Q1 is connected to the auxiliary power supply VCC through the 21st resistor 2R1; and the collector of the 21st transistor 2Q1 serves as the output terminal of the second locking signal. The connection method of the second drive control circuit is as follows: the second lock signal passes through the cathode of the Zener diode 2Z1 and is connected from the anode of the Zener diode 2Z1 to the base of the 22nd transistor 2Q2. The base of the 22nd transistor 2Q2 is connected to the control ground GND through the 28th resistor 2R8. The emitter of the 22nd transistor 2Q2 is connected to the control ground GND. The collector of the 22nd transistor 2Q2 is connected to one end of the coil of the second relay K2 and the anode of the 21st diode 2D1. The other end of the coil of the second relay K2 and the cathode of the 21st diode 2D1 are connected to the second power supply. The normally open contact of the second relay K2 is the drive signal output terminal of the second drive control circuit, that is, the output terminal of the inverter drive signal of the second control unit. The connection method of the second state detection circuit is as follows: the second lock signal is connected to the non-inverting input terminal of the third operational amplifier U3. The non-inverting input terminal of the third operational amplifier U3 is connected to the output terminal of the third operational amplifier U3 through the twenty-fifth resistor 2R5. The inverting input terminal of the third operational amplifier U3 is connected to the auxiliary power supply VCC through the twenty-fourth resistor 2R4. The inverting input terminal of the third operational amplifier U3 is connected to the control ground GND through the twenty-sixth resistor 2R6 and the twenty-second capacitor 2C2. The output terminal of the third operational amplifier U3 is connected to the cathode of the Zener diode 2Z2 and one end of the twenty-third capacitor 2C3 through the resistor 2R7. The anode of the Zener diode 2Z2 and the other end of the twenty-third capacitor 2C3 are connected to the control ground GND. The cathode of the Zener diode 2Z2 serves as the output terminal of the second state detection circuit, that is, the second operating signal output terminal of the second control unit. In the second control unit, after the second CPU control circuit is working normally, it outputs the second normal signal M-2 to the switching unit and outputs a high-level switching control signal to the second switching switch SW2 of the second locking circuit. The other end of the second switching switch SW2 is connected to the output terminal of the second locking signal. The second CPU control circuit outputs the second inverter drive signal to one end of the normally open contact of the second relay K2 of the second drive control circuit. The normally open contact of the second relay K2 is the output terminal of the inverter drive signal of the second control unit.

[0029] Furthermore, in the switching unit, the CPU main control circuit outputs a first working signal WORK1 based on the first normal signal and the first running signal of the first control unit, and outputs a second working signal WORK based on the second normal signal and the second running signal of the second control unit.

[0030] The first interlock circuit includes a first NAND gate chip U1A, a second NOT gate chip U1B, a first interlock switch element, and a non-inverting drive circuit. The second interlock circuit includes a third NAND gate chip U1C, a fourth NAND gate chip U1D, a second interlock switch element, and an inverting drive circuit.

[0031] The first NAND gate chip U1A and the third NAND gate chip U1C are respectively configured such that when the input is high, the output is low and when the input is low, the output is cut off; the second NOT gate chip U1B and the fourth NAND gate chip U1D are respectively configured such that when the input is low, the output is high and when the input is high, the output is cut off; the input terminal of the first interlock switch element is connected to the first NAND gate chip U1A and the output terminal is connected to the fourth NAND gate chip U1D, the input terminal of the second interlock switch element is connected to the third NAND gate chip U1C and the output terminal is connected to the second NAND gate chip U1B; the output terminal of the first NAND gate chip U1A is connected to the input terminal of the second NOT gate chip U1B, the output terminal of the third NAND gate chip U1C is connected to the input terminal of the fourth NOT gate chip U1D, the output terminal of the second NOT gate chip U1B is connected to the input terminal of the non-inverting drive circuit, and the output terminal of the fourth NOT gate chip U1D is connected to the input terminal of the inverting drive circuit; the signals output by the output terminals of the non-inverting drive circuit and the inverting drive circuit are respectively the first locking signal.

[0032] The output signal of the first NAND gate chip U1A is connected to the input terminal of the first interlock switch element. The first interlock switch element is cut off when the input terminal is high and turned on when the input terminal is low, and inputs a high level to the fourth NAND gate chip U1D to turn off the fourth NAND gate chip U1D. The output signal of the third NAND gate chip U1C is connected to the input terminal of the second interlock switch element. The second interlock switch element is cut off when the input terminal is high and turned on when the input terminal is low, and inputs a high level to the second NAND gate chip U1B to turn off the second NAND gate chip U1B.

[0033] The first working signal WORK1 is connected to the input terminal of the first NAND gate chip U1A. When the first working signal WORK1 is high, the first NAND gate chip U1A outputs a low level and turns off the second switching element, turns on the second NAND gate U1B and outputs a high level, and outputs a high level through the non-inverting drive circuit. At this time, the first locking signal is high.

[0034] The second working signal WORK2 is connected to the input terminal of the third NAND gate chip U1C. When the second working signal WORK2 is high, the third NAND gate chip U1C outputs a low level and turns off the first switching element, turns on the fourth NAND gate U1D and outputs a high level, and outputs a low level through the inverting drive circuit. At this time, the first locking signal is low.

[0035] Furthermore, the first interlocking switching element is a first interlocking transistor Q1, and the second interlocking switching element is a second interlocking transistor Q2. Both interlocking MOSFETs are PNP transistors. The input terminals of the first interlocking switching element and the second interlocking switching element are both bases, and the output terminals of the first interlocking switching element and the second interlocking switching element are both collectors. The emitters of the first interlocking switching element and the second interlocking switching element are respectively connected to their respective interlocking power supplies. The non-inverting drive circuit includes a third transistor Q3 and a fifth transistor Q5, and the inverting drive circuit includes a fourth transistor Q4, a sixth transistor Q6, and a seventh transistor Q7. The third transistor Q3, the fourth transistor Q4, and the seventh transistor Q7 are all NPN transistors, and the fifth transistor Q5 and the sixth transistor Q6 are both PNP transistors.

[0036] Specifically, the output of the second NAND gate U1B is connected to the base of the third transistor Q3 via the seventh resistor R7. The emitter of the third transistor Q3 is connected to the control ground GND. The collector of the third transistor Q3 is connected to the base of the fifth transistor Q5 via the ninth resistor R9. The base of the fifth transistor Q5 is connected to the auxiliary power supply via the tenth pull-up resistor R10. The emitter of the fifth transistor Q5 is connected to the auxiliary power supply. The collector of the fifth transistor Q5 is connected to the output of the first lock signal of the switching unit via the thirteenth resistor R13. The output of the fourth NAND gate U1D is connected to the base of the fourth transistor Q4 via the eighth resistor R8. The emitter of the fourth transistor Q4 is connected to the control ground GND. The collector of the fourth transistor Q4 is connected to the base of the sixth transistor Q6 via the eleventh resistor R11; the base of the sixth transistor Q6 is connected to the auxiliary power supply via the twelfth pull-up resistor R12; the emitter of the sixth transistor Q6 is connected to the auxiliary power supply; the collector of the sixth transistor Q6 is connected to the base of the seventh transistor Q7 via the fourteenth resistor R14; the base of the seventh transistor Q7 is connected to the control ground GND via the fifteenth pull-down resistor R15; the emitter of the seventh transistor Q7 is connected to the control ground GND; and the collector of the seventh transistor Q7 is connected to the output terminal of the first lock signal (i.e., J1-LOCK) of the switching unit via the sixteenth resistor R16.

[0037] Another aspect of this invention provides a switching method for a reliable inverter-driven dual-backup control system, applicable to the high-reliability inverter-driven dual-backup control system described above. The method includes the following steps: In step S10, in the initial state or when powered on, the first locking circuit can output a locking signal to the second locking circuit, and at the same time, the second locking circuit can output a locking signal to the first locking circuit. The outputs of the first control unit and the second control unit are interlocked and compete autonomously, and one of the control units outputs the inverter drive signal.

[0038] In step S20, the first locking circuit provides an on / off signal to the first drive control circuit based on the second locking signal to determine whether the first CPU control circuit outputs an inverter drive signal. The first state detection circuit outputs a first operating signal to the CPU main control circuit based on the first output signal of the first locking circuit. The first CPU control circuit sends a first normal signal to the CPU main control circuit based on the working state. Specifically, when the second locking signal is high, the first control unit is locked, that is, the level in the first locking circuit is pulled low, the transistor in the first drive control circuit is not conducting, thereby turning off the output of the first control unit, and the second control unit outputs the inverter drive signal. Conversely, when the second locking signal is low, the first control unit is unlocked, that is, the transistor in the first locking circuit is turned off, the first power supply is maintained at a high level, the transistor in the first drive control circuit is turned on, thereby energizing the first relay K1 and the first control unit outputs, while the second control unit turns off its output.

[0039] In step S30, the second locking circuit provides an on / off signal to the second drive control circuit based on the first locking signal to determine whether the second CPU control circuit outputs an inverter drive signal. The second state detection circuit outputs a second operating signal to the CPU main control circuit based on the second output signal of the second locking circuit. The second CPU control circuit sends a second normal signal to the CPU main control circuit based on the working state. Similarly to step S20, when the first locking signal is high, the second control unit is locked, the transistor in the second locking circuit is turned on, i.e., the level in the second locking circuit is pulled low, and the transistor in the second drive control circuit is not turned on, thereby turning off the output of the second control unit and allowing the first control unit to output the inverter drive signal. Conversely, when the first locking signal is low, the second control unit is unlocked, i.e., the transistor in the second locking circuit is turned off, the second power supply is maintained at a high level, the transistor in the second drive control circuit is turned on, thereby energizing the first relay K1 and allowing the output of the second control unit to be turned on, while the first control unit turns off its output.

[0040] In step S40, the switching unit outputs a first locking signal based on the received first normal signal, first running signal, second normal signal, and second running signal. When the first locking signal output by the switching unit is a locking signal, the first control unit is locked and the second control unit is unlocked. When the first locking signal output by the switching unit is an unlocking signal, the second control unit is locked and the second control unit is locked. The locking signal is a low-level signal, and the unlocking signal is a high-level signal. The specific interlocking method is as described above and will not be repeated here.

[0041] Step S50: When the first normal signal and the first running signal received by the CPU main control circuit are normal operation or running signals, the first working signal is output to the first interlock circuit. The first interlock circuit is turned on and outputs the first locking signal, and at the same time, the second interlock circuit is turned off. At this time, the first locking signal output is a high-level signal. The high-level signal locks the second locking circuit, that is, it pulls down the second power supply in the second locking circuit, and the second relay K2 is in the off state. When the CPU main control circuit receives the second normal signal and the second running signal, which are normal operation or running signals, it outputs the second working signal to the second interlock circuit. The second interlock circuit is turned on and outputs the first locking signal, while simultaneously turning off the first interlock circuit. At this time, the output first locking signal is a low-level signal. The interlocking method for the first and second interlock circuits is as described above and will not be repeated here.

[0042] In step S60, when the CPU main control circuit receives a signal indicating that one of the two control units is not working or is malfunctioning, the corresponding operating signal is set to a low level to deactivate the corresponding interlock circuit and automatically activate the other interlock circuit, thereby automatically switching the output of the inverter drive signal. For example, if the first control unit fails, the second control power supply immediately provides the inverter drive signal output; if the second control unit fails, the output will immediately switch to the first control unit. The first and second control units ensure system redundancy.

[0043] In addition, as mentioned above, the first control unit and the second control unit are respectively equipped with a manual switching scheme. The operation mode of the manual selection circuit is as follows: when both the first control unit and the second control unit are normal, the control signal of the first switching output terminal LOCK1 of the first CPU control circuit and the control signal of the second switching output terminal LOCK2 of the second CPU control circuit are both set to high level; when the system is running, if the first control unit is in the main power supply state and the second control unit is in the standby state, the second control unit can be manually switched to the main power supply state by pressing the second switching switch SW2 of the second control unit, and the first control unit will automatically switch to the standby state; similarly, when the second control unit is in the main power supply output state, the first control unit can also be manually switched to the main power supply state by pressing the first switching switch SW1, and the second control unit will automatically switch to the standby state.

[0044] It should be noted that the present invention is not limited to the above-described embodiments. Based on the inventive spirit of the present invention, those skilled in the art can make other changes, and these changes made in accordance with the inventive spirit of the present invention should be included within the scope of protection claimed by the present invention.

Claims

1. A highly reliable inverter-driven dual-backup control system, characterized in that, It includes a first control unit, a second control unit, and a switching unit. The first control unit and the second control unit serve as backups for each other and can output inverter drive signals when in operation. The switching unit can switch based on the operating states of the two control units. The first control unit includes a first CPU control circuit, a first locking circuit, a first state detection circuit, and a first drive control circuit, wherein the first drive control circuit has a first switching element; the second control unit includes a second CPU control circuit, a second locking circuit, a second state detection circuit, and a second drive control circuit, wherein the second drive control circuit has a second switching element; the switching unit includes a CPU main control circuit and a first interlock circuit and a second interlock circuit that are backups of each other. The first CPU control circuit is connected to the output terminal of the inverter drive signal via a first switching element. The first switching element is switched on and off under the control of the first drive control circuit. The first locking circuit has a first locking signal input terminal to receive a first locking signal from the switching unit and a second locking signal input terminal to receive a second locking signal from the second locking circuit. The output terminal of the first locking circuit is connected to a first state detection circuit and a first drive control circuit. The first state detection circuit outputs a first running signal to the CPU main control circuit based on the first output signal of the first locking circuit. The first drive control circuit outputs a first drive signal based on the first output signal of the first locking circuit to control the switching on and off of the first switching element. The second CPU control circuit is connected to the output terminal of the inverter drive signal via a second switching element. The second switching element is switched on and off under the control of the second drive control circuit. The second locking circuit has a first locking signal input terminal to receive a first locking signal from the switching unit or the first locking circuit. The output terminal of the second locking circuit is connected to the second state detection circuit and the second drive control circuit. The second state detection circuit outputs a second running signal to the CPU main control circuit based on the second output signal of the second locking circuit. The second drive control circuit outputs a second drive signal based on the second output signal of the second locking circuit to control the switching on and off of the second switching element. When the first CPU control circuit is working normally, it outputs a first normal signal. When the second CPU control circuit is working normally, it outputs a second normal signal. The CPU main control circuit receives the first normal signal and the first running signal and outputs a first working signal to the first interlock circuit. The CPU main control circuit receives the second normal signal and the second running signal and outputs a second working signal to the second interlock circuit. When one of the two working signals is working normally, the corresponding interlock circuit is turned on and outputs the first locking signal, while locking the other interlock circuit so that the other interlock circuit is not turned on. When the first locking signal output by the switching unit is a locking signal, the first control unit is locked and the second control unit is unlocked. When the first locking signal output by the switching unit is an unlocking signal, the second control unit is locked and the first control unit is unlocked. When the first locking signal output by the switching unit is an unlocking signal or the system is in the default initial state, the first locking circuit is in the unlocked state and provides a first drive signal to the first drive control circuit to turn on the first drive control circuit, provides a trigger signal to the first state detection circuit to output a first running signal, and provides a locking signal to the second locking circuit. Simultaneously, the second locking circuit is in the unlocked state and provides a second drive signal to the second drive control circuit to turn on the second drive control circuit, provides a trigger signal to the second state detection circuit to output a second running signal, and provides a locking signal to the first locking circuit, so that the output of the first control unit and the output of the second control unit are interlocked and compete autonomously, and one of the control units outputs the inverter drive signal. When the first locking signal output by the switching unit is a locking signal, the first locking circuit is in a locked state and the first drive control circuit is not turned on, the first state detection circuit does not output the first running signal, and the second locking circuit receives the unlocking signal. Simultaneously, the second locking circuit is in an unlocked state and provides a second drive signal to the second drive control circuit to turn on the second drive control circuit, provides a trigger signal to the second state detection circuit to output the second running signal, and provides a locking signal to the first locking circuit, so that the system outputs the inverter drive signal by the second control unit.

2. The high-reliability inverter drive dual-backup control system as described in claim 1, characterized in that, When the first control unit malfunctions or fails to operate, it outputs a signal to the CPU main control circuit and / or the first status detection circuit does not output a first operating signal. The switching unit then outputs a first locking signal to the first locking circuit and locks the first locking circuit, and outputs a first locking signal to the second locking circuit and unlocks the second locking circuit, causing the system to output an inverter drive signal from the second control unit. When the second control unit malfunctions or fails to operate, it outputs a signal to the CPU main control circuit and / or the second status detection circuit does not output a second operating signal. The switching unit then outputs a first locking signal to the first locking circuit and unlocks the first locking circuit, and outputs a first locking signal to the second locking circuit and locks the second locking circuit, causing the system to output an inverter drive signal from the first control unit.

3. The high-reliability inverter drive dual-backup control system as described in claim 1, characterized in that, The first locking signal is either high or low. When the first locking signal is high, the first locking circuit is unlocked and the second locking circuit is locked. When the first locking signal is low, the second locking circuit is unlocked and the first locking circuit is locked. When the second locking signal is high, it is used to lock the first locking circuit and make the first locking signal low. When the second locking signal is low, it unlocks the first locking circuit and locks the second locking circuit.

4. The high-reliability inverter drive dual-backup control system as described in claim 3, characterized in that, Each of the first and second locking circuits includes a power supply and a switching device; The power supply is connected to the corresponding state detection circuit and drive control circuit. The input terminal of the switching device receives the corresponding lock signal, the second terminal is connected to the power supply, and the third terminal is grounded. When the lock signal received by the input terminal of the switching device in one of the lock circuits is high, the switching device in that lock circuit is in the conducting state, so that the power supply is directly grounded and the voltage is pulled low, so that the lock circuit with the switching device is in the locked state and the low level is provided to the input terminal of the switching device in another lock circuit to unlock the other lock circuit. When the lock signal received at the input of the switching device in one of the locking circuits is low, the switching device in that locking circuit is in an open state so that the power supply is not pulled down and is kept at a high level, so that the locking circuit with the switching device is in an unlocked state and provides the high level to the input of the switching device in another locking circuit to lock the other locking circuit.

5. The high-reliability inverter drive dual-backup control system as described in claim 4, characterized in that, Each state detection circuit in the first state detection circuit and the second state detection circuit includes an operational amplifier and a detection Zener diode. The first lock signal is connected to the non-inverting input terminal of the operational amplifier, the inverting input terminal of the operational amplifier is connected to a predetermined voltage power supply, the output terminal of the operational amplifier is connected to one end of the cathode of the detection Zener diode, and the anode of the detection Zener diode is connected to the control ground GND. The cathode of the detection Zener diode serves as the output terminal of the first operating signal of the first state detection circuit.

6. The high-reliability inverter drive dual-backup control system as described in claim 1, characterized in that, The first CPU control circuit has a first switching output terminal to output a first switching signal. The first switching output terminal is connected to the input terminal of the first state detection circuit and the input terminal of the first drive control circuit through a first switching switch. The second CPU control circuit has a second switching output terminal to output a second switching signal. The second switching output terminal is connected to the input terminal of the second state detection circuit and the input terminal of the second drive control circuit through a second switching switch. After the first CPU control circuit or the second CPU control circuit operates, it outputs a first normal signal or a second normal signal to the switching unit accordingly, and outputs a high-level first switching signal or a second switching signal to the corresponding switching switch through the first switching output terminal and the second switching output terminal. The first switching switch and the second switching switch are both manual switches.

7. The high-reliability inverter drive dual-backup control system as described in claim 1, characterized in that, Both the first drive control circuit and the second drive control circuit include a drive transistor, a drive Zener diode, and a relay. The corresponding lock signal passes through the cathode of the drive Zener diode and is connected from the anode of the drive Zener diode to the base of the drive transistor. The emitter of the drive transistor is connected to control ground (GND), the collector of the drive transistor is connected to one end of the relay coil, the other end of the relay coil is connected to a preset power supply, one contact of the relay is connected to the corresponding CPU control circuit, and the normally open contact of the relay is the drive signal output terminal of the corresponding drive control circuit and outputs an inverter drive signal during operation.

8. The high-reliability inverter drive dual-backup control system as described in claim 1, characterized in that, In the switching unit, the CPU main control circuit outputs a first working signal WORK1 based on the first normal signal and the first running signal of the first control unit, and outputs a second working signal WORK2 based on the second normal signal and the second running signal of the second control unit. The first interlock circuit includes a first NAND gate chip U1A, a second NOT gate chip U1B, a first interlock switch element, and a non-inverting drive circuit; the second interlock circuit includes a third NAND gate chip U1C, a fourth NAND gate chip U1D, a second interlock switch element, and an inverting drive circuit. The first NAND gate chip U1A and the third NAND gate chip U1C are respectively configured such that a high-level input results in a low-level output and a low-level input results in a cutoff signal; the second NOT gate chip U1B and the fourth NAND gate chip U1D are respectively configured such that a low-level input results in a high-level output and a high-level input results in a cutoff signal; the input terminal of the first interlock switch element is connected to the first NAND gate chip U1A and its output terminal is connected to the fourth NAND gate chip U1D; the input terminal of the second interlock switch element is connected to the third NAND gate chip U1C and its output terminal is connected to the second NAND gate chip U1B; the output terminal of the first NAND gate chip U1A is connected to the input terminal of the second NOT gate chip U1B; the output terminal of the third NAND gate chip U1C is connected to the input terminal of the fourth NOT gate chip U1D; the output terminal of the second NOT gate chip U1B is connected to the input terminal of the non-inverting drive circuit; and the output terminal of the fourth NOT gate chip U1D is connected to the input terminal of the inverting drive circuit; the signals output by the output terminals of the non-inverting drive circuit and the inverting drive circuit are respectively the first locking signal. The output signal of the first NAND gate chip U1A is connected to the input terminal of the first interlock switch element. The first interlock switch element is cut off when the input terminal is high and turns on when the input terminal is low, and inputs a high level to the fourth NAND gate chip U1D to turn off the fourth NAND gate chip U1D. The output signal of the third NAND gate chip U1C is connected to the input terminal of the second interlock switch element. The second interlock switch element is cut off when the input terminal is high and turns on when the input terminal is low, and inputs a high level to the second NAND gate chip U1B to turn off the second NAND gate chip U1B. The first working signal WORK1 is connected to the input terminal of the first NAND gate chip U1A; when the first working signal WORK1 is high, the first NAND gate chip U1A outputs a low level and turns off the second switching element, turns on the second NAND gate U1B and outputs a high level, and outputs a high level through the non-inverting drive circuit. At this time, the first locking signal is high. The second working signal WORK2 is connected to the input terminal of the third NAND gate chip U1C. When the second working signal WORK2 is high, the third NAND gate chip U1C outputs a low level and turns off the first switching element, turns on the fourth NAND gate U1D and outputs a high level, and outputs a low level through the inverting drive circuit. At this time, the first locking signal is low.

9. The high-reliability inverter drive dual-backup control system as described in claim 8, characterized in that, The first interlocking switch element is a first interlocking transistor Q1, and the second interlocking switch element is a second interlocking transistor Q2. Both interlocking MOSFETs are PNP transistors. The input terminals of the first interlocking switch element and the second interlocking switch element are both bases, and the output terminals of the first interlocking switch element and the second interlocking switch element are both collectors. The emitters of the first interlocking switch element and the second interlocking switch element are respectively connected to their respective interlocking power supplies. The non-inverting drive circuit includes a third transistor Q3 and a fifth transistor Q5, and the inverting drive circuit includes a fourth transistor Q4, a sixth transistor Q6, and a seventh transistor Q7. The third transistor Q3, the fourth transistor Q4, and the seventh transistor Q7 are all NPN transistors, and the fifth transistor Q5 and the sixth transistor Q6 are both PNP transistors. The output of the second NAND gate U1B is connected to the base of the third transistor Q3 via the seventh resistor R7. The emitter of the third transistor Q3 is connected to the control ground GND. The collector of the third transistor Q3 is connected to the base of the fifth transistor Q5 via the ninth resistor R9. The base of the fifth transistor Q5 is connected to the auxiliary power supply via the tenth pull-up resistor R10. The emitter of the fifth transistor Q5 is connected to the auxiliary power supply. The collector of the fifth transistor Q5 is connected to the output of the first lock signal of the switching unit via the thirteenth resistor R13. The output of the fourth NAND gate U1D is connected to the base of the fourth transistor Q4 via the eighth resistor R8. The emitter of the fourth transistor Q4 is connected to the control ground GND. The collector of the fourth transistor Q4 is connected to the base of the sixth transistor Q6 via the eleventh resistor R11; the base of the sixth transistor Q6 is connected to the auxiliary power supply via the twelfth pull-up resistor R12; the emitter of the sixth transistor Q6 is connected to the auxiliary power supply; the collector of the sixth transistor Q6 is connected to the base of the seventh transistor Q7 via the fourteenth resistor R14; the base of the seventh transistor Q7 is connected to the control ground GND via the fifteenth pull-down resistor R15; the emitter of the seventh transistor Q7 is connected to the control ground GND; and the collector of the seventh transistor Q7 is connected to the output terminal of the first lock signal of the switching unit via the sixteenth resistor R16.

10. A switching method for a reliable inverter-driven dual-backup control system, applicable to the high-reliability inverter-driven dual-backup control system as described in any one of claims 1-9, characterized in that, The method includes the following steps: In the initial state or when powered on, the first locking circuit can output a locking signal to the second locking circuit, and at the same time, the second locking circuit can output a locking signal to the first locking circuit. The outputs of the first control unit and the second control unit are interlocked and compete autonomously, with one of the control units outputting the inverter drive signal. The first locking circuit provides an on or off signal to the first drive control circuit based on the second locking signal to determine whether the first CPU control circuit outputs an inverter drive signal. The first state detection circuit outputs a first running signal to the CPU main control circuit based on the first output signal of the first locking circuit. The first CPU control circuit sends a first normal signal to the CPU main control circuit based on the working state. The second locking circuit provides an on or off signal to the second drive control circuit based on the first locking signal to determine whether the second CPU control circuit outputs an inverter drive signal. The second state detection circuit outputs a second running signal to the CPU main control circuit based on the second output signal of the second locking circuit. The second CPU control circuit sends a second normal signal to the CPU main control circuit based on the working state. The switching unit outputs a first locking signal based on the received first normal signal, first running signal, second normal signal, and second running signal. When the first locking signal output by the switching unit is a locking signal, the first control unit is locked and the second control unit is unlocked. When the first locking signal output by the switching unit is an unlocking signal, the second control unit is locked and the second control unit is locked. The locking signal is a low-level signal, and the unlocking signal is a high-level signal. When the CPU main control circuit receives the first normal signal and the first running signal as normal operation or running signal, it outputs the first working signal to the first interlock circuit. The first interlock circuit is turned on and outputs the first locking signal, while simultaneously turning off the second interlock circuit. At this time, the first locking signal output is a high-level signal. When the CPU main control circuit receives the second normal signal and the second running signal as normal operation or running signal, it outputs the second working signal to the second interlock circuit. The second interlock circuit is turned on and outputs the first locking signal while simultaneously turning off the first interlock circuit. At this time, the first locking signal output is a low-level signal. When the CPU main control circuit receives a signal indicating that one of the two control units is not working or is malfunctioning, the corresponding working signal will be at a low level to prevent the corresponding interlock circuit from conducting and automatically turn on the other interlock circuit, thereby achieving automatic switching of the inverter drive signal output.

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