Bias circuit, power amplifier and electronic device

Abstract

The application provides a bias circuit, a power amplifier and an electronic device. The bias circuit is applied to a power amplifier including multiple parallel power amplifier branches, and includes a direct current reference circuit, a multi-stage voltage dividing circuit and multiple bias control circuits corresponding to the branches; the direct current reference circuit outputs a constant reference current to provide a direct current bias basis; the multi-stage voltage dividing circuit is connected in series on a direct current loop to form multiple voltage dividing nodes with gradually decreasing potentials, and outputs multiple gradient direct current voltages; a direct current input end of each bias control circuit is connected to a corresponding voltage dividing node to receive a gradient direct current voltage to establish a static bias reference; the bias control circuit is further coupled with a radio frequency input port, dynamically adjusts an output bias voltage according to an input radio frequency signal power, and provides the voltage to a bias end of a corresponding branch; the bias circuit makes part of the branches conductive at low input power, and makes the branches conductive gradually according to preset thresholds as the input power increases.

Description

Technical Field

[0001] This application relates to power amplifier technology, and more particularly to a bias circuit, a power amplifier, and an electronic device. Background Technology

[0002] Power amplifiers are key components in wireless communication systems. Their bias circuits provide an appropriate quiescent operating point for the amplifying device, directly affecting the amplifier's linearity and efficiency. To improve efficiency while maintaining a certain level of linearity, the bias state typically needs to be designed appropriately based on the signal power characteristics.

[0003] In related technologies, to improve the efficiency of power amplifiers, a common approach is to reduce the quiescent bias current, allowing the power amplifier to operate in a shallow bias state, such as Class C, to reduce DC power consumption. At low input power, the bias circuit provides a fixed low quiescent current to the amplifier; as the input power increases, the amplifier gradually enters the normal amplification region through the self-biasing effect. This method is simple in structure and requires only one fixed bias circuit.

[0004] However, while the above-mentioned solutions reduce static bias current, they introduce gain expansion and phase distortion, leading to a significant deterioration in output signal linearity. Furthermore, the small-signal gain is insufficient under low static bias, limiting output power. A single-path bias architecture struggles to simultaneously achieve high efficiency and good linearity over a wide dynamic power range. Summary of the Invention

[0005] This application provides a bias circuit, a power amplifier, and an electronic device.

[0006] Firstly, a bias circuit is provided for use in a power amplifier. The power amplifier includes multiple power amplification branches connected in parallel. The bias circuit includes a DC reference circuit, a multi-stage voltage divider circuit, and multiple bias control circuits corresponding one-to-one with the multiple power amplification branches. The DC reference circuit outputs a constant reference current to provide a DC bias basis for the bias circuit. The multi-stage voltage divider circuit is connected in series in the DC loop of the DC reference circuit to form multiple voltage divider nodes with progressively decreasing potentials, thereby outputting multiple gradient DC voltages. Each of the bias control circuits... The DC input terminal of the circuit is connected to a corresponding voltage divider node to receive the DC voltage of the corresponding gradient to establish a static bias reference; the bias control circuit is also coupled to the RF input port of the power amplifier to dynamically adjust the output bias voltage according to the power of the input RF signal and provide the bias voltage to the bias terminal of the corresponding power amplification branch; the bias circuit is configured to: turn on some of the power amplification branches under low input power conditions, and turn on the multiple power amplification branches step by step according to a preset threshold as the input power increases.

[0007] In some embodiments, the DC reference circuit includes a constant current source and a diode reference circuit; the constant current source is used to provide a DC current with stable amplitude; the diode reference circuit includes a diode device or multiple diode devices connected in series, and the constant current source, the multi-stage voltage divider circuit and the diode reference circuit are connected in series to form a DC loop.

[0008] In some embodiments, the multi-stage voltage divider circuit includes a plurality of voltage divider resistor units connected in series, and the connection point of two adjacent voltage divider resistor units constitutes the voltage divider node; the DC potential of each voltage divider node and the turn-on threshold of the corresponding power amplification branch are jointly determined by the resistance ratio of each voltage divider resistor unit.

[0009] In some embodiments, the voltage divider resistor unit is a resistor device; along the current flow direction, the DC potential of each voltage divider node decreases step by step, and the static bias voltage output by each bias control circuit gradually decreases.

[0010] In some embodiments, the bias control circuit includes an emitter follower bias unit and an RF coupling unit; the emitter follower bias unit is used to output a static bias voltage to the corresponding power amplifier branch based on the DC voltage of the voltage divider node; the RF coupling unit is used to couple the input RF signal to the bias circuit, and use the rectification effect of the transistor emitter junction to make the output bias voltage dynamically increase as the input power increases.

[0011] In some embodiments, the emitter follower bias unit is a bias transistor; the base of the bias transistor is connected to the corresponding voltage divider node, the collector is connected to the power supply, and the emitter is connected to the bias terminal of the corresponding power amplifier branch via an emitter resistor; the base of the bias transistor is also connected in parallel to ground with a bypass capacitor, which is used to provide a low impedance path for the radio frequency signal.

[0012] In some embodiments, the RF coupling unit includes an input DC blocking capacitor connected in series between the RF input port and the bias terminal of the power amplification branch; at least one of the bias control circuits further includes an enhancement coupling capacitor; the enhancement coupling capacitor is connected across the RF input port and the emitter of the bias transistor to directly couple RF energy, thereby improving the turn-on response speed of the corresponding power amplification branch.

[0013] In some embodiments, the plurality of power amplification branches include a first power amplification branch and a second power amplification branch; the first power amplification branch corresponds to the voltage divider node with the highest potential, operates in a Class AB amplification state under static conditions, and remains on within the full power range; the second power amplification branch corresponds to the voltage divider node with a lower potential, is in a near-cutoff state under static conditions, and gradually turns on after the input power reaches a first threshold.

[0014] In a second aspect, a power amplifier is provided, comprising at least two power amplification branches connected in parallel and a bias circuit as described in the first aspect; the bias terminal of each power amplification branch is respectively connected to the output terminal of a bias control circuit in the bias circuit, the RF input terminal of each power amplification branch is connected to the input RF signal, and the output terminals of all power amplification branches are connected in parallel to form the RF output port of the power amplifier; the bias circuit provides a gradient-distributed static bias level for each power amplification branch, and dynamically adjusts the bias state of each branch according to the magnitude of the RF input power, so that each power amplification branch is turned on step by step according to a preset threshold as the input power increases.

[0015] Thirdly, an electronic device is provided, comprising: a bias circuit as described in the first aspect, or comprising at least one power amplifier as described in the second aspect.

[0016] The technical solutions provided by the embodiments of this application may include the following beneficial effects: The bias circuit provided by the embodiments of this application, through the cooperation of DC reference circuit, multi-stage voltage divider circuit and multi-channel bias control circuit, realizes the gradient bias and step-by-step conduction of multiple power amplification branches. In the low power state, only some branches are conducted, the static current is significantly reduced, and the power back-off efficiency is effectively improved; in the high power state, all branches are conducted step-by-step, ensuring the output power.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] Figure 1 This is a schematic diagram of the bias circuit provided in the embodiments of this application. Figure 1 ; Figure 2 This is a schematic diagram of the bias circuit provided in the embodiments of this application. Figure 2 ; Figure 3 This is a schematic circuit of the bias circuit provided in the embodiments of this application. Figure 1 ; Figure 4 This is a schematic circuit of the bias circuit provided in the embodiments of this application. Figure 2 . Detailed Implementation

[0020] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0021] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0022] If similar descriptions such as "first / second" appear in the published documents, the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0023] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0024] Power amplifiers are key components in wireless communication systems. Their bias circuits provide an appropriate quiescent operating point for the amplifying device, directly affecting the amplifier's linearity and efficiency. To improve efficiency while maintaining a certain level of linearity, the bias state typically needs to be designed appropriately based on the signal power characteristics.

[0025] In current RF power amplifier designs, to improve efficiency at low output power, the industry commonly attempts to reduce the static bias current of the power amplifier transistors, causing them to operate in Class C or near-cutoff mode. However, excessively low static bias severely degrades the amplifier's linearity and leads to a decrease in output power capability. Although traditional Class AB bias schemes can achieve a good balance between linearity and peak power, their efficiency performance in the high power back-off region has reached a bottleneck, making it difficult to meet the increasingly stringent requirements of modern communication systems for the battery life of terminal devices. Therefore, the contradiction between static bias current and linearity / efficiency has become a pressing technical problem that needs to be solved in this field.

[0026] To address the aforementioned problems, embodiments of this application provide a bias circuit, a power amplifier, and an electronic device. Embodiments of this application construct a bias circuit capable of outputting multiple gradient DC voltages. This circuit provides a constant reference current through a DC reference circuit and utilizes a multi-stage voltage divider circuit connected in series in its loop to form multiple voltage divider nodes with progressively decreasing potentials. Each bias control circuit acquires the DC voltage of one voltage divider node as a static bias reference and simultaneously couples it with an input RF signal, enabling its output bias voltage to be dynamically adjusted according to the input power. By configuring this gradient distribution of dynamic bias for multiple parallel power amplifier branches, a step-by-step conduction mechanism that varies with input power is achieved: when the input power is low, only some branches with higher bias voltages are in the conducting state, while the remaining branches remain in a near-off state, thereby significantly reducing the overall quiescent current and greatly improving power back-off efficiency; as the input power gradually increases, each power amplifier branch is turned on sequentially according to its preset bias threshold, and the subsequently turned-on branches exhibit gain expansion characteristics, compensating for the gain compression that occurs in the first-turned AB-class branches, thus widening the high output power range while compensating for amplitude distortion (AM-AM), achieving a technical effect that balances high linearity and high efficiency.

[0027] Figure 1This is a schematic diagram of the bias circuit 100 provided in an embodiment of this application. The bias circuit 100 is applied to a power amplifier 200, which includes multiple power amplification branches PA1, PA2, ..., PAn connected in parallel. In other words, the power amplifier 200 used in this application is a multi-channel parallel amplification structure formed by multiple power amplification units connected in parallel. Each power amplification branch has an independent RF input terminal and an RF output terminal. The input RF signal is simultaneously distributed to each power amplification branch, and each branch amplifies the signal and then performs power combining at the output terminal to jointly output the amplified RF signal. In this embodiment, each power amplification branch can be multiple smaller transistor units obtained by splitting a large power transistor. Each transistor unit is independently biased and operates independently, collectively forming a complete power amplifier.

[0028] Figure 1 The bias circuit 100 includes a DC reference circuit 110, a multi-stage voltage divider circuit 120, and multi-channel bias control circuits 130A, 130B, ..., 130N corresponding to multiple power amplifier branches PA1, PA2, ..., PAn.

[0029] The DC reference circuit 110 outputs a constant reference current, providing the DC bias basis for the bias circuit 100. The subsequent voltage divider node voltages and the bias reference of the bias control circuit are all based on the voltage drop generated by this constant current flowing through the multi-stage resistors in the multi-stage voltage divider circuit 120. For example, a constant reference current flowing through a series resistor network with a total resistance of 5KΩ produces a stable total voltage drop (e.g., 5V), thus forming the DC bias basis of the entire bias network.

[0030] A multi-stage voltage divider circuit 120 is connected in series in the DC loop of the DC reference circuit 110. In other words, the multi-stage voltage divider circuit 120 is connected in series between the DC source and the reference ground of the DC reference circuit 110, forming part of the DC loop. The multi-stage voltage divider circuit 120 forms voltage divider nodes P1, P2, ..., Pn with progressively decreasing potentials to output multiple gradient DC voltages.

[0031] The multiple voltage divider nodes P1, P2, ..., Pn mentioned in the embodiments of this application refer to the physical connection points at the ends of each impedance element in the multi-stage voltage divider circuit 120, starting from the first impedance element into which a constant reference current flows, and the characteristic that the potential of each voltage divider node decreases in a step-like manner relative to the reference ground.

[0032] Taking a voltage divider circuit consisting of four equal resistors (R) connected in series as an example, a constant current I is injected from the top. The potential of the first voltage divider node (top node) is I4R; the potential of the second voltage divider node is I3R; the third is I2R; and the potential of the last node is IR or directly grounded. The above structure forms multiple voltage divider nodes with progressively decreasing potentials, each decreasing by a step size of IR.

[0033] For example, the resistance values ​​can be set to differentiated ratios to obtain non-uniform gradient voltages. For instance, if R1=R, R2=2R, and R3=3R, the voltage attenuation between each voltage divider node will increase with the number of stages, forming a non-linear potential decreasing law at each stage.

[0034] Correspondingly, multi-gradient DC voltage refers to a set of DC voltages that are drawn from voltage divider nodes that decrease in potential between multiple potentials, forming a stepped distribution or a distribution with a specific proportion.

[0035] The gradient DC voltages output by the aforementioned voltage divider nodes P1, P2, ..., Pn are connected to the DC input terminals of each bias control circuit, establishing a static bias reference for each bias control circuit. In this embodiment, the static bias reference refers to the gradient DC voltage received by the bias control branch when there is no RF signal input or the RF signal power is low. This gradient DC voltage determines the initial DC potential of the base or gate of the power amplifier transistor within the corresponding power amplifier branch, thereby determining whether the branch is initially in a conducting state, a near-cutoff state, or a completely off state.

[0036] In this embodiment, each bias control circuit includes at least one DC input terminal 131, one RF input terminal 132, and one bias voltage output terminal 133. The bias control circuit can be an emitter follower bias unit, constructed from an NPN transistor. The collector of the transistor is connected to the power supply Vcc, the base serves as the DC input terminal 131 connected to a voltage divider node to receive the gradient DC voltage Vb, and the emitter serves as the bias voltage output terminal 133. When there is no RF signal, the bias control circuit can output a stable DC bias voltage.

[0037] The RF input terminal 132 of the bias control circuit is coupled to the RF input port RFIN of the power amplifier. This coupling is used to couple the energy of the input RF signal and dynamically adjust the output bias voltage according to the power of the input RF signal, providing this bias voltage to the bias terminal of the corresponding power amplification branch. The physical mechanism of this dynamic adjustment is that when the positive half-cycle of the RF signal voltage is superimposed on the base of the transistor in the bias control circuit, the equivalent DC potential of the base is instantaneously raised, driving the active device into a stronger conduction state. This, in turn, through rectification or averaging effects, raises the bias voltage at the output terminal. For example, in a bias control circuit with a transistor as its core, as the input RF power increases from 0dBm to 10dBm, the RF voltage swing at the transistor base increases. This results in an increase in the average rectified current flowing through the base-emitter junction within one cycle, which is equivalent to an increase in the average DC potential of the base, thus raising the bias voltage output from the emitter.

[0038] Based on the above circuit structure, the entire circuit is configured to realize a step-by-step conduction mechanism for power changes. Under low input power conditions, the power amplifier branch with the highest static bias reference voltage is in the conducting state, generating effective RF output power; while the power amplifier tubes of the other branches with lower static bias reference voltages are in the cutoff or near-cutoff state, consuming almost no static power.

[0039] As the input power continues to increase from the low operating condition, the voltage swing of the RF signal increases. When the input power crosses the preset threshold of a certain branch, the dynamic bias voltage of that branch will break through the turn-on voltage of the power transistor, causing the branch to change from an inactive state to a conducting state and begin to amplify the RF signal.

[0040] A preset threshold is a predefined and designed input RF power threshold that switches a specific power amplifier branch from a non-conducting state to a conducting state. This preset threshold is determined by the static bias reference of the power amplifier branch, the threshold voltage of the power transistor, and the dynamic response gain of the bias control circuit. For example, the preset turn-on threshold of the PA2 branch is +5dBm input power. When the input power rises to +5dBm, the dynamic bias voltage of PA2 exactly reaches the turn-on voltage of the PA2 power transistor, 1.25V, and PA2 begins to conduct. The gain of PA2 increases rapidly from zero, resulting in gain expansion. As another example, in a four-channel system, the preset threshold is designed in steps of +2dBm, +6dBm, and +10dBm. A new branch joins the operation with each 4dB increase, smoothly compensating for the compression of the overall gain.

[0041] In the embodiments of this application, the aforementioned step-by-step conduction process is automatically completed by the bias circuit at the hardware level, without the need for external digital control circuit intervention. For example, in a three-way parallel system, when the input power is 0dBm, only PA1 operates in Class AB, exhibiting high linearity; when the input power increases to 6dBm, PA1 tends to be in a gain compression state, while the dynamic bias voltage of PA2 exceeds the turn-on threshold of PA2, starting to conduct and exhibiting gain expansion, which at this time just compensates for the compression of PA1; when the input power further increases to 12dBm, PA3 also reaches the preset threshold of PA3 and starts to conduct, further compensating for the possible total gain compression. This three-way coordinated operation mode enables the entire amplifier to have excellent linearity in the high, medium, and low power ranges.

[0042] Based on the above technical means, through the cooperation of DC reference circuit 110, multi-stage voltage divider circuit 120 and multi-channel bias control circuit 130A, 130B, ..., 130N, gradient bias and step-by-step conduction of multiple power amplifier branches are realized. In the low power state, only some branches are conducted, the static current is significantly reduced, and the power back-off efficiency is effectively improved. In the high power state, all branches are conducted step by step, ensuring the output power.

[0043] In some embodiments, see Figure 1 The DC reference circuit 110 includes a constant current source 111 and a diode reference circuit 112.

[0044] The constant current source 111 is an electronic circuit or device that can output a constant current. The magnitude of the output current of the constant current source 111 does not fluctuate significantly with changes in load impedance or supply voltage. In this embodiment, the constant current source 111 can provide a stable and accurate reference current for the subsequent diode reference circuit 112 and the multi-stage voltage divider circuit 120, thereby ensuring that the multiple reference voltages generated by the entire bias network are stable and reliable.

[0045] The diode reference circuit 112 includes a diode device or diode devices connected in series. The diode reference circuit 112 can use the relatively stable voltage drop of the diode PN junction when it is forward-conducting as a reference voltage.

[0046] The aforementioned constant current source 111, multi-stage voltage divider circuit 120, and diode reference circuit 112 are connected in series to form a DC loop. More specifically, the output terminal of the constant current source 111 is connected to one end of the multi-stage voltage divider circuit 120, the other end of the voltage divider circuit is connected to the positive terminal of the diode reference circuit 112, and the negative terminal of the diode reference circuit 112 is connected to ground (or the loop terminal of the constant current source 111), thus forming a complete current loop.

[0047] The stable DC provided by the constant current source 111 generates a voltage drop across each resistor node of the multi-section voltage divider circuit and across the diode of the diode reference circuit 112. This voltage drop is then led out to provide different bias voltages for different power amplifier transistors.

[0048] According to the above-mentioned technical means, by setting up a diode reference circuit 112 containing diode devices, and connecting the diode reference circuit 112, constant current source 111, and multi-stage voltage divider circuit 120 in series to form a closed DC loop, the stable forward voltage drop of the diode can be used as a precise voltage reference, and the stable current of the constant current source 111 can be converted into multiple stable and precise bias voltages through the closed loop, thereby providing appropriate static operating points for different power amplifier transistors.

[0049] In some embodiments, see Figure 2 The multi-stage voltage divider circuit 120 includes multiple voltage divider resistor units 121A, 121B, ..., 121N arranged in series, and the connection point of two adjacent voltage divider resistor units forms a voltage divider node.

[0050] In the embodiments of this application, the voltage divider resistor unit can be composed of a single resistor, or it can be composed of an equivalent resistance network formed by multiple resistors connected in series, parallel, or a combination thereof. The resistance value of the voltage divider resistor unit determines the magnitude of the voltage drop generated across the voltage divider resistor unit, thereby directly affecting the potential at the voltage divider node.

[0051] The specific implementation methods of the aforementioned voltage divider resistor unit include, but are not limited to, high-precision thin-film resistors, adjustable resistors, or digital potentiometers. Among them, high-precision thin-film resistors have a low temperature coefficient and are suitable for scenarios with high voltage accuracy requirements; the resistance or potentiometer value of adjustable resistors or digital potentiometers can be adjusted by electrical signals, making them suitable for flexible application scenarios that require dynamic adjustment of bias voltage.

[0052] A voltage divider node is an electrical connection point where multiple voltage divider resistor units 121A, 121B, ..., 121N are connected in series. It is a voltage output port. The potential value of a voltage divider node is determined by the ratio of the sum of the resistances of all voltage divider resistor units between the voltage divider node and the reference ground to the total loop resistance. For example, in a circuit consisting of three voltage divider resistor units R1, R2, and R3 connected in series, the high-potential terminal of R1 is connected to the power supply Vcc, and the low-potential terminal of R3 is grounded. The connection point of R1 and R2 forms the first voltage divider node, and the voltage of the first voltage divider node is Vcc(R2+R3) / (R1+R2+R3); the connection point of R2 and R3 forms the second voltage divider node, and the voltage of the second voltage divider node is Vcc(R3) / (R1+R2+R3).

[0053] In the embodiments of this application, the current potential of each voltage divider node and the turn-on threshold of the corresponding power amplification branch are related to the resistance ratio of each voltage divider resistor unit.

[0054] DC potential refers to the stable voltage value of a point in a circuit relative to a reference point (usually ground) under DC operating conditions. In this embodiment, it refers to the static DC voltage output at each voltage divider node, used to bias the corresponding power amplifier branch. The DC potential determines the initial operating state of the transistors in the power amplifier branch when there is no RF signal input.

[0055] The turn-on threshold is the minimum input bias voltage required for a transistor in a power amplifier branch to transition from the cutoff region or a weakly conducting state to the turn-on or significantly conducting state. For example, for a bipolar junction transistor (BJT), the turn-on threshold is approximately the base-emitter turn-on voltage, typically around 0.7V.

[0056] The resistance ratio refers to the relative proportional relationship between the resistance values ​​of each voltage divider resistor unit in the multi-stage voltage divider circuit 120. By reasonably adjusting the resistance ratio of each voltage divider resistor unit, the DC potential of each voltage divider node can be precisely set so that the DC potential of each voltage divider node forms a specific relationship with the turn-on threshold of the corresponding power amplifier branch. For example, the voltage of a certain node can be made slightly lower than the turn-on threshold of the corresponding power amplifier branch to achieve the initial off state of the power amplifier branch; or slightly higher than the threshold to achieve the initial on state of the power amplifier branch.

[0057] For example, in an amplifier with two power amplification branches, the first power amplification branch needs to be always biased in Class AB mode. Since the turn-on threshold of the first power amplification branch is 0.7V, the DC potential of the first voltage divider node can be set to 0.75V, making the DC potential of the first voltage divider node greater than the turn-on threshold and thus turning it on. The second power amplification branch needs to be turned off when the signal is low to save power. The turn-on threshold of the second power amplification branch is also 0.7V. Therefore, the DC potential of the second voltage divider node can be set to 0.5V, making the DC potential of the second voltage divider node lower than the turn-on threshold and thus turning it off. When the input power increases, due to the self-biasing effect generated by the bias circuit 100, the effective bias voltage of the second power amplification branch is increased to above 0.7V, causing the second power amplification branch to gradually turn on, achieving gain expansion.

[0058] Based on the above technical means, by adjusting the resistance ratio of the voltage divider resistor unit, the static bias level and turn-on threshold of each power amplifier branch can be flexibly configured, so as to achieve precise control over the sequential conduction and power distribution ratio of multiple branches.

[0059] Figure 3The schematic circuit diagram of the bias circuit 100 provided in this application embodiment, in some embodiments, such as Figure 3 As shown, the voltage divider resistor unit is a resistor device, which can be a fixed-value chip resistor, a metal film resistor, a wire-wound resistor, a variable resistor with adjustable resistance, or a digital potentiometer, etc.

[0060] The aforementioned resistors R1, R2, ..., Rn are connected in series. When powered by a DC power supply, each voltage divider resistor unit draws a portion of the voltage along the current flow direction, causing the DC potential of each voltage divider node to be lower than the DC potential of the previous voltage divider node. In other words, the DC potential of each voltage divider node decreases progressively along the current flow direction. Correspondingly, the static bias voltage of the bias control circuit connected to the lower potential voltage divider node will be lower than the static bias voltage output by the bias control circuit connected to the higher potential voltage divider node. For example, the bias control circuit corresponding to the first voltage divider node may output a higher static bias voltage, biasing the corresponding first power amplifier branch in Class AB state; the bias control circuit of the second voltage divider node outputs a lower static bias voltage, initially keeping the corresponding second power amplifier branch in a cutoff or deep Class C state, gradually turning it on as the input power increases.

[0061] In some embodiments, see Figure 2 The bias control circuit includes an emitter follower bias unit 131 and an RF coupling unit 132.

[0062] The emitter follower bias unit 131 is used to output a static bias voltage to the corresponding power amplifier branch based on the DC voltage of the voltage divider node. More specifically, the voltage divider node provides the DC voltage of the voltage divider node to the emitter follower bias unit 131. The emitter follower bias unit 131 utilizes the emitter follower characteristic of the transistor, that is, the base voltage and emitter voltage differ only by the forward conduction voltage drop of the PN junction, and has the characteristics of high input impedance and low output impedance. After impedance transformation, the DC voltage of the voltage divider node is output as the static bias voltage to the power amplifier branch.

[0063] The RF coupling unit 132 couples the input RF signal to the bias circuit, utilizing the rectification effect of the transistor's emitter junction to dynamically increase the output bias voltage as the input power increases. Specifically, the RF signal, through coupling elements such as capacitors, injects a portion of the input RF signal energy into the bias circuit. The injected RF signal, combined with the original static bias voltage, acts on the emitter junction of the transistor in the power amplifier branch. Due to the rectification effect of the transistor's emitter junction, the superimposed RF signal is rectified, generating a DC component proportional to the RF signal amplitude. This DC component is superimposed on the original static bias voltage, resulting in a dynamic increase in the final output bias voltage. The higher the input power and the greater the RF signal amplitude, the larger the rectified DC component, and the higher the bias voltage rise.

[0064] Based on the above technical means, the emitter follower bias unit 131 provides a stable static bias basis, and the radio frequency coupling unit 132 realizes the dynamic rise of the bias voltage with the input power. The combination of the two enables the bias control circuit to have a stable static operating point and to adjust the bias state in real time according to the input power.

[0065] See in some embodiments Figure 3 The aforementioned emitter follower bias unit 131 is a bias transistor D1. The base of the bias transistor D1 is connected to the corresponding voltage divider node, the collector is connected to the power supply, and the emitter is connected to the bias terminal of the corresponding power amplifier branch via the emitter resistor Ra.

[0066] The bias transistor D1 is the core active device constituting the emitter follower bias unit 131. Operating in the amplification region, D1 utilizes the clamping characteristic of the base-emitter voltage to provide a stable bias voltage for the power amplification branch. The reference voltage signal output from the voltage divider node is input through the base of the bias transistor D1, controlling its emitter current. The power supply provides the collector operating voltage for D1. The emitter current flows through the emitter resistor to generate the bias voltage, which is ultimately transmitted to the bias terminal of the power amplification branch, completing the transfer and transformation from the reference voltage to the bias voltage.

[0067] The bias transistor D1 can be an NPN bipolar transistor or a PNP bipolar transistor. In this embodiment, an NPN transistor is used as an example. The bias transistor D1 has the characteristics of high input impedance and low output impedance, which can effectively isolate the load effect between the voltage divider node and the power amplifier branch.

[0068] The base of the bias transistor D1 is also connected in parallel with a bypass capacitor C1 to ground. The bypass capacitor C1 is connected in parallel between the base of the bias transistor D1 and ground. Its impedance decreases as the frequency increases, which can bypass the radio frequency signal to ground and prevent the radio frequency signal from entering the bias circuit 100 and causing interference or modulation.

[0069] In some embodiments, continue reading Figure 3 The radio frequency coupling unit 132 includes an input DC blocking capacitor C2, which is connected in series between the radio frequency input port RFIN and the bias terminal of the power amplifier branch to form a high-pass filter path. This can block the DC bias current from passing through while transmitting radio frequency signals, preventing the DC bias voltage from interfering with the preceding circuit or signal source.

[0070] In the embodiments of this application, at least one bias control circuit among the multiple bias control circuits 130A, 130B, ..., 130N further includes an enhanced coupling capacitor C3, which is connected between the RF input port RFIN and the emitter of the bias transistor D1, for directly coupling RF energy to improve the turn-on response speed of the corresponding power amplifier branch.

[0071] More specifically, the enhanced coupling capacitor C3 provides an additional, low-impedance coupling path for the radio frequency (RF) signal, directly injecting some RF energy into the emitter of the bias transistor D1. Thus, when a high-power RF signal is input, the strong RF energy acts directly on the bias transistor D1 through the enhanced coupling capacitor C3, causing a rapid change in the emitter voltage of D1. This accelerates the transition of the power amplifier branch (such as PA2) controlled by D1 from the off state to the on state, thereby improving the turn-on response speed of the power amplifier branch.

[0072] Figure 4 This is a circuit diagram of a bias circuit 100 provided in another embodiment of this application, applied... Figure 4 The bias circuit 100 and the power amplifier 200 include a first power amplifier branch PA1 and a second power amplifier branch PA2.

[0073] Correspondingly, the multi-stage voltage divider circuit 120 includes two voltage divider nodes P1 and P2. The first power amplifier branch PA1 corresponds to the high-potential voltage divider node P1, and operates in Class AB amplification mode under static conditions, remaining on across the full power range. The power transistor area of ​​the first power amplifier branch PA1 can be half that of the conventional scheme, and its static bias is relatively high, providing the main signal amplification in low-power and medium-power states.

[0074] The second power amplifier branch PA2 corresponds to the low-potential voltage divider node P2, which is in a near-off state (close to Class C) under static conditions. It gradually turns on after the input power reaches the first threshold. The power transistor area of ​​the second power amplifier branch PA2 can also be half that of the traditional scheme. Its static bias is low, and it remains off in the low-power state, saving static power consumption. When the input power increases to a certain level, the bias voltage provided by the bias control circuit rises rapidly, causing the second power amplifier branch to gradually turn on.

[0075] In the first power amplifier branch PA1, the output gain gradually decreases (gain collapse) as the input power increases. In the second power amplifier branch PA2, the gain increases with the input power after it is turned on (gain expansion), and the gain changes of the two branches are opposite. After the output signals of the two branches are superimposed, the gain changes cancel each other out, thereby improving the AM-AM linearity of the overall amplifier.

[0076] Based on the bias circuit 100 provided in the above embodiments, this application also provides a power amplifier, which includes at least two power amplification branches connected in parallel and the bias circuit 100 as described in any of the preceding embodiments.

[0077] The bias terminals of each power amplifier branch are respectively connected to the output terminal of one bias control circuit in the bias circuit 100. The RF input terminals of each power amplifier branch are connected to the input RF signal. The output terminals of all power amplifier branches are connected in parallel to each other to form the RF output port of the power amplifier. The bias circuit 100 provides a gradient-distributed static bias level for each power amplifier branch and dynamically adjusts the bias state of each branch according to the magnitude of the RF input power, so that each power amplifier branch is turned on step by step according to a preset threshold as the input power increases.

[0078] This application also provides an electronic device that includes the bias circuit 100 and / or the aforementioned power amplifier described in any of the preceding embodiments. This electronic device can be any electronic device requiring radio frequency power amplification, such as a mobile phone, tablet computer, wireless router, base station, IoT device, or smart home device. By integrating the aforementioned bias circuit 100 and / or power amplifier into the electronic device, the device's radio frequency performance and signal transmission quality can be improved.

[0079] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0080] It is understood that in this disclosure, "multiple" refers to two or more, and other quantifiers are similar. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. The singular forms "a," "the," and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0081] It is further understood that the terms "first," "second," etc., are used to describe various types of information, but this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another, and do not indicate a specific order or degree of importance. In fact, expressions such as "first," "second," etc., are completely interchangeable.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0083] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0084] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0085] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can read or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0086] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0087] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A bias circuit, characterized in that, Applied to a power amplifier, the power amplifier includes multiple power amplification branches arranged in parallel, and the bias circuit includes a DC reference circuit, a multi-stage voltage divider circuit, and a multi-channel bias control circuit corresponding to each of the multiple power amplification branches. The DC reference circuit is used to output a constant reference current, providing a DC bias basis for the bias circuit. The multi-stage voltage divider circuit is connected in series in the DC loop of the DC reference circuit to form multiple voltage divider nodes with progressively decreasing potentials, so as to output multiple gradient DC voltages. Each of the bias control circuits has its DC input terminal connected to a corresponding voltage divider node to receive the DC voltage of the corresponding gradient to establish a static bias reference. The bias control circuit is also coupled to the RF input port of the power amplifier, and is used to dynamically adjust the output bias voltage according to the power of the input RF signal, and provide the bias voltage to the bias terminal of the corresponding power amplifier branch. The bias circuit is configured to: turn on some of the power amplification branches under low input power conditions, and turn on the power amplification branches step by step according to a preset threshold as the input power increases.

2. The bias circuit according to claim 1, characterized in that, The DC reference circuit includes a constant current source and a diode reference circuit; The constant current source is used to provide a DC current with stable amplitude; The diode reference circuit includes a single diode device or multiple diode devices connected in series. The constant current source, the multi-stage voltage divider circuit, and the diode reference circuit are connected in series to form a DC circuit.

3. The bias circuit according to claim 1, characterized in that, The multi-stage voltage divider circuit includes multiple voltage divider resistor units connected in series, and the connection point of two adjacent voltage divider resistor units constitutes the voltage divider node. The DC potential of each voltage divider node and the turn-on threshold of the corresponding power amplification branch are related to the resistance ratio of each voltage divider resistor unit.

4. The bias circuit according to claim 3, characterized in that, The voltage divider resistor unit is a resistive device; Along the current flow direction, the DC potential of each voltage divider node decreases step by step, and the static bias voltage output by each bias control circuit gradually decreases.

5. The bias circuit according to claim 1, characterized in that, The bias control circuit includes an emitter follower bias unit and an RF coupling unit; The emitter follower bias unit is used to output a static bias voltage to the corresponding power amplifier branch based on the DC voltage of the voltage divider node; The radio frequency coupling unit is used to couple the input radio frequency signal to the bias circuit, and uses the rectification effect of the transistor emitter junction to make the output bias voltage dynamically increase as the input power increases.

6. The bias circuit according to claim 5, characterized in that, The emitter follower bias unit is a bias transistor; the base of the bias transistor is connected to the corresponding voltage divider node, the collector is connected to the power supply, and the emitter is connected to the bias terminal of the corresponding power amplifier branch via an emitter resistor. The base of the bias transistor is also connected in parallel to ground via a bypass capacitor, which is used to provide a low-impedance path for radio frequency signals.

7. The bias circuit according to claim 6, characterized in that, The radio frequency coupling unit includes an input DC blocking capacitor, which is connected in series between the radio frequency input port and the bias terminal of the power amplifier branch. At least one of the bias control circuits further includes an enhanced coupling capacitor; the enhanced coupling capacitor is connected between the RF input port and the emitter of the bias transistor to directly couple RF energy, thereby improving the turn-on response speed of the corresponding power amplifier branch.

8. The bias circuit according to any one of claims 1 to 7, characterized in that, The plurality of power amplification branches include a first power amplification branch and a second power amplification branch; The first power amplification branch corresponds to the voltage divider node with the highest potential, and operates in Class AB amplification mode under static conditions, remaining on throughout the full power range; The second power amplification branch corresponds to a voltage divider node with a lower potential. It is in a near-off state under static conditions and gradually turns on after the input power reaches the first threshold.

9. A power amplifier, characterized in that, It includes at least two power amplifier branches connected in parallel and a bias circuit as described in any one of claims 1 to 8; The bias terminals of each power amplifier branch are respectively connected to the output terminal of one bias control circuit in the bias circuit. The RF input terminals of each power amplifier branch are connected to the input RF signal. The output terminals of all power amplifier branches are connected in parallel to each other to form the RF output port of the power amplifier. The bias circuit provides a gradient-distributed static bias level for each power amplification branch and dynamically adjusts the bias state of each branch according to the magnitude of the RF input power, so that each power amplification branch is turned on step by step according to a preset threshold as the input power increases.

10. An electronic device, characterized in that, include: The bias circuit as described in any one of claims 1 to 8, or, comprising at least one power amplifier as described in claim 9.

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