A binary tree-shaped multi-frequency signal synthesis method

Abstract

The application relates to the technical field of digital signal processing and multi-carrier communication, and discloses a binary tree-shaped multi-frequency signal synthesis method, which takes multiple independent complex direct current components as a modulation base, realizes accurate reconstruction of a multi-frequency signal through binary tree step-by-step interpolation and frequency mixing iteration. The first stage is synthesized without filtering by using the natural isolation characteristics of double-frequency points, and the hardware zero multiplication cost is saved; the second stage is synthesized by using +pi / 4 symmetric frequency mixing and fixed 7-tap HBF filtering in a 2:1 mode; the third stage to the eleventh stage are synthesized by using +pi / 4 symmetric frequency mixing and fixed 15-tap HBF filtering in a 2:1 mode; and the last stage is synthesized by using +pi / 2 symmetric frequency mixing in a 2:1 mode, and the positive and negative frequencies are decoupled throughout the process. The application supports any integer number of sub-channels (including prime numbers), the branches at all stages are physically independent and are equipped with gate clocks, and the idle branches can be completely turned off. Compared with IFFT, the area is reduced by more than 50%, the power consumption of sparse frequency points is reduced by more than 90%, the group delay is short and controllable, and the application is suitable for low-power multi-frequency transmission and a software radio platform.

Description

Technical Field

[0001] This invention relates to the fields of digital signal processing, multi-frequency waveform synthesis, and wireless communication multi-carrier transmission technology, and particularly to a high-precision multi-frequency signal synthesis method based on bipartite tree iteration, namely a bipartite tree multi-frequency signal synthesis method. This method can be widely used in wireless communication base stations, satellite communication terminals, software radio platforms, radar agile signal generators, optical communication modulators, and high-precision arbitrary waveform generators. Background Technology

[0002] In contemporary wireless communication and radar detection systems, multi-frequency signal synthesis is a core technical requirement. Taking a 5G base station as an example, its downlink needs to simultaneously carry multiple sub-bands or component carriers, each carrying different user data or control signaling. The transmitter must synthesize multiple narrowband signals dispersed in the frequency domain into a broadband time-domain signal in real time and radiate it through the antenna. Similarly, in cognitive radio and spectrum sensing systems, equipment needs to simultaneously monitor or occupy multiple discontinuous frequency bands within a wide bandwidth, with the center frequency, bandwidth, and amplitude of each band independently configurable. In multi-target radar detection scenarios, transmitters often need to simultaneously generate multiple pulse signals with different carrier frequencies to cover targets at different distances and speeds. In dense wavelength division multiplexing (DWDM) systems for optical communication, multiple optical signals of different wavelengths need to undergo electrical pre-compensation and waveform synthesis at the transmitting end before driving the optical modulator. The aforementioned application scenarios all face a common underlying signal processing problem: how to efficiently, accurately, and with low power consume multiple independently controllable sub-channel / sub-band signals in the frequency domain to synthesize a single time-domain digital baseband signal for subsequent digital-to-analog conversion and RF up-conversion. The engineering and technical level of this type of problem directly determines the transmission quality, spectrum utilization efficiency, terminal power consumption, and equipment cost of the communication system.

[0003] In existing engineering implementations, the mainstream technical solution for solving the aforementioned multi-frequency signal synthesis problem is the large-point inverse fast Fourier transform (IFFT) time-domain reconstruction method. Taking a 4096-point IFFT as an example, the typical operation process of this method is as follows: First, the frequency domain data of each frequency point / subband to be synthesized is mapped to the corresponding position in a frequency domain sequence of length 4096 according to the subcarrier interval, and the remaining unused subcarrier positions are set to zero; then, the complete 4096-point IFFT operation is performed through a radix-2 or radix-4 butterfly operation architecture to transform the frequency domain sequence into a time domain sequence output. This scheme has become the preferred solution for most broadband multicarrier transmitters, arbitrary waveform generators, and radar signal sources because it strictly corresponds to the orthogonal frequency division multiplexing (OFDM) modulation principle in mathematics, and its computational efficiency is better than the direct digital frequency synthesis (DDS) accumulation method when the number of frequency points is large. For many years, it has been regarded as the standard technical path in academia and industry.

[0004] However, the IFFT scheme has a series of structural defects when dealing with the aforementioned multi-frequency synthesis requirements. These defects stem from the global transformation and fixed pipeline architecture of IFFT, as follows:

[0005] First, the hardware resource overhead is enormous. Implementing a 4096-point IFFT requires a large amount of hardware resources: each butterfly operation requires complex multipliers, complex adders, and twiddle factor memory, and the data path also requires multiple levels of large-capacity FIFOs or dual-port RAM for pipeline caching. The registers, multipliers, and memory units of the entire arithmetic array occupy a very large chip area, leading to a significant increase in chip manufacturing costs. For resource-constrained portable devices or IoT terminals, such hardware overhead even directly excludes the possibility of integrating multi-frequency synthesis functionality.

[0006] Second, it suffers from high power consumption and lacks the ability to dynamically prune. IFFT employs a fixed pipeline architecture, where each butterfly operation must complete all input data points, regardless of the actual number of valid frequency points. In practical engineering, systems often only need to synthesize a small number of frequency points (e.g., 4, 8, or 16) – this is the "sparse frequency point scenario." In this case, the vast majority of IFFT operations operate on invalid subcarriers that have been set to zero, constituting purely redundant computation. However, existing IFFT hardware architectures lack the ability to shut down invalid computation paths as needed, requiring the full 4096-point transformation to be completed, resulting in persistently high static and dynamic power consumption. This deficiency is particularly critical for battery-powered mobile communication devices, portable spectrum analyzers, and radar nodes deployed in the field.

[0007] Third, the group delay is fixed and relatively large. The pipeline delay of IFFT is determined by the total number of stages ( The group delay is determined by the flow depth at each stage. For a fixed 4096-point transformation, the group delay is a fixed value, typically ranging from hundreds to thousands of clock cycles. In high-speed frequency-hopping communication, agile radar, and real-time spectrum monitoring scenarios requiring real-time response, this fixed and relatively large delay introduces a significant system lag, directly affecting the stability of the control closed loop and the agility of waveform switching.

[0008] Fourth, the flexibility of spectrum control is poor. IFFT is a global integrated transform, which cannot independently and precisely adjust the amplitude and phase of a single frequency point without affecting other frequencies; moreover, it cannot shut down the computation branch of a specific idle frequency point during runtime to save power. The isolation between subbands and the passband flatness are limited by the inherent spectrum leakage and picket-fence effect of IFFT, making it difficult to meet the requirements of multi-frequency point independent control scenarios.

[0009] Fifth, it cannot adapt to differences in spectral density. IFFT uses the same transform precision for all frequency points, without distinguishing between dense and sparse frequency bands. Therefore, it cannot perform differentiated filtering optimization for aliasing risks in different frequency bands. In dense frequency areas, aliasing and adjacent channel crosstalk are very likely to occur, seriously affecting signal quality.

[0010] Therefore, those skilled in the art urgently need a multi-frequency signal synthesis technology solution that takes into account multiple requirements such as multi-frequency reconstruction accuracy, hardware simplicity, low latency, low power consumption and high control flexibility. Summary of the Invention

[0011] The core technical problem addressed by this invention is how to construct a multi-frequency signal synthesis method that is extremely simple in hardware, dynamically scalable in power consumption, has low and controllable group latency, and is finely adjustable in frequency points, without relying on large-scale butterfly operation arrays and rotation factor storage, so as to fundamentally overcome the inherent technical limitations of the IFFT architecture in terms of area, power consumption, latency, and flexibility.

[0012] For those skilled in the art, if the aforementioned core technical problems can be solved, low-power portable devices will have high-precision multi-frequency concurrent transmission capabilities, power consumption in sparse spectrum scenarios can be reduced by more than an order of magnitude, and waveform switching delay of radar and communication systems will be shortened by several times. This will substantially promote the engineering and miniaturization of technologies such as software radio, cognitive radio, multi-base radar, and spaceborne communication that rely on high dynamic spectrum management and low-power concurrent transmission.

[0013] To address the aforementioned core technical problems, this invention designs a binary tree-based multi-frequency signal synthesis method. Its purpose is to introduce a tree-based iterative architecture based on the duality of signal decomposition and synthesis into the transmitter's digital baseband processing stage. This architecture should possess the following characteristics:

[0014] First, using multiple independent complex DC components as the modulation basis, the spectrum is gradually encrypted and reconstructed through binary tree-style interpolation and mixing iteration.

[0015] Secondly, filters at each stage should be configured according to the differences in spectral density to minimize hardware overhead;

[0016] Finally, branches should be physically independent to support the complete shutdown of idle branches.

[0017] The above technical solutions can be applied to scenarios such as wireless base station downlink, radar excitation signal generation, software radio transmission channels, and arbitrary waveform generators.

[0018] To achieve the above objectives, the specific technical solution of the present invention is a binary tree-structured multi-frequency signal synthesis method, the method comprising the following steps:

[0019] Step S1: Obtain sub-channel signals: Obtain N sub-channel complex baseband signals to be synthesized, where N is any positive integer, and each sub-channel signal is represented in the form of independent complex DC components;

[0020] Step S2: Perform the first-level multi-frequency unfiltered synthesis: Divide the N sub-channels into N / 2 groups, each group containing two sub-channels. Based on the duality of multi-frequency synthesis, modulate the complex DC components of the two sub-channels in each group to the first carrier frequency and the second carrier frequency, respectively. After combining, output N / 2 channels of first-level synthesized signals. In the first-level synthesis process, no interpolation filtering operation is set. The aliasing-free synthesis is achieved through the natural spectral isolation characteristics of the dual frequency points.

[0021] Step S3: Perform the second-level interpolation process: Perform 2x interpolation on the N / 2 channels of the first-level synthesized signals respectively. Use a half-band filter (if the image frequency is far enough during the first-level synthesis, it can be reduced to a 7-tap HBF) or an FIR filter to perform image filtering on each interpolated signal. Then, perform ±π / 4 complex frequency mixing and frequency shifting on the filtered signal. Finally, combine every two mixed signals into one signal.

[0022] Step S4: Perform a 2:1 synthesis process from level 3 to level K-1, where K is the total number of tree levels. For level m (2≤m≤K-1): perform 2x interpolation on each signal output from the previous level, perform mirror filtering through the interpolation filter, perform ±π / 4 complex frequency mixing and frequency shifting on the filtered signal, and finally combine every two mixed signals into one signal, resulting in a multi-channel synthesized signal with half the number of outputs.

[0023] Step S5: Perform the final synthesis process: Perform ±π / 2 complex frequency mixing and shifting processing on the two signals output from the K-1th stage, and combine the digital frequency group represented by the upper half circle and the digital frequency group represented by the lower half circle into a final multi-frequency time-domain complex signal.

[0024] Preferably, in step S2, the modulation of the first carrier frequency and the second carrier frequency adopts any one of the dual-mode mixing topologies:

[0025] The first mode is a ±Fs / 8 digital complex mixer topology, and the second mode is a ±Fs / 4 semi-circular symmetrical mixer topology, where Fs is the sampling rate of the current stage. Both modes ensure that the interpolation mirror frequency interval is large enough (compared to the cut-through + sign mixer topology).

[0026] Preferably, the half-band filter in step S3 is a 15-tap half-band filter with an out-of-band image rejection of not less than 72dB, and the target value is π / 2.

[0027] Preferably, the interpolation filter in step S4 is a half-band filter with a fixed number of taps, the fixed number of taps being 15 taps, and each interpolation filter has the same order configuration, without increasing the order step by step as the order increases.

[0028] Preferably, the ±π / 4 complex frequency mixing and shifting in step S4 is achieved by multiplying the current signal by... and This causes the spectrum to be symmetrically shifted along the positive and negative frequency directions by Fs / 4, completely separating the spectra of the upper and lower quadrants.

[0029] Preferably, each branch in each stage of steps S2 to S5 is configured with an independent gated clock and a branch enable signal. In response to external branch encoding control commands, the clock supply for interpolation, mixing and filtering operations of any branch can be independently turned off so that the branch enters a zero dynamic power consumption state.

[0030] Preferably, the method further includes a hierarchical truncation step S6: in response to an external truncation control command, after completing the synthesis processing of the Lth level (L≤K-1), immediately extract each signal output of the current level as the final multi-frequency synthesis result, and shut down the clock supply and operation of all branches from the L+1th level to the Kth level.

[0031] Preferably, when N is a prime number, the method synthesizes the N sub-channels by grouping them into groups according to the non-fully balanced structure of a binary tree. The number of synthesized branches at each level is ceil(N / 2) rounded down or up, until they are finally synthesized into a single signal. No DFT or hybrid-based FFT assistance is required throughout the process.

[0032] Preferably, the 2x interpolation process in step S2 uses a sample-and-hold method, which can eliminate the need for filtering and allow direct digital complex mixing in the subsequent steps.

[0033] Preferably, the 2x interpolation process in step S3 uses a zero-insertion method: a zero-value sample is inserted between every two adjacent samples of each first-level synthesized signal, and then fed into the half-band filter or FIR filter for image suppression filtering.

[0034] Preferably, the 2x interpolation process in step S4 uses a zero-insertion method: a zero-value sample is inserted between every two adjacent samples of each signal output from the previous stage, and then sent to the interpolation filter for image suppression filtering.

[0035] Preferably, in step S4, the signals after ±π / 4 complex frequency mixing and frequency shifting satisfy the condition that the spectra of the positive frequency branch and the negative frequency branch do not overlap at all. The superposition and merging is a direct arithmetic addition, without the need for additional anti-aliasing processing.

[0036] Preferably, the total group delay of the method is the sum of the group delays of each stage of the interpolation filter plus the pipeline delay of each stage of mixing and combining. The total group delay is independent of the value of N and is determined only by the selected number of filter taps.

[0037] Preferably, the method further includes an independent amplitude and phase configuration step: in step S1, the amplitude and phase of the complex baseband signal of each sub-channel are independently assigned and uncoupled, so that the frequency point amplitude and phase of each sub-channel are independently controlled in the final multi-frequency time domain signal.

[0038] Preferably, the interpolation filters in steps S2 to S5 are selected from any one or a combination of the following linear filter groups: half-band filter HBF, cascaded integrator comb filter CIC, and finite impulse response filter FIR.

[0039] Preferably, the present invention also discloses a binary tree-structured multi-frequency signal synthesis system, the system comprising:

[0040] The input interface is configured to receive N sub-channel complex baseband signals to be synthesized, where N is any positive integer;

[0041] The first-stage unfiltered synthesis unit is connected to the input interface and is configured to divide N sub-channels into N / 2 groups. The complex DC components of the two sub-channels in each group are modulated to the first carrier frequency and the second carrier frequency respectively and then combined to output N / 2 first-stage synthesized signals. The first-stage unfiltered synthesis unit does not contain any interpolation filter.

[0042] The second-level interpolation unit is connected to the first-level unfiltered synthesis unit and is configured to perform 2x interpolation processing on the N / 2 channels of the first-level synthesized signals and filter them through the interpolation filter. Each filtered signal is output independently and is not combined in pairs.

[0043] A multi-stage 2:1 synthesis unit is connected to the second-stage interpolation unit and is configured to perform 2x interpolation, interpolation filtering, ±π / 4 complex frequency mixing and frequency shifting, and pairwise combining operations on each of the signals output from the previous stage. The number of synthesized signals is halved after each stage until two synthesized signals are output.

[0044] The final synthesis unit, which is connected to the multi-stage 2:1 synthesis unit, is configured to perform pass-through processing and complex mixing and frequency shifting processing on the two synthesized signals respectively, and then superimpose the output of the pass-through branch and the output of the mixing branch into a final multi-frequency time-domain signal.

[0045] Preferably, the interpolation filter of the second-stage interpolation unit and the interpolation filter of the multi-stage 2:1 synthesis unit are both fixed 15-tap half-band filters, and the system does not contain any rotation factor ROM storage module.

[0046] Preferably, both the first-stage unfiltered synthesis unit and the multi-stage 2:1 synthesis unit adopt a ±Fs / 4 symmetrical mixing topology, so that the spectrum of each branch always maintains complete symmetry between the positive and negative frequencies and does not overlap with each other.

[0047] Preferably, each branch of the system is provided with an independent gated clock circuit and a branch enable register. The branch enable register is connected to an external branch encoder / decoder. The branch encoder / decoder is configured to control the opening and closing of the independent gated clock circuit according to the input branch code.

[0048] Preferably, the system further includes a hierarchical truncation controller, which is configured to receive an external truncation level instruction, and in response to the truncation level instruction L (L≥1), immediately output each signal of the current level after the multi-level 2:1 synthesis unit has completed the Lth level operation and set the enable registers of all branches from the L+1th level to the last level to an invalid state.

[0049] Preferably, when the first-stage unfiltered synthesis unit adopts the ±Fs / 8 complex mixing mode in the dual-mode mixing topology, the first-stage unfiltered synthesis unit does not contain any multipliers.

[0050] Preferably, the half-band filter (7-tap or 15-tap filter or any selected fixed-coefficient filter) and complex mixer, after CSE and RAG simplification, are reduced to a limited number of adders and contain no multipliers, which can significantly speed up their operation to suit high-speed processing scenarios such as optical communication.

[0051] Preferably, the present invention also discloses a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps of the method.

[0052] Compared with the prior art, the technical solution disclosed in this application has the following non-obvious technical features:

[0053] 1. This application adopts a duality-based multi-frequency synthesis architecture: it proposes that multi-frequency synthesis is a strictly dual process of signal decomposition, using multiple independent complex DC components as modulation bases to modulate to different carrier frequencies, rather than using the overall frequency domain sequence mapping method of IFFT. This technical concept breaks away from the technical bias that "time-domain reconstruction must be done through IFFT", and reconstructs the multi-frequency synthesis problem from the underlying principle of signal decomposition / synthesis duality.

[0054] 2. This application employs a first-stage filter-free binary tree interpolation structure: In the first-stage 2x interpolation, the inherent spectral isolation of the two frequency points is utilized to completely eliminate the interpolation filter, directly completing the interpolation in sample-and-hold (ZOH) form, achieving initial synthesis with zero multiplication and zero convolution operations. In common knowledge in the art, interpolation operations must be followed by a low-pass filter to eliminate mirroring; this invention breaks this established technical convention.

[0055] 3. This application implements a differentiated processing strategy for reducing the order of the second-stage filter: after changing the first stage to a ±π / 4 (i.e., ±Fs / 8) symmetrical mixing topology, the image frequency interval after interpolation in the second stage is as high as 3*π / 4. Therefore, a short HBF with a fixed 7 taps can be used. In addition, the careful design of interpolation + half-band filtering + mixing, and the non-obvious processing keep the transition band width above π / 2, significantly reducing the filtering pressure of subsequent stages, so that the subsequent stages can use a short HBF with a fixed 15 taps throughout without increasing the order step by step—this is completely different from the conventional iterative approach in this field of "synthesis after each stage of interpolation".

[0056] 4. This application employs a multi-stage ±π / 4 (i.e., ±Fs / 8) symmetrical mixing topology: preferably, ±π / 4 complex mixing is used to achieve symmetrical separation of positive and negative frequencies in the spectrum, resulting in a regular spectrum distribution and clear boundaries. This topology is naturally compatible with the passband / stopband structure of each stage of HBF, significantly reducing the difficulty of filter design and eliminating crosstalk between positive and negative frequencies, while conventional practices in the field mostly use zero-IF or low-IF mixing topologies.

[0057] 5. This application implements a two-level hierarchical decoupling iteration: the second level is clearly separated from the third to 12th levels in terms of synthesis timing—the second level can reduce the number of HBF taps and reduce the overall delay, the third to 11th levels are synthesized at a 2:1 ratio, and the last level is ±π / 2 complex mixing. This differentiated synthesis timing strategy prevents the overall passband ripple from accumulating step by step, which is unprecedented in the conventional "full synthesis immediately after interpolation at each level" architecture in this field.

[0058] 6. This application has the capability to synthesize an arbitrary integer number of sub-channels: it supports tree synthesis of an arbitrary integer number of sub-channels (including a prime number of sub-channels), while IFFT requires the number of sub-channels to be an integer power of 2 (such as 256, 512, 1024, 2048, 4096, etc.). Prime-point IFFT is extremely difficult and costly to implement in hardware, and this invention fundamentally avoids this inherent limitation.

[0059] 7. This application possesses the capability of extracting sub-channel synthesis results at any level: it allows direct extraction of sub-channel synthesis results at any level of the tree structure, and after completing the synthesis of a low number of points (such as 256, 1024 points, or any other integer), all subsequent level operations can be shut down. This "hierarchical truncation + complete shutdown of redundant levels" mechanism is completely impossible to implement in the IFFT architecture, providing an unprecedented dynamic trade-off capability between synthesis accuracy, power consumption, and latency.

[0060] 8. This application adopts a fully physically independent tributary architecture with independent gating of tributary coding: each tributary at each frequency point is a physically independent data path, and each tributary is configured with an independent gating clock and enable signal. The tributary coding can directly control the clock supply and register toggling of the interpolation, mixing, and filtering operations of the corresponding tributary, realizing true "zero dynamic power consumption of idle tributaries".

[0061] Compared with existing IFFT schemes, the present invention has the following advantages:

[0062] 1. This invention significantly reduces hardware area: It eliminates the resource-intensive modules required for IFFT, such as massive butterfly operation units, twiddle factor ROMs, and multi-level large-capacity caches. Instead, it employs only a step-by-step 2x zero-plugging, simple complex mixing, and a layered HBF (fixed 15-tap) structure, without a large-scale complex multiplication array. Actual measurements show that the chip area is reduced by more than 50% at the same precision (4096 points), greatly saving chip hardware resources and enabling the integration of multi-frequency synthesis functionality into area-sensitive portable and IoT devices.

[0063] 2. This invention offers significant advantages in terms of reduced computational power consumption and dynamic scalability: The front-end of this invention primarily uses addition, sign flipping, and simple complex exponential modulation, resulting in an extremely low logic flip rate. Only the last two stages employ lightweight filtering operations, leading to dynamic power consumption far lower than the globally dense multiply-accumulate array of IFFT. More importantly, each branch of this invention is physically independent, and the entire computation path of idle frequency points can be directly shut down through branch coding—in sparse frequency point operating scenarios (such as when only 4 frequency points need to be output), the computational load and dynamic power consumption are reduced by more than 90%, a capability completely unavailable in IFFT solutions.

[0064] 3. The group delay of the present invention is lower and more controllable: The present invention abandons the long-delay architecture of the fixed 4096-point pipeline of IFFT, and adopts a hierarchical iterative and first-stage filter-free design. The total group delay is strictly controlled by the sum of the group delays of each HBF stage (which is much smaller than the delay of IFFT), and can be further compressed through hierarchical truncation, which fully meets the real-time requirements of short-latency scenarios such as high-speed frequency hopping and agile radar.

[0065] 4. This invention improves the accuracy and flexibility of frequency control: Based on the principle of "one DC modulation and one carrier wave," the amplitude and phase of each frequency point can be independently and precisely configured without coupling. Compared with the inherent limitation of IFFT global transform, which cannot independently adjust parameters at a single point, this invention achieves a comprehensive improvement in multi-frequency isolation, passband flatness, and phase consistency.

[0066] 5. This invention possesses strong spectral anti-aliasing capabilities: relying on a ±π / 4 symmetrical mixing and positive / negative frequency decoupling architecture, the positive and negative frequencies are processed independently throughout the entire iteration process, eliminating the inherent spectral leakage, picket fence effect, and positive / negative frequency crosstalk problems of IFFT. Combined with a hierarchical differentiated filtering strategy, the spectral purity and subband uniformity after multi-level synthesis are far superior to the IFFT scheme.

[0067] 6. This invention can cover prime point scenarios that IFFT cannot handle: This invention supports the synthesis of any integer number of sub-channels (including prime numbers), while IFFT only supports integer powers of 2. For prime point sub-channel synthesis, traditional solutions can only use hybrid radix FFT or direct DFT with extremely high computational complexity, resulting in a sharp increase in hardware overhead; the tree architecture of this invention adds almost no extra area and power consumption, greatly expanding the application boundaries of multi-frequency synthesis technology. Attached Figure Description

[0068] Figure 1 This is a flowchart of the method described in this invention;

[0069] Figure 2 This is a pipeline architecture diagram of the synthesis of 4096 sub-channels described in this invention;

[0070] Figure 3This is the first-level architecture diagram of the tree-shaped binary channel synthesis described in this invention;

[0071] Figure 4 This is a second-level architecture diagram of the tree-shaped binary channel synthesis described in this invention;

[0072] Figure 5 This is a diagram of the third-level architecture of the tree-shaped binary channel synthesis described in this invention;

[0073] Figure 6 This is the fourth-level architecture diagram of the tree-shaped binary channel synthesis described in this invention;

[0074] Figure 7 This is a schematic diagram of the system described in this invention. Detailed Implementation

[0075] The following is in conjunction with the appendix Figures 1 to 7 The main technical features and embodiments of the present invention are described in detail below;

[0076] In the technical solution of this invention, the principle of multi-frequency synthesis duality is that the synthesis of multi-frequency signals is a strictly inverse process of signal decomposition: a broadband multi-frequency signal can be decomposed into multiple sub-band equivalent complex DC components in the frequency domain. During inverse synthesis, multiple independent complex DC components are used as the basis, modulated to different fixed carrier frequencies, and then reconstructed through interpolation time spreading, frequency mixing and shifting, and superposition and combining. This principle determines that each sub-channel is completely independent and controllable, making independent frequency point parameter tuning and branch shutdown possible, which is a fundamental difference in technical approach compared to IFFT global transformation.

[0077] In the technical solution of this invention, the first-stage filter-free synthesis strategy achieves aliasing-free synthesis in the first-stage 2x interpolation because the two frequency points are naturally isolated (spaced π) after 2x interpolation, without any interpolation filter. Interpolation is directly performed using a sample-and-hold (ZOH) method. This first-stage implementation achieves zero multiplication and zero convolution operations, significantly reducing hardware initialization overhead and first-stage group latency. This feature is a key starting point for reducing overall hardware area and power consumption.

[0078] In the technical solution of this invention, the second-stage interpolation non-merging strategy involves performing a 2x interpolation on each signal separately and completing mirror filtering via HBF. However, the filtered signals do not merge in a 2:1 ratio, maintaining independent output and keeping the transition band width above π / 2. This strategy significantly reduces the filtering pressure on subsequent stages, allowing the entire process to use a fixed 15-tap short HBF without progressively increasing the order. This is the core guarantee for maintaining constant and controllable hardware overhead in the entire tree architecture.

[0079] In the technical solution of this invention, the ±π / 4 (±Fs / 4) symmetric mixing topology is obtained by multiplying the interpolated and filtered signals by... and This topology shifts the spectrum by Fs / 4 along both the positive and negative frequency directions, achieving complete symmetrical separation and independent iteration of the positive and negative spectra. This topology results in a regular spectrum distribution and clear boundaries at each stage, naturally adapting to the passband / stopband structure of the HBF, significantly reducing the design difficulty and order of the filter, and fundamentally eliminating crosstalk between positive and negative frequencies. It is the core topology for maintaining spectral purity in multi-stage iterations.

[0080] In the technical solution of this invention, the fixed-tap-count HBF differential filtering architecture uses a fixed number of taps (e.g., 15 taps) for the entire process from stage 2 to stage K, with no step-by-step increase in order as the stage number increases, and the filter parameters of each stage remain consistent. This architecture ensures that the hardware overhead is independent of the stage number, achieving predictability and controllability of the hardware area. The extremely small number of multipliers in the fixed-tap short HBF is the direct reason for the overall area reduction of more than 50% compared to IFFT.

[0081] In the technical solution of this invention, the branch coding independent gating shutdown mechanism equips each branch at each stage with an independent gating clock circuit and branch enable signal. The external branch coding can directly control the clock supply and register toggling of the corresponding branch's interpolation, mixing, and filtering operations. This achieves true "zero dynamic power consumption in idle branches." Reducing dynamic power consumption by more than 90% in sparse frequency scenarios is the most competitive differentiating feature of this solution in low-power applications.

[0082] In the technical solution of this invention, the positive and negative frequency fully decoupled iterative topology adopts an independent synthesis method with upper and lower semicircles and dual branches. The positive and negative frequency branches independently complete interpolation, frequency shifting, and filtering operations throughout the entire iteration process, only performing combining and superposition at the final stage. This iterative topology can completely eliminate cross-frequency distortion superposition and multi-frequency crosstalk, ensuring the spectral purity and isolation of each sub-band after multi-level iterations. This is the underlying structural guarantee that the spectral quality is superior to the IFFT scheme.

[0083] In the technical solution of this invention, the tree-structured synthesis capability for arbitrary integer points (including prime numbers) means that the tree structure does not require the total number of sub-channels to be an integer power of 2. It can perform incompletely balanced binary tree grouping synthesis on any N (including prime numbers), with the number of synthesis branches at each level being the floor of ceil (existing branch number / 2). This capability allows the technology of this invention to cover prime-point sub-channel synthesis scenarios that IFFT cannot handle, greatly expanding the application boundaries of multi-frequency synthesis technology while maintaining almost no change in hardware overhead.

[0084] In the technical solution of this invention, the ability to truncate at any level and shut down redundant levels is achieved through a tree structure that allows the current level output to be directly extracted after completing the synthesis of any Lth level (1≤L≤K-1), and the clock and operation of all branches from L+1 to K levels to be completely shut down. This realizes a three-dimensional dynamic trade-off between "synthesis accuracy / number of points-power consumption-latency", enabling the same hardware to flexibly adapt to the continuous spectrum requirements from extremely low-power sparse synthesis to high-precision full-number-point synthesis.

[0085] In the technical solution of this invention, the recursive law of bisection interpolation spectrum is that after each level of 2x interpolation, the angular frequency interval between the effective in-band spectrum and the interpolated image is halved level by level, with the interval at the kth level being... This principle drives the design of a hierarchical differentiated filtering strategy: the first-stage interval can be filtered without filtering if it is the largest, while the last-stage interval requires fine HBF filtering if it is the smallest, so that the filtering intensity of each stage is precisely matched with the spectral spacing, thus minimizing the filtering overhead.

[0086] refer to Figure 1 This document illustrates a flowchart of a binary tree-structured multi-frequency signal synthesis method according to one or more embodiments of this application. This method is applied in the digital baseband processing unit of a wireless communication base station downlink multi-carrier transmit link, a radar agile signal generator, or a software-defined radio transmit platform, for efficiently synthesizing multiple independently controllable sub-channel / sub-band signals in the frequency domain into a single time-domain digital baseband signal. (Reference) Figure 2 The diagram illustrates a pipeline architecture using the synthesis of 4096 sub-channels as an example. The method generally includes the following steps: Step S1: Obtain N complex baseband signals of the sub-channels to be synthesized; Step S2: Perform the first-stage multi-frequency unfiltered synthesis; Step S3: Perform the second-stage interpolation and synthesis processing. Because the image frequency is significantly different from the actual frequency, the number of taps of the HBF filter can be reduced by half, significantly reducing the time delay; Step S4: Perform the step-by-step 2:1 synthesis processing from the third stage to the (K-1)th stage; Step S5: Perform the final stage synthesis processing.

[0087] In one or more embodiments, the input interface of the digital baseband processing unit in step S1 is configured to receive N sub-channel complex baseband signals to be synthesized, where N is any positive integer, and each sub-channel signal is characterized in the form of independent complex DC components, that is, each sub-channel signal can be represented in complex form, wherein, The amplitude of the nth sub-channel. This is the initial phase of the nth sub-channel. Specifically, when the system needs to synthesize multiple independent frequency points, the complex baseband data of each sub-channel is input from the corresponding digital up-conversion (DUC) channel or direct digital frequency synthesis (DDS) channel. The amplitude and phase of each channel can be configured independently and are not coupled to each other, providing a basis for subsequent independent frequency point control.

[0088] In one or more embodiments, the first-stage unfiltered synthesis unit in step S2 performs first-stage multi-frequency unfiltered synthesis: dividing N sub-channels into N / 2 groups, each group containing two sub-channels, and based on the duality of multi-frequency synthesis, modulating the complex DC components of the two sub-channels in each group to the first carrier frequency and the second carrier frequency respectively, and outputting N / 2 channels of first-stage synthesized signals after combining. In this first-stage synthesis process, no interpolation filtering operations are performed, and aliasing-free synthesis is achieved through the natural spectral isolation characteristics of the two frequency points. Figure 3 As shown, taking 4096 sub-channels as an example, the first-stage input is 4096 channels, and after being combined by grouped dual-frequency modulation, the output is 2048 channels, each containing two frequency points.

[0089] In one or more embodiments, reference Figure 3 The first-level architecture diagram shown indicates that for any pair of two sub-channels, their complex baseband signals are respectively and When using a ±Fs / 4 symmetrical mixer topology, with the first carrier frequency at -Fs / 4 and the second carrier frequency at +Fs / 4, the combined output signal is:

[0090] ;

[0091] Where Fs is the current sampling rate. Since the two carrier frequency points are separated by Fs / 2, they are located in the spectrum after double interpolation. and The location is naturally isolated, eliminating the risk of aliasing, thus allowing direct combining without any low-pass filtering. This step achieves multi-frequency initialization combining with zero multiplication and zero convolution operations, significantly reducing initial hardware overhead and group latency.

[0092] In one or more embodiments, the second-level interpolation unit in step S3 performs a second-level interpolation process: the N / 2 channels of the first-level synthesized signals are each subjected to a 2x interpolation, and the interpolated signals are mirror-filtered using a half-band filter or an FIR filter. The filtered signals are output independently and are not combined pairwise, so that the transition band width remains above the target value. Figure 4 As shown, the second-stage input has 2048 channels. After 2x interpolation and short-tap HBF filtering, it is then synthesized at a 2:1 ratio.

[0093] In one or more embodiments, the 2x interpolation process in step 3 employs zero-placing: a zero-value sample is inserted between every two adjacent samples of each first-stage synthesized signal, increasing the sampling rate by a factor of 2. Zero-placing generates a mirror spectrum around the original in-band spectrum. Since the transition band width after interpolation is greater than π / 2, a fixed 15-tap half-band filter (HBF) can achieve out-of-band image rejection of at least 72dB. Each signal is output independently after filtering without being combined pairwise, ensuring that the transition band width is not reduced due to combining, thus minimizing the pressure on subsequent interpolation filtering stages.

[0094] In one or more embodiments, the second-stage halfband filter can also be replaced with a regular linear FIR filter. The number of taps can be selected between 11 and 31 taps depending on the actual scenario requirements. Fewer taps result in lower hardware overhead but a slight decrease in image suppression performance. More taps result in better image suppression performance but an increase in hardware area and power consumption. The specific choice depends on the application scenario's requirements for spectral purity and hardware resources.

[0095] In one or more embodiments, the multi-level 2:1 synthesis unit in step S4 performs a step-by-step 2:1 synthesis process from level 2 to level K, where K is the total number of tree levels. For synthesis of 4096 sub-channels, K=12. Specifically, for level m (3≤m≤K-1): each signal output from the previous level is subjected to a 2x interpolation, mirrored by an interpolation filter, and then the filtered signal is subjected to ±π / 4 complex frequency mixing and shifting. Finally, every two mixed signals are superimposed and combined into one signal, resulting in a multi-channel synthesized signal with half the number of output channels. Figure 5 and Figure 6 As shown, starting from the second stage, the signals are synthesized in a 2:1 ratio. The second stage combines 2048 pairs of signals into 1024 channels, the third stage combines them into 512 channels, and so on, until the 12th stage outputs 1 signal.

[0096] In one or more embodiments, for any signal to be synthesized in the m-th level and Perform the following operations: First, for and Each sample is subjected to double zero-interpolation, that is, a zero-value sample is inserted between every two adjacent sample points to obtain the interpolated signal. and Then and The signals are fed into a fixed 15-tap half-band filter for image filtering to remove the image spectrum generated by the 2x interpolation, thus obtaining the filtered signal. and Then on and Perform ±π / 4 complex mixing and frequency shifting processing respectively, i.e. Multiply Y2(t) multiplied by The spectrum of the two signals is symmetrically shifted by Fs / 4 along the positive and negative frequency directions. Finally, the two mixed signals are directly arithmetically added to complete the 2:1 combining and output a single synthesized signal. Taking the second stage as an example, the input is 2048 signals, which are paired to form 1024 pairs. Each pair is processed as described above and outputs one signal, for a total of 1024 output signals.

[0097] In one or more embodiments, the final synthesis unit in step S5 performs the final synthesis process: it performs pass-through processing and complex mixing and frequency shifting processing on the two signals output from the Kth stage, respectively, and then superimposes the output of the pass-through branch and the output of the mixing branch into a single final multi-frequency time-domain signal. For 4096-point synthesis (K=12), the 11th stage output is two signals, and the final stage combines these two signals into an upper and lower semicircle (multiplied by...). After processing, they are summed to obtain a final output of 1 channel. The purpose of this final synthesis stage is to combine the positive and negative semicircular frequency regions into a complete full-circular digital frequency band signal, and output a time-domain digital baseband signal that can be directly fed into a digital-to-analog converter (DAC).

[0098] In one or more embodiments, the modulation of the first carrier frequency and the second carrier frequency in step S2 adopts any one of the dual-mode mixing topologies.

[0099] The first mode is a ±Fs / 8 mixing topology, which significantly reduces the pressure of subsequent mirror filtering and also reduces one stage of circuitry compared to the pass-through + sign mixing mode.

[0100] The second mode is a ±Fs / 4 semi-circular symmetrical mixing topology, where the two signals are multiplied by... Achieving symmetrical frequency shifting, this mode exhibits a symmetrical positive and negative spectrum, regular distribution, and clear boundaries. It is naturally compatible with the filtering construction and image suppression logic of each level of HBF, making it suitable for scenarios with high requirements for spectrum quality and filtering performance.

[0101] In one or more embodiments, the ±π / 4 complex frequency mixing and shifting in step S4 is achieved by multiplying the current signal by... and This shifts the spectrum symmetrically along the positive and negative frequency directions by Fs / 4, completely separating the upper and lower semicircular spectra. The digital domain implementation of this operation is: for the in-phase component I and the quadrature component Q, multiply by... Equivalent to execution ,because Since it is a constant, this operation can be implemented using constant multipliers and adders, without requiring rotation factor ROM storage.

[0102] In one or more embodiments, when N is a prime number, the method synthesizes the N sub-channels by grouping them level by level according to a non-fully balanced binary tree structure. Specifically, when N is odd, the number of synthesized branches at each level is ceil(N / 2) (rounded up) or floor(N / 2) (rounded down). A non-fully balanced binary tree structure is used, meaning that some branches may contain 3 sub-channels (requiring an additional level of internal synthesis) while some branches contain 2 sub-channels, until finally synthesized into a single signal. Taking N=4093 (a prime number) as an example, the first level is divided into 2047 groups (2046 groups each with 2 channels, and 1 group with 1 channel that is directly connected). Subsequent levels are merged level by level according to the same rules. The entire process does not require the assistance of Discrete Fourier Transform (DFT) or Mixed Basis Fast Fourier Transform (FFT), while the traditional IFFT scheme cannot be directly implemented for prime points and must use a mixed basis algorithm or direct DFT with extremely high computational complexity, resulting in an exponential increase in hardware overhead.

[0103] In one or more embodiments, the method further includes a hierarchical truncation step S6: in response to an external truncation control command, after completing the synthesis processing of the Lth level (L≤K-1), the signals output by the current level are immediately extracted as the final multi-frequency synthesis result, and the clock supply and operation of all branches from the L+1th level to the Kth level are shut down. For example, when the system only needs to synthesize 1024 sub-channels, it can directly output and shut down all subsequent level operations after completing the synthesis of the 2nd level (which is equivalent to completing the synthesis of 1024 points), thereby saving about 75% of the computation and power consumption, while the IFFT architecture must run all 12 levels of butterfly operations regardless of the number of output points.

[0104] In some embodiments, optionally or additionally, the interpolation filters at each stage are selected from any one or a combination of the following linear filter banks: half-band filter (HBF), cascaded integrator-comb filter (CIC), and finite impulse response filter (FIR). When using a CIC filter, since the CIC filter does not require a multiplier and consists only of an adder and a delay unit, the hardware area can be further reduced by about 80%, but the out-of-band image rejection performance is about 40-60dB, making it suitable for scenarios where the requirements for spectral purity are not extreme but the requirements for area and power consumption are extremely stringent. When using an FIR filter with a higher number of taps (such as 31 taps or 63 taps), the out-of-band image rejection can reach more than 90dB, making it suitable for applications such as radar and satellite communication that have extremely high requirements for spectral purity. Filters at each stage can be used in combination.

[0105] In one or more embodiments, the signals after ±π / 4 complex frequency mixing and shifting in step S4 satisfy the condition that the spectra of the positive frequency branch and the negative frequency branch do not overlap at all. The superposition and merging is a direct arithmetic addition, requiring no additional anti-aliasing processing. Specifically, taking the synthesis of a certain path in the third stage as an example, let the spectra of the two input signals be respectively... and Its effective frequency band is within the range of [-Fs / 8, Fs / 8] (after pre-stage filtering). After 2x interpolation, the effective frequency range is [-Fs / 4, Fs / 4], and the mirrored frequency range is located in the intervals of [Fs / 4, 3Fs / 4] and [-3Fs / 4, -Fs / 4]. After ±π / 4 mixing, the first signal (multiplied by...) The spectrum of the second signal (multiplied by 0) is shifted to the [-Fs / 2, 0] interval. The spectrum of ) is shifted to the interval [0, Fs / 2]. Since the two do not overlap at all in the frequency domain, they can be synthesized by direct arithmetic addition without any additional anti-aliasing filter.

[0106] In one or more embodiments, the total group delay of the method is the sum of the group delays of each stage of the interpolation filter plus the pipeline delay of each stage of mixing and combining. The total group delay is independent of the value of N and is determined solely by the selected number of filter taps. For example, a fixed 15-tap HBF has a group delay of approximately 7 clock cycles (for a symmetric FIR filter, group delay = (number of taps - 1) / 2). The 4096-point combining process has 12 stages, of which 11 stages (stages 2 through 11) use HBF (stage 1 has no filtering).

[0107] The method further includes an independent amplitude and phase configuration step: In step S1, the amplitude and phase of the complex baseband signal of each sub-channel are independently assigned and decoupled from each other, so that the frequency point amplitude and phase of each sub-channel are independently controlled in the final multi-frequency time-domain signal. Specifically, the complex baseband signal of each sub-channel... In and Each subchannel is stored independently in a configuration register, allowing modification of any subchannel's... or It only affects the output frequency point corresponding to the sub-channel and is completely unrelated to other sub-channels, realizing true independent fine control of a single frequency point. This is fundamentally different from the global coupling characteristic of the IFFT scheme, where any change at any point in the frequency domain will spread to all output time domain samples through butterfly operation.

[0108] In one or more embodiments, to ensure the security of branch shutdown operations at each level and to prevent data corruption caused by accidental shutdown during branch operations, the branch shutdown operations in steps S3 to S5 are executed through the following atomic process. Specifically, each branch in each level of steps S2 to S5 is configured with an independent gated clock and branch enable signal. In response to external branch encoding control commands, the clock supply for interpolation, mixing, and filtering operations of any branch can be independently shut down, so that the branch enters a zero dynamic power consumption state. Each branch is physically independent and does not affect the others. The specific process of the shutdown operation is as follows: First, the external controller sends the target tributary code and shutdown command through the tributary encoding bus; then, the enable register of the corresponding tributary captures the command and sets the tributary enable signal to an invalid state at the boundary of the current pipeline cycle (i.e., after the current data frame is processed); next, the gated clock circuit corresponding to the tributary cuts off the clock supply to all registers and combinational logic of the tributary in the next clock cycle, and forces the output port of the tributary to a logic low level to avoid floating; finally, the tributary status register feeds back the shutdown completion status code to the external controller, completing the atomic shutdown operation and ensuring data integrity before and after shutdown.

[0109] In the hierarchical truncation step S6, in response to the external truncation control command, after completing the synthesis processing of level L, the output signals of the current level are immediately extracted as the final multi-frequency synthesis result, and the clock supply and operation of all branches from level L+1 to level K are shut down. Specifically, after receiving the truncation level command L, the external truncation controller latches the output data of the current level into the output FIFO when the data pipeline of the current frame completes the processing of level L, and simultaneously sets the enable registers of all branches from level L+1 to level K to an invalid state via broadcast, cutting off the clock supply of all subsequent levels. This operation is also executed through an atomic process to ensure that the truncation time is aligned with the data boundary and that no truncation data corruption occurs.

[0110] In one or more embodiments, an error handling process is executed in response to abnormal conditions. These abnormal conditions include: the number of input sub-channels N being zero or negative, external tributary coding exceeding the valid tributary range, and abnormal tributary status feedback from the gated clock circuit. The error handling process includes at least one of the following operations: terminating the current operation, i.e., stopping all pipelines and resetting all status registers; recording an error log, i.e., recording the exception type, occurrence time, and corresponding tributary code through the error status register; and performing system state rollback, i.e., restoring to the state before the previous frame of data processing began and restarting the pipeline.

[0111] refer to Figure 7This diagram illustrates a binary tree-structured multi-frequency signal synthesis system according to one or more embodiments of this application. The system is applied in the digital baseband processing unit of a wireless communication base station downlink multi-carrier transmit link, a radar agile signal generator, or a software-defined radio transmit platform, for efficiently synthesizing multiple independently controllable sub-channel / sub-band signals in the frequency domain into a single time-domain digital baseband signal. (Reference) Figures 2 to 6 The pipeline architecture shown in the diagram includes the following core modules: input interface, first-stage unfiltered synthesis unit, second-stage interpolation unit, multi-stage 2:1 synthesis unit, and final-stage synthesis unit.

[0112] In one or more embodiments, the input interface is configured to receive N sub-channel complex baseband signals to be synthesized, where N is any positive integer. Specifically, the input interface includes N parallel data input channels, each channel being configured to receive complex data signals. Baseband data, amplitude of each channel and phase All can be configured independently. The input interface also includes a data valid indication signal and a frame synchronization signal for data synchronization with the front-end digital upconversion (DUC) channel or direct digital frequency synthesis (DDS) channel.

[0113] In one or more embodiments, a first-stage unfiltered synthesis unit, connected to the input interface, is configured to divide N sub-channels into N / 2 groups. The complex DC components of the two sub-channels in each group are modulated to a first carrier frequency and a second carrier frequency, respectively, and then combined to output N / 2 channels of the first-stage synthesized signal. The first-stage unfiltered synthesis unit does not contain any interpolation filters. Specifically, as shown... Figure 3 As shown, the first-stage unfiltered synthesis unit consists of N / 2 dual-frequency modulation combining submodules, each submodule containing two constant complex multipliers (used to multiply by respectively). It includes a complex adder to perform carrier modulation and superposition of the two signals. When using the pass-through +Fs / 2 symbol mixing mode, this unit only contains an adder and a symbol flipper, and does not contain any multipliers at all, further simplifying the hardware to the extreme.

[0114] In one or more embodiments, a second-stage interpolation unit, connected to a first-stage unfiltered synthesis unit, is configured to perform 2x interpolation processing on each of the N / 2 channels of the first-stage synthesized signals and then filter them using an interpolation filter. Each filtered signal is output independently without being combined pairwise. Specifically, as shown... Figure 4As shown, the second-stage interpolation unit consists of N / 2 parallel interpolation filtering submodules. Each submodule contains a 2x zero-injector (inserting a zero sample between every two adjacent samples) and a fixed 15-tap half-band filter (HBF). The 15 tap coefficients of the HBF are constants and stored in a read-only register, eliminating the need for dynamic reading of the rotation factor ROM. Each signal remains independently output after being filtered by the HBF, without any combining operation, thus maintaining the transition band width above π / 2.

[0115] In one or more embodiments, a multi-stage 2:1 synthesis unit, connected to the second-stage interpolation unit, is configured to perform 2x interpolation, interpolation filtering, ±π / 4 complex frequency shifting, and pairwise combining operations on each of the signals output from the previous stage. Each stage outputs a multi-channel synthesized signal with half the number of signals, until two synthesized signals are output. Specifically, as shown... Figure 5 and Figure 6 As shown, the multi-stage 2:1 synthesis unit consists of multiple cascaded synthesis sub-units. Each synthesis sub-unit includes: a 2x zero-plugging array, a fixed 15-tap HBF array, and a ±π / 4 complex mixer array (which multiplies the two signals by π / 4 respectively). and This includes a complex adder array (which directly adds the two mixed signals arithmetically). Starting from stage 1, the number of output signals is halved for each stage. Taking 4096-point synthesis as an example, stage 1 outputs 2048 channels, stage 2 outputs 1024 channels, stage 3 outputs 512 channels, stage 4 outputs 256 channels, stage 5 outputs 128 channels, stage 6 outputs 64 channels, stage 7 outputs 32 channels, stage 8 outputs 16 channels, stage 9 outputs 8 channels, stage 10 outputs 4 channels, and stage 11 outputs 2 channels.

[0116] In one or more embodiments, the final-stage synthesis unit, connected to the multi-stage 2:1 synthesis unit, is configured to perform ±π / 2 complex mixing and frequency shifting on the two synthesized signals respectively, superimposing the digital frequency group represented by the upper semicircle and the digital frequency group represented by the lower semicircle into a single final multi-frequency time-domain signal. Specifically, the final-stage synthesis unit includes two parallel branches: a complex mixing branch that shifts the right semicircle to the upper semicircle (multiplied by...). ) and move the right semicircle of the other path to the lower semicircle complex mixer branch (multiplied by ) After processing, the two signals are combined into one output by a complex adder. The output signal can be directly fed into the subsequent digital-to-analog converter (DAC) and RF upconversion link.

[0117] In one or more embodiments, the interpolation filter of the second-stage interpolation unit and the interpolation filter of the multi-stage 2:1 synthesis unit are both fixed 15-tap half-band filters, and the system does not contain any twiddle factor ROM storage module. Unlike traditional IFFT architectures that require storing a large number of twiddle factors (approximately 2048 complex twiddle factors are required for a 4096-point IFFT, occupying a large ROM area), this system uses 15 fixed real constant HBF coefficients, requiring only a very small amount of registers or read-only memory, resulting in negligible area overhead. Furthermore, since the HBF coefficients are constants, complex multiplication can be simplified to a constant multiplier, significantly reducing area and power consumption compared to the dynamic complex multiplier of IFFT.

[0118] In one or more embodiments, both the first-stage unfiltered synthesis unit and the multi-stage 2:1 synthesis unit employ a ±Fs / 4 symmetrical mixing topology, ensuring that the spectrum of each branch always maintains perfect symmetry between the positive and negative frequencies and that they do not overlap. Specifically, the two signals in each synthesis submodule are multiplied by... and This ensures that one branch processes the positive frequency component and the other branch processes the negative frequency component, maintaining complete spectral separation throughout the entire iteration process and preventing any cross-frequency interference.

[0119] In one or more embodiments, the interpolation filters at each stage can be selected from any one or a combination of the following linear filter banks: half-band filter (HBF), cascaded integrator-comb filter (CIC), and finite impulse response filter (FIR). When using an HBF, due to its characteristic that half of the tap coefficients are zero, the number of multipliers can be further halved, while maintaining linear phase characteristics to ensure no phase distortion within the signal passband. When using a CIC filter, since no multipliers are required, and it consists only of adders and delay units, the system area can be further reduced by approximately 80%, making it suitable for portable devices with less stringent requirements for spectral purity but with strict requirements for area and power consumption. When using an FIR filter with a higher number of taps, the out-of-band image rejection performance can be further improved to over 90dB, making it suitable for high-end applications such as radar and satellite communications.

[0120] In one or more embodiments, the system further includes a hierarchical truncation controller configured to receive an external truncation level instruction L (L≥1), and in response to the truncation level instruction L, immediately output all signals of the current level after the multi-level 2:1 synthesis unit completes the L-th level operation and sets the enable registers of all branches from the (L+1)-th level to the final level to an invalid state. For example, when the external truncation controller receives an instruction for truncation level L=2, the system directly outputs all 2048 signals of the current level after the second-level interpolation unit completes processing, without initiating any subsequent operations from the 3rd to the 13th levels, and completely shuts off the clock supply, achieving approximately 75% power saving.

[0121] In one or more embodiments, each branch of the system is provided with an independent gated clock circuit and a branch enable register. The branch enable register is connected to an external branch codec, which is configured to control the opening and closing of the independent gated clock circuit according to the input branch code.

[0122] In one or more embodiments, the gated clock circuit employs a standard Integrated Clock Gating (ICG). Its input is connected to the system master clock, its enable terminal is connected to the output of the branch enable register, and its output is connected to the clock input ports of all registers and combinational logic of that branch. When the branch enable register outputs a high level, the ICG outputs the system master clock normally, and the branch operates normally. When the branch enable register outputs a low level, the ICG output remains consistently low or high, cutting off the clock supply to all sequential logic of that branch. The register data retains its current value, the combinational logic does not flip, and the branch enters a zero-dynamic-power state.

[0123] In one or more embodiments, the tributary codec is implemented using combinational logic decoding circuitry. Its inputs are the tributary code (e.g., 12-bit binary code, addressable for 4096 branches) transmitted via an external bus and operation commands (on / off). The output is the set / reset signal for the corresponding tributary enable register. This decoder employs a one-hot decoding method, ensuring that at most one instruction is executed at any given time, avoiding instruction conflicts, and achieving a decoding latency of less than one clock cycle, thus enabling rapid response to tributary shutdown.

[0124] In one or more embodiments, to ensure the atomicity and data integrity of tributary shutdown and hierarchical truncation operations, the system employs the following mechanism in critical operations. For tributary shutdown operations, the system's tributary enable register uses a dual-edge triggered update mechanism, updating the enable state only on the rising edge of the clock after the last sample of the current data frame has been output, ensuring that tributary shutdown does not interrupt ongoing operations in the current frame. Specifically, after the external tributary encoder / decoder parses the shutdown instruction, it temporarily stores the tributary code to be shut down in the instruction buffer register; when the frame end flag signal of the current data frame is valid, the instruction buffer register writes data into the tributary enable register, completing the atomic state update; if a new conflicting instruction is received during the instruction buffering period, the system executes it in a first-in-first-out order through arbitration logic.

[0125] In one or more embodiments, the hierarchical truncation controller employs a "frame boundary alignment" strategy for hierarchical truncation operations. When an external truncation level instruction L is received, the hierarchical truncation controller does not immediately execute truncation. Instead, it waits until the data frame currently at level L has been processed and then completes the truncation operation during the gap between frames. Specifically, the hierarchical truncation controller calculates the pipeline progress of the current frame. After latching the data at level L into the output FIFO, it sends a broadcast clear signal to the enable registers of all branches from level L+1 to level K, and simultaneously switches the output data path from the level L output to the final output port. The entire truncation operation is completed within one clock cycle without any data loss or corruption.

[0126] In one or more embodiments, the system executes an error handling procedure in response to abnormal conditions such as operational conflicts, invalid branch codes, or clock failures. These abnormal conditions include: external branch codes exceeding the range of valid branch numbers in the current level (e.g., branch codes greater than 2047 in a 4096-point scenario), truncated stages L exceeding the total number of stages K, and abnormal clock signal feedback from the gated clock unit. The error handling procedure includes at least one of the following operations: terminating the current operation, i.e., stopping all pipelines and resetting all status registers to their initial state; recording an error log, i.e., latching the exception type code, occurrence timestamp, and corresponding branch / stage number in the error status register for external reading; and performing system state rollback, i.e., restoring the system state to the start of the previous frame and issuing an interrupt signal to notify an external processor for processing.

[0127] In one or more embodiments, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is capable of implementing the steps of any of the methods described above.

[0128] Specifically, the computer-readable storage medium may be a read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive, solid-state drive, optical disc (CD-ROM, DVD), or any other form of non-volatile storage medium. The computer program is stored in the storage medium in the form of executable binary code or intermediate code compiled from a high-level language.

[0129] When the computer program is executed by a processor (such as a digital signal processor (DSP), a soft-core processor in a field-programmable gate array (FPGA), or an embedded processor in an application-specific integrated circuit (ASIC), the processor sequentially performs all operations from steps S1 to S5 above: acquiring N sub-channel complex baseband signals to be synthesized; performing the first-stage multi-frequency unfiltered synthesis; performing the second-stage interpolation processing; performing the third to Kth stages of stepwise 2:1 synthesis processing; performing the final stage of synthesis processing, and finally outputting one multi-frequency time-domain digital baseband signal. This storage medium can be applied to software-defined radio platforms, general-purpose computer simulation systems, and FPGA-based hardware-in-the-loop test systems.

[0130] In one or more embodiments, the computer program in the storage medium, when executed, further implements the additional steps and operations in the preferred embodiments described above, including: selection of dual-mode mixing topology, independent gated clock and branch shutdown control, hierarchical truncation control, incomplete balanced tree synthesis of any integer number (including prime) subchannels, and optional configuration of filter types at each level. Implementing these functions through software configuration allows for flexible adaptation to the number of synthesis points, power consumption requirements, and spectral quality requirements of different application scenarios without changing the hardware platform, greatly improving the portability and flexibility of the technical solution.

[0131] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, the phrase "comprising an element defined as..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0132] The above technical solutions only embody the preferred technical solutions of the present invention. Any modifications that may be made by those skilled in the art to certain parts thereof embody the principles of the present invention and fall within the protection scope of the present invention.

Claims

1. A method for synthesizing bipartite tree-structured multi-frequency signals, characterized in that, The method includes the following steps: Step S1: Obtain sub-channel signals: Obtain N sub-channel complex baseband signals to be synthesized, where N is any positive integer, and each sub-channel signal is represented in the form of independent complex DC components; Step S2: Perform the first-level multi-frequency unfiltered synthesis: Divide the N sub-channels into N / 2 groups, each group containing two sub-channels. Based on the duality of multi-frequency synthesis, modulate the complex DC components of the two sub-channels in each group to the first carrier frequency and the second carrier frequency, respectively. After combining, output N / 2 channels of the first-level synthesized signal. In the first-level multi-frequency unfiltered synthesis process, no filtering operation is set, and aliasing-free synthesis is achieved through the natural spectral isolation characteristics of the dual frequency points. Step S3: Perform the second-level interpolation process: perform 2x interpolation on the N / 2 channels of the first-level synthesized signal, perform mirror filtering on each interpolated signal through a half-band filter or an FIR filter, perform ±π / 4 complex frequency mixing and frequency shifting on the filtered signal, and finally combine every two mixed signals into one signal. Step S4: Perform a 2:1 synthesis process from level 3 to level K-1, where K is the total number of tree levels, and for level m, 2 ≤ m ≤ K-1. Each signal output from the previous stage is interpolated by 2 times, then mirror filtered by an interpolation filter, and then the filtered signal is mixed and frequency shifted by ±π / 4 complex number. Finally, every two mixed signals are superimposed and combined into one signal, resulting in a multi-channel composite signal with half the number of output signals. Step S5: Perform the final synthesis process: Perform ±π / 2 complex frequency mixing and frequency shifting on the two signals output from the K-1th stage, and superimpose the digital frequency group represented by the upper half circle and the digital frequency group represented by the lower half circle into a final multi-frequency time domain signal.

2. The method according to claim 1, characterized in that, In step S2, the modulation of the first carrier frequency and the second carrier frequency adopts any one of the dual-mode mixing topologies: the first mode is a ±Fs / 8 symmetric complex mixing topology, and the second mode is a ±Fs / 4 upper and lower semi-circular symmetric mixing topology, where Fs is the sampling rate of the current stage.

3. The method according to claim 1, characterized in that, Each branch in each stage of steps S2 to S5 is configured with an independent gated clock and a branch enable signal. In response to external branch encoding control commands, the clock supply for interpolation, mixing and filtering operations of any branch can be independently turned off so that the branch enters a zero dynamic power consumption state.

4. The method according to claim 1, characterized in that, It also includes a hierarchical truncation step S6: In response to an external truncation control command, after completing the synthesis processing of the Lth level, the output signals of the current level are immediately extracted as the final multi-frequency synthesis result, and the clock supply and operation of all branches from the L+1th level to the Kth level are turned off.

5. The method according to claim 1, characterized in that, In step S2, the multi-frequency unfiltered synthesis adopts a sample-and-hold method, which eliminates the need for filtering.

6. The method according to claim 1, characterized in that, The 2x interpolation process in steps S3 and S4 uses a zero-insertion method: a zero-value sample is inserted between every two adjacent samples of each signal output from the previous stage, and then fed into the interpolation filter for image suppression filtering.

7. The method according to claim 1, characterized in that, It also includes an independent amplitude and phase configuration step: In step S1, the amplitude and phase of the complex baseband signal of each sub-channel are independently assigned and uncoupled, so that the frequency point amplitude and phase of each sub-channel are independently controlled in the final multi-frequency time domain signal.

8. The method according to claim 1, characterized in that, The interpolation filters in steps S2 to S4 are selected from any one or a combination of the following linear filter groups: half-band filter HBF, cascaded integrator comb filter CIC, and finite impulse response filter FIR.

9. A binary tree-structured multi-frequency signal synthesis system, characterized in that, The system operates based on the method as described in any one of claims 1 to 8, comprising: The input interface is configured to receive N sub-channel complex baseband signals to be synthesized, where N is any positive integer; The first-stage unfiltered synthesis unit is connected to the input interface and is configured to divide N sub-channels into N / 2 groups. The complex DC components of the two sub-channels in each group are modulated to the first carrier frequency and the second carrier frequency respectively and then combined to output N / 2 first-stage synthesized signals. The first-stage unfiltered synthesis unit does not contain any interpolation filter. The second-level interpolation unit is connected to the first-level unfiltered synthesis unit and is configured to perform 2x interpolation processing on the N / 2 channels of the first-level synthesized signals and filter them through the interpolation filter. Each filtered signal is output independently and is not combined in pairs. A multi-stage 2:1 synthesis unit is connected to the second-stage interpolation unit and is configured to perform 2x interpolation, interpolation filtering, ±π / 4 complex frequency mixing and frequency shifting, and pairwise combining operations on each of the signals output from the previous stage. The number of synthesized signals is halved after each stage until two synthesized signals are output. The final synthesis unit, which is connected to the multi-stage 2:1 synthesis unit, is configured to perform ±π / 2 complex frequency mixing and shifting processing on the two synthesized signals respectively, and to superimpose and combine the digital frequency group represented by the upper half circle and the digital frequency group represented by the lower half circle into a final multi-frequency time-domain complex signal.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it can implement the steps of the method as described in any one of claims 1 to 8.

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