An implementation method for PCIE physical layer receiving end fast link equalization

Abstract

The application discloses an implementation method for PCIE physical layer receiving end fast link equalization, and relates to the technical field of link configuration. The method comprises the following steps: based on statistical confidence interval theory and error code rate distribution model, error code rates of a plurality of sampling offset points are evaluated by using short sequence error code test; based on the evaluation result of the error code rates of the offset points, an eye diagram boundary meeting a protocol target error code rate is determined; and according to the eye diagram boundary, link quality is evaluated or receiving end equalization configuration is completed. The technical problem that the existing link equalization takes a long time, it is difficult to accurately evaluate link quality and complete receiving end equalization configuration, and data transmission stability and reliability are affected is solved.

Description

Technical Field

[0001] This application relates to the field of link configuration technology, specifically to an implementation method for fast link equalization at the PCIE physical layer receiver. Background Technology

[0002] With the continuous increase in data transmission rates, PCIe physical layer receivers face more challenges. Traditional link equalization methods require long test sequences and complex calculations to assess bit error rate and determine eye diagram boundaries, resulting in excessively long link equalization times that cannot meet the real-time requirements of high-speed data transmission. Simultaneously, in complex electromagnetic environments, signal interference and attenuation are more severe, making it difficult for existing link equalization methods to accurately assess link quality and complete receiver equalization configuration, thus affecting the stability and reliability of data transmission. Summary of the Invention

[0003] This application provides a method for implementing fast link equalization at the PCIE physical layer receiver, which solves the technical problems of long link equalization time, difficulty in accurately assessing link quality and completing receiver equalization configuration, thus affecting the stability and reliability of data transmission.

[0004] The technical solution to the above-mentioned technical problems in this application is as follows: On the one hand, this application provides a method for implementing fast link equalization at the PCIe physical layer receiver, the method comprising: Based on the statistical confidence interval theory and the bit error rate distribution model, the bit error rate at multiple sampling offset points is evaluated using short sequence bit error rate testing; wherein, the bit error rate distribution model is a bathtub curve model. Based on the evaluation results of the offset bit error rate, the eye diagram boundary that satisfies the target bit error rate of the protocol is determined; Based on the eye diagram boundaries, assess link quality or complete receiver equalization configuration.

[0005] This application provides one or more technical solutions, which have at least the following technical effects or advantages: This application provides a method for implementing fast link equalization at the PCIe physical layer receiver, applicable to PCIe Gen5 and later versions. First, short-sequence bit error rate (BER) testing combined with statistical confidence interval theory and bathtub curve model is used to evaluate the BER at multiple sampling offset points. By shortening the test sequence length, testing time is reduced, improving link equalization efficiency and meeting the real-time requirements of high-speed data transmission. Second, the evaluation results of the BER at offset points determine the eye diagram boundary that meets the protocol target BER, enabling a more accurate understanding of the actual link situation. Third, by calculating the link's quality factor (FOM), link performance is quantified, providing a direct understanding of the link's quality. Furthermore, adjusting the receiver equalizer parameters based on the signal integrity status reflected by the eye diagram boundary effectively compensates for signal interference and attenuation during transmission, improving data transmission stability and reliability.

[0006] Through the above technical solutions, this application has advantages in improving link equalization efficiency, accurately assessing link quality, and completing receiver equalization configuration, and can provide a guarantee for high-speed data transmission. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a flowchart illustrating an implementation method for fast link equalization at the PCIe physical layer receiver provided in an embodiment of this application. Figure 2 This is a schematic diagram of a PCIE link operation, illustrating an implementation method for fast link equalization at the PCIE physical layer receiver provided in this application embodiment. Detailed Implementation

[0009] This application provides a method for implementing fast link equalization at the PCIe physical layer receiver, which addresses the technical problems of long link equalization time, difficulty in accurately assessing link quality and completing receiver equalization configuration, thus affecting the stability and reliability of data transmission.

[0010] Examples, such as Figure 1 As shown in the figure, this application embodiment provides a method for implementing fast link equalization at the PCIe physical layer receiver, including: S10: Based on the statistical confidence interval theory and the bit error rate distribution model, the bit error rate of multiple sampling offset points is evaluated using short sequence bit error rate testing; wherein, the bit error rate distribution model is a bathtub curve model; In this embodiment, firstly, the statistical confidence interval theory, based on probability statistics, can estimate the range of values ​​for population parameters at a certain confidence level. In this application, this theory is used to infer the true bit error rate at sampling offset points based on short sequence bit error rate testing.

[0011] Furthermore, the bathtub curve model is a common bit error rate (BER) distribution model, which is a curve model describing the change in failure rate of hardware, components, or systems throughout their entire service life. In this application, the bathtub curve model can describe the BER variation characteristics at different stages. Specifically, the bathtub curve model uses the following double exponential function form to describe the relationship between the BER and the sampling offset t (or voltage offset v): BER(t) = α·e^{β·|t|} + γ, where t is the sampling offset (in UI or mV), α, β, and γ are model parameters, determined by least-squares fitting of discrete sampling point data obtained through short-sequence bit error rate testing; γ is the background bit error rate constant, reflecting the inherent noise level of the channel, for example, it can be taken as the upper limit of the target bit error rate specified in the protocol, and can be adaptively adjusted according to the test results during actual fitting.

[0012] Secondly, short-sequence bit error rate (BER) tests are performed at multiple preset sampling offset points on the horizontal and / or vertical axes of the eye diagram to replace direct measurement of the target low BER. Since traditional long-sequence tests are time-consuming, while short-sequence tests can significantly shorten the test duration and improve the efficiency of link equalization, short sequences are chosen. The bit sequence length of the short sequence is less than the statistical requirement for the target BER.

[0013] For sampling offset points where no errors occurred in the short sequence test, based on the statistical confidence interval theory, their true bit error rate is determined to be lower than the preset confidence upper limit. This is because, at a certain confidence level, if no errors occurred in the short sequence test, the true bit error rate at that sampling offset point is likely to be low.

[0014] Specifically, step S10 in the method includes: At multiple sampling offset points on the horizontal or vertical axis of the eye diagram, short sequence bit error rate tests are performed respectively. The number of bit errors occurring at each sampling offset point in the short sequence test is recorded, and the ratio of the number of bit errors to the number of sampling offset points is used as the direct bit error rate. Based on the statistical confidence interval theory, for sampling offset points where no errors are observed, the true bit error rate of the sampling offset point is determined to be lower than the preset upper limit value at a preset confidence level. The bit error rate obtained directly from each sampling offset point and the upper limit of the bit error rate derived from the confidence interval theory are used together as the bit error rate evaluation result for that sampling offset point.

[0015] In this embodiment, firstly, short-sequence bit error rate (BER) tests are performed at multiple preset sampling offset points on the horizontal or vertical axis of the eye diagram, where the bit sequence length is less than the target BER statistical requirement. The bit sequence length of the short-sequence BER test is less than or equal to 10^6. This value is set considering both testing efficiency and the reliability of BER assessment. Short-sequence BER testing can compress the testing time at each offset point, improving testing efficiency while ensuring testing accuracy. Compared to traditional long-sequence testing, it can obtain preliminary BER information for multiple sampling offset points in a shorter time.

[0016] For sampling offset points where errors occur in short sequence tests, the ratio of the number of errors to the number of sampling offset points is used as the direct bit error rate (BER). For sampling offset points where no errors occur, based on the statistical confidence interval theory, the true BER is determined to be lower than a preset confidence upper limit. The statistical confidence interval theory states that if N bits are tested without errors, at a confidence level of CL, the true BER p satisfies... From this, the upper limit of p can be derived, which can be used as the bit error rate estimate for that sampling offset point, thus completing the bit error rate assessment for all sampling offset points.

[0017] Secondly, by fitting the measured bit error rate (BER) values ​​or upper confidence limits at each sampling offset point to the bathtub curve model, the variation characteristics of BER at different stages can be described more accurately. The bathtub curve model reflects the variation law of BER at different stages, providing a basis for subsequently determining the eye diagram boundary. In the fitting process, data obtained from short-sequence tests are used as data points, and mathematical methods are used to match them with the bathtub curve model, so that the model can better fit the actual BER distribution.

[0018] Then, based on the fitted bathtub curve model, the boundary positions within the eye diagram region that satisfy the protocol target bit error rate are extrapolated. Specifically, the extrapolated boundary position t_boundary that satisfies the protocol target bit error rate BER_target is calculated as follows: make Substituting the fitted model equations, we obtain the following solution: ,like If the eye diagram boundary in that direction approaches infinity, it means that the current channel quality is significantly better than the protocol requirements.

[0019] The above process is based on the bit error rate variation pattern reflected by the model. Through mathematical calculation and reasoning, it predicts at what offset the bit error rate can reach the target value required by the protocol, thereby determining the boundary of the eye diagram.

[0020] In the above process, the accuracy and reliability of the model are considered. Although the bathtub curve model can describe the characteristics of bit error rate variation well, there may be factors in reality that affect the model's fitting effect. For example, complex electromagnetic environments may cause signal interference and attenuation, causing the bit error rate variation to deviate from the model's prediction. Therefore, when extrapolating, the model is appropriately modified and adjusted to ensure that the obtained eye diagram boundary positions are as accurate as possible.

[0021] For example, to control extrapolation error, the error correction mechanism is as follows: (a) Confidence interval constraint: Extrapolation is allowed only when the goodness of fit is ≥0.95; otherwise, the number of short test points is increased or the length of the single-point test sequence is extended. (b) Boundary verification: Near the boundary position obtained by extrapolation, an additional verification sampling point is set up to conduct actual bit error test. If the relative deviation between the measured bit error rate and the target bit error rate exceeds ±50%, the method is reverted to binary search for repositioning. (c) Limiting protection: The extrapolation boundary shall not exceed 1.5 times the initially set maximum offset to avoid unreliable results caused by over-extrapolation.

[0022] Simultaneously, in determining the eye diagram boundary, actual test data can be used for verification and optimization. By analyzing and comparing the test results of multiple sampling offset points, the reasonableness of the extrapolated eye diagram boundary can be determined. If a significant deviation is found between the actual test results and the model prediction, the model parameters and fitting method should be re-examined, and the model should be further optimized and improved.

[0023] Furthermore, sampling offset points that prematurely terminate the evaluation during short sequence testing require special handling. Since the cumulative bit error rate reaches the early termination threshold, they are deemed not to meet the protocol's target bit error rate requirements. In subsequent analysis and processing, offset points that meet the requirements will be excluded, or subjected to additional testing and evaluation to ensure that they do not affect the determination of the final eye diagram boundaries and the assessment of link quality.

[0024] The above steps provide a basis for subsequent link quality assessment and receiver load balancing configuration, thereby improving the efficiency of PCIe physical layer receiver load balancing and the stability and reliability of data transmission.

[0025] S20: Based on the evaluation results of the offset bit error rate, determine the eye diagram boundary that satisfies the target bit error rate of the protocol; In this embodiment, the eye diagram boundary is first determined based on the evaluation results of the bit error rate at each sampling offset point, including the bit error rate obtained by direct measurement and the upper confidence limit of the bit error rate obtained by statistical confidence interval theory.

[0026] It should be noted that the steps S10, "extrapolating the eye diagram boundary based on the bathtub curve model," and S20, "finding the boundary point by iteratively adjusting the offset using the bisection method," are not two independent steps that must be executed simultaneously. Instead, they are two boundary localization strategies that can be used individually or in combination, depending on the actual link quality and test conditions. The specific logic is as follows: (a) Choose one to use: When the number of sampling points obtained from the short sequence bit error test is sufficient (≥5 effective offset points) and the goodness of fit is ≥0.95, the extrapolation method in step S10 is preferred to directly calculate the eye diagram boundary without performing the bisection method iteration. When the number of sampling points is insufficient, the data dispersion is large, or the goodness of fit is lower than 0.95, the bisection method in step S20 is used for boundary localization.

[0027] (ii) Combined use: First, the boundary position is quickly estimated using the extrapolation method in step S10, and then the estimation result is used as the initial maximum offset or initial search center for the bisection method in step S20. Specifically, the extrapolated boundary position t_boundary is used as the boundary or center point of the starting search range of the bisection method. The search window width is set to ±Δ, where Δ can be 0.5UI or 10mV. The bisection method iteration is performed within this window, and the final output is the precise boundary point that satisfies the target bit error rate of the protocol.

[0028] (III) Rollback Mechanism: If the extrapolated boundary position t_boundary fails the verification during the verification process, the system automatically switches to the bisection method in step S20 for relocation to ensure the reliability of the final boundary result.

[0029] Through the above-mentioned selection, combination, and backoff mechanisms, this application can balance the speed and accuracy of boundary positioning under different channel conditions, avoiding the limitations of a single method in a specific scenario.

[0030] Specifically, by acquiring bit error rate (BER) data from multiple sampling offset points, an offset point at the middle position is selected from the range formed by the data. The BER of this point is then used to determine whether it meets the protocol's target BER requirement. If it does, a binary search is performed between this point and the upper limit of the range; if not, the search continues between this point and the lower limit of the range. By continuously narrowing the search range, the eye diagram boundary that satisfies the protocol's target BER is gradually approached.

[0031] In determining the eye diagram boundary, the discreteness and uncertainty of the data also need to be considered. Since the sampling offset points are finite, it may not be possible to accurately find the boundary position that satisfies the target bit error rate of the protocol. Therefore, in practice, an error range is set, for example, ±1%. When the difference between the bit error rate of the found offset point and the target bit error rate of the protocol is within this error range, the offset point is approximated as the eye diagram boundary.

[0032] Specifically, based on the evaluation results of the bit error rate at the offset point, the eye diagram boundary that satisfies the target bit error rate of the protocol is determined, which is performed by a binary search method, including: Set the maximum offset for each direction of the eye diagram; By iteratively adjusting the offset using the binary search method, the boundary point where the bit error rate meets the target value can be found.

[0033] In this embodiment of the application, for the eye diagram, the closer to the center point O of the eye diagram, the smaller the impact of time jitter and voltage noise, and therefore the lowest bit error rate; conversely, for the edge of the eye diagram, since the signal amplitude is close to the decision threshold, time jitter is likely to cause the sampling point to shift, and therefore the bit error rate is the highest.

[0034] First, for each direction of the eye diagram, a maximum offset is set to define the range for the subsequent search process. The maximum offset is determined based on the actual hardware conditions and protocol requirements, representing the maximum possible offset in that direction. After setting the maximum offset, the offset is iteratively adjusted using a binary search algorithm. The binary search algorithm halves the search range each time, enabling it to quickly approach the target value.

[0035] Furthermore, during the iteration process, the middle offset of the current search range is first taken, and the bit error rate (BER) is tested at this offset. If the BER at this offset meets the target value, it indicates that the eye diagram boundary may be between this offset and the upper limit of the current range, so the search range is narrowed to the area between this offset and the upper limit; if the BER at this offset does not meet the target value, it indicates that the eye diagram boundary may be between this offset and the lower limit of the current range, so the search range is narrowed to the area between this offset and the lower limit.

[0036] Repeat the above steps until a boundary point is found where the bit error rate meets the target value. In practice, due to measurement errors and data dispersion, it may be impossible to find a boundary point that is exactly equal to the target bit error rate. In this case, based on the previously set error range, when the difference between the bit error rate of the found offset point and the target bit error rate is within the error range, the offset point is approximated as the eye diagram boundary.

[0037] By employing a binary search method based on limited sampling offset data, the eye diagram boundaries that satisfy the protocol's target bit error rate are determined. This not only improves search efficiency but also, to some extent, overcomes the impact of data discreteness and uncertainty, providing a basis for subsequent link quality assessment and receiver equalization configuration.

[0038] After determining the eye diagram boundaries, the parameters of the receiver equalizer can be adjusted based on the signal integrity reflected by these boundaries. The position and shape of the eye diagram boundaries directly reflect the signal distortion and noise interference levels during transmission. A narrow eye diagram boundary indicates significant signal distortion and noise interference, requiring adjustment of receiver equalizer parameters such as gain and phase to compensate for interference and attenuation during transmission, thereby improving data transmission stability and reliability.

[0039] Furthermore, by iteratively adjusting the offset using a binary search method, the boundary points where the bit error rate meets the target value are found, including: Initially set the maximum offset x; Test the bit error rate at offset x / 2; Based on the bit error rate result, adjust the offset by half the amount of the previous adjustment until the offset is 1. Repeat the process in the four directions of the eye diagram to locate boundary points A, B, C, and D, and use the final determined offset points as the eye diagram boundary points.

[0040] In this embodiment, firstly, a maximum offset x is initially set. The maximum offset x is determined based on the actual situation and protocol requirements of the PCIe physical layer receiver link, representing the maximum possible offset in each direction. Testing the bit error rate at offset x / 2 is the starting step of the binary search iteration. Taking the intermediate offset for testing can quickly narrow down the search range.

[0041] Secondly, after obtaining the bit error rate (BER) at offset x / 2, the offset is adjusted based on this result, with the adjustment amount being half of the previous one, until the adjustment amount is 1. If the BER at offset x / 2 meets the target value, it means that the eye diagram boundary may be between this offset and the maximum offset x, then the offset for the next test is (x + x / 2) / 2; if the BER at offset x / 2 does not meet the target value, it means that the eye diagram boundary may be between 0 and x / 2, then the offset for the next test is x / 4. This process is iterated continuously, with the adjustment amount gradually decreasing, approaching the boundary point that meets the protocol's target BER.

[0042] Then, the above process is repeated for the four directions of the eye diagram: the left and right sides in the horizontal direction and the top and bottom sides in the vertical direction. The above steps are performed in each direction to finally locate the boundary points A, B, C, and D. The finally determined offset points are used as the eye diagram boundary points in that direction.

[0043] In finding the boundary points that satisfy the target value, attention should be paid to the impact of measurement errors and data dispersion on the results. Due to various interference factors in actual measurements, the measured bit error rate may have some error. Furthermore, the sampling offset points are finite, and it may be impossible to accurately find the boundary positions that satisfy the protocol's target bit error rate. Therefore, in practice, based on the previously set error range, when the difference between the bit error rate of the found offset point and the protocol's target bit error rate is within the error range, the offset point is approximated as an eye diagram boundary point.

[0044] For example, the coordinates of ABCD can be quickly found based on the principle of bisection. The specific steps are as follows: First, select one of the directions OA, OB, OC, or OD, set the maximum offset x from point O, and set the bit error rate (BER) threshold for each point. If the accumulated BER at a point exceeds the threshold, the BER measurement for that point is immediately terminated. If the BER at a point is less than the protocol requirement, that point is determined to be a boundary point; otherwise, the next offset is half of the selected maximum value, x / 2. Secondly, if the bit error rate at point x / 2 is less than the protocol requirement, then add x / 4 to the current offset; otherwise, subtract x / 4 from the current offset and recalculate the bit error rate at the resulting offset position. Next, repeat step two in a loop, dividing the offset modification by 2 each time. So the configuration modification amount is x / 2, x / 4, x / 8, etc., until the configuration modification amount becomes 1. The final boundary point is the offset obtained from the last calculation.

[0045] Finally, the values ​​for the four directions of the X and Y axes are repeated to determine the offset of ABCD, which serves as the criterion for judging the current channel signal quality.

[0046] Once the four boundary points A, B, C, and D of the eye diagram are determined, its boundaries can be delineated. The eye diagram boundaries visually reflect the signal quality during transmission, providing a basis for subsequent link quality assessment and receiver equalization configuration. By analyzing the eye diagram boundaries, information such as signal distortion, noise interference, and timing jitter can be obtained, allowing for targeted adjustments to the receiver equalizer parameters to improve the efficiency of PCIe physical layer receiver link equalization and the stability and reliability of data transmission.

[0047] Meanwhile, when calculating the link quality factor (FOM) using the eye diagram boundaries, the eye diagram boundaries are already determined, allowing for more accurate acquisition of parameters such as eye diagram height and width. This, combined with bit error rate (BER) information, enables the calculation of a more precise FOM. Based on the calculated FOM value, the parameters of the receiver equalizer are further optimized, enabling the PCIe physical layer receiver link to achieve optimal performance.

[0048] S30: Evaluate link quality or complete receiver equalization configuration based on the eye diagram boundaries.

[0049] In this embodiment, link quality is evaluated by analyzing the signal transmission information at the eye diagram boundary. From the overall shape of the eye diagram boundary, if the boundary is relatively regular, clear, and has a large angle, it indicates that the signal distortion during transmission is small, noise interference is relatively weak, and the link quality is good. Conversely, if the eye diagram boundary is blurry, irregular, or has a small angle, it indicates that the signal may have suffered significant interference and attenuation, resulting in poor link quality.

[0050] Specifically, the height of the eye diagram reflects the amplitude of the signal. A higher eye diagram height indicates a stronger signal, which can resist noise interference to some extent. The width of the eye diagram is related to the timing jitter of the signal; a wider eye diagram indicates less timing jitter and more stable signal transmission. At the same time, a steeper slope at the eye diagram boundary indicates shorter rise and fall times, which is beneficial for improving data transmission rate.

[0051] Based on the analysis of the eye diagram boundaries, the equalization configuration at the receiver is completed. If the evaluation reveals poor link quality, such as narrow eye diagram boundaries or severe signal distortion, the parameters of the receiver equalizer are adjusted. For insufficient signal amplitude, the equalizer gain can be appropriately increased to improve signal strength. For significant time jitter, the equalizer phase parameters can be adjusted to reduce the signal time offset.

[0052] During the adjustment of the receiver equalizer parameters, multiple tests and optimizations were performed. After each parameter adjustment, the eye diagram boundaries and bit error rate were remeasured, and the changes in link quality were observed. If the link quality improved after the adjustment but still did not reach the ideal state, the parameters were fine-tuned until the link quality met the protocol requirements.

[0053] Furthermore, the method is applied to the receiver link equalization process of the PCIE protocol physical layer, and the eye diagram boundary is used to calculate the link quality factor (FOM).

[0054] In this embodiment, the Link Quality Factor (FOM) is an indicator of PCIe link performance. It reflects the overall quality of the link by considering factors such as signal amplitude, noise, and jitter. When calculating the FOM through the eye diagram boundary, parameters such as the height, width, and bit error rate of the eye diagram are taken into account.

[0055] Specifically, the height of the eye diagram reflects the amplitude of the signal; the greater the height, the stronger the signal. The width of the eye diagram is related to the timing jitter of the signal; the wider the width, the smaller the timing jitter. When calculating the link quality factor (FOM), the height and width of the eye diagram are quantified and combined with bit error rate (BER) information for calculation.

[0056] For example, the height and width of the eye diagram are normalized, and then weighted according to the bit error rate to obtain the link quality factor (FOM). The higher the calculated FOM value, the better the link performance, and the higher the stability and reliability of data transmission.

[0057] After obtaining the link quality factor (FOM), the parameters of the receiver equalizer are further optimized. A low FOM value indicates poor link performance, requiring adjustments to the equalizer parameters, such as increasing gain to improve signal amplitude or adjusting phase to reduce timing jitter. Through continuous adjustment and optimization, the FOM is brought to its optimal state, thereby improving the efficiency of PCIe physical layer receiver link equalization and the stability and reliability of data transmission.

[0058] Specifically, step S30 in the method includes: Based on the coordinates of the eye diagram boundary on the horizontal and vertical axes, the quality factor (FOM) of the link is calculated. Based on the signal integrity status reflected by the eye diagram boundary, adjust the parameters of the receiver equalizer, including at least one of the gain of the continuous-time linear equalizer (CTLE) and the tap coefficients of the decision feedback equalizer (DFE).

[0059] In this embodiment, the quality factor (FOM) of the link is first calculated based on the coordinates of the eye diagram boundaries on the horizontal and vertical axes. The horizontal axis coordinates are related to the signal's time jitter, while the vertical axis coordinates reflect the signal's amplitude. The coordinate information is quantized by first normalizing the horizontal and vertical axis coordinates to ensure they are under a unified metric, and then weighted by the bit error rate. The resulting FOM value comprehensively reflects the overall performance of the link, including signal strength, time jitter, and anti-interference capabilities.

[0060] For example, the time jitter represented by the horizontal axis and the signal amplitude represented by the vertical axis are normalized so that their values ​​range from 0 to 1. Assume the normalized horizontal axis is X, the normalized vertical axis is Y, and the bit error rate is BER. The formula FOM = (X...) The link quality factor (FOM) is calculated using (X) / BER. The product of X and Y reflects the overall performance of the signal in both time and amplitude dimensions, while dividing by the bit error rate highlights the impact of the bit error rate on link performance.

[0061] Secondly, adjust the parameters of the receiver equalizer based on the signal integrity reflected by the eye diagram boundaries. If the eye diagram boundaries indicate amplitude attenuation during transmission, adjust the gain of the continuous-time linear equalizer (CTLE). Increasing the CTLE gain enhances the signal amplitude, making it better able to resist noise interference and improve signal strength. For example, when the eye diagram height is small, it indicates insufficient signal amplitude. In this case, gradually increase the CTLE gain value while observing changes in the eye diagram boundaries and bit error rate.

[0062] If the eye diagram boundary indicates severe inter-symbol interference (ISI), the tap coefficients of the decision feedback equalizer (DFE) need to be adjusted. The DFE predicts and cancels ISI for the current symbol by weighted summation of sampled values ​​from past symbols. Adjusting the DFE tap coefficients can effectively reduce ISI and improve signal transmission quality. For example, optimizing the DFE tap coefficients based on the eye diagram shape and bit error rate (BER) allows for more accurate compensation for signal distortion during transmission.

[0063] During parameter adjustments, monitor changes in link quality. After each adjustment, remeasure the eye diagram boundaries and bit error rate to evaluate the effect. If link quality improves after adjustment but does not yet meet protocol requirements, continue fine-tuning. By continuously optimizing the receiver equalizer parameters, the link quality factor (FOM) is optimized to achieve the best possible state, thereby improving the efficiency of PCIe physical layer receiver link equalization and the stability and reliability of data transmission.

[0064] The quality factor (FOM) of the calculated link includes: FOM = f(Ax, Bx, Cy, Dy); Where Ax and Bx are the left and right boundary coordinates of the eye diagram on the time axis, respectively; Cy and Dy are the lower and upper boundary coordinates of the eye diagram on the voltage axis, respectively; and f is the mapping function defined according to the protocol.

[0065] In this embodiment, the mapping function f defined by the protocol is used to synthesize the boundary coordinates into a single quality assessment value. It comprehensively considers the boundary information of the signal in both time and voltage dimensions, integrating the left and right boundary coordinates Ax and Bx of the eye diagram on the time axis, and the lower and upper boundary coordinates Cy and Dy on the voltage axis. Based on the requirements and standards of the PCIE protocol, the mapping function can convert the coordinate information of the eye diagram boundaries into specific numerical values, namely the link quality factor (FOM).

[0066] Different protocols may have different mapping functions f to suit different link performance evaluation needs. In practical applications, the appropriate mapping function is determined based on the specific PCIe protocol version and related specifications. The FOM value obtained through function calculation reflects the current performance status of the PCIe physical layer receiver link.

[0067] For example, in a specific PCIe protocol, the mapping function f may weight the difference between Ax and Bx and the difference between Cy and Dy, and then combine it with factors such as bit error rate to finally obtain the link quality factor (FOM). After obtaining the FOM value, the parameters of the receiver equalizer are adjusted.

[0068] Specifically, assessing link quality or completing receiver equalization configuration based on the eye diagram boundaries also includes: The calculated link quality factor is reported to the PCIe controller layer, which then determines whether the current link quality meets the equalization requirements based on the comparison between the link quality factor (FOM) and the protocol target value. If the link quality factor (FOM) is lower than the target value of the protocol, the controller layer issues an equalization parameter adjustment instruction to iteratively optimize the parameters of the receiver equalizer. The equalization parameters include the gain level of the continuous-time linear equalizer and the tap coefficient of the decision feedback equalizer. If the link quality factor (FOM) still fails to reach the protocol target value within the preset maximum number of iterations, the link balancing is deemed to have failed, triggering a link retraining or deceleration negotiation process. The iterative optimization of the equilibrium parameters adopts a gradient descent strategy. After each adjustment, the eye diagram boundary localization and link quality factor (FOM) calculation are re-executed until the link quality factor (FOM) meets the protocol target value or reaches the maximum number of iterations.

[0069] In this embodiment of the application, the calculated link quality factor (FOM) is first reported to the PCIe controller layer. The controller layer compares the received FOM value with the target value required by the protocol to determine whether the link quality after the current equalization adjustment meets the standard.

[0070] Specifically, if the FOM reaches or exceeds the protocol target value, it means that the current link equalization effect meets the requirements, the entire equalization process can end, and the link enters the normal data transmission state; if the FOM is lower than the protocol target value, the controller layer will send adjustment instructions for the equalization parameters downward, so that the receiving end can adjust the equalization parameters such as the gain level of the continuous-time linear equalizer and the tap coefficient of the decision feedback equalizer, and gradually optimize the parameters through iteration.

[0071] The iterative optimization process employs a gradient descent strategy, using the direction of FOM improvement as the direction of parameter adjustment. After each parameter adjustment, the eye diagram boundary localization step must be re-executed, and the current link quality factor FOM must be recalculated. This process of adjustment-measurement-calculation is repeated until the link quality factor FOM meets the protocol target value or reaches the maximum number of iterations.

[0072] Furthermore, an implementation method for fast link equalization at the PCIe physical layer receiver also includes: During the short sequence error test at each offset point, the number of errors is accumulated in real time. When the cumulative number of bit errors exceeds the preset bit error threshold, the bit error test at the current offset point is terminated in advance, and the current offset point is directly determined to not meet the protocol target bit error rate requirement.

[0073] In this embodiment, it is not necessary to wait for the entire short sequence test to be completed before obtaining the result. Once the cumulative number of bit errors exceeds the preset threshold, the offset point is directly determined to be unacceptable and the test is terminated. This can reduce the time consumed by a single bit error test, speed up the entire eye diagram boundary localization and link balancing process, and the early termination mechanism effectively avoids unnecessary test time consumption. In particular, for offset points with bit error rates far exceeding the protocol requirements, the judgment result can be given quickly, thereby improving the efficiency of the entire link balancing process and shortening the link training and balancing time.

[0074] The preset bit error rate threshold is determined based on two parameters: the target bit error rate specified in the PCIE protocol and the total test length of the current short sequence bit error test. The value of the preset bit error rate threshold is directly proportional to the target bit error rate and inversely proportional to the total test length. Under the premise of ensuring the accuracy of bit error judgment, the early termination mechanism should be retained as much as possible to improve test efficiency and avoid misjudgment due to unreasonable threshold setting. For example, it can be obtained by multiplying the target bit error rate by the total test length and then rounding up.

[0075] Furthermore, such as Figure 2 As shown, the method is executed by controlling the physical layer SerDes through the PCIe controller layer. The controller layer issues equalization commands, and the physical layer performs eye diagram scanning and boundary point localization. The pre-emphasis configuration at the transmitting end is located at the transmitting end of the local physical layer and is used to compensate for high-frequency signal attenuation and coordinate with the equalization at the receiving end, thereby optimizing end-to-end signal integrity. The high-speed serial port transmitting end is located at the end of the transmitting path of the local physical layer and serves as the driving circuit for the output signal. The high-speed serial port receiving end is located at the beginning of the receiving path of the receiving end of the physical layer and is the core circuit for signal reception and quality assessment, responsible for recovering correct data from damaged signals and determining channel quality.

[0076] In this embodiment, the controller layer issues equalization commands based on the feedback results of link requirements and link performance. These commands include specific requirements for adjusting the parameters of the receiver equalizer, such as the gain adjustment value of the continuous-time linear equalizer (CTLE) and the tap coefficient adjustment scheme of the decision feedback equalizer (DFE).

[0077] The physical layer (SerDes) is responsible for the actual execution. Upon receiving the equalization command from the controller layer, the physical layer begins eye diagram scanning and boundary point localization. Utilizing its own hardware circuitry and signal processing capabilities, it samples and analyzes the input signal to draw the eye diagram. During the scanning process, the physical layer gradually determines the boundary points A, B, C, and D of the eye diagram using methods such as the previously described bisection method.

[0078] The physical layer feeds back the eye diagram boundary point information obtained from the localization to the controller layer. The controller layer, combining protocol requirements and performance targets, calculates the link's quality factor (FOM) and determines whether further adjustments to the receiver equalizer parameters are needed. If adjustments are required, the controller layer issues a new equalization command, and the physical layer continues to execute the corresponding operations. This process iterates until the link reaches its optimal performance state.

[0079] By controlling the physical layer SerDes execution through the PCIe controller layer, effective management and control of link balancing at the PCIe physical layer receiver is achieved. Leveraging the decision-making capabilities of the controller layer and the execution capabilities of the physical layer improves the efficiency and accuracy of link balancing, ensuring the stability and reliability of data transmission at the PCIe physical layer receiver. Simultaneously, the layered control architecture also provides the system with better scalability and flexibility, enabling it to adapt to different application scenarios and protocol requirements.

[0080] In summary, compared with the prior art, this application, without changing the protocol process, clarifies the logical relationship between the bathtub curve extrapolation method and the bisection method based on the confidence interval theory of statistics, and discloses the specific mathematical form, calculation logic and error correction method of the extrapolation method. By adjusting the bit error rate measurement method of the X-axis and Y-axis, the statistical time of bit error rate is shortened, thereby meeting the time requirements of the protocol for RX end equalization.

[0081] In summary, the embodiments of this application have at least the following technical effects: This application provides a method for implementing fast link equalization at the PCIe physical layer receiver, applicable to PCIe Gen5 and above. First, it utilizes short-sequence bit error rate testing combined with statistical confidence interval theory and bathtub curve models to evaluate the bit error rate at multiple sampling offset points. By shortening the test sequence length, testing time is reduced, improving link equalization efficiency and meeting the real-time requirements of high-speed data transmission. Second, based on the evaluation results of the offset point bit error rate, methods such as binary search are used to determine the eye diagram boundary that meets the protocol target bit error rate, enabling a more accurate understanding of the actual link situation. Third, by calculating the link's quality factor (FOM), link performance is quantified, providing a direct understanding of the link's quality. Furthermore, by adjusting the parameters of the receiver equalizer based on the signal integrity status reflected by the eye diagram boundary, interference and attenuation during signal transmission can be effectively compensated, improving data transmission stability and reliability. Through the above technical solutions, this application has advantages in improving link equalization efficiency, accurately evaluating link quality, and completing receiver equalization configuration, providing assurance for high-speed data transmission.

[0082] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this specification. Additionally, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are possible or may be advantageous.

[0083] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for implementing fast link equalization at the PCIe physical layer receiver, characterized in that, The method includes: Based on the statistical confidence interval theory and the bit error rate distribution model, the bit error rate of multiple sampling offset points is evaluated using short sequence bit error rate testing, wherein the bit error rate distribution model is a bathtub curve model; Based on the evaluation results of the offset bit error rate, the eye diagram boundary that satisfies the target bit error rate of the protocol is determined; Based on the eye diagram boundaries, assess link quality or complete receiver equalization configuration.

2. The method for implementing fast link equalization at the PCIe physical layer receiver according to claim 1, characterized in that, Based on statistical confidence interval theory and bit error rate distribution models, the bit error rate at multiple sampling offset points is evaluated using short sequence bit error rate testing, including: At multiple sampling offset points on the horizontal or vertical axis of the eye diagram, short sequence bit error rate tests are performed respectively. The number of bit errors occurring at each sampling offset point in the short sequence test is recorded, and the ratio of the number of bit errors to the number of sampling offset points is used as the direct bit error rate. Based on the statistical confidence interval theory, for sampling offset points where no errors are observed, the true bit error rate of the sampling offset point is determined to be lower than the preset upper limit value at a preset confidence level. The bit error rate obtained directly from each sampling offset point and the upper limit of the bit error rate derived from the confidence interval theory are used together as the bit error rate evaluation result for that sampling offset point.

3. The method for implementing fast link equalization at the PCIe physical layer receiver according to claim 1, characterized in that, Based on the evaluation results of the offset point bit error rate, the eye diagram boundaries that satisfy the protocol target bit error rate are determined, including: Set the maximum offset for each direction of the eye diagram; By iteratively adjusting the offset using the binary search method, the boundary point where the bit error rate meets the target value can be found.

4. The method for implementing fast link equalization at the PCIe physical layer receiver according to claim 3, characterized in that, By iteratively adjusting the offset using a binary search method, the boundary points where the bit error rate meets the target value are found, including: Initially set the maximum offset x; Test the bit error rate at offset x / 2; Based on the bit error rate result, adjust the offset by half the amount of the previous adjustment until the offset is 1. Repeat the process in the four directions of the eye diagram to locate boundary points A, B, C, and D, and use the final determined offset points as the eye diagram boundary points.

5. The method for implementing fast link equalization at the PCIe physical layer receiver according to claim 1, characterized in that, Based on the eye diagram boundaries, assess link quality or complete receiver equalization configuration, including: Based on the coordinates of the eye diagram boundary on the horizontal and vertical axes, calculate the link quality factor (FOM). Based on the signal integrity status reflected by the eye diagram boundary, adjust the parameters of the receiver equalizer, including at least one of the gain of the continuous-time linear equalizer (CTLE) and the tap coefficients of the decision feedback equalizer (DFE).

6. The method for implementing fast link equalization at the PCIe physical layer receiver according to claim 5, characterized in that, The quality factor (FOM) of the link is calculated, including: FOM = f(Ax, Bx, Cy, Dy); Where Ax and Bx are the left and right boundary coordinates of the eye diagram on the time axis, respectively; Cy and Dy are the lower and upper boundary coordinates of the eye diagram on the voltage axis, respectively; and f is the mapping function defined according to the protocol.

7. The method for implementing fast link equalization at the PCIe physical layer receiver according to claim 2, characterized in that, The method further includes: During the short sequence error test at each offset point, the number of errors is accumulated in real time. When the cumulative number of bit errors exceeds the preset bit error threshold, the bit error test at the current offset point is terminated in advance, and the current offset point is directly determined to not meet the protocol target bit error rate requirement.

8. The method for implementing fast link equalization at the PCIe physical layer receiver according to claim 6, characterized in that, Based on the eye diagram boundaries, assessing link quality or completing receiver equalization configuration further includes: The calculated link quality factor is reported to the PCIe controller layer, which then determines whether the current link quality meets the equalization requirements based on the comparison between the link quality factor (FOM) and the protocol target value. If the link quality factor (FOM) is lower than the target value of the protocol, the controller layer issues an equalization parameter adjustment instruction to iteratively optimize the parameters of the receiver equalizer. The equalization parameters include the gain level of the continuous-time linear equalizer and the tap coefficient of the decision feedback equalizer. If the link quality factor (FOM) still fails to reach the protocol target value within the preset maximum number of iterations, the link balancing is deemed to have failed, triggering a link retraining or deceleration negotiation process. The iterative optimization of the equilibrium parameters adopts a gradient descent strategy. After each adjustment, the eye diagram boundary localization and link quality factor (FOM) calculation are re-executed until the link quality factor (FOM) meets the protocol target value or reaches the maximum number of iterations.

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