A three-layer hybrid longest prefix matching lookup method, system and hot updating method thereof

Abstract

The application discloses a three-layer hybrid longest prefix matching searching method, a system and a hot updating method thereof, and relates to the technical field of computer networks. The method comprises the following steps: obtaining a perfect hash searching result; obtaining a cuckoo hash searching result; obtaining an updatable CAM searching result; delaying and aligning the three searching results to obtain an aligned searching result; selecting the longest prefix from the aligned searching result and a default empty result to obtain a matching searching result. The system comprises a perfect hash engine, a cuckoo hash engine, an updatable CAM engine, a delay alignment unit and a longest prefix matching arbitration unit. The perfect hash engine, the cuckoo hash engine and the updatable CAM engine perform the input searching request in parallel, and the output ends are connected with the delay alignment unit. The delay alignment unit is connected with the longest prefix matching arbitration unit. The application can simultaneously achieve the best in the three dimensions of static density, incremental updating delay and transient updating atomicity.

Description

Technical Field

[0001] This invention belongs to the field of message processing technology in computer networks, specifically relating to a three-layer hybrid longest prefix matching search method, system, and its hot update method. Background Technology

[0002] Longest Prefix Match (LPM) is a critical operation for packet forwarding in IP routers. Given a lookup IP and a routing table storing N (prefix, mask length, next hop) triples, LPM requires returning the entry with the longest mask that matches the lookup IP. In line-speed Ethernet processing of 100 Gbps and higher, LPM is typically implemented in hardware, and existing solutions can be broadly categorized into four types: 1) Ternary Content Addressable Memory (TCAM) scheme. Each route is encoded as a (value, mask) tuple, and the entire table is matched in parallel. The advantage is that the longest match is output per cycle. The disadvantages are large chip area, high power consumption, limited scale, high price, and the off-chip TCAM interface bandwidth is difficult to match the speed of 100 Gbps or higher.

[0003] 2) Multi-hash bucketing + Cuckoo relocation scheme. This scheme has a space utilization rate of approximately 94% and low latency for single incremental updates. However, it is prone to Cuckoo deadlock when the prefix distribution is uneven, and it requires 1W6R multi-port memory, with over a thousand on-chip BRAM (Block Random Access Memory) ports. Under adversary attack scenarios, the load factor may further degrade.

[0004] 3) Trie-based multi-step pipelined schemes (such as FlashTrie and Tree Bitmap). This involves dividing the prefix into several hierarchical tree structures based on bits and performing pipelined lookups. The advantage is support for high-density storage; the disadvantage is that each route update involves cascading modifications to multiple tree nodes, making it difficult to achieve hot updates without frame loss, and the storage bandwidth requirement increases linearly with the number of levels.

[0005] 4) Early Minimal Perfect Hash Function (MPHF) schemes. The density (≈80%) and construction speed of early MPHF algorithms were lower than those of the PTHash / PtrHash algorithm proposed by Pibiri & Trani in 2021 (97% density, 64K records constructed in 0.23 seconds), and it was not combined with incremental learning engines or transient update engines to form a complete hot update chain.

[0006] The existing solutions have the following main problems: during online updates, finding the path requires a long pause (during the reconstruction of the entire PTHash / PtrHash table) or an intermediate state of "half new, half old" (multi-hash in-situ rewriting) or data frame loss due to Cuckoo chain breakage; the distribution characteristics of the mask length of each route are not utilized, resulting in low actual utilization of on-chip memory (BRAM / URAM); the lack of a unified and standardized configuration interface and initialization mechanism leads to complex hardware initial value writing paths and the possibility of the query interface outputting incorrect results during the initialization window; in IPv6 scenarios, if the complete 64-bit or 128-bit prefix is ​​directly used as the storage field, it will occupy a large amount of on-chip URAM (Ultra Random Access Memory, high-density memory) resources. Summary of the Invention

[0007] To address the aforementioned problems in the existing technology, this invention provides a three-layer hybrid longest prefix matching search method, system, and its hot update method.

[0008] The technical problem to be solved by this invention is achieved through the following technical solution: A three-layer hybrid longest prefix matching search method includes the following steps: S1. For the input query request, use the minimum perfect hash function to accurately map the static route prefix of the corresponding mask length to obtain the perfect hash lookup result; S2. Map the prefix with mask length salt value to the bucket number using a hybrid hash function, store and search for newly added or changed incremental routing table entries, and obtain the cuckoo hash lookup results. S3. Complete the parallel mask comparison and output the longest prefix matching result from the championship comparison tree to obtain the updatable CAM search result; S4. Perform delayed alignment on the perfect hash lookup result, the cuckoo hash lookup result, and the updatable CAM lookup result to obtain the aligned lookup result; S5. Select the longest prefix from the aligned search results and the default empty results to match the search results.

[0009] A three-layer hybrid longest prefix matching search system includes: a perfect hash engine, a cuckoo hash engine, an updatable CAM engine, a delayed alignment unit, and a longest prefix matching arbitration unit; The perfect hash engine, the cuckoo hash engine, and the updatable CAM engine execute the input lookup request in parallel. Their outputs are all connected to the input of the delayed alignment unit. The output of the delayed alignment unit is connected to the input of the longest prefix matching arbitration unit. The longest prefix matching arbitration unit outputs the lookup result. The perfect hash engine is used to accurately map the static route prefix of the corresponding mask length using the minimum perfect hash function, and obtain the perfect hash lookup result; The Cuckoo Hash Engine is used to map a prefix with a mask length salt value to a bucket number using a hybrid hash function, store and search for incremental routing table entries added or changed during operation, and obtain the Cuckoo Hash lookup results. The updatable CAM engine is used to perform parallel mask comparisons and outputs the longest prefix matching result from the championship comparison tree to obtain the updatable CAM search result; The delayed alignment unit is used to perform delayed alignment on the perfect hash lookup result, the cuckoo hash lookup result, and the updatable CAM lookup result to obtain the aligned lookup result. The longest prefix matching arbitration unit is used to select the longest prefix from the aligned search results and the default empty results to match the search results.

[0010] In one embodiment of the present invention, the perfect hash engine includes N perfect hash sub-units divided according to the prefix mask length, where N≥2, and each perfect hash sub-unit performs precise mapping of the routing prefix of its respective mask length based on the offline constructed PTHash / PtrHash class minimum perfect hash function; The perfect hash subunit includes a pilots memory, a main table memory, and a prefix matching verification unit. After the main table is read, the prefix matching verification unit compares the stored prefix with the query prefix bit by bit to eliminate false hits.

[0011] In one embodiment of the present invention, the perfect hash engine further includes: The system consists of two internally independent perfect hash engine instances, Bank A and Bank B, and a Bank selection register. A dedicated bit in the high-order address space of the configuration bus is used to select the target Bank, allowing the control software to write new pilots and main table content to the inactive Bank without affecting the active Bank's lookup path. Once all the new table content for the inactive Bank has been written, the control software sends a single-clock-cycle switching pulse to the Bank selection register, switching subsequent input lookup requests to the new Bank. Requests that have already entered the old Bank's lookup pipeline before the switch continue to be output by the old Bank, ensuring that any lookup request corresponds to the table content of only one Bank. This achieves an atomic switch from the old table to the new table without interrupting the lookup path, losing input requests, or generating intermediate lookup results.

[0012] In one embodiment of the present invention, the Cuckoo Hash Engine includes multiple small-capacity Cuckoo Hash Tables independently configured according to the prefix mask length. Each Cuckoo Hash Table adopts a W-way group-associative structure and maps the prefix with mask length salt value to the bucket number through a hybrid hash function, where W≥2, and is used to carry routing table entries for online incremental learning. The bucket number is calculated by the splitmix64 type hash function for the prefix with mask length salt value.

[0013] In one embodiment of the present invention, each entry of the updatable CAM engine includes a prefix field, a mask length field, a next-hop index field, and a valid bit field. The updatable CAM engine completes parallel mask comparison of all entries and outputs the longest prefix matching result within the updatable CAM engine by the championship comparison tree.

[0014] In one embodiment of the present invention, the three-layer hybrid longest prefix matching search system further includes a unified configuration bus; The high-order address encoding field of the configuration bus is used to route configuration write operations between the perfect hash engine, the cuckoo hash engine and the updatable CAM engine, so that the initialization and runtime updates of the three engines can be completed by a single control interface. The configuration bus includes a 32-bit address channel and a 64-bit data channel. The highest two bits of the address channel are used for routing between the Perfect Hash Engine, the Cuckoo Hash Engine, and the Updatable CAM Engine. When the highest two bits are 00, write to Bank A of the perfect hash engine; When the highest two bits are 0 or 1, write to Bank B of the perfect hash engine; When the highest two bits are 10, write to the updatable CAM engine; When the highest two bits are 11, write to the Cuckoo Hash Engine; The remaining 30 bits of address are used as internal sub-addresses of the target engine, and sub-units, sub-tables, table entries, and sub-registers are selected according to the fields of the sub-address.

[0015] In one embodiment of the present invention, the three-layer hybrid longest prefix matching search system further includes: configuring a serial loader and initializing a read-only memory; The initial read-only memory stores all initial values ​​of the perfect hash engine, the cuckoo hash engine, and the updatable CAM engine in a pre-compiled initialization sequence; After the system is reset and released, the configuration serial loader is driven by a finite state machine to sequentially read the initialization sequence and output it to the configuration bus. After all initial values ​​are written, the initialization completion bit is set to be valid. The query interface is gated and blocked while the initialization completion bit is invalid. The query request is accepted only after the initialization completion bit is valid, thereby ensuring that the query path does not output incorrect results within the initialization window.

[0016] A hot update method for the above-mentioned three-layer hybrid longest prefix matching search system includes the following steps: The set of routes to be changed is divided into persistent route set, incremental learning route set and transient route set according to the change type; For the transient route set, the control software directly writes each entry into the corresponding entry of the updatable CAM engine. The writing order follows the atomic commit protocol, so that each entry is visible to subsequent query requests one clock cycle after the valid bits are written in the updatable CAM engine and there will be no half-written state. For the incremental learning route set, the control software selects the corresponding Cuckoo Hash sub-table according to the mask length for each table entry and writes it into the sub-table slots in order. When all the group-associative slots are occupied, the Cuckoo kick-out migration is performed. The control software incorporates the persistent route set into the next perfect hash engine static route table reconstruction process, continues to serve queries in the current active bank, and builds a new perfect hash table offline on inactive banks. The new perfect hash table includes pilot table content, main table content, and metadata content. The control software writes the new perfect hash table into the inactive Bank one by one through the unified configuration bus. The address field of the unified configuration bus is used to select the target Bank, target sub-unit and target storage location, and the data field is used to carry the content to be written. After all the new table contents of the inactive Bank are written, the control software sends a single-clock-cycle switching pulse to the Bank selection register, so that subsequent input lookup requests are switched to the new Bank, and requests that have entered the lookup pipeline of the old Bank before the switch continue to be completed and output by the old Bank. After the switch is completed, the control software clears the updatable CAM table and cuckoo hash table that have been covered by the new perfect hash table, so that the perfect hash engine, the cuckoo hash engine and the updatable CAM engine return to the steady-state division of labor where the perfect hash engine carries static routes, the cuckoo hash engine carries incremental routes and the updatable CAM engine carries transient routes.

[0017] A network processing chip or network processing board that employs the above-mentioned three-layer hybrid longest prefix matching search method and the above-mentioned three-layer hybrid longest prefix matching search system.

[0018] This invention presents a three-layer hybrid longest prefix matching search method. It utilizes a three-engine, specialized division of labor to decouple the search process. "High density" is handled by an offline-built perfect hash engine, "fast incremental" by a cuckoo hash engine, and "transient atomicity" by an updatable CAM engine. These three engines execute in parallel, undergo delayed alignment, and then perform longest prefix selection, matching, and labeling of the search results. This avoids the problem that a single search engine cannot simultaneously achieve optimal performance in terms of static density, incremental update latency, and transient update atomicity. This invention enables batch hot updates without frame loss. During the pre-reconstruction of inactive banks in the PHF's ping-pong dual-bank architecture, the search path of the active bank is not affected at all; after a single-frame flip, the search request naturally transitions to the new bank in the bank selection register.

[0019] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating the three-layer hybrid longest prefix matching search method provided in an embodiment of the present invention; Figure 2 This is a structural block diagram of the three-layer hybrid longest prefix matching search system provided in the embodiments of the present invention; Figure 3 This is a schematic diagram of the overall structure of the three-layer hybrid longest prefix matching search system provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the dual-bank query structure of the PHF static routing engine provided in this embodiment of the invention; Figure 5 This is a flowchart of the two-level hash lookup pipeline for the PHF sub-table provided in this embodiment of the invention; Figure 6 This is a schematic diagram of the updatable CAM lookup engine structure provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the internal structure of the Cuckoo incremental routing engine provided in an embodiment of the present invention; Figure 8 This is a flowchart of the search result delayed alignment and longest prefix selection provided in the embodiments of the present invention; Figure 9 This is a schematic diagram of address distribution for the unified configuration bus provided in an embodiment of the present invention; Figure 10 This is a PHF dual-bank hot update timing diagram provided in an embodiment of the present invention; Figure 11 This is a flowchart of the power-on configuration loader state machine provided in an embodiment of the present invention; Figure 12This is a schematic diagram of the SLR deployment of the xcvu13p board provided in an embodiment of the present invention. Detailed Implementation

[0021] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0022] A single search engine cannot simultaneously achieve optimal performance in three dimensions: static density, incremental update latency, and transient update atomicity. Therefore, this invention provides a three-layer hybrid longest prefix matching search method, system, and its hot update method.

[0023] Reference Figure 1 The three-layer hybrid longest prefix matching search method includes the following steps: S1. Input the query request, and use the minimum perfect hash function to accurately map the static route prefix of the corresponding mask length to obtain the perfect hash lookup result; S2. Map the prefix with mask length salt value to the bucket number using a hybrid hash function, store and search for newly added or changed incremental routing table entries, and obtain the cuckoo hash lookup results. S3. Complete the parallel mask comparison and output the longest prefix matching result from the championship comparison tree to obtain the updatable CAM (Content Addressable Memory) lookup result; S4. Perform delayed alignment on the perfect hash lookup results, cuckoo hash lookup results, and updatable CAM lookup results to obtain the aligned lookup results; S5. Select the longest prefix from the aligned search results and the default empty results, match the search results and mark them.

[0024] The three-layer hybrid longest prefix matching search method of this invention executes a perfect hash engine, a cuckoo hash engine, and an updatable CAM engine in parallel. The perfect hash engine uses the PTHash / PtrHash algorithm to offline construct dozens of minimal perfect hash tables allocated according to the mask length, carrying the vast majority of static routes. The cuckoo hash engine is divided into multiple small-capacity two-way group-associative hash sub-tables according to the prefix mask length, used to store and search incremental route table entries added or changed during operation. The updatable CAM engine handles sub-millisecond transient updates. The three engines perform the search in parallel for each query, and the output is arbitrated by a delay alignment and 4-in LPM comparison module to determine the longest matching result, avoiding the problem that a single search engine cannot simultaneously achieve optimal performance in the three dimensions of static density, incremental update latency, and transient update atomicity.

[0025] Based on the same inventive concept, embodiments of the present invention also provide a three-layer hybrid longest prefix matching search system, referring to... Figure 2The three-layer hybrid longest prefix matching search system includes: a perfect hash engine, a cuckoo hash engine, an updatable CAM engine, a delayed alignment unit, and a longest prefix matching arbitration unit. The perfect hash engine, cuckoo hash engine, and updatable CAM engine execute the input search requests in parallel. Their outputs are all connected to the input of the delayed alignment unit, whose output is connected to the input of the longest prefix matching arbitration unit. The longest prefix matching arbitration unit outputs the search result.

[0026] The Perfect Hash Engine is used to precisely map static route prefixes of the corresponding mask length using the minimum perfect hash function, obtaining the perfect hash lookup result; the Cuckoo Hash Engine is used to map prefixes with mask length salt values ​​to bucket numbers using a hybrid hash function, store and look up incremental routing table entries added or changed during runtime, obtaining the Cuckoo Hash lookup result; the Updatable CAM Engine is used to perform parallel mask comparisons and output the longest prefix matching result from the championship comparison tree, obtaining the Updatable CAM lookup result; the Delayed Alignment Unit is used to perform delayed alignment of the perfect hash lookup result, the Cuckoo Hash lookup result, and the Updatable CAM lookup result, obtaining the aligned lookup result; the Longest Prefix Matching Arbitration Unit is used to select the longest prefix from the aligned lookup result and the default empty result, match the lookup result, and identify it.

[0027] The three-layer hybrid longest prefix matching search system of this invention sets up three search engines in parallel on a single chip: a perfect hash engine that offline constructs dozens of minimal perfect hash tables allocated according to mask length using the PTHash / PtrHash algorithm, carrying the vast majority of static routes; a cuckoo hash engine that divides the prefix mask length into multiple small-capacity two-way group-associative hash sub-tables for storing and searching incremental routing table entries added or changed during operation; and an updatable CAM engine that handles sub-millisecond transient updates. The three engines perform searches in parallel for each query, and the output is arbitrated by a delay alignment and 4-input LPM comparison module to determine the longest match result. This system is flexible; the three engines are not indispensable, and the number and type of engines used can be switched according to the application scenario, avoiding the problem that a single search engine cannot simultaneously achieve optimal performance in terms of static density, incremental update latency, and transient update atomicity.

[0028] The perfect hash engine of this invention includes N perfect hash subunits divided according to the prefix mask length, where N≥2. Each perfect hash subunit accurately maps the routing prefix of its corresponding mask length based on the offline-built PTHash / PtrHash class minimum perfect hash function. The perfect hash subunit includes a pilots memory, a main table memory, and a prefix matching verification unit (PMU). After reading from the main table, the prefix matching verification unit compares the stored prefix with the queried prefix bit by bit to eliminate false hits.

[0029] Specifically, the Perfect Hash Engine (PHF Engine) comprises 17 perfect hash subunits (phf_units) divided by mask length. Each subunit is responsible for all prefixes of a mask length ( / 9~ / 25 for IPv4, / 32~ / 48 for IPv6). The subunits establish an offline, precise mapping for all their responsible prefixes based on the smallest perfect hash function of the PTHash / PtrHash class. Internally, each subunit employs a two-level hash pipeline (splitmix64×2 + skew_bucketer + 128-bitremap), and PMU verification is used after reading from the main table to prevent false hits. The results from the 17 subunits are compared across mask LPM competitions using an lpm_cmp_tree to obtain the final result of the PHF engine. Furthermore, the PHF engine sets up two completely independent instances (phf_pingpong) for Bank A and Bank B to support atomic switching.

[0030] Specifically, the perfect hash engine also includes: The system consists of two internally independent perfect hash engine instances, Bank A and Bank B, and a Bank selection register. A dedicated bit in the high-order address space of the configuration bus is used to select the target Bank, allowing the control software to write new pilots and main table content to the inactive Bank without affecting the active Bank's lookup path. Once all the new table content in the inactive Bank has been written, the control software sends a single-clock-cycle switching pulse to the Bank selection register, switching subsequent input lookup requests to the new Bank. Requests that have already entered the old Bank's lookup pipeline before the switch continue to be output by the old Bank, ensuring that any lookup request corresponds to the table content of only one Bank. This achieves an atomic switch from the old table to the new table without interrupting the lookup path, losing input requests, or generating intermediate lookup results.

[0031] The hardware implementation type of the pilots memory and main table memory of the perfect hash subunit is adaptively selected by the control software at compile time or synthesis time according to the following rules based on the number of buckets (NB) and slots (TS) of the subunit: When NB (or TS) ≤ the first threshold, the memory is mapped to a distributed lookup table RAM (Random Access Memory). When NB (or TS) > the first threshold and ≤ the second threshold, the memory is mapped to the on-chip block RAM; When NB (or TS) > the second threshold, the memory is mapped to high-density ultra-large RAM.

[0032] The selection is made to apply the attribute instructions of the synthesis tool independently to each sub-unit, so that all sub-units coexist in the same search engine and are implemented using three different memories, thereby significantly reducing the total on-chip block RAM usage while maintaining peak throughput.

[0033] In this embodiment of the invention, each sub-unit independently selects one of three memory types: LUT-RAM, Block RAM, and UltraRAM (determined by NB / TS thresholds), resulting in a 99% reduction in the number of BRAM ports compared to the pure Cuckoo solution and a 17% increase in density compared to the earlier BPZ MPHF solution.

[0034] Each perfect hash subunit internally sets up the following pipeline stages in sequence: Mask truncation stage, performing a bitwise AND operation between the query IP and the subunit's inherent mask; First-level hash stage, inputting the truncated prefix with mask length, salt value, and seed into a splitmix64-type hash function; Bucketing stage, obtaining the bucket number from the high-order bits of the first-level hash result using a bucketing function; Pilots readout stage, reading the pilot value from the bucket number; Mixing stage, mixing the low-order bits of the first-level hash result with the pilot value twice using a mixing constant; Second-level hash stage, performing a splitmix64-type hash on the mixed result; Slot remapping stage, converting the second-level hash result to the main table slot number using a 128-bit remainder remapping; Main table readout stage, reading the stored item from the main table slot number; Prefix matching verification stage, comparing the prefix field in the stored item with the query prefix bit by bit according to the mask to output the hit bit.

[0035] For IPv6 prefix fields longer than 32 bits, the Perfect Hash Engine replaces the complete prefix in its main table storage entry with a 32-bit fingerprint calculated using a splitmix64-type hash function. The prefix matching verification unit compares this 32-bit fingerprint with the fingerprint calculated using the same hash function for the query IP to determine a match. In this embodiment, the position in the main table storage entry of the PHF subunit that would normally store a 64-bit or 128-bit IPv6 prefix is ​​replaced by splitmix64 processing of the prefix, taking the lower 32 bits as the fingerprint. During a query, the same transformation is applied to the query IP to obtain the query fingerprint, and the PMU compares the two fingerprints for equality. This halving of the field width reduces the main table URAM capacity requirement by approximately 50%.

[0036] The perfect hash engine in this embodiment of the invention further employs a ping-pong dual-bank architecture to achieve batch atomic hot updates, and adopts a resource allocation strategy that adaptively selects LUT-RAM, Block RAM, or UltraRAM based on table size. Under 64K IPv4 / IPv6 routes, a single VU13P FPGA chip can support 6×100GbE line-speed lookups and supports hot updates of table entries without frame loss.

[0037] The cuckoo hash engine of this invention includes multiple small-capacity cuckoo hash tables independently configured according to the prefix mask length. Each cuckoo hash table adopts a W-way group associative structure and maps the prefix with mask length salt value to the bucket number through a hybrid hash function, where W≥2, and is used to carry routing table entries for online incremental learning.

[0038] Specifically, the Cuckoo hash engine uses a separate 2-way set-associative, 64-slot small Cuckoo hash table for each mask length. All 17 sub-tables, totaling 2,176 slots, are used to store incrementally learned routes. Each sub-table uses splitmix64 hashing to calculate the bucket number for the prefix with the mask length and salt value. Upon a hit, the result is fed into a 17-input LPM tournament comparison tree.

[0039] The Cuckoo Hash Engine instantiates a Cuckoo Hash sub-table for each independent mask length. The index width INDEX_W of each sub-table is no more than 6 bits, and the group associativity W=2. The internal storage items of the sub-table include the valid bits, the prefix field, and the next-hop index field. The bucket number of the sub-table is calculated by the splitmix64 type hash function for the prefix with the salt value of the mask length. All mask sub-tables perform parallel searches for the same query and send the hit results to the LPM championship comparison tree across sub-tables.

[0040] Each entry in the updatable CAM engine of this invention includes a prefix field, a mask length field, a next-hop index field, and a valid bit field. The updatable CAM engine completes parallel mask comparisons for all entries and outputs the longest prefix match result within the updatable CAM engine via a tournament comparison tree. Specifically, the updatable CAM engine (Update CAM engine) performs parallel CAM comparisons on all entries in each clock cycle, and the hit vector is fed into a 256-level internal LPM tournament comparison tree (log2256 = 8 levels) to output the longest match within the engine.

[0041] The updatable CAM engine performs three parallel operations on all D entries (D≥64) in each clock cycle: First, it compares the query IP with the prefix field of each entry bit by bit according to the entry's mask length to generate a hit bit; second, it sends the mask lengths of all hit entries into a log2D-level internal tournament comparison tree and eliminates them in pairs according to the rule of "longer prefix wins"; third, it outputs the next-hop index, mask length, and prefix field of the globally longest hit entry. Thus, the updatable CAM engine itself can solve the longest prefix matching within a group without the need for additional external comparison circuitry.

[0042] The delay alignment unit in this embodiment of the invention is used to configure shift register groups of different depths for the fixed lookup delay of each of the three engines, so that the three lookup results appear at the input of the arbitration unit in the same clock cycle.

[0043] The delayed alignment unit is configured with a length of (LAT_PHF) for both the Cuckoo Hash Engine and the Updatable CAM Engine. The shift register group consists of LAT_X shift registers, where LAT_PHF is the fixed lookup latency of the perfect hash engine, and LAT_X is the lookup latency of the engine to be aligned (i.e., 13-step latency for the cuckoo engine and 26-step latency for the cam engine). The shift register group simultaneously aligns the valid bits, hit bits, mask length field, next-hop index field, and matching prefix field. The longest prefix matching arbitration unit uses a piped 4-in LPM championship comparison tree, and uses the valid bits of the perfect hash engine as the synchronization benchmark for the final result.

[0044] The longest prefix matching arbitration unit is used to receive the three aligned results and one reserved input. It performs a 4-input LPM tournament comparison according to the decision rule of "based on the hit bit and prioritizing the larger prefix length", and adds an identifier field to indicate which search engine generated the final hit.

[0045] The three-layer hybrid longest prefix matching search system of this invention also includes a unified configuration bus. The high-order address encoding field of the configuration bus is used to route configuration write operations between the perfect hash engine, the cuckoo hash engine, and the updatable CAM engine, so that the initialization and runtime updates of the three engines can be completed by a single control interface.

[0046] The configuration bus includes a 32-bit address channel and a 64-bit data channel. The highest two bits of the address channel are used for routing between the Perfect Hash Engine, the Cuckoo Hash Engine, and the Updatable CAM Engine.

[0047] When the highest two bits are 00, write to Bank A of the perfect hash engine; When the highest two bits are 0 or 1, write to Bank B of the perfect hash engine; When the highest two bits are 10, write to the updatable CAM engine; When the highest two bits are 11, write to the Cuckoo Hash Engine; The remaining 30 bits of address are used as internal sub-addresses of the target engine, and sub-units, sub-tables, table entries, and sub-registers are selected according to the fields of the sub-address.

[0048] In this embodiment of the invention, when writing the initial configuration, the highest 2 bits of the 32-bit cfg address are used for routing between the three engines, and the remaining 30 bits are the internal sub-addresses of the engines; upon power-up, the cfg serial loader outputs the cfg write sequence from the initialization ROM in sequence, and after all the writing is completed, it pulls init_done high; the query interface is gated and blocked during the invalid init_done period, fundamentally avoiding incorrect routing during the initialization window.

[0049] The three-layer hybrid longest prefix matching search system of this invention further includes: a configuration serial loader and an initialization read-only memory. The initialization read-only memory stores all initial values ​​of the perfect hash engine, the cuckoo hash engine, and the updatable CAM engine using a pre-compiled initialization sequence. After system reset and release, the configuration serial loader, driven by a finite state machine, sequentially reads the initialization sequence and outputs it to the configuration bus. After all initial values ​​have been written, the initialization completion bit is set to valid. The query interface is gated and blocked while the initialization completion bit is invalid. Query requests are only accepted after the initialization completion bit is valid, thus ensuring that the query path does not output erroneous results within the initialization window.

[0050] The system of this invention is deployed on a single-chip programmable logic device, which includes at least four super logic regions (SLRs), several Block RAMs, several UltraRAMs, and several DSP resources; two or more lookup system instances of the system are respectively deployed in different super logic regions, wherein each instance serves two or more RX data paths of 100 Gigabit Ethernet Media Access Controllers (CMACs).

[0051] Based on the same inventive concept, this invention also provides a hot update method for the three-layer hybrid longest prefix matching search system described above, which includes the following steps: Step 1: Divide the set of routes to be changed into persistent route set, incremental learning route set and transient route set according to the change type.

[0052] Step 2: For the transient route set, the control software directly writes each entry into the corresponding entry of the updatable CAM engine. The writing order follows the atomic commit protocol, so that each entry is visible to subsequent query requests one clock cycle after the valid bits are written within the updatable CAM engine, and there will be no half-written state.

[0053] Step 3: For the incremental learning route set, the control software selects the corresponding Cuckoo Hash sub-table for each entry according to the mask length and writes it into the sub-table slots in order. When all the associated slots are occupied, the Cuckoo kick-out migration is performed. The order of "writing the prefix field first, then the next hop field, and finally the valid bits" ensures that at any time, the query request will either read the old slot state of all 0s / all invalids or read the complete and consistent new entry state, thereby avoiding the lookup of incorrect routes caused by reading the intermediate state of partial writing.

[0054] Step 4: The control software will incorporate the persistent route set into the next perfect hash engine static route table reconstruction process, continue to serve queries in the current active bank, and build a new perfect hash table offline on the inactive bank. The new perfect hash table includes pilot table content, main table content, and metadata content.

[0055] Step 5: The control software writes the new perfect hash table to the inactive Bank one by one through the unified configuration bus. The address field of the unified configuration bus is used to select the target Bank, target sub-cell and target storage location, and the data field is used to carry the content to be written.

[0056] Step Six: After all the new table content of the inactive Bank has been written, the control software sends a single-clock-cycle switching pulse to the Bank selection register, so that subsequent input lookup requests are switched to the new Bank. Requests that have entered the lookup pipeline of the old Bank before the switch continue to be output by the old Bank, thereby avoiding any query request from using both the old table and the new table at the same time.

[0057] Step 7: After the switch is completed, the control software clears the updatable CAM table and the cuckoo hash table that have been overwritten by the new perfect hash table, so that the perfect hash engine, the cuckoo hash engine and the updatable CAM engine return to the steady-state division of labor where the perfect hash engine carries static routes, the cuckoo hash engine carries incremental routes and the updatable CAM engine carries transient routes.

[0058] Based on the semantics of each route change (transient / incremental / resident), it is routed to one of three engines: Perfect Hash Engine, Cuckoo Hash Engine, or Updatable CAM Engine. For Updatable CAM Engine and Cuckoo Hash Engine, a "valid-last" secure write order is used to ensure atomic visibility of table entries. For Perfect Hash Engine, a complete new table is built offline on an inactive Bank, and finally, atomic switching is achieved by flipping the Bank selection register in a single cycle. After the switching is completed, the corresponding CAM and Cuckoo Hash table entries are recycled, so that the three layers return to a stable state.

[0059] Based on the same inventive concept, embodiments of the present invention also provide a network processing chip or network processing board for a three-layer hybrid longest prefix matching search method and a three-layer hybrid longest prefix matching search system using the above embodiments.

[0060] Embodiment 1 of this invention deploys a 4×100 GbE network processing board based on Xilinx Virtex UltraScale+ xcvu13p, featuring four CMACs (100 Gigabit Ethernet Media Access Controllers) and a CAUI-4 physical channel; it uses an onboard 200 MHz differential crystal oscillator SYSCLK_200, multiplied by MMCM to generate 312.5 MHz as the LPM engine's operating clock, and receives initialization images and runtime update commands from the host machine via the PCIeGen3×8 interface. For example... Figure 3 As shown, this embodiment deploys two complete LPM engine instances, lpm_engine_2port, within the chip, with each instance serving two CMAC RX data paths. Each instance integrates: One IPv4 hybrid_top (containing phf_pingpong (including two phf_tops for Bank A and Bank B), update_cam #(.W(32)) and cuckoo_bank); One IPv6 hybrid_top_v6 (containing phf_top_v6, update_cam #(.W(64)) and cuckoo_bank_v6); One time-division multiplexing (TDM) polling arbitrator distributes query requests from two CMAC channels to the v4 or v6 engine according to the protocol. Two cfg serial loaders (one for v4 and one for v6) read the cfg write sequence from a deep ROM and output it to the cfg bus of their respective hybrid_top. After all the writing is complete, they pull init_done high.

[0061] Example 1 is laid out to SLR2, and Example 2 is laid out to SLR1, which is hard-specified by the pblock constraint of the Vivado tool to alleviate the timing pressure caused by routing across SLRs.

[0062] For PHF engine implementation details, please refer to Figure 4 , Figure 5The PHF engine carries the most numerous and relatively slow-changing static routing table entries, serving as the main lookup layer of this system. Taking the IPv4 implementation as an example, this engine internally divides into 17 parallel static routing sub-units according to the prefix mask length, corresponding to mask lengths from / 9, / 10, / 11 to / 25, respectively. Each sub-unit is responsible for routing prefixes under only one mask length, thus splitting the originally mixed routing table into multiple independent small tables according to the mask length. For prefixes with fewer numbers or unstable distributions, such as / 8 and below, and / 26 and above, the CAM or Cuckoo engine can be used as supplementary paths. The division of labor among layers can be readjusted later according to the actual route distribution. When constructing each PHF sub-unit, the number of buckets and the number of main table slots are configured according to the actual number of routes under the corresponding mask length. For example, in the current IPv4 parameters, the sub-unit covering a large number of / 24 prefixes is configured with a larger number of buckets and a larger main table size, while the sub-unit covering sparse prefixes such as / 9 is configured with a smaller table size. The aforementioned capacity parameters are typically rounded up to the power of 2, with space reserved for a number greater than the actual number of routes to ensure that the address index and configuration fields can completely cover all table entries. Regarding storage resources, the system automatically selects the implementation method based on the table size of each sub-unit: small tables are mapped to LUT-RAM, medium-sized tables to BlockRAM, and large tables to UltraRAM; for example, the large-capacity main table corresponding to / 24 can be mapped to UltraRAM cascaded, while the small-capacity main table corresponding to / 9 can be mapped to LUT-RAM. During queries, each sub-unit first extracts the prefix of the query IP based on its own mask length, then calculates the main table address through a two-level hash process. After reading the candidate route entries, the prefix verification unit reconfirms whether the candidate entries match the query prefix, avoiding false matches caused by hash addressing. After each sub-unit outputs the hit results in parallel, the PHF engine internally selects the entry with the longest prefix length as the final result of this engine. Figure 5 The pipeline structure shown has a fixed delay of 36 clock cycles from the input IP entering the PHF subunit to the output query result.

[0063] For details on the implementation of the updatable CAM engine, please refer to [link / reference]. Figure 6The updatable CAM engine is a set of parallel updatable matching tables of fixed depth, used to carry transient routing entries that need to be written quickly and immediately participate in lookups. The engine includes 256 entries, each containing at least a valid flag field, a mask length field, a routing prefix field, and a next-hop index field. The control software selects entries to be written via a unified configuration bus and writes them in the order of routing prefix, mask length, next-hop index, and valid flag, ensuring that entries are only visible to the query path after all fields have been written, thus avoiding reading partially updated entries during the query process. During a lookup, the query IP address enters the engine and is compared with all 256 entries in parallel using a mask prefix comparison, generating candidate hit results. Subsequently, these candidate hit results are sent to an internal multi-level longest prefix selection structure, selecting the final entry based on the principle of a valid hit with the largest mask length. Therefore, the updatable CAM engine can complete parallel matching and longest prefix selection of transient routes within a fixed pipeline delay and output the engine's best matching result to the subsequent arbitration unit.

[0064] For Cuckoo engine implementation details, please refer to... Figure 7 This engine stores incremental routing entries added or changed during runtime, serving as an online supplementary layer between two batch reconstructions of the PHF static routing table. The engine is divided into 17 small-capacity hash sub-tables based on prefix mask length. Each sub-table corresponds to a specific mask length and uses a two-way grouped associative structure. Each sub-table contains 64 buckets, and each bucket has two candidate storage locations, thus providing 128 slots per sub-table, for a total of 2176 incremental routing slots across the 17 sub-tables. During a query, the input IP address is simultaneously sent to each mask sub-table. Each sub-table extracts the query prefix according to its corresponding mask length, calculates the bucket number using a hash algorithm, and then simultaneously reads the two candidate slots in that bucket, comparing the prefix in the candidate entries with the query prefix. If a match is found, the sub-table outputs the hit result, prefix length, and next-hop index. Since the same query IP may simultaneously hit multiple sub-tables with different mask lengths, the hit results of all sub-tables also need to be sent to the longest prefix selection module across sub-tables. The best matching result within the Cuckoo engine is selected according to the rule of "hit priority, longer prefix priority". During configuration writing, the control logic selects the target slot based on the mask sub-table number, group associative route number, bucket number, and write field in the configuration address, and completes the update in the order of "write the route prefix first, then the next-hop index, and finally the valid flag". Writing the valid flag last ensures that the query path will not read half-written entries, thus avoiding erroneous hits during the update process. This engine is suitable for carrying a small number of incremental routes that need to be effective online. After the PHF static table is rebuilt and switched over, the corresponding incremental entries can be recycled or cleared.

[0065] See the implementation details for delayed alignment and final arbitration modules. Figure 8 The query latency of the three search engines—PHF, Update CAM, and Cuckoo—is different, at 36, 10, and 23 clock cycles respectively. To ensure that the three results enter the final selection module within the same clock cycle, the system pads the Update CAM results with a 26-clock-cycle delay and the Cuckoo results with a 13-clock-cycle delay, aligning all three results to the 36-clock output time of PHF. After alignment, the final arbitration module receives four candidate results—PHF, Update CAM, Cuckoo, and one empty input—and performs a two-level comparison according to the rule of "first determining whether there is a match, and if there is a match, selecting the one with the longest prefix length," outputting the globally longest prefix match result and providing the source identifier of which search engine the result came from.

[0066] See cfg bus and serial loader. Figure 9 and Figure 11 The system employs a unified configuration bus to handle the initialization and runtime configuration writing of the PHF dual-bank, Update CAM, and Cuckoo engines. This bus includes configuration addresses, configuration data, and write enable signals. The high-order bits of the address select the write target: corresponding to PHF Bank A, PHF Bank B, Update CAM, and the Cuckoo engine, respectively. The remaining address serves as the internal address of the target engine, used to further locate specific sub-tables, entries, or registers. After system power-on or reset, the serial loader sequentially reads the pre-stored configuration sequence from the initialization ROM and sends it to the configuration bus one by one until all initial entries and control parameters are written. After loading, the system sets the initialization completion flag. During the period when this flag is invalid, the query interface remains gated closed, not accepting external lookup requests, thus avoiding erroneous lookup results before the routing table is fully initialized. This mechanism enables the three lookup engines to complete unified initialization through the same configuration entry point and ensures that the system only enters normal lookup operation mode after the configuration state is complete.

[0067] For the PHF Ping Pong Dual Bank hot update process, please refer to [link / reference]. Figure 10The PHF engine employs two independent static tables, Bank A and Bank B, to achieve non-stop hot updates. Under normal operating conditions, one Bank acts as the active Bank, continuously serving query requests, while the other acts as the inactive Bank, used for background writing to new tables. During batch updates, the control software first performs offline PTHash / PtrHash construction on the new static route set on the host or embedded processor, generating the corresponding pilot table, master table, and metadata configuration. Then, these configuration contents are written to the inactive Bank via a unified configuration bus, while the active Bank continues normal lookups during the writing process. After the new tables are written, the control software issues a single-clock-cycle Bank switching pulse, causing subsequent new query requests to switch to the new Bank. In-flight queries that had already entered the old Bank pipeline before the switch continue to be output by the old Bank and are naturally drained after approximately 38 clock cycles. After the switch, the original active Bank becomes an idle Bank, available for the next round of table reconstruction. Simultaneously, CAM and Cuckoo incremental entries that have been covered by the new PHF static table can be cleaned up, allowing the system to return to a steady-state division of labor: PHF carries static routes, Cuckoo carries incremental routes, and CAM carries transient routes. Throughout the process, the query channel remains operational without requiring pauses in inputting the query, and no half-new or half-old search results are generated.

[0068] Attached are resource data for the example: Target frequency: 312.5 MHz (measured routed WNS = +0.103 ns, meeting setup timing constraints); Throughput: 312.5 Mlps per instance, 2 instances × 2 ports = 4 × 100 GbE line speed; PHF usage: BRAM≈28 blocks, UltraRAM≈12 blocks (two instances × v4 + v6, a total of four). CAM usage: LUT≈8 K×4 = 32 K (two instances × v4 + v6); Cuckoo's usage: Distributed LUT-RAM ≈ 17 × 64 × 2 × 41 bits = 89 Kbit; Pin configuration: sys_clk_p = AE32, sys_clk_n = AE31, 200 MHz differential crystal oscillator; Board: 4×100GbE daughter cards, CMAC0 / 1→SLR2, CMAC2 / 3→SLR1.

[0069] Example 2 is an ASIC-based high-density routing lookup accelerator, porting the present invention from an FPGA to an ASIC using a 28 nm or more advanced process. The CAM is replaced with a fully custom SRAM-based ternary CAM; the PHF master table is replaced with embedded SRAM; the pipeline number remains unchanged. A single instance is expected to operate at over 1 GHz, and a single chip is expected to support 16×100 GbE or higher.

[0070] Example 3 employs a degraded implementation of only two layers out of the three-layer architecture. In certain resource-constrained scenarios, only the PHF engine and CAM engine can be instantiated, without instantiating the Cuckoo engine. In this case, all "online incremental" routes are written uniformly through CAM; when CAM is full, the control software triggers PHF reconstruction. This degraded scheme still falls within the protection scope of the claims of this invention.

[0071] It should be noted that, for network processing chip or network processing board embodiments, since they are basically similar to the method and system embodiments, the description is relatively simple. For relevant parts, please refer to the description of the method and system embodiments. All embodiments of the above-mentioned three-layer hybrid longest prefix matching search method and system are applicable to the network processing chip or network processing board, and can achieve the same or similar beneficial effects.

[0072] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A three-layer hybrid longest prefix matching search method, characterized in that, Including the following steps: S1. For the input query request, use the minimum perfect hash function to accurately map the static route prefix of the corresponding mask length to obtain the perfect hash lookup result; S2. Map the prefix with mask length salt value to the bucket number using a hybrid hash function, store and search for newly added or changed incremental routing table entries, and obtain the cuckoo hash lookup results. S3. Complete the parallel mask comparison and output the longest prefix matching result from the championship comparison tree to obtain the updatable CAM search result; S4. Perform delayed alignment on the perfect hash lookup result, the cuckoo hash lookup result, and the updatable CAM lookup result to obtain the aligned lookup result; S5. Select the longest prefix from the aligned search results and the default empty results to match the search results.

2. A three-layer hybrid longest prefix matching search system, characterized in that, include: Perfect hash engine, Cuckoo hash engine, Updatable CAM engine, Delayed alignment unit, and Longest prefix matching arbitration unit; The perfect hash engine, the cuckoo hash engine, and the updatable CAM engine execute the input lookup request in parallel. Their outputs are all connected to the input of the delayed alignment unit. The output of the delayed alignment unit is connected to the input of the longest prefix matching arbitration unit. The longest prefix matching arbitration unit outputs the lookup result. The perfect hash engine is used to accurately map the static route prefix of the corresponding mask length using the minimum perfect hash function, and obtain the perfect hash lookup result; The Cuckoo Hash Engine is used to map a prefix with a mask length salt value to a bucket number using a hybrid hash function, store and search for newly added or changed incremental routing table entries, and obtain the Cuckoo Hash lookup results. The updatable CAM engine is used to perform parallel mask comparisons and outputs the longest prefix matching result from the championship comparison tree to obtain the updatable CAM search result; The delayed alignment unit is used to perform delayed alignment on the perfect hash lookup result, the cuckoo hash lookup result, and the updatable CAM lookup result to obtain the aligned lookup result. The longest prefix matching arbitration unit is used to select the longest prefix from the aligned search results and the default empty results to match the search results.

3. The three-layer hybrid longest prefix matching search system according to claim 2, characterized in that, The perfect hash engine includes N perfect hash sub-units divided according to the prefix mask length, where N≥2. Each perfect hash sub-unit accurately maps the routing prefix of its respective mask length based on the offline-built PTHash / PtrHash class minimum perfect hash function. The perfect hash subunit includes a pilots memory, a main table memory, and a prefix matching verification unit. After the main table is read, the prefix matching verification unit compares the stored prefix with the query prefix bit by bit to eliminate false hits.

4. The three-layer hybrid longest prefix matching search system according to claim 3, characterized in that, The perfect hash engine also includes: The system consists of two internally independent perfect hash engine instances, Bank A and Bank B, and a Bank selection register. A dedicated bit in the high-order address space of the configuration bus is used to select the target Bank, allowing the control software to write new pilots and main table content to the inactive Bank without affecting the active Bank's lookup path. Once all the new table content for the inactive Bank has been written, the control software sends a single-clock-cycle switching pulse to the Bank selection register, switching subsequent input lookup requests to the new Bank. Requests that have already entered the old Bank's lookup pipeline before the switch continue to be output by the old Bank, ensuring that any lookup request corresponds to the table content of only one Bank. This achieves an atomic switch from the old table to the new table without interrupting the lookup path, losing input requests, or generating intermediate lookup results.

5. The three-layer hybrid longest prefix matching search system according to claim 2, characterized in that, The Cuckoo Hash Engine includes multiple small-capacity Cuckoo Hash Tables independently configured according to the prefix mask length. Each Cuckoo Hash Table adopts a W-way group associative structure and maps the prefix with mask length salt value to the bucket number through a hybrid hash function. W≥2, which is used to carry routing table entries for online incremental learning. The bucket number is calculated by the splitmix64 type hash function for the prefix with mask length salt value.

6. The three-layer hybrid longest prefix matching search system according to claim 2, characterized in that, Each entry in the updatable CAM engine includes a prefix field, a mask length field, a next-hop index field, and a valid bit field. The updatable CAM engine performs parallel mask comparisons on all entries and outputs the longest prefix matching result within the updatable CAM engine through the championship comparison tree.

7. The three-layer hybrid longest prefix matching search system according to claim 2, characterized in that, It also includes a unified configuration bus; The high-order address encoding field of the configuration bus is used to route configuration write operations between the perfect hash engine, the cuckoo hash engine and the updatable CAM engine, so that the initialization and runtime updates of the three engines can be completed by a single control interface. The configuration bus includes a 32-bit address channel and a 64-bit data channel. The highest two bits of the address channel are used for routing between the Perfect Hash Engine, the Cuckoo Hash Engine, and the Updatable CAM Engine. When the highest two bits are 00, write to Bank A of the perfect hash engine; When the highest two bits are 0 or 1, write to Bank B of the perfect hash engine; When the highest two bits are 10, write to the updatable CAM engine; When the highest two bits are 11, write to the Cuckoo Hash Engine; The remaining 30 bits of address are used as internal sub-addresses of the target engine, and sub-units, sub-tables, table entries, and sub-registers are selected according to the fields of the sub-address.

8. The three-layer hybrid longest prefix matching search system according to claim 7, characterized in that, Also includes: Configure the serial loader and initialize the read-only memory; The initial read-only memory stores all initial values ​​of the perfect hash engine, the cuckoo hash engine, and the updatable CAM engine in a pre-compiled initialization sequence; After the system is reset and released, the configuration serial loader is driven by a finite state machine to sequentially read the initialization sequence and output it to the configuration bus. After all initial values ​​are written, the initialization completion bit is set to be valid. The query interface is gated and blocked while the initialization completion bit is invalid. The query request is accepted only after the initialization completion bit is valid, thereby ensuring that the query path does not output incorrect results within the initialization window.

9. A hot update method for the three-layer hybrid longest prefix matching search system according to any one of claims 2 to 8, characterized in that, Includes the following steps: The set of routes to be changed is divided into persistent route set, incremental learning route set and transient route set according to the change type; For the transient route set, the control software directly writes each entry into the corresponding entry of the updatable CAM engine. The writing order follows the atomic commit protocol, so that each entry is visible to subsequent query requests one clock cycle after the valid bits are written in the updatable CAM engine and there will be no half-written state. For the incremental learning route set, the control software selects the corresponding Cuckoo Hash sub-table according to the mask length for each table entry and writes it into the sub-table slots in order. When all the group-associative slots are occupied, the Cuckoo kick-out migration is performed. The control software incorporates the persistent route set into the next perfect hash engine static route table reconstruction process, continues to serve queries in the current active bank, and builds a new perfect hash table offline on inactive banks. The new perfect hash table includes pilot table content, main table content, and metadata content. The control software writes the new perfect hash table into the inactive Bank one by one through the unified configuration bus. The address field of the unified configuration bus is used to select the target Bank, target sub-unit and target storage location, and the data field is used to carry the content to be written. After all the new table contents of the inactive Bank are written, the control software sends a single-clock-cycle switching pulse to the Bank selection register, so that subsequent input lookup requests are switched to the new Bank, and requests that have entered the lookup pipeline of the old Bank before the switch continue to be completed and output by the old Bank. After the switch is completed, the control software clears the updatable CAM table and cuckoo hash table that have been covered by the new perfect hash table, so that the perfect hash engine, the cuckoo hash engine and the updatable CAM engine return to the steady-state division of labor where the perfect hash engine carries static routes, the cuckoo hash engine carries incremental routes and the updatable CAM engine carries transient routes.

10. A network processing chip or network processing board employing the three-layer hybrid longest prefix matching search method according to claim 1, or the three-layer hybrid longest prefix matching search system according to any one of claims 2 to 8.

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