Brain-machine interface module and packaging method

Abstract

The disclosure provides a brain-computer interface module and a packaging method. The packaging method includes: providing a conversion substrate, wherein the conversion substrate includes a conductive part extending from the surface of the first side of the conversion substrate towards the inside of the conversion substrate; forming a first interconnection structure, a second interconnection structure and an electrode at the first side of the conversion substrate, wherein the first interconnection structure is electrically connected with the electrode, and the second interconnection structure is electrically connected with the conductive part; forming a third interconnection structure electrically connected with the conductive part at the second side of the conversion substrate, wherein the second side is opposite to the first side; releasing at least a part of the electrode; and bonding the conversion substrate with a chip at the first side of the conversion substrate, and bonding the conversion substrate with a printed circuit board at the second side of the conversion substrate, wherein the electrode is electrically connected with a first interface site of the chip via the first interconnection structure, and the terminal of the printed circuit board is electrically connected with a second interface site of the chip via the third interconnection structure, the conductive part and the second interconnection structure.

Description

Technical Field

[0001] This disclosure relates to the field of brain-computer interfaces, and more specifically, to a brain-computer interface module and a packaging method. Background Technology

[0002] In recent years, with the deep integration and rapid development of multiple disciplines such as materials science, micro-nano fabrication technology, computer science, electronic engineering, and neuroscience, brain-computer interface technology has made significant progress. Its application scenarios are constantly expanding, covering cutting-edge areas such as rehabilitation treatment of diseases like Parkinson's disease and epilepsy, assistive devices for motor dysfunction, visual and auditory restoration, enhancement of motor abilities, and even super vision enhancement, demonstrating important scientific research value and broad clinical application prospects.

[0003] Brain-computer interface (BCI) systems typically require complete implantation and are classified as Class III implantable medical devices, placing extremely high demands on device size, biocompatibility, and long-term reliability. To minimize implantation trauma, reduce immune responses, and minimize tissue damage, BCI devices must continuously evolve towards miniaturization, lightweight design, and high integration.

[0004] In this evolution, achieving high-density, compact integration of chips, electrodes (e.g., flexible electrodes), and printed circuit boards (PCBs) to accommodate limited implantation space has become a key bottleneck in current device design. However, existing packaging solutions still have shortcomings in interconnect structure, arrangement, and overall thickness control, making it difficult to meet increasingly stringent miniaturization requirements. Therefore, there is an urgent need for a solution that can achieve compact, integrated packaging of chips, electrodes, and PCBs. Summary of the Invention

[0005] One of the purposes of this disclosure is to provide a packaging method and a brain-computer interface module.

[0006] According to a first aspect of this disclosure, a packaging method is provided, the packaging method comprising: An adapter substrate is provided, wherein the adapter substrate includes a conductive portion that extends from a surface on a first side of the adapter substrate toward the interior of the adapter substrate. A first interconnect structure, a second interconnect structure, and an electrode are formed on a first side of the adapter substrate, wherein the first interconnect structure is electrically connected to the electrode, and the second interconnect structure is electrically connected to the conductive portion; A third interconnect structure electrically connected to the conductive portion is formed on the second side of the adapter substrate, wherein the second side is opposite to the first side; Release at least a portion of the electrode; and The adapter substrate is bonded to the chip at a first side of the adapter substrate, and the adapter substrate is bonded to the printed circuit board at a second side of the adapter substrate, wherein the electrode is electrically connected to the first interface site of the chip via the first interconnect structure, and the terminals of the printed circuit board are electrically connected to the second interface site of the chip via the third interconnect structure, the conductive portion and the second interconnect structure.

[0007] In some embodiments, providing an adapter substrate includes: A patterned first dielectric layer is formed on the surface of a first side of the substrate, and an opening in the first dielectric layer exposes at least a portion of the substrate. Deep etching is performed on the substrate at the opening of the first dielectric layer to form a hole; An adhesion layer is formed on the first dielectric layer and in the hole; A first conductive layer is formed on the adhesive layer; A second conductive layer is formed on the first conductive layer, wherein at least a portion of the second conductive layer fills the hole to form the conductive portion.

[0008] In some embodiments, the hole includes a blind hole or a through hole.

[0009] In some embodiments, the encapsulation method further includes: In the case where the hole includes a blind hole, before forming the third interconnect structure, the adapter substrate is thinned on the second side of the adapter substrate so that the conductive portion is exposed on the surface of the second side of the adapter substrate.

[0010] In some embodiments, the aperture of the pore is in the range of 10-50 micrometers.

[0011] In some embodiments, the aspect ratio of the hole is in the range of 5:1 to 10:1.

[0012] In some embodiments, the first dielectric material of the first dielectric layer includes silicon dioxide.

[0013] In some embodiments, the adhesive material of the adhesive layer includes at least one of titanium and chromium.

[0014] In some embodiments, the first conductive material of the first conductive layer includes copper.

[0015] In some embodiments, the second conductive material of the second conductive layer includes copper.

[0016] In some embodiments, the substrate includes a silicon substrate.

[0017] In some embodiments, forming a first interconnect structure, a second interconnect structure, and electrodes at a first side of the adapter substrate includes: A patterned third conductive layer and a sacrificial layer are formed on a first side of the adapter substrate. The third conductive layer includes a first conductive portion and a second conductive portion that are insulated from each other. The sacrificial layer is spaced apart from the third conductive layer. A patterned second dielectric layer is formed on the first side of the uncovered portion of the third conductive layer, the sacrificial layer, and the adapter substrate. A first via of the second dielectric layer exposes at least a portion of the first conductive portion, a second via of the second dielectric layer exposes at least another portion of the first conductive portion, and a third via of the second dielectric layer exposes at least a portion of the second conductive portion. A conductive element is formed, wherein the conductive element includes a third conductive portion, a fourth conductive portion, a fifth conductive portion and a sixth conductive portion, the third conductive portion is filled in the first through hole, the fourth conductive portion is filled in the second through hole, the fifth conductive portion is located above the first side of the second dielectric layer and is electrically connected to the fourth conductive portion, and the sixth conductive portion is filled in the third through hole; A patterned third dielectric layer is formed on a first side of the portion of the conductive element and the second dielectric layer not covered by the conductive element. A fourth via in the third dielectric layer exposes the third conductive portion, a fifth via in the third dielectric layer exposes at least a portion of the fifth conductive portion, and a sixth via in the third dielectric layer exposes the sixth conductive portion; and A site coating is formed, which fills the fifth through-hole. The first interconnect structure includes a first conductive portion and a third conductive portion, the electrode includes a fourth conductive portion, a fifth conductive portion and a site coating, and the second interconnect structure includes a second conductive portion and a sixth conductive portion.

[0018] In some embodiments, the third conductive material of the third conductive layer includes aluminum.

[0019] In some embodiments, the sacrificial material of the sacrificial layer includes aluminum.

[0020] In some embodiments, the second dielectric material of the second dielectric layer includes polyimide.

[0021] In some embodiments, the conductive material of the conductive element includes gold.

[0022] In some embodiments, the third dielectric material of the third dielectric layer includes polyimide.

[0023] In some embodiments, the site coating material of the site coating includes at least one of titanium nitride, platinum black, and iridium oxide.

[0024] In some embodiments, both the third conductive material and the sacrificial material are aluminum, and the third conductive layer and the sacrificial layer are formed simultaneously.

[0025] In some embodiments, releasing at least a portion of the electrode includes: Remove the portion of the sacrificial layer and the adapter substrate located on the second side of the sacrificial layer to release the portion of the electrode located on the first side of the sacrificial layer.

[0026] In some embodiments, the encapsulation method further includes: The adapter substrate is diced to obtain one or more adapter substrate assemblies.

[0027] In some embodiments, the encapsulation method further includes: Prior to forming the third interconnect structure, a protective layer is formed on the first side of the third dielectric layer and the site coating; and After at least a portion of the electrode is released, the protective layer is removed.

[0028] In some embodiments, bonding the adapter substrate to a chip at a first side of the adapter substrate and bonding the adapter substrate to a printed circuit board at a second side of the adapter substrate includes: First, one of the chip and the printed circuit board is bonded to the adapter substrate using a first bonding process; and The chip and the other component of the printed circuit board are then bonded to the adapter substrate using a second bonding process. Wherein, the first bonding temperature of the first bonding process is higher than the second bonding temperature of the second bonding process.

[0029] In some embodiments, the first bonding temperature is greater than 260 degrees Celsius.

[0030] In some embodiments, the first bonding material used in the first bonding process includes at least one of high-temperature tin-based solder and gold.

[0031] In some embodiments, the second bonding temperature is in the range of 150-200 degrees Celsius.

[0032] In some embodiments, the second bonding material used in the second bonding process includes a low-temperature tin-based solder.

[0033] According to a second aspect of this disclosure, a brain-computer interface module is provided, the brain-computer interface module including a chip, electrodes and a printed circuit board, wherein the chip, the electrodes and the printed circuit board are packaged by a packaging method according to any embodiment of the first aspect of this disclosure.

[0034] Other features and advantages of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0035] The foregoing and other features and advantages of this disclosure will become clear from the following description of embodiments illustrated in conjunction with the accompanying drawings. The drawings, incorporated herein and forming a part of the specification, are further used to explain the principles of this disclosure and to enable those skilled in the art to make and use it. Wherein: Figure 1 A schematic flowchart of an encapsulation method according to an exemplary embodiment of the present disclosure is shown; Figure 2 A schematic diagram of the structure of a brain-computer interface module according to an exemplary embodiment of the present disclosure is shown; Figures 3 to 19 A schematic diagram of a packaging process according to an exemplary embodiment of the present disclosure is shown.

[0036] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0037] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0038] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0039] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. Those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and are not exhaustive.

[0040] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0041] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0042] Currently, the back-end assembly methods between chips, electrodes, and printed circuit boards in the field of brain-computer interfaces are still immature, and the package size is generally too large. One approach is to use discrete device back-end assembly processes such as flying wire bonding. However, this type of process has revealed several shortcomings in application. First, in terms of space occupation, the bonding area, interconnect leads, and auxiliary structures occupy additional space, making it difficult to meet the stringent requirements of ultra-small size for fully implantable devices. Second, regarding electrical connection quality, the alignment accuracy and contact reliability of flying wire bonding under micro-pitch conditions are limited, especially in multi-channel, high-throughput scenarios, where bonding points are prone to problems such as cold solder joints, open circuits, or high impedance, leading to a decrease in overall conductivity. Furthermore, in terms of manufacturing feasibility, the back-end assembly process for discrete devices is lengthy, with prominent interface matching and thermal mismatch issues, high process complexity, and limited yield, which is not conducive to achieving large-scale, high-consistency mass production.

[0043] To address at least one of the aforementioned problems, this disclosure provides a packaging method that, from a system-level integration perspective, achieves high-density, high-reliability vertical interconnection between the chip, electrodes, and printed circuit board by fabricating electrodes on an adapter substrate including conductive vias (e.g., through-silicon vias, TSVs) and then bonding the chip and printed circuit board to opposite sides of the adapter substrate.

[0044] The packaging methods according to various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It will be understood that actual methods may include other steps, which are not shown in the drawings and will not be discussed herein in order to avoid obscuring the key points of the present disclosure.

[0045] like Figure 1 As shown, the packaging method proposed in this disclosure may include: step S110, providing an adapter substrate; step S120, forming a first interconnect structure, a second interconnect structure, and an electrode on a first side of the adapter substrate; step S130, forming a third interconnect structure electrically connected to a conductive portion on a second side of the adapter substrate; step S140, releasing at least a portion of the electrode; and step S150, bonding the adapter substrate to a chip on the first side of the adapter substrate, and bonding the adapter substrate to a printed circuit board on the second side of the adapter substrate.

[0046] The following will combine Figures 3 to 19 This document provides a detailed description of a specific implementation of the packaging method provided herein. This implementation corresponds to a preferred execution flow of steps S110 to S150 described above, wherein the specific operations, sequence arrangement, and structural features of each step will be explained below.

[0047] First, in step S110, an adapter substrate is provided.

[0048] Specifically, such as Figure 3 As shown, providing an adapter substrate may include: forming a patterned first dielectric layer 3020 on the surface of a first side of the substrate 3010, wherein an opening 3021 in the first dielectric layer 3020 exposes at least a portion of the substrate. In this disclosure, "first side" refers to... Figures 3 to 19 The upper side, also known as the front; the "second side" is the side opposite to the first side, that is... Figures 3 to 19 The lower side, also known as the back side, is the substrate. The substrate can be a silicon substrate. In other embodiments, the substrate can also be a glass substrate, a ceramic substrate, etc. In some embodiments, a first dielectric material can be deposited using plasma-enhanced chemical vapor deposition (PECVD) or thermal oxidation, followed by patterning of the first dielectric material using photolithography and etching processes. The first dielectric layer provides an electrical isolation basis for subsequent metal interconnect structures, defines the formation location of conductive vias, and provides thermal stability for subsequent high-temperature processes. In some embodiments, the first dielectric material can be silicon dioxide (SiO2).

[0049] like Figure 4 As shown, providing an adapter substrate may further include: deeply etching the substrate 3010 at the opening 3021 of the first dielectric layer 3020 to form a hole 3011. For example, deep reactive ion etching (DRIE) can be used to achieve deep etching. In some embodiments, the aperture of the hole 3011 can be 10-50 μm, and the aspect ratio can be 5:1-10:1. In some embodiments, the hole 3011 can be a blind hole, i.e., a hole closed at one end. In this way, it is not necessary to use a thin substrate for front-side preparation in advance, but a thicker substrate with better rigidity can be used, making the substrate less prone to warping during photolithography, thin film deposition and other processing, thereby reducing the risk of device damage and improving process yield.

[0050] like Figure 5As shown, the adapter substrate may further include: forming an adhesive layer on the first dielectric layer 3020 and in the via 3011; and forming a first conductive layer on the adhesive layer. The adhesive layer and the first conductive layer can be considered as a seed layer 3030, which provides a conductive substrate and a good adhesion interface for subsequent electroplating of metal. For example, the seed layer 3030 can be formed by physical vapor deposition (PVD). For example, the adhesive layer can be formed by sputtering an adhesive material, and then the first conductive layer can be formed by sputtering a first conductive material. In some embodiments, the adhesive material may include at least one of titanium (Ti) and chromium (Cr). In some embodiments, the first conductive material may include copper (Cu).

[0051] like Figure 6 As shown, the adapter substrate may further include: forming a second conductive layer 3040 on a first conductive layer, wherein at least a portion of the second conductive layer 3040 fills the vias 3011 to form conductive portions. For example, an electrochemical deposition process (electroplating) can be used to grow a second conductive material on a seed layer 3030. In some embodiments, the second conductive material may be copper. Optionally, after electroplating, excess second conductive material and the seed layer on the surface of the first dielectric layer 3020 can be removed by chemical mechanical polishing (CMP) until the top surface of the dielectric layer is exposed, achieving surface planarization. The structure prepared by this process is as follows: Figure 6 As shown, the seed layer remaining inside the hole 3011, together with the second conductive layer, constitutes a conductive portion extending from the surface of the first side of the adapter substrate toward the interior of the adapter substrate, and there is no excess metal residue on the front side of the adapter substrate, resulting in a flat structure. Thus, the substrate 3010, the first dielectric layer 3020, and the conductive portion together constitute the adapter substrate. In some embodiments, the conductive portion can be a through-silicon via (TSV) conductive structure.

[0052] By combining a seed layer with electroplating for thickening, a thin seed layer can achieve uniform coverage, while electroplating thickens the metal to reduce interconnect resistance and improve signal transmission performance. Compared to methods that rely solely on evaporation or sputtering to deposit thick metals, electroplating thickening offers higher material utilization for the same thickness and a faster deposition rate, which helps reduce manufacturing costs.

[0053] Then, in step S120, a first interconnect structure, a second interconnect structure, and an electrode are formed on the first side of the adapter substrate.

[0054] like Figure 7As shown, forming the first interconnect structure, the second interconnect structure, and the electrodes includes forming a patterned third conductive layer and a sacrificial layer 3060 on a first side of the adapter substrate. In some embodiments, the materials of the third conductive layer and the sacrificial layer 3060 can be the same, for example, both the third conductive material and the sacrificial material are aluminum (Al), then the third conductive layer and the sacrificial layer 3060 can be formed simultaneously. Exemplarily, an aluminum metal layer can be deposited by electron beam evaporation or thermal evaporation. Then, a positive photoresist is coated, and the pattern of the third conductive layer and the sacrificial layer (i.e., covering the area to be exposed in the future) is formed by photolithography. Then, an etching process matching the aluminum is used to remove the exposed excess aluminum. The remaining photoresist is then removed to obtain the desired result. Figure 7 The patterned structure shown comprises three spaced-apart, insulated, and non-contacting parts: a first conductive portion 3051 of the third conductive layer, a second conductive portion 3052 of the third conductive layer, and a sacrificial layer 3060. The first conductive portion 3051 forms a conductive path between the flexible electrode and the chip. The second conductive portion 3052 covers the conductive portion, serving as a top pad and forming a conductive path between the chip and the conductive portion. The sacrificial layer 3060 is a process aid layer for subsequent floating electrode fabrication, used to define the floating electrode forming area. Each area is electrically isolated and does not interfere with the others. In other embodiments, the third conductive layer and the sacrificial layer are made of different materials, and are formed sequentially. Alternatively, to control their thickness and pattern size separately, the third conductive layer and the sacrificial layer can also be formed sequentially. In some embodiments, the third conductive layer may include a redistribution layer (RDL). The first conductive portion 3051 and the second conductive portion 3052 can each be configured with wiring segments matching their own paths, each forming an independent and complete redistribution path. By redistributing the locations of densely packed and narrowly spaced I / O ports on the chip, the chip electrode ports can be repositioned to layouts that are more suitable for electrode docking and TSV vertical interconnects, avoiding bonding interference issues of high-density pins and improving the layout flexibility and manufacturability of the package.

[0055] like Figure 8As shown, forming the first interconnect structure, the second interconnect structure, and the electrodes further includes forming a patterned second dielectric layer 3070 on the first side of the uncovered portion of the third conductive layer, the sacrificial layer 3060, and the transition substrate. To form the second dielectric layer, for example, a second dielectric material can be spin-coated first, and then patterned by photolithography and development to form the desired window region. The window region includes a first via 3071, a second via 3072, and a third via 3073. The first via 3071 exposes at least a portion of the first conductive portion 3051 to expose pads for interconnecting the electrode with the chip. The second via 3072 exposes at least a portion of the first conductive portion 3051, where the proximal end of the electrode will subsequently be fabricated. The third via 3073 exposes at least a portion of the second conductive portion 3052 to expose pads for interconnecting the chip with the conductive portion. The second dielectric layer 3070 serves as a substrate for the electrodes and also isolates the underlying conductive structures, achieving electrical insulation. In some embodiments, the second dielectric material is polyimide (PI), which has good flexibility and biocompatibility.

[0056] like Figure 9As shown, forming the first interconnect structure, the second interconnect structure, and the electrodes further includes forming conductive elements. For example, conductive element material can be deposited by evaporation or sputtering, and then patterned by photolithography and etching to form the desired conductive portions. The conductive elements may include a third conductive portion 3081, a fourth conductive portion 3082, a fifth conductive portion 3083, and a sixth conductive portion 3084. The third conductive portion 3081 fills the first via 3071 and extends vertically, extending the electrical connection of the electrode to the chip interconnect pad to the top surface of the package structure to facilitate subsequent packaging with the chip. The fourth conductive portion 3082 fills the second via 3072 to achieve vertical conduction; the fifth conductive portion 3083 is located above the first side of the second dielectric layer 3070 and electrically connected to the fourth conductive portion 3082, serving as a planar lead-out wiring; the two together form the electrode body. It can be observed that at least a portion of the fifth conductive portion 3083 is located directly above the sacrificial layer 3060, allowing this portion to form a suspended structure after the sacrificial layer is subsequently removed. Furthermore, the division between the fourth and fifth conductive portions is merely for ease of description of the technical solution of this disclosure; in actual manufacturing, these two portions can be manufactured simultaneously, and there may not be a clear structural boundary between them. The sixth conductive portion 3084 fills the third via 3073 and extends vertically in a similar manner to the third conductive portion 3081, extending the electrical connection between the conductive portion (e.g., the TSV conductive portion) and the chip interconnect pads to the top surface of the package structure. In some embodiments, the conductive material may include gold (Au). In this disclosure, "vertical direction" refers to the direction perpendicular to the first side surface of the adapter substrate, i.e., the thickness direction of the adapter substrate.

[0057] like Figure 10 As shown, forming the first interconnect structure, the second interconnect structure, and the electrode further includes forming a patterned third dielectric layer 3090 on a first side of the portion of the conductive element and the second dielectric layer 3070 not covered by the conductive element. To form the third dielectric layer 3090, for example, a third dielectric material can be spin-coated first, and then the third dielectric material can be patterned by photolithography and development to form the desired window region. The window region includes a fourth via 3091, a fifth via 3092, and a sixth via 3093. The fourth via 3091 exposes the third conductive portion 3081, i.e., exposes the electrical connection path between the electrode and the chip, facilitating packaging with the chip. The fifth via 3092 exposes at least a portion of the fifth conductive portion 3083 to expose the distal end of the electrode for subsequent electrode site fabrication. The sixth via 3093 exposes the sixth conductive portion 3084, i.e., exposes the electrical connection path between the conductive portion (e.g., the TSV conductive portion) and the chip. The third dielectric layer 3090 can serve as a top insulating layer for the electrode. In some embodiments, the third dielectric material includes polyimide.

[0058] like Figure 11 As shown, forming the first interconnect structure, the second interconnect structure, and the electrode further includes forming a site coating 3100. For example, a functional coating can be selectively deposited in the electrode site region defined by the fifth via 3092. Exemplarily, the site coating 3100 can be formed by sputtering or electrodepositing a site coating material of a set thickness (e.g., 0.5-5 μm). In some embodiments, the site coating material may include at least one of titanium nitride, platinum black, and iridium oxide. The site coating 3100 serves as a collection / stimulation site for the electrode, allowing direct contact with brain tissue after implantation to achieve the collection of neural signals or the application of electrical stimulation signals.

[0059] This allows us to obtain, as follows: Figure 11 The diagram shows a first interconnect structure, a second interconnect structure, and an electrode. The electrode, serving as a neural interface portion (also referred to as a flexible electrode), includes a site coating 3100 for contact with brain tissue, a fifth conductive portion 3083, and a fourth conductive portion 3082. The first interconnect structure includes a first conductive portion 3051 and a third conductive portion 3081. One end of the first interconnect structure is connected to the electrode, and the other end is connected to a corresponding pad on the chip. The electrode and the first interconnect structure together form a pathway for acquiring neural signals or applying electrical stimulation signals from the brain tissue to the chip. The second interconnect structure includes a second conductive portion 3052 and a sixth conductive portion 3084. One end of the second interconnect structure is connected to a conductive portion (e.g., a TSV conductive portion), and the other end is also connected to a corresponding pad on the chip.

[0060] In some embodiments, the third dielectric layer 3090 and the second dielectric layer 3070 may also be etched to form a release trench (not shown in the figure). This release trench extends through each of the dielectric layers along the electrode trace contour, spatially separating the dielectric layer to which the electrode trace region is attached from the surrounding dielectric layers. Thus, after subsequent removal of the sacrificial layer 3060, the electrode can be separated from the surrounding dielectric structure as an independent flexible strip, allowing it to be bent, extended, and implanted into the target brain tissue region.

[0061] In some embodiments, before step S130, such as Figure 12 As shown, a protective layer 3110 can also be formed on the first side of the third dielectric layer 3090 and the site coating 3100. For example, a forward photoresist can be uniformly coated on the surface of the device with completed wiring, and key areas can be selectively protected through exposure and development processes to prevent damage to the formed structure by subsequent processes (including but not limited to etching, thinning, release, etc.). The protective layer 3110 protects the front side of the package structure.

[0062] In some embodiments, such as Figure 13As shown, the adapter substrate can be thinned on its second side to expose the conductive portion on the surface of the second side of the adapter substrate. For example, the adapter substrate can be flipped over and its back side can be mechanically ground and chemically mechanically polished until the conductive portion (e.g., the TSV conductive portion) is exposed, or until it is thinned to a set thickness. This back side thinning can remove the remaining silicon substrate at the bottom of the blind via, opening up vertical conductive paths on both sides of the substrate; it can also reduce the overall thickness of the substrate, shrink the overall package size, and improve device integration.

[0063] Then in step S130, as Figure 14 As shown, a third interconnect structure 3120 electrically connected to the conductive portion is formed on the second side of the adapter substrate. For example, photolithography can be performed on the back side of the adapter substrate, and pads can be formed by a long seed layer and electroplating (e.g., sequentially sputtering titanium, copper, and then electroplating copper) to achieve electrical lead-out on the back side of the conductive portion. In some embodiments, the third interconnect structure 3120 may include a redistribution structure to achieve more flexible electrical connections. In this way, one end of the third interconnect structure is connected to the end of the conductive portion located on the second side, and the other end of the third interconnect structure is connected to a corresponding terminal on the printed circuit board. The second interconnect structure, the conductive portion, and the third interconnect structure 3120 together form a signal transmission path from the printed circuit board to the chip.

[0064] Then, in step S140, at least a portion of the electrode is released.

[0065] like Figure 15 As shown, releasing at least a portion of the electrode includes removing the sacrificial layer 3060. For example, the component can be immersed in a sacrificial layer etchant that enters from the exposed side surface of the sacrificial layer 3060 and laterally etches the sacrificial layer 3060 in a direction substantially parallel to a first side surface of the adapter substrate. As the sacrificial layer 3060 is gradually removed, the electrode portion located above the sacrificial layer 3060 separates from the adapter substrate, thereby forming a flexible structure that can be bent relative to the adapter substrate.

[0066] like Figure 16 As shown, at least a portion of the release electrode further includes: a portion of the adapter substrate located on the second side of the sacrificial layer that can be removed. It should be understood that "the portion located on the second side of the sacrificial layer" refers to a region in the adapter substrate corresponding to the sacrificial layer in the vertical direction. The horizontal extent of this region can be approximately the same as, or slightly larger than, or slightly smaller than, the coverage area of ​​the sacrificial layer. In some embodiments, this portion can be the portion located directly below the second side of the sacrificial layer. Specifically, laser cutting or diamond scribing can be used to remove the corresponding portions of the substrate 3010 and the first dielectric layer 3020 along a pre-defined cutting path, thereby providing sufficient space for the suspended portion of the electrode to move.

[0067] In some embodiments, such as Figure 17 As shown, after at least a portion of the electrode is released, the protective layer 3110 can also be removed. For example, the protective layer 3110 can be removed by oxygen plasma ashing or by immersing the device in a resist remover to obtain a complete adapter-electrode integrated device.

[0068] Finally, in step S150, the adapter substrate is bonded to the chip 500 on the first side of the adapter substrate, and the adapter substrate is bonded to the printed circuit board 400 on the second side of the adapter substrate.

[0069] like Figure 18 and Figure 19 As shown, the adapter substrate can be bonded to the printed circuit board 400 first, and then to the chip 500.

[0070] First, such as Figure 18 As shown, high-temperature solder (e.g., high-temperature tin-based solder or gold) is used to form solder balls at the third interconnect structure 3120 of the terminal of the printed circuit board 400 or the adapter substrate, and flip bonding is completed at a bonding temperature greater than 260°C to form a stable and reliable metal interconnect interface, thereby establishing a conductive path between the printed circuit board 400 and the conductive part in the adapter substrate.

[0071] Then, as Figure 19 As shown, low-temperature solder (e.g., low-temperature tin-based solder) is used to form solder balls (not shown) at the pads of chip 500 or the first and second interconnect structures of the adapter substrate. Flip bonding is completed in the temperature range of 150°C to 200°C, establishing conductive paths between the first interface site (e.g., analog interface site) of chip 500 and the electrode, and between the second interface site (e.g., digital interface site) of chip 500 and the conductive part in the adapter substrate. This process sequence treats low-temperature bonding as a subsequent process, avoiding reflow and melting failure of the preceding high-temperature solder joints, and ensuring the connection stability and reliability of the double-sided bonding structure.

[0072] In other embodiments, the bonding sequence can be adjusted, with the chip first bonded using a high-temperature bonding process and the printed circuit board then bonded using a low-temperature bonding process.

[0073] In the final package structure, the electrodes are electrically connected to the first interface site of the chip 500 via the first interconnect structure, and the terminals of the printed circuit board 400 are electrically connected to the second interface site of the chip via the third interconnect structure, the conductive portion, and the second interconnect structure. Due to the use of flip-chip bonding, the chip, the adapter substrate, and the printed circuit board are stacked vertically, which helps to further compress the planar dimensions of the entire package structure, meeting the miniaturization requirements of brain-computer interface devices.

[0074] It should be noted that the entire fabrication process of the aforementioned adapter substrate and electrodes can be completed using wafer-level batch processing technology. In some embodiments, after the fabrication process is completed, the entire wafer can be diced to obtain one or more independent adapter substrate assemblies, which are then bonded to chips and printed circuit boards respectively. Wafer-level batch processing can improve device production efficiency and reduce the manufacturing cost per device.

[0075] In the above reference Figures 3 to 19 In the described embodiment, the conductive portion is first formed in the substrate 3010 as a blind via and then exposed to the second side in a subsequent thinning process. However, this disclosure is not limited thereto. As a variation of the above embodiment, the hole 3011 can be a through hole, i.e., a hole that penetrates the substrate 3010 (not shown in the figure). In this way, interconnect structures can be directly fabricated at both ends of the hole to complete the vertical interconnect, and the substrate backside thinning process can be an optional step, thereby shortening the overall process flow.

[0076] Furthermore, in the above reference Figures 3 to 19 In the described embodiment, the electrode is exposed at least partially by releasing the sacrificial layer 3060. However, this disclosure is not limited to this. In another variant embodiment, the fabrication process may omit the aforementioned aluminum sacrificial layer 3060, and the electrode can be suspended and released solely through selective etching of the silicon substrate on the back side. Specifically, on the second side of the adapter substrate, portions of the substrate 3010 and the first dielectric layer 3020 corresponding to the electrode region in the thickness direction can be selectively removed, forming a hollow space below the electrode, thus giving the electrode a deformable suspended structure. The etching method can be dry etching (e.g., xenon difluoride (XeF2) vapor phase dry etching) or wet etching (e.g., tetramethylammonium hydroxide (TMAH) aqueous solution wet etching). In such an embodiment, the steps of sacrificial layer deposition, patterning, and etching removal are eliminated, simplifying the overall process flow. Subsequently, residual impurities such as surface photoresist and organic protective layers can be removed by oxygen plasma ashing or a dedicated resist remover.

[0077] It should be understood that the accompanying drawings only exemplarily show various functional structures such as a single hole, a single flexible electrode, and a single set of interface sites. This application does not limit the number of any structure, and multiple sets of corresponding structures can be flexibly set according to the signal channel, device performance, and integration requirements.

[0078] According to another aspect of this disclosure, a brain-computer interface module is also provided. For example... Figure 2As shown, the brain-computer interface module may include a chip 210, electrodes 220, and a printed circuit board 230. Electrical connections between the chip 210, electrodes 220, and printed circuit board 230 are achieved via an adapter substrate 240. It is understood that the brain-computer interface module may also include other components (not shown) to achieve desired electrical functions. Furthermore, the chip, electrodes, and printed circuit board in the brain-computer interface module of this disclosure can be packaged using the packaging method described above.

[0079] In this disclosed technical solution, electrodes with a suspended release structure are first integrated and fabricated on an adapter substrate. Vertical conductive interconnects are then built using TSV conductive parts. Finally, a high-low temperature stepwise flip-chip bonding process is employed to complete the three-dimensional interconnection of the chip and printed circuit board on both sides of the adapter substrate. This packaging method abandons traditional wire bonding structures, effectively improving device fabrication consistency and achieving miniaturization, enabling high-density, high-reliability multilayer electrical interconnections. The entire fabrication process exhibits strong process controllability and outstanding process stability, reducing the probability of interconnect failures and structural defects during mass production. This solution demonstrates excellent process compatibility, fully adapting to high-throughput fully implantable brain-computer interface systems, meeting the comprehensive requirements of miniaturized implantable devices, multi-channel high-density interconnection, and long-term reliability.

[0080] In the specification and claims, when an element is described as being "on top of," "attached to," "connected to," "coupled to," or "in contact with" another element, the element may be directly located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. Conversely, when an element is described as being "directly" located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with another element, no intermediate elements are present. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that a feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0081] As used herein, the term “exemplary” means “serving as an example, instance, or illustration” and not as a “model” to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, this disclosure is not limited to any theory expressed or implied as given in the field of art, background art, summary of invention, or detailed description.

[0082] As used herein, the term "substantially" means any minor variation resulting from design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0083] Furthermore, terms such as “first,” “second,” etc., may be used in this document for reference purposes only and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence.

[0084] It should also be understood that when the term “including / contains” is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0085] In this disclosure, the term “provide” is used broadly to cover all ways of obtaining an object, and therefore “provide an object” includes, but is not limited to, “purchasing,” “preparing / manufacturing,” “arranging / setting up,” “installing / assembling,” and / or “ordering” an object.

[0086] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0087] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Aspects and elements of all the embodiments disclosed above may be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0088] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A packaging method, characterized in that, The encapsulation method includes: An adapter substrate is provided, wherein the adapter substrate includes a conductive portion that extends from a surface on a first side of the adapter substrate toward the interior of the adapter substrate. A first interconnect structure, a second interconnect structure, and an electrode are formed on a first side of the adapter substrate, wherein the first interconnect structure is electrically connected to the electrode, and the second interconnect structure is electrically connected to the conductive portion. The formation of the first interconnect structure, the second interconnect structure, and the electrode on the first side of the adapter substrate includes the formation of a patterned third conductive layer and a sacrificial layer on the first side of the adapter substrate. The third conductive layer includes a first conductive portion and a second conductive portion that are insulated from each other, and the sacrificial layer is spaced apart from the third conductive layer. A third interconnect structure electrically connected to the conductive portion is formed on the second side of the adapter substrate, wherein the second side is opposite to the first side; Releasing at least a portion of the electrode, wherein releasing at least a portion of the electrode includes removing the portion of the sacrificial layer and the adapter substrate located on the second side of the sacrificial layer to release the portion of the electrode located on the first side of the sacrificial layer; and The adapter substrate is bonded to the chip at a first side of the adapter substrate, and the adapter substrate is bonded to the printed circuit board at a second side of the adapter substrate, wherein the electrode is electrically connected to the first interface site of the chip via the first interconnect structure, and the terminals of the printed circuit board are electrically connected to the second interface site of the chip via the third interconnect structure, the conductive portion and the second interconnect structure.

2. The method according to claim 1, characterized in that, The adapter board includes: A patterned first dielectric layer is formed on the surface of a first side of the substrate, and an opening in the first dielectric layer exposes at least a portion of the substrate. Deep etching is performed on the substrate at the opening of the first dielectric layer to form a hole; An adhesion layer is formed on the first dielectric layer and in the hole; A first conductive layer is formed on the adhesive layer; and A second conductive layer is formed on the first conductive layer, wherein at least a portion of the second conductive layer fills the hole to form the conductive portion.

3. The method according to claim 2, characterized in that, The hole includes a blind hole or a through hole.

4. The method according to claim 3, characterized in that, The encapsulation method further includes: In the case where the hole includes a blind hole, before forming the third interconnect structure, the adapter substrate is thinned on the second side of the adapter substrate so that the conductive portion is exposed on the surface of the second side of the adapter substrate.

5. The method according to claim 2, characterized in that: The aperture of the pore is in the range of 10-50 micrometers; and / or The aspect ratio of the hole is in the range of 5:1 to 10:1; and / or The first dielectric material of the first dielectric layer includes silicon dioxide; and / or The adhesive material of the adhesive layer includes at least one of titanium and chromium; and / or The first conductive material of the first conductive layer includes copper; and / or The second conductive material of the second conductive layer includes copper; and / or The substrate includes a silicon plate.

6. The method according to claim 1, characterized in that, The first interconnect structure, the second interconnect structure, and the electrode formed on the first side of the adapter substrate further include: A patterned second dielectric layer is formed on the first side of the uncovered portion of the third conductive layer, the sacrificial layer, and the adapter substrate. A first via of the second dielectric layer exposes at least a portion of the first conductive portion, a second via of the second dielectric layer exposes at least another portion of the first conductive portion, and a third via of the second dielectric layer exposes at least a portion of the second conductive portion. A conductive element is formed, wherein the conductive element includes a third conductive portion, a fourth conductive portion, a fifth conductive portion and a sixth conductive portion, the third conductive portion is filled in the first through hole, the fourth conductive portion is filled in the second through hole, the fifth conductive portion is located above the first side of the second dielectric layer and is electrically connected to the fourth conductive portion, and the sixth conductive portion is filled in the third through hole; A patterned third dielectric layer is formed on a first side of the portion of the conductive element and the second dielectric layer not covered by the conductive element. A fourth via in the third dielectric layer exposes the third conductive portion, a fifth via in the third dielectric layer exposes at least a portion of the fifth conductive portion, and a sixth via in the third dielectric layer exposes the sixth conductive portion; and A site coating is formed, which fills the fifth through-hole. The first interconnect structure includes a first conductive portion and a third conductive portion, the electrode includes a fourth conductive portion, a fifth conductive portion and a site coating, and the second interconnect structure includes a second conductive portion and a sixth conductive portion.

7. The method according to claim 6, characterized in that: The third conductive material of the third conductive layer includes aluminum; and / or The sacrificial material of the sacrificial layer includes aluminum; and / or The second dielectric material of the second dielectric layer includes polyimide; and / or The conductive material of the conductive element includes gold; and / or The third dielectric material of the third dielectric layer includes polyimide; and / or The site coating material of the site coating includes at least one of titanium nitride, platinum black, and iridium oxide.

8. The method according to claim 7, characterized in that, Both the third conductive material and the sacrificial material are aluminum, and the third conductive layer and the sacrificial layer are formed simultaneously.

9. The method according to claim 1, characterized in that, The encapsulation method further includes: The adapter substrate is diced to obtain one or more adapter substrate assemblies.

10. The method according to claim 6, characterized in that, The encapsulation method further includes: Prior to forming the third interconnect structure, a protective layer is formed on the first side of the third dielectric layer and the site coating; and After at least a portion of the electrode is released, the protective layer is removed.

11. The method according to claim 1, characterized in that, Bonding the adapter substrate to a chip at a first side of the adapter substrate, and bonding the adapter substrate to a printed circuit board at a second side of the adapter substrate, includes: First, one of the chip and the printed circuit board is bonded to the adapter substrate using a first bonding process; and The chip and the other component of the printed circuit board are then bonded to the adapter substrate using a second bonding process. Wherein, the first bonding temperature of the first bonding process is higher than the second bonding temperature of the second bonding process.

12. The method according to claim 11, characterized in that: The first bonding temperature is greater than 260 degrees Celsius; and / or The first bonding material used in the first bonding process includes at least one of high-temperature tin-based solder and gold; and / or The second bonding temperature is in the range of 150-200 degrees Celsius; and / or The second bonding material used in the second bonding process includes low-temperature tin-based solder.

13. A brain-computer interface module, characterized in that, The brain-computer interface module includes a chip, electrodes, and a printed circuit board, wherein the chip, the electrodes, and the printed circuit board are packaged by the packaging method according to any one of claims 1 to 12.

Images