Packaging method and brain-computer interface module

Abstract

The disclosure provides a packaging method and a brain-computer interface module. The packaging method comprises: providing a wafer comprising a substrate and a chip located on a first side of the substrate; forming a sacrificial layer on the first side of the wafer, the opening of the sacrificial layer exposing the chip; forming a first dielectric layer, wherein the first via and the second via of the first dielectric layer expose the first interface site and the second interface site of the chip respectively; forming a first electrode and a second electrode, the first electrode part of the first electrode being filled in the first via and being electrically connected with the first interface site, the second electrode part and the third electrode part of the first electrode being located above the first side of the sacrificial layer, the fourth electrode part of the second electrode being filled in the second via and being electrically connected with the second interface site; removing the sacrificial layer and the part of the substrate located on the second side of the sacrificial layer to release the third electrode part, the second side being opposite to the first side; and bonding the chip with a printed circuit board, the terminal of the printed circuit board being electrically connected with the second interface site.

Description

Technical Field

[0001] This disclosure relates to the field of brain-computer interfaces, and more specifically, to an encapsulation method and a brain-computer interface module. Background Technology

[0002] In recent years, with the deep integration and rapid development of multiple disciplines such as materials science, micro-nano fabrication technology, computer science, electronic engineering, and neuroscience, brain-computer interface technology has made significant progress. Its application scenarios are constantly expanding, covering cutting-edge areas such as rehabilitation treatment of diseases like Parkinson's disease and epilepsy, assistive devices for motor dysfunction, visual and auditory restoration, enhancement of motor abilities, and even super vision enhancement, demonstrating important scientific research value and broad clinical application prospects.

[0003] Brain-computer interface (BCI) systems typically require complete implantation and are classified as Class III implantable medical devices, placing extremely high demands on device size, biocompatibility, and long-term reliability. To minimize implantation trauma, reduce immune responses, and minimize tissue damage, BCI devices must continuously evolve towards miniaturization, lightweight design, and high integration.

[0004] In this evolution, achieving high-density, compact integration of chips, electrodes (e.g., flexible electrodes), and printed circuit boards (PCBs) to accommodate limited implantation space has become a key bottleneck in current device design. However, existing packaging solutions still have shortcomings in interconnect structure, arrangement, and overall thickness control, making it difficult to meet increasingly stringent miniaturization requirements. Therefore, there is an urgent need for a solution that can achieve compact, integrated packaging of chips, electrodes, and PCBs. Summary of the Invention

[0005] One of the purposes of this disclosure is to provide a packaging method and a brain-computer interface module.

[0006] According to a first aspect of this disclosure, a packaging method is provided, the packaging method comprising: A wafer is provided, the wafer comprising a substrate and a chip located on a first side of the substrate; A patterned sacrificial layer is formed on a first side of the wafer, wherein openings in the sacrificial layer expose the chip; A patterned first dielectric layer is formed on the sacrificial layer and the first side of the chip, wherein a first via in the first dielectric layer exposes a first interface site of the chip, and a second via in the first dielectric layer exposes a second interface site of the chip; A first electrode and a second electrode are formed, wherein a first electrode portion of the first electrode fills the first through-hole and is electrically connected to the first interface site, a second electrode portion and a third electrode portion of the first electrode are located above the first side of the sacrificial layer, and a fourth electrode portion of the second electrode fills the second through-hole and is electrically connected to the second interface site. Remove the sacrificial layer and the portion of the substrate located on the second side of the sacrificial layer to release the third electrode portion of the first electrode, the third electrode portion being flexible, wherein the second side is opposite to the first side; and The chip is bonded to a printed circuit board, wherein the terminals of the printed circuit board are electrically connected to the second interface site via the second electrode.

[0007] In some embodiments, forming a patterned first dielectric layer includes: A first dielectric material is deposited on the sacrificial layer and on a first side of the chip; Chemical mechanical polishing is performed to planarize the first dielectric material; A patterned anti-etching layer is formed on a first side of the first dielectric material; The portion of the first dielectric material not covered by the etching resist layer is etched to form the first via and the second via; and Remove the remaining anti-etching layer.

[0008] In some embodiments, the first dielectric material comprises silicon dioxide.

[0009] In some embodiments, depositing a first dielectric material on the sacrificial layer and a first side of the chip includes depositing the first dielectric material by plasma-enhanced chemical vapor deposition.

[0010] In some embodiments, forming the first electrode and the second electrode includes... A patterned second dielectric layer is formed on a first side of the first dielectric layer, a third via in the second dielectric layer is aligned with the first via in the vertical direction, and a fourth via in the second dielectric layer is aligned with the second via in the vertical direction. A conductive element is formed, the conductive element comprising: The first conductive portion fills the first through hole and the third through hole and is electrically connected to the first interface site. A second conductive portion and a third conductive portion, wherein the second conductive portion is located above the first side of the second dielectric layer and electrically connected to the first conductive portion, and the third conductive portion is located above the first side of the second dielectric layer and electrically connected to the second conductive portion, and The fourth conductive portion fills the second through hole and the fourth through hole and is electrically connected to the second interface site; A patterned third dielectric layer is formed on a first side of the portion of the conductive element and the second dielectric layer not covered by the conductive element. A fifth via in the third dielectric layer exposes at least a portion of the third conductive portion, and a sixth via in the third dielectric layer exposes the fourth conductive portion. A site coating is formed, which fills the fifth and sixth through holes.

[0011] In some embodiments, forming a conductive element includes: A first conductive material is deposited on the second dielectric layer, the first interface site, and the first side of the second interface site; A patterned mask layer is formed on a first side of the first conductive material; A second conductive material is electroplated or chemically plated on the first side of the portion of the first conductive material not covered by the mask layer to form the conductive element; Remove the mask layer; and Etch the exposed portion of the first conductive material.

[0012] In some embodiments, the second dielectric material forming the second dielectric layer includes polyimide.

[0013] In some embodiments, the third dielectric material forming the third dielectric layer includes polyimide.

[0014] In some embodiments, the first conductive material includes at least one of titanium / gold and chromium / gold.

[0015] In some embodiments, the second conductive material comprises gold.

[0016] In some embodiments, the coating material forming the site coating includes at least one of gold, platinum, iridium oxide, and a conductive polymer.

[0017] In some embodiments, removing the sacrificial layer and the portion of the substrate located on the second side of the sacrificial layer includes: A protective layer is formed on the first side of the third dielectric layer and the site coating; The wafer is diced to obtain one or more chip components; and For at least one chip component, Remove the sacrificial layer from the chip assembly to release the third electrode portion. Cut and remove the portion of the substrate located on the second side of the sacrificial layer in the chip assembly, and Remove the protective layer from the chip assembly.

[0018] In some embodiments, removing the sacrificial layer and the portion of the substrate located on the second side of the sacrificial layer further includes: Before removing the sacrificial layer in the chip assembly, the substrate is thinned on a second side of the substrate.

[0019] In some embodiments, bonding the chip to a printed circuit board includes: Solder balls are formed on the second electrode and the terminal; Flip the chip so that the first side of the chip faces the printed circuit board and align the second electrode with the terminal; The second electrode is bonded to the terminal via the solder ball; and A filler layer is formed between the chip and the printed circuit board.

[0020] In some embodiments, the chip is manufactured directly on the substrate.

[0021] In some embodiments, a groove is formed on a first side of the substrate, and the chip is embedded and fixed in the groove.

[0022] In some embodiments, the wafer is formed by the following steps: The substrate is thinned on a second side of the substrate; A groove is made on the first side of the substrate; The chip is bonded to the carrier substrate; The chip is placed in the groove and glue is applied around the chip and inside the groove; The substrate, the chip, and the carrier substrate are evacuated. Curing the adhesive; and The bonding between the chip and the carrier substrate is released, and the carrier substrate is removed.

[0023] In some embodiments, the wafer is further formed by the following steps: After thinning the substrate, a stress-buffering material is deposited on the second side of the substrate to form a stress-buffering layer.

[0024] In some embodiments, the stress-relief material includes at least one of silicon dioxide and silicon nitride.

[0025] In some embodiments, the adhesive comprises polyimide.

[0026] In some embodiments, the packaging method further includes forming a redistribution layer, and the redistribution layer being formed simultaneously with the conductive element.

[0027] According to a second aspect of this disclosure, a brain-computer interface module is provided, the brain-computer interface module including a chip, electrodes and a printed circuit board, wherein the chip, the electrodes and the printed circuit board are packaged by the packaging method according to any embodiment of the first aspect of this disclosure.

[0028] Other features and advantages of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0029] The foregoing and other features and advantages of this disclosure will become clear from the following description of embodiments illustrated in conjunction with the accompanying drawings. The drawings, incorporated herein and forming a part of the specification, are further used to explain the principles of this disclosure and to enable those skilled in the art to make and use it. Wherein: Figure 1 A schematic flowchart of an encapsulation method according to an exemplary embodiment of the present disclosure is shown; Figure 2 A schematic diagram of the structure of a brain-computer interface module according to an exemplary embodiment of the present disclosure is shown; Figures 3 to 16 A schematic diagram of a packaging process according to an exemplary embodiment of the present disclosure is shown.

[0030] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0031] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0032] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0033] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. Those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and are not exhaustive.

[0034] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0035] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0036] Currently, the back-end assembly methods between chips, electrodes, and printed circuit boards in the field of brain-computer interfaces are still immature, and the package size is generally too large. One approach is to use discrete device back-end assembly processes such as flying wire bonding. However, this type of process has revealed several significant shortcomings in application. First, in terms of space occupation, the bonding area, interconnect leads, and auxiliary structures occupy additional space, making it difficult to meet the stringent requirements of ultra-small size for fully implantable devices. Second, regarding electrical connection quality, the alignment accuracy and contact reliability of flying wire bonding under micro-pitch conditions are limited, especially in multi-channel, high-throughput scenarios, where bonding points are prone to problems such as cold solder joints, open circuits, or high impedance, leading to a decrease in overall conductivity. Furthermore, in terms of manufacturing feasibility, the back-end assembly process for discrete devices is lengthy, with prominent interface matching and thermal mismatch issues, high process complexity, and limited yield, which is not conducive to achieving large-scale, high-consistency mass production.

[0037] To address at least one of the aforementioned problems, this disclosure provides a packaging method that, from a system-level integration perspective, integrates the chip and electrodes into a single unit and then directly bonds this integrated structure to a printed circuit board, thereby achieving high-density, high-reliability interconnection between the chip, electrodes, and the printed circuit board.

[0038] The packaging methods according to various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It will be understood that actual methods may include other steps, which are not shown in the drawings and will not be discussed herein in order to avoid obscuring the key points of the present disclosure.

[0039] In one exemplary embodiment of this disclosure, such as Figure 1 and Figures 3 to 16 As shown, the encapsulation method may include: In step S110, a wafer 310 is provided, which includes a substrate 3110 and a chip 3120 located on a first side of the substrate 3110. For example, the wafer may be a silicon wafer, and the substrate may be a silicon substrate. In other embodiments, the substrate may also be a glass substrate, a ceramic substrate, etc.

[0040] In some embodiments, such as Figure 3 As shown, a groove 3111 is formed on the first side of the substrate 3110, and the chip 3120 is embedded and fixed in the groove 3111. Specifically, the wafer is formed by the following steps: thinning the substrate on the second side; creating a groove on the first side of the substrate; bonding the chip to a carrier substrate; placing the chip in the groove and applying adhesive around the chip and inside the groove; evacuating the substrate, chip, and carrier substrate; curing the adhesive; and releasing the bond between the chip and the carrier substrate, and removing the carrier substrate.

[0041] The substrate 3110 is thinned on its second side. In this disclosure, the "first side" refers to... Figures 3-15 The upper side of the middle and Figure 16 The lower side; the "second side" is the side opposite to the first side, that is... Figures 3-15 The lower side of the middle and Figure 16 The upper side of the substrate. For example, mechanical grinding combined with chemical mechanical polishing (CMP) can be used to reduce the wafer thickness from an initial approximately 725 μm to a target thickness of 50-200 μm to reduce the overall size of the package structure. In some embodiments, stress-relieving etching can be performed on the second side of the substrate 3110 after thinning. Exemplarily, TMAH wet etching or SF6 / O2 plasma dry etching can be used to remove the damage layer introduced on the substrate surface during the thinning process, restoring the flatness and structural integrity of the substrate surface.

[0042] In some embodiments, after thinning the substrate 3110, a stress-reducing material can be deposited on a second side of the substrate 3110 to form a stress-reducing layer (not shown in the figure). For example, the stress-reducing material includes at least one of silicon dioxide (SiO2) and silicon nitride (Si3N4). The stress-reducing layer can also serve as an insulating layer to mitigate stress within the substrate and provide electrical isolation.

[0043] A groove 3111 is made on the first side of the substrate 3110. For example... Figure 3As shown, the slotted area can be defined by photolithography to accommodate the chip 3120 according to the design. For example, deep reactive ion etching (DRIE) or laser dicing can be used to form through-hole or non-through-hole / cavity structures on the wafer. The size of the slot 3111 can be determined based on the size of the chip 3120 or design requirements; for example, the depth of the slot 3111 can be 50–150 μm. The purposes of slotting include: alignment during subsequent chip fixing, cavity formation, or channel release.

[0044] The chip 3120 is bonded to the carrier substrate (not shown in the figure). The chip 3120 can be temporarily fixed on the carrier substrate to keep the chip 3120 in a stable position during subsequent adhesive coating and vacuum processing, and to prevent the chip from shifting, floating or tilting due to adhesive flow or vacuum suction.

[0045] Chip 3120 is placed in groove 3111 and adhesive is applied around chip 3120 and inside groove 3111. For example, adhesive may include polyimide (PI) due to its low viscosity (e.g., 5~50 cP) so that it can flow sufficiently during subsequent vacuum processing to fill the micro gaps between the chip and the groove wall and the various corners of the bottom of the groove.

[0046] The substrate 3110, chip 3120, and carrier substrate are evacuated. For example, these three components can be placed together in a vacuum chamber, evacuated to a predetermined pressure (e.g., ≤10 Pa), and maintained for a predetermined time (e.g., 5-15 minutes) to remove air bubbles from the cavities and allow the adhesive to further penetrate and completely fill all microcavities and gaps under negative pressure, thereby improving the density and bonding strength of the adhesive layer after subsequent curing.

[0047] Curing adhesive. The entire assembly can be placed in a heating device for segmented curing. For example, for polyimide adhesive, it can first be kept at 80°C for 30 minutes, then heated to 150°C and kept at 150°C for 30 minutes, and finally kept at 250°C for 1 hour to fully imidize the polyimide adhesive and form a stable mechanical fixing and insulating layer.

[0048] The bond between the chip and the carrier substrate is released, and the carrier substrate is removed. This temporary bond can be achieved using reversible bonding methods such as heat-release tape, UV-dissolving tape, or low-melting-point wax. After curing and subsequent processes, the carrier substrate can be removed by heating, UV irradiation, or solvent dissolution.

[0049] Ultimately, we can obtain the following: Figure 4The chip 310 is shown. In some embodiments, the surface of the chip 3120 is substantially flush with or slightly lower than the first side surface of the substrate 3110, providing a flat base surface for subsequent electrode fabrication and interconnect wiring on the first side of the substrate without increasing the overall height of the package structure.

[0050] For chips that have already been cut out, the above-mentioned embedding and fixing method can make them compatible with subsequent wafer-level processes, improving the compatibility and process flexibility of the packaging solution with different chip sources.

[0051] In other embodiments, chip 3120 is manufactured directly on substrate 3110. The wafer used to manufacture the chip itself serves as the wafer in the subsequent packaging steps, avoiding the cutting, transport, and realignment steps associated with transferring the chip between different carriers, which helps to simplify the process flow and shorten the production cycle.

[0052] Back Figure 1 In step S120, a patterned sacrificial layer 320 is formed on a first side of the wafer 310. The openings in the sacrificial layer 320 expose the chip 3120. Figure 5 In the illustrated embodiment, the opening region of the sacrificial layer 320 allows the chip 3120 to be exposed (i.e., the upper surface of the chip 3120 is not completely covered by the sacrificial layer). In other embodiments, the edge of the sacrificial layer 320 may overlap the edge region of the chip 3120, as long as it does not cover the interface pads on the chip 3120.

[0053] The fabrication process of the sacrificial layer 320 includes, for example, depositing a sacrificial material with a set thickness (e.g., 200 nm–2 μm) by electron beam evaporation or magnetron sputtering. The sacrificial material can be aluminum (Al). A positive photoresist is then coated, and a sacrificial layer pattern (i.e., covering the areas to be exposed in the future) is formed by photolithography. Next, an etching process matching the sacrificial material is used to remove the exposed excess sacrificial material. For example, when the sacrificial material is aluminum, wet etching can be used with an etching solution of phosphoric acid, nitric acid, acetic acid, and water (volume ratio approximately 16:1:1:2) at an etching temperature of approximately 50°C; or Cl2 / BCl3-based dry plasma etching can be used. Through the above etching process, the aluminum layer in the areas not covered by the photoresist is completely removed, and then the remaining photoresist is removed, resulting in a patterned aluminum sacrificial layer 320 on the first side of the wafer 310.

[0054] In step S130, a patterned first dielectric layer 330 is formed on the sacrificial layer 320 and the first side of the chip 3120. A first via 331 in the first dielectric layer 330 exposes a first interface site 3121 of the chip 3120, and a second via 332 in the first dielectric layer 330 exposes a second interface site 3122 of the chip 3120. Specifically, forming the patterned first dielectric layer includes: depositing a first dielectric material on the sacrificial layer and the first side of the chip; performing chemical mechanical polishing to planarize the first dielectric material; forming a patterned resist layer on the first side of the first dielectric material; etching the portion of the first dielectric material not covered by the resist layer to form the first via and the second via; and removing the remaining resist layer.

[0055] A first dielectric material is deposited on the sacrificial layer 320 and the first side of the chip 3120. This deposition is a full-surface deposition, with the first dielectric material covering all exposed surfaces during the deposition process. In some embodiments, the first dielectric material may include silicon dioxide. In some embodiments, the first dielectric material can be deposited using plasma-enhanced chemical vapor deposition (PECVD). PECVD technology enables the fabrication of dense, stress-controlled silicon dioxide films at low temperatures (≤200°C), which not only facilitates strong adhesion to the wafer carrier but also provides thermal stability for subsequent high-temperature processes.

[0056] Chemical mechanical polishing is performed to planarize the first dielectric material. Global planarization grinding is then performed on the surface to eliminate microscopic morphological differences, providing an atomically flat substrate for subsequent high-precision photolithography and electrode patterning, which helps ensure the yield of electrodes in wafer-level manufacturing.

[0057] A patterned resist layer (not shown) is formed on a first side of the first dielectric material. For example, photoresist can be coated on the surface of the first dielectric material by photolithography, and after exposure and development, a pattern of the resist layer is formed in the area where the first dielectric material needs to be retained, so as to define the position and opening size of subsequent vias.

[0058] The portion of the first dielectric material not covered by the resist layer is etched to form a first via 331 and a second via 332. Specifically, a plasma etching process can be used for etching until the underlying chip interface sites are exposed. In this disclosure, the first via exposes the first interface site of the chip, which can serve as an analog signal port for subsequent interconnection with electrodes (especially flexible electrodes); the second via exposes the second interface site of the chip, which can serve as a digital signal port for subsequent interconnection with a printed circuit board. It should be understood that this disclosure does not limit the number of vias, but rather, more vias can be formed according to the actual number and layout of interface sites on the chip to expose the corresponding interface sites respectively.

[0059] Remove the remaining resist layer. For example, organic solvent stripping or oxygen plasma ashing can be used to completely remove the resist layer remaining on the surface of the first dielectric material after etching, exposing the complete surface of the first dielectric material and the via opening area below.

[0060] Ultimately, we can obtain the following: Figure 6 The first dielectric layer 330 is shown.

[0061] The first dielectric layer provides electrical isolation to the chip surface, preventing short circuits and signal crosstalk between interconnect traces. It also provides a flat process substrate for subsequent electrode wiring, improving process yield. Furthermore, as a dense thin-film structure, the first dielectric layer achieves good adhesion to the substrate surface and possesses sufficient thermal stability to withstand the temperatures of subsequent processes.

[0062] Back Figure 1 In step S140, a first electrode and a second electrode are formed. The first electrode portion of the first electrode fills the first through-hole 331 and is electrically connected to the first interface site 3121. The second and third electrode portions of the first electrode are located above the first side of the sacrificial layer 320. The fourth electrode portion of the second electrode fills the second through-hole 332 and is electrically connected to the second interface site 3122. Specifically, forming the first and second electrodes includes: forming a patterned second dielectric layer on the first side of the first dielectric layer; forming a conductive element; forming a patterned third dielectric layer on the first side of the conductive element and the portion of the second dielectric layer not covered by the conductive element; and forming a site coating.

[0063] A patterned second dielectric layer 340 is formed on a first side of the first dielectric layer 330. A third via 341 in the second dielectric layer 340 is aligned vertically with the first via 331, and a fourth via 342 in the second dielectric layer 340 is aligned vertically with the second via 332. "Vertical direction" refers to the direction perpendicular to the first side surface of the wafer 310. It should be understood that "alignment" does not require the center points of the upper and lower vias to completely coincide, but rather that, within the alignment accuracy allowed by the process, the opening areas of the upper and lower vias at least partially overlap to ensure the subsequent through-filling and electrical connection of conductive material. In other words, the third via 341 allows the first interface site 3121 to remain exposed, and the fourth via 342 allows the second interface site 3122 to remain exposed. In some embodiments, the second dielectric material forming the second dielectric layer includes polyimide. For example, a polyimide of a predetermined thickness (e.g., 5-15 μm or 5-20 μm) can be spin-coated onto the surface of the first dielectric layer 330 and then thermally cured (e.g., segmented curing as described above). Then, positive photoresist is coated onto the cured polyimide surface, and the window area is defined through the exposure and development steps of the photolithography process. Subsequently, using the patterned photoresist as a mask, oxygen plasma reactive ion etching (etching parameters include, for example, O2 flow rate of 50-200 sccm and power of 100-300 W) is employed to etch the polyimide until the underlying chip interface sites are exposed. After etching, any remaining photoresist is removed. The final result is as follows... Figure 7 The second dielectric layer 340 is shown.

[0064] A conductive element 350 is formed. The conductive element 350 includes: a first conductive portion 351, filling the first through-hole 331 and the third through-hole 341 and electrically connected to the first interface point 3121; a second conductive portion 352 and a third conductive portion 353, the second conductive portion 352 being located above the first side of the second dielectric layer 340 and electrically connected to the first conductive portion 351, and the third conductive portion 353 being located above the first side of the second dielectric layer 340 and electrically connected to the second conductive portion 352; and a fourth conductive portion 354, filling the second through-hole 332 and the fourth through-hole 342 and electrically connected to the second interface point 3122. Specifically, forming the conductive element 350 includes: A first conductive material is deposited on the first side of the second dielectric layer 340, the first interface site 3121, and the second interface site 3122. In some embodiments, the first conductive material includes at least one of titanium / gold (Ti / Au) and chromium / gold (Cr / Au). For example, the first conductive material can be deposited by sputtering or evaporation to form a seed layer. The seed layer may include an adhesion layer and a conductive layer. The adhesion layer may be made of titanium (e.g., 20 nm thick) or chromium (e.g., 10 nm thick) to enhance the adhesion between the conductive layer and the underlying dielectric layer. The conductive layer is made of gold and has a thickness of 100 nm, serving as a conductive substrate for subsequent electroplating.

[0065] The formation of conductive element 350 also includes forming a patterned mask layer (not shown) on a first side of the first conductive material. For example, photoresist can be coated on the surface of the first conductive material, and a wiring pattern can be formed on the photoresist by exposure and development steps in a photolithography process. The wiring pattern defines the shape of the electrode.

[0066] The formation of the conductive element 350 further includes electroplating or chemically plating a second conductive material on the first side of the portion of the first conductive material not covered by the mask layer to form the conductive element. In some embodiments, the second conductive material may include gold. For example, gold may be deposited in the exposed area of ​​the first conductive material (i.e., the aforementioned seed layer) by electroplating to thicken to a desired thickness (e.g., 0.5~3 μm) to form a conductive element with good conductivity and mechanical strength.

[0067] Forming the conductive component 350 also includes removing the mask layer. The process for removing the mask layer is similar to the aforementioned process for removing the resist layer, and will not be elaborated further.

[0068] Forming the conductive element 350 also includes etching the exposed portion of the first conductive material. For example, the conductive element can be used as a mask to sequentially etch the exposed first conductive material using a gold etching solution (e.g., a mixed solution of iodine and potassium iodide) and a titanium etching solution (e.g., dilute hydrofluoric acid) or a chromium etching solution, removing the seed layer portion not protected by the conductive element, and forming a patterned metal wiring that serves as a signal transmission channel.

[0069] Ultimately, we can obtain the following: Figure 8 The conductive element 350 is shown. It should be noted that, for ease of description, the conductive structure is referred to as a "conductive portion" in this disclosure, while an "electrode portion" is understood as the entirety comprising the conductive structure and its associated dielectric structure (e.g., a dielectric layer located above, below, or around the conductive structure). For example, a first electrode portion corresponds to a first conductive portion, and the first electrode portion includes the first conductive portion and the dielectric structure associated with the first conductive portion. Specifically, as shown... Figure 8In the illustrated embodiment, the first electrode includes a first conductive portion 351, a second conductive portion 352, and a third conductive portion 353, and the second electrode includes a fourth conductive portion 354. Furthermore, the distinction between "conductive portion" and "electrode portion" is merely for the purpose of describing the technical solution of this disclosure. In actual manufacturing, each conductive portion and electrode portion can be manufactured simultaneously, and there may not be a clear structural boundary between them.

[0070] By combining a seed layer with electroplating for thickening, a thin seed layer can achieve uniform coverage and reliable contact with chip interface sites, while electroplating thickens the layer to reduce interconnect resistance and improve signal transmission performance. Compared to methods that rely solely on evaporation or sputtering to deposit thick metals, electroplating thickening offers higher material utilization for the same thickness and a faster deposition rate, which helps reduce manufacturing costs. Furthermore, the electroplating process can be performed near room temperature, reducing thermal damage to the chip and organic dielectric layer caused by high-temperature processes.

[0071] In some embodiments, the packaging method may further include forming a redistribution layer 360, and the redistribution layer 360 being formed simultaneously with the conductive element 350. The redistribution layer is used to redistribute the interface sites of the chip to predetermined geometric locations to accommodate subsequent connections with peripheral circuits (e.g., printed circuit boards), such as... Figure 8 As shown. For example, a dielectric material (e.g., polyimide) can be coated on the first side of the formed conductive element 350 as a dielectric layer; metal interconnects are formed on this dielectric layer to redistribute the interface sites (especially digital interface sites) of the chip 3120 according to a preset layout; another dielectric material (e.g., polyimide) is then coated above the metal interconnects, and the corresponding connection ports are exposed through selective apertures to achieve electrical lead-out. In this way, the original tightly arranged I / O ports of the chip are redistributed to geometric positions more suitable for external interconnection, thereby reducing the bonding difficulty between the high-density chip and the peripheral electrodes or printed circuit board, and improving the flexibility and manufacturability of the packaging process. In some embodiments, the redistribution layer 360 can be formed simultaneously with the aforementioned conductive element 350 in the same process, that is, the metal layer deposition and patterning steps of both share the same set of process sequences, without the need for additional independent photolithography and deposition processes, which helps to simplify process steps, shorten production cycle and reduce costs.

[0072] Returning to the process of forming the first and second electrodes, a patterned third dielectric layer 370 is formed on the first side of the portion of the conductive element 350 and the second dielectric layer 340 not covered by the conductive element. A fifth via 371 in the third dielectric layer exposes at least a portion of the third conductive portion 353, and a sixth via 372 in the third dielectric layer exposes the fourth conductive portion 354. In some embodiments, the third dielectric material forming the third dielectric layer may include polyimide. Specifically, a polyimide of a predetermined thickness (e.g., 5-20 μm) can be coated on the exposed surfaces of the conductive element 350 and the second dielectric layer 340 and then thermally cured. Photoresist is coated onto the cured polyimide surface, and a window pattern is formed using a photolithography process. This pattern defines the location and size of the conductive areas to be exposed. Subsequently, using the patterned photoresist as a mask, the polyimide is etched using an oxygen plasma etching process to form the fifth via 371 and the sixth via 372. After etching, any remaining photoresist is removed. In some embodiments, if the encapsulation method further includes forming a redistribution layer, then the area exposed in this step may be a defined area of ​​the redistribution layer 360. For example, in... Figure 9 In the embodiment shown, the redistribution layer 360 is electrically connected to the fourth conductive portion 354, so the sixth via 372 exposes the corresponding area of ​​the redistribution layer 360, rather than the fourth conductive portion 354 itself.

[0073] A site coating 380 is formed, which fills the fifth through-hole 371 and the sixth through-hole 372. For example... Figure 10 As shown, the site coating 380 may include a first site coating portion 381 and a second site coating portion 382, ​​wherein the first site coating portion 381 fills the fifth via 371 and is electrically connected to the third conductive portion 353. This first site coating portion 381 serves as the acquisition / stimulation site for the first electrode, allowing direct contact with brain tissue after implantation to acquire neural signals or apply electrical stimulation signals. The second site coating portion 382 fills the sixth via 372 and is electrically connected to the fourth conductive portion 354 (via the redistribution layer 360), forming a connection point with the printed circuit board. The material of the site coating 380 can be selected according to actual functional requirements, such as at least one of gold (for improved solderability), platinum (for electrochemical sensing), iridium oxide, or conductive polymers (such as PEDOT:PSS, for reduced impedance). The site coating 380 can be deposited by electroplating (current density of 0.5-2 A / dm²), electroless plating (e.g., cyanide-free gold plating solution), or mask sputtering, with a deposition thickness of 50 nm-5 μm.

[0074] It should be understood that this disclosure uses the first point coating portion and the second point coating portion as examples for illustration. These represent one type of point coating for neural acquisition / stimulation and another type for printed circuit board connections, respectively, and do not limit the total number of point coating portions. In practical applications, multiple acquisition / stimulation sites can be provided on the first electrode (e.g., a flexible electrode) as needed, and correspondingly, the number of first point coating portions can also be multiple. Similarly, the number of second point coating portions can also be set according to the actual number and layout of the chip's second interface sites (e.g., digital interface sites).

[0075] Ultimately, we can obtain the following: Figure 10 The first electrode and the second electrode are shown. The first electrode, as the neural interface portion of a flexible electrode, includes a first site coating portion 381 in contact with brain tissue, a third conductive portion 353, a second conductive portion 352, and a first conductive portion 351 electrically connected to a first interface site 3121 on the chip, forming a pathway for neural signal acquisition or electrical stimulation signal application from the brain tissue to the chip. The first electrode can be partially released in a subsequent step to become flexible and bendable for implantation into a target area of ​​brain tissue. The second electrode includes a second site coating portion 382 and a fourth conductive portion 354 electrically connected to a second interface site 3122 on the chip (and, in embodiments where a redistribution layer 360 is present), forming a signal transmission pathway from the chip to the printed circuit board for data interaction with external circuitry. The second electrode extends vertically, extending the electrical connection of the second interface site 3122 to the top surface of the package structure (i.e., the surface of the first side of the third dielectric layer 370) to facilitate subsequent encapsulation with the printed circuit board.

[0076] Back Figure 1 In step S150, the sacrificial layer 320 and the portion 3112 of the substrate located on the second side of the sacrificial layer are removed to release the third electrode portion of the first electrode, the third electrode portion being flexible. Specifically, removing the sacrificial layer and the portion of the substrate located on the second side of the sacrificial layer includes: forming a protective layer on the first side of the third dielectric layer and the site coating; dicing the wafer to obtain one or more chip assemblies; and for at least one chip assembly, removing the sacrificial layer in the chip assembly to release the third electrode portion, cutting and removing the portion of the substrate located on the second side of the sacrificial layer in the chip assembly, and removing the protective layer in the chip assembly.

[0077] A protective layer 390 is formed on the first side of the third dielectric layer 370 and the site coating 380. For example... Figure 11As shown. The protective layer 390 is used to protect the completed device structure from etchant corrosion or dust contamination during subsequent release of the sacrificial layer and dicing. Specifically, a photoresist (e.g., a positive photoresist, such as AZ4620) of a predetermined thickness (e.g., 2-10 μm) can be spin-coated onto the surfaces of the third dielectric layer 370 and the site coating 380. The photoresist is selectively retained in the device areas requiring protection, including electrode areas, via areas, and site coating areas, by a photolithography process, exposing the area where the sacrificial layer 320 is located for subsequent release. A post-bake treatment (e.g., baking at 110°C for 60 seconds) is then performed to enhance the etching resistance of the protective layer 390.

[0078] In some embodiments, prior to forming the protective layer, the third dielectric layer 370, the second dielectric layer 340, and the first dielectric layer 330 may be etched to form a release trench (not shown). This release trench extends through each of the dielectric layers along the trace outline of the first electrode, spatially separating the dielectric layer to which the first electrode trace area is attached from the surrounding dielectric layers. Thus, after the sacrificial layer 320 is subsequently removed, the first electrode can be separated from the surrounding dielectric structure as an independent flexible strip, allowing it to be bent, extended, and implanted into the target brain tissue region.

[0079] Dicing a wafer yields one or more chip assemblies. Dicing separates a completed front-end wafer into individual chip units. Dicing methods can include mechanical cutting with diamond blades or laser cutting. After dicing, each chip assembly includes a chip and electrodes connected to it.

[0080] In some embodiments, before removing the sacrificial layer 320 in the chip assembly, the substrate 3110 can be thinned on the second side of the substrate. Specifically, the chip assembly can be flipped so that the second side of the substrate 3110 faces upwards, and thinning can be performed using mechanical grinding combined with chemical mechanical polishing to reduce the remaining thickness of the substrate 3110 to a set thickness (e.g., 20-50 μm). After thinning, the exposed surface can optionally be plasma cleaned (e.g., using oxygen or argon plasma) to remove contaminants. In some embodiments, this thinning step can be performed on the entire wafer before dicing to further improve process efficiency. Figure 12 The thinned substrate shown facilitates faster penetration of the etchant to the sacrificial layer location during subsequent release of the sacrificial layer, and also contributes to the miniaturization of the packaging structure.

[0081] For at least one chip assembly: the sacrificial layer 320 in the chip assembly is removed to release the third electrode portion. Specifically, the chip assembly is immersed in a sacrificial layer etching solution (e.g., when the sacrificial layer material is aluminum, the etching solution can be a 5% TMAH aqueous solution at 50°C, or a mixture of hydrochloric acid and copper sulfate) for etching. The etching time depends on the thickness of the sacrificial layer; for example, for an aluminum sacrificial layer with a thickness of 1 μm, the etching time is approximately 5-10 minutes. After the sacrificial layer 320 is removed, the portion of the first electrode located directly above the first side of the sacrificial layer 320 (i.e., the third electrode portion including the third conductive portion 353) separates from the substrate 3110, forming a flexible, bendable structure, such as... Figure 13 As shown. The second electrode portion, including the second conductive portion 352, is not grown on the sacrificial layer and maintains a relatively fixed positional relationship with the substrate 3110, and will not be released into a free and flexible state.

[0082] For at least one chip assembly: 3112. The portion 3112 of the substrate located on the second side of the sacrificial layer in the chip assembly is cut and removed. It should be understood that "the portion located on the second side of the sacrificial layer" refers to a region in the substrate corresponding to the sacrificial layer in the vertical direction. The horizontal extent of this region may be approximately the same as, or slightly larger than, or slightly smaller than, the coverage area of ​​the sacrificial layer. In some embodiments, this portion may be the portion located directly below the second side of the sacrificial layer. Specifically, laser cutting or diamond scribing can be used to remove this portion of the substrate material along a pre-defined cutting path, thereby providing sufficient space for the suspended portion of the first electrode to move, such as... Figure 14 As shown. During cutting, the device area can be kept moist or covered with a protective film to prevent debris contamination.

[0083] For at least one chip assembly: Remove the protective layer from the chip assembly. Specifically, immerse the chip assembly in a resist remover, such as N-methylpyrrolidone (NMP), at 60°C, and then sonicate for 10-30 minutes to remove the protective layer 390 covering the device area. Subsequently, rinse sequentially with acetone, isopropanol, and deionized water, then dry with nitrogen gas, and finally dry in an oven at 120°C for 15 minutes to remove residual solvent, obtaining a complete chip-electrode integrated device, such as... Figure 15 As shown.

[0084] The above method allows for the direct integration of implantable brain tissue flexible electrodes onto the chip, eliminating the chip-electrode bonding interface. The entire packaging process can be completed at the wafer level, which simplifies the process flow, improves manufacturing efficiency and consistency, and significantly reduces the final device's package size, thereby better meeting the stringent miniaturization requirements of fully implantable brain-computer interface modules.

[0085] Back Figure 1 In step S160, the chip 3120 is bonded to the printed circuit board 400. The terminals of the printed circuit board 400 are electrically connected to the second interface site 3122 via a second electrode. Specifically, bonding the chip to the printed circuit board includes: forming solder balls on the second electrode and terminals; flipping the chip so that the first side of the chip faces the printed circuit board and aligning the second electrode with the terminals; bonding the second electrode to the terminals via solder balls; and forming a filler layer between the chip and the printed circuit board.

[0086] Solder balls are formed on the second electrode and the terminal. Specifically, a solder ball implantation machine can be used to implant solder balls on the exposed area of ​​the second electrode and the corresponding terminal of the printed circuit board 400. The material of the solder balls can be tin or gold, and the diameter of the solder balls is determined according to the pad spacing, for example, 30-80μm.

[0087] Flip the chip so that its first side faces the printed circuit board and align the second electrode with the terminal.

[0088] The second electrode is bonded to the terminal using solder balls. For example... Figure 16 As shown. Specifically, a flip-chip bonding process can be used, where the solder balls are melted or deformed under pressure through reflow soldering or thermocompression bonding, so that the second electrode forms an electrical and mechanical connection with the terminals of the printed circuit board 400. The peak temperature of reflow soldering can be 200-260°C; the pressure of thermocompression bonding can be adjusted according to the number of solder pads.

[0089] A filler layer is formed between the chip and the printed circuit board. Optionally, after bonding is completed, a filler material (such as epoxy resin) can be injected into the gap between the chip 3120 and the printed circuit board 400 and heated to cure, thereby forming a filler layer and enhancing the mechanical reliability of the bonding interface.

[0090] The above method allows for electrical connection and mechanical fixation of the chip and printed circuit board via flip-chip bonding. Flip-chip bonding occupies a small area, and the chip and printed circuit board are stacked vertically, which helps to further reduce the planar size of the entire package structure, meeting the miniaturization requirements of brain-computer interface devices.

[0091] According to another aspect of this disclosure, a brain-computer interface module is also provided. For example... Figure 2 As shown, the brain-computer interface module may include a chip 210, electrodes 220, and a printed circuit board 230. It is understood that the brain-computer interface module may also include other components (not shown) to achieve the desired electrical functions. Furthermore, the chip, electrodes, and printed circuit board in the brain-computer interface module of this disclosure can be packaged using the packaging method described above.

[0092] In this disclosed technical solution, the chip and flexible electrode (i.e., the first electrode) are integrated at the wafer level, eliminating the intermediate step of separate chip and electrode manufacturing followed by post-assembly in traditional solutions. This facilitates smaller device size, simplifies the process flow, and improves manufacturing consistency. Furthermore, the chip-electrode integrated structure is interconnected with the printed circuit board via flip-chip bonding, eliminating the need for wire bonding or intermediate connectors. This shortens the signal transmission path, reduces parasitic inductance and resistance, and improves the quality of high-frequency signal transmission. Simultaneously, the vertically stacked structure helps compress the package planar size. The above technical solution is applicable to high-throughput fully implantable brain-computer interface systems and can meet the comprehensive requirements of miniaturization, high-density interconnection, and long-term reliability.

[0093] In the specification and claims, when an element is described as being "on top of," "attached to," "connected to," "coupled to," or "in contact with" another element, the element may be directly located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. Conversely, when an element is described as being "directly" located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with another element, no intermediate elements are present. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that a feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0094] As used herein, the term “exemplary” means “serving as an example, instance, or illustration” and not as a “model” to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, this disclosure is not limited to any theory expressed or implied as given in the field of art, background art, summary of invention, or detailed description.

[0095] As used herein, the term "substantially" means any minor variation resulting from design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0096] Furthermore, terms such as “first,” “second,” etc., may be used in this document for reference purposes only and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence.

[0097] It should also be understood that when the term “including / contains” is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0098] In this disclosure, the term “provide” is used broadly to cover all ways of obtaining an object, and therefore “provide an object” includes, but is not limited to, “purchasing,” “preparing / manufacturing,” “arranging / setting up,” “installing / assembling,” and / or “ordering” an object.

[0099] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0100] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Aspects and elements of all the embodiments disclosed above may be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0101] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A packaging method, characterized in that, The encapsulation method includes: A wafer is provided, the wafer comprising a substrate and a chip located on a first side of the substrate; A patterned sacrificial layer is formed on a first side of the wafer, wherein openings in the sacrificial layer expose the chip; A patterned first dielectric layer is formed on the sacrificial layer and the first side of the chip, wherein a first via in the first dielectric layer exposes a first interface site of the chip, and a second via in the first dielectric layer exposes a second interface site of the chip; A first electrode and a second electrode are formed, wherein a first electrode portion of the first electrode fills the first through-hole and is electrically connected to the first interface site, a second electrode portion and a third electrode portion of the first electrode are located above the first side of the sacrificial layer, and a fourth electrode portion of the second electrode fills the second through-hole and is electrically connected to the second interface site. Remove the sacrificial layer and the portion of the substrate located on the second side of the sacrificial layer to release the third electrode portion of the first electrode, the third electrode portion being flexible, wherein the second side is opposite to the first side; and The chip is bonded to a printed circuit board, wherein the terminals of the printed circuit board are electrically connected to the second interface site via the second electrode.

2. The packaging method according to claim 1, characterized in that, The first dielectric layer forming the pattern includes: A first dielectric material is deposited on the sacrificial layer and on a first side of the chip; Chemical mechanical polishing is performed to planarize the first dielectric material; A patterned anti-etching layer is formed on a first side of the first dielectric material; The portion of the first dielectric material not covered by the etching resist layer is etched to form the first via and the second via; and Remove the remaining anti-etching layer.

3. The packaging method according to claim 2, characterized in that, The first dielectric material includes silicon dioxide, and / or Depositing a first dielectric material on the sacrificial layer and the first side of the chip includes: depositing the first dielectric material by plasma-enhanced chemical vapor deposition.

4. The packaging method according to claim 1, characterized in that, Forming the first electrode and the second electrode includes, A patterned second dielectric layer is formed on a first side of the first dielectric layer, a third via in the second dielectric layer is aligned with the first via in the vertical direction, and a fourth via in the second dielectric layer is aligned with the second via in the vertical direction. A conductive element is formed, the conductive element comprising: The first conductive portion fills the first through hole and the third through hole and is electrically connected to the first interface site. A second conductive portion and a third conductive portion, wherein the second conductive portion is located above the first side of the second dielectric layer and electrically connected to the first conductive portion, and the third conductive portion is located above the first side of the second dielectric layer and electrically connected to the second conductive portion, and The fourth conductive portion fills the second through hole and the fourth through hole and is electrically connected to the second interface site; A patterned third dielectric layer is formed on the first side of the portion of the conductive element and the second dielectric layer not covered by the conductive element, wherein a fifth via in the third dielectric layer exposes at least a portion of the third conductive portion, and a sixth via in the third dielectric layer exposes the fourth conductive portion. as well as A site coating is formed, which fills the fifth and sixth through holes.

5. The packaging method according to claim 4, characterized in that, Forming a conductive element includes: A first conductive material is deposited on the second dielectric layer, the first interface site, and the first side of the second interface site; A patterned mask layer is formed on a first side of the first conductive material; A second conductive material is electroplated or chemically plated on the first side of the portion of the first conductive material not covered by the mask layer to form the conductive element; Remove the mask layer; and Etch the exposed portion of the first conductive material.

6. The packaging method according to claim 5, characterized in that: The second dielectric material forming the second dielectric layer includes polyimide; and / or The third dielectric material forming the third dielectric layer includes polyimide; and / or The first conductive material includes at least one of titanium / gold and chromium / gold; and / or The second conductive material includes gold; and / or The coating material forming the site coating includes at least one of gold, platinum, iridium oxide, and a conductive polymer.

7. The packaging method according to claim 4, characterized in that, Removing the sacrificial layer and the portion of the substrate located on the second side of the sacrificial layer includes: A protective layer is formed on the first side of the third dielectric layer and the site coating; The wafer is diced to obtain one or more chip components; and For at least one chip component, Remove the sacrificial layer from the chip assembly to release the third electrode portion. Cut and remove the portion of the substrate located on the second side of the sacrificial layer in the chip assembly, and Remove the protective layer from the chip assembly.

8. The packaging method according to claim 7, characterized in that, Removing the sacrificial layer and the portion of the substrate located on the second side of the sacrificial layer further includes: Before removing the sacrificial layer in the chip assembly, the substrate is thinned on a second side of the substrate.

9. The packaging method according to claim 1, characterized in that, Bonding the chip to a printed circuit board includes: Solder balls are formed on the second electrode and the terminal; Flip the chip so that the first side of the chip faces the printed circuit board and align the second electrode with the terminal; The second electrode is bonded to the terminal via the solder ball; and A filler layer is formed between the chip and the printed circuit board.

10. The packaging method according to claim 1, characterized in that, The chip is manufactured directly on the substrate.

11. The packaging method according to claim 1, characterized in that, A groove is formed on the first side of the substrate, and the chip is embedded and fixed in the groove.

12. The packaging method according to claim 11, characterized in that, The wafer is formed by the following steps: The substrate is thinned on a second side of the substrate; A groove is made on the first side of the substrate; The chip is bonded to the carrier substrate; The chip is placed in the groove and glue is applied around the chip and inside the groove; The substrate, the chip, and the carrier substrate are evacuated. Curing the adhesive; as well as The bonding between the chip and the carrier substrate is released, and the carrier substrate is removed.

13. The packaging method according to claim 12, characterized in that, The wafer is further formed by the following steps: After thinning the substrate, a stress-buffering material is deposited on the second side of the substrate to form a stress-buffering layer.

14. The packaging method according to claim 13, characterized in that: The stress-relief material includes at least one of silicon dioxide and silicon nitride; and / or The adhesive includes polyimide.

15. The packaging method according to claim 4, characterized in that, The encapsulation method further includes forming a redistribution layer, and the redistribution layer being formed simultaneously with the conductive element.

16. A brain-computer interface module, characterized in that, The brain-computer interface module includes a chip, electrodes, and a printed circuit board, wherein the chip, the electrodes, and the printed circuit board are packaged by the packaging method according to any one of claims 1 to 15.

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