Semiconductor device

Abstract

A semiconductor device includes a substrate including a cell active region and a boundary region; a bit line extending in a first direction parallel to a top surface of the substrate; a semiconductor pattern extending vertically to the top surface of the substrate; a back gate electrode extending in a second direction intersecting the first direction; and a gate electrode spaced apart from the back gate electrode in the first direction, the semiconductor pattern being between the gate electrode and the back gate electrode. The semiconductor pattern includes a first outer wall extending in the second direction and adjacent to the back gate electrode, a second outer wall opposite to the first outer wall in the first direction, and a first side wall connecting the first outer wall and the second outer wall. An angle between the first side wall and the first outer wall is in a range of 40° to 80°.

Description

[0001] Cross-reference of related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2025-0027766, filed on March 4, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device. Background Technology

[0004] Semiconductor devices have become a major focus in the electronics industry due to their characteristics such as miniaturization, multifunctionality, and / or low manufacturing cost. Semiconductor devices can be divided into semiconductor memory devices that store logic data, semiconductor logic devices that perform operations on logic data, and hybrid semiconductor devices that include both storage and logic elements.

[0005] In recent years, with the increase in the speed and decrease in the power consumption of electronic devices, it has become advantageous for the semiconductor devices they contain to have higher operating speeds and / or lower operating voltages. To meet these requirements, semiconductor devices are becoming increasingly highly integrated. Therefore, a great deal of research has been conducted to improve the integration level of semiconductor devices. Summary of the Invention

[0006] According to some embodiments of this disclosure, a semiconductor device with improved reliability and productivity, as well as a method of manufacturing the semiconductor device, are provided.

[0007] According to some embodiments of this disclosure, a semiconductor device may include: a substrate including a cell active region and a boundary region; a bit line extending along a first direction parallel to the top surface of the substrate; a semiconductor pattern extending along a direction perpendicular to the top surface of the substrate and disposed on the bit line; a back gate electrode extending along a second direction parallel to the top surface of the substrate and intersecting the first direction; and a gate electrode spaced apart from the back gate electrode in the first direction, the semiconductor pattern being between the gate electrode and the back gate electrode, wherein the semiconductor pattern includes: a first outer wall extending in the second direction and adjacent to the back gate electrode; a second outer wall opposite to the first outer wall in the first direction; and a first sidewall connecting the first outer wall and the second outer wall, wherein the angle between the first sidewall and the first outer wall is 40° to 80°.

[0008] According to some embodiments of this disclosure, a semiconductor device may include: a substrate including a cell active region and a boundary region; a bit line extending along a first direction parallel to the top surface of the substrate; a semiconductor pattern extending along a direction perpendicular to the top surface of the substrate and disposed on the bit line; a back gate electrode extending along a second direction parallel to the top surface of the substrate and intersecting the first direction; and a gate electrode spaced apart from the back gate electrode in the first direction, wherein the cell active region includes a memory cell, the boundary region surrounds the cell active region and connects the cell active region and a sense amplifier, and the top surface of the semiconductor pattern in the cell active region and the top surface of the semiconductor pattern in the boundary region are at the same level.

[0009] According to some embodiments of this disclosure, a semiconductor device may include: a substrate including a cell active region and a boundary region; a bit line extending along a first direction parallel to the top surface of the substrate; a semiconductor pattern extending along a direction perpendicular to the top surface of the substrate and disposed on the bit line; a back gate electrode extending along a second direction parallel to the top surface of the substrate and intersecting the first direction; a gate electrode spaced apart from the back gate electrode in the first direction; the semiconductor pattern between the gate electrode and the back gate electrode; a gate insulating pattern between the semiconductor pattern and the gate electrode; and a back gate insulating pattern between the semiconductor pattern and the back gate electrode, wherein the semiconductor pattern includes: a first outer wall extending in the second direction and adjacent to the back gate electrode; a second outer wall opposite to the first outer wall in the first direction; and a first sidewall connecting the first outer wall and the second outer wall, wherein the length of the first outer wall in the second direction is greater than the length of the second outer wall in the second direction, and wherein the ratio of the maximum width of the semiconductor pattern in the first direction to the length of the second outer wall in the second direction is in the range of 0.5 to 0.8.

[0010] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device may include: forming a preliminary semiconductor pattern on a substrate and a preliminary back gate structure between the preliminary semiconductor patterns, the preliminary back gate structure including a preliminary back gate insulating pattern and a first preliminary back gate capping pattern; forming etch spacers covering the sidewalls of the preliminary back gate insulating pattern on the preliminary semiconductor pattern; forming a polycrystalline insulating layer covering the sidewalls of the etch spacers on the preliminary semiconductor pattern; and forming a first mask pattern on the etch spacers, the polycrystalline insulating layer and the preliminary back gate insulating pattern, wherein the etch spacers include a material having etch selectivity relative to each of the polycrystalline insulating layer and the preliminary back gate insulating pattern.

[0011] According to some embodiments, a method for manufacturing a semiconductor device may include etching spacers comprising titanium nitride.

[0012] According to some embodiments, a method for manufacturing a semiconductor device may include: performing an etching process using a first mask pattern as a mask; and removing etch spacers and a polycrystalline insulating layer exposed by the etching process.

[0013] According to some embodiments, a method for manufacturing a semiconductor device may include reducing the height of each of an initial back gate insulating pattern and a first initial back gate capping pattern by means of an etching process.

[0014] According to some embodiments, a method for manufacturing a semiconductor device may include: leaving portions of the etch spacer adjacent to the initial back gate insulating pattern unetched.

[0015] According to some embodiments, a method for manufacturing a semiconductor device may include: etching a preliminary semiconductor pattern using an etching process that uses an etch spacer as a mask to form a semiconductor pattern.

[0016] According to some embodiments, a method for manufacturing a semiconductor device may include forming a pad pattern between a preliminary semiconductor pattern and etch spacers.

[0017] According to some implementations, a method for manufacturing a semiconductor device may include removing etch spacers and pad patterns.

[0018] According to some embodiments, a method for manufacturing a semiconductor device may include: a semiconductor pattern comprising: a first outer wall adjacent to a back gate electrode and extending in a second direction; a second outer wall opposite to the first outer wall in a first direction; and a first sidewall connecting the first outer wall and the second outer wall, wherein the angle between the first sidewall and the first outer wall is 40° to 80°.

[0019] According to some embodiments, a method for manufacturing a semiconductor device may include: the length of a first outer wall in a second direction is greater than the length of a second outer wall in the second direction. Attached Figure Description

[0020] Figure 1 This is a block diagram illustrating an example of a semiconductor device.

[0021] Figure 2 and Figure 3 This is a perspective view that schematically illustrates an example of a semiconductor device.

[0022] Figure 4 This is a plan view of an example semiconductor device.

[0023] Figure 5 yes Figure 4 An enlarged view of an example of part P in the diagram.

[0024] Figure 6A , Figure 6B and Figure 6C yes Figure 5 An enlarged view of part M in the example.

[0025] Figure 7A It is along Figure 5 The cross-sectional view taken by line AA′ in the diagram.

[0026] Figure 7B It is along Figure 5 The cross-sectional view taken from line BB′ in the diagram.

[0027] Figure 7C It is along Figure 5 The cross-sectional view taken by line CC′ in the diagram.

[0028] Figure 7D It is along Figure 5 The cross-sectional view taken from line DD′ in the diagram.

[0029] Figures 8A to 18C This is a diagram illustrating an example of a method for manufacturing semiconductor devices.

[0030] Figure 19A and Figure 19B This is a diagram illustrating an example of a method for manufacturing semiconductor devices.

[0031] Figures 20A to 20D This is a diagram illustrating an example of a method for manufacturing semiconductor devices.

[0032] Figures 21A to 21F This is a diagram illustrating an example of a method for manufacturing semiconductor devices. Detailed Implementation

[0033] Figure 1 This is a block diagram illustrating examples of semiconductor devices according to some embodiments of the present disclosure.

[0034] refer to Figure 1 The semiconductor device may include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and control logic 5.

[0035] The memory cell array 1 may include multiple memory cells MC arranged in two or three dimensions. Each memory cell MC may be connected between intersecting word lines WL and bit lines BL. Each memory cell MC may include a select element TR and a data storage device DS. The select element TR and the data storage device DS may be electrically connected to each other. The select element TR may be connected to both word lines WL and bit lines BL. In other words, the select element TR may be located at the intersection of word lines WL and bit lines BL.

[0036] The selection element TR may include a field-effect transistor. The data storage device DS may include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. For example, the gate terminal of the transistor serving as the selection element TR may be connected to the word line WL, and the source / drain terminals of the transistor may be connected to the bit line BL and the data storage device DS, respectively.

[0037] The row decoder 2 can decode an externally input address to select one of the word lines WL of the memory cell array 1. The address decoded by the row decoder 2 can be provided to the row driver, and the row driver can, in response to the control of the control circuit, provide a predetermined voltage to the selected word line WL and the unselected word line WL.

[0038] The sense amplifier 3 can sense, amplify and output the voltage difference between the selected bit line BL (which is selected based on the address decoded by the column decoder 4) and the reference bit line.

[0039] The column decoder 4 can provide a data transfer path between the sense amplifier 3 and an external device (e.g., a memory controller). The column decoder 4 can decode the address of an external input to select one of the bit lines BL. The control logic 5 can generate control signals that control the operation of writing data to or reading data from the memory cell array 1.

[0040] Figure 2 and Figure 3 This is a perspective view that schematically illustrates an example of a semiconductor device.

[0041] refer to Figure 2 and Figure 3 The semiconductor device may include a peripheral circuit structure PS on a substrate SUB1 and a cell array structure CS connected to the peripheral circuit structure PS. The substrate SUB1 may have a plate shape extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 are respectively parallel to the top surface of the substrate SUB and may intersect each other. The first direction D1 and the second direction D2 may be perpendicular to each other. A third direction D3 may be perpendicular to the top surface of the substrate SUB and may intersect with the first direction D1 and the second direction D2.

[0042] The peripheral circuit structure PS may include a core and peripheral circuitry formed on the substrate SUB. The core and peripheral circuitry may include a reference... Figure 1 The description includes row decoder 2, column decoder 4, readout amplifier 3, and control logic 5.

[0043] The cell array structure CS can include Figure 1 The storage cell array 1 includes Figure 1 Storage cells (MCs) arranged in two or three dimensions. For example, Figure 1 The selection element TR for each memory cell in the memory cell MC may include a vertical channel transistor VCT. The vertical channel transistor may include a channel whose longitudinal direction is D3.

[0044] refer to Figure 2 The peripheral circuit structure PS can be disposed on the substrate SUB. The cell array structure CS can be disposed on the peripheral circuit structure PS. The peripheral circuit structure PS can be connected to the cell array structure CS through contact portions.

[0045] refer to Figure 3 The semiconductor device may include a chip-to-chip (C2C) structure. A peripheral circuit structure PS may be disposed on a substrate SUB1. A first metal pad LMP may be disposed on top of the peripheral circuit structure PS. The first metal pad LMP may be electrically connected to the core and the peripheral circuitry. The first metal pad LMP in the peripheral circuit structure PS may be bonded to a second metal pad UMP of the cell array structure CS, which will be described later. Therefore, the peripheral circuit structure PS and the cell array structure CS can be bonded.

[0046] The cell array structure CS can be disposed on the carrier substrate SUB2. The second metal pad UMP can be disposed on the lower part of the cell array structure CS. The second metal pad UMP can be electrically connected to the memory cell array 1 (e.g., Figure 1 (As shown).

[0047] Figure 4 This is a plan view of an example semiconductor device. Figure 5 yes Figure 4 A magnified view of part P in the image. Figures 6A to 6C yes Figure 5 An enlarged view of part M in the example. Figures 7A to 7D They are along Figure 5 The cross-sectional view taken from lines AA′, BB′, CC′ and DD′.

[0048] First refer to Figure 4 and Figures 7A to 7D , will describe reference Figure 2 and Figure 3 The cell array structure CS.

[0049] Semiconductor devices may include a lower insulating layer (LIL). The lower insulating layer (LIL) may include an insulating material. For example, the lower insulating layer (LIL) may be disposed on a reference... Figure 2 The described cell array structure CS is located on the lower part. In this case, the lower insulating layer LIL can be connected to the reference. Figure 2 The peripheral circuit structures PS are adjacent and in contact. Furthermore, refer to... Figure 2 The described peripheral circuit structure PS can be referenced. Figure 2 Between the substrate SUB and the lower insulating layer LIL. Furthermore, the lower insulating layer LIL may include connections to a reference. Figure 2 The description includes the core and wiring of the peripheral circuit structure PS.

[0050] In some implementations, the cell array structure of the semiconductor device ( Figure 2 The CS in the reference is flipped (inverted), so that the lower insulating layer LIL can be set at the reference. Figure 3 The upper part of the described cell array structure CS. In this case, the lower insulating layer LIL can be connected to the reference. Figure 3 The carrier substrate SUB2 is adjacent to and in contact with the semiconductor device in its uninverted state, showing a cell array structure. Figure 2 The plan and cross-sectional views of the CS (cell array) will be used as a reference to describe semiconductor devices, but the cell array structure is not limited to this.

[0051] Bit lines BL can be disposed in the lower insulating layer LIL. Bit lines BL can extend along a first direction D1 within the lower insulating layer LIL. Bit lines BL can include a conductive material. For example, bit lines BL can include at least one of the following: doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), metallic materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), metal silicides (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), or metal nitrides (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). Bit lines BL can be a single layer or a composite layer. Multiple bit lines BL can be disposed. Bit lines BL can be spaced apart from each other along a second direction D2.

[0052] Bit line contacts DC can be disposed in the lower insulating layer LIL. Bit line contacts DC can be disposed on the bit line BL. Bit line contacts DC can be located between the semiconductor pattern SP and the bit line BL, as will be described later. Accordingly, the bit line BL can be connected to the semiconductor pattern SP via the bit line contacts DC. Bit line contacts DC can include a conductive material. For example, bit line contacts DC can include doped silicon. Multiple bit line contacts DC can be disposed. Bit line contacts DC can be spaced apart from each other along a first direction D1 on a bit line BL.

[0053] Semiconductor patterns SP can be disposed on bit lines BL. For example, semiconductor patterns SP can be disposed on the top surface of bit line contact DC. Semiconductor patterns SP can extend along a third direction D3 on bit line BL. Multiple semiconductor patterns SP can be disposed. Semiconductor patterns SP can be spaced apart from each other along a first direction D1 on a bit line BL. Semiconductor patterns SP can be spaced apart from each other along a second direction D2.

[0054] The semiconductor pattern SP can include semiconductor materials. For example, the semiconductor pattern SP can include at least one of silicon (e.g., single-crystal silicon), germanium, or silicon-germanium. For example, the semiconductor pattern SP can include oxide semiconductors. Oxide semiconductors can include at least one of, but are not limited to, InGaZnO, InGaSiO, InSnZnO, InZnO, ZnO, ZnSnO, ZnON, ZrZnSnO, SnO, HfInZnO, GaZnSnO, AlZnSnO, YbGaZnO, or InGaO. For example, the semiconductor pattern SP can include indium gallium zinc oxide (IGZO). For example, the semiconductor pattern SP can include two-dimensional semiconductor materials. For example, two-dimensional semiconductor materials can include graphene, carbon nanotubes, or combinations thereof.

[0055] Word lines WL can be disposed on the sidewalls of semiconductor patterns SP. Word lines WL can be located between adjacent semiconductor patterns SP in the first direction D1. Word lines WL can extend along the second direction D2. Multiple word lines WL can be disposed. Word lines WL can be spaced apart from each other along the first direction D1. For example, a pair of word lines WL adjacent to each other in the first direction D1 can be located between adjacent semiconductor patterns SP in the first direction D1. For example, a pair of word lines WL adjacent to each other in the first direction D1 can be spaced apart from each other by a cut pattern CT (described later) located between the pair of word lines WL.

[0056] The word line WL may include a gate electrode GE extending along a second direction D2 and a third direction D3, a gate insulating pattern GI between the semiconductor pattern SP and the gate electrode GE, a first gate capping pattern GC1 on the top surface of the gate electrode GE, and a second gate capping pattern GC2 on the bottom surface of the gate electrode GE. The gate electrode GE may include a conductive material. For example, the gate electrode GE may include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), a metal silicide (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), or a metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ir, Co, etc.). For example, the gate insulating pattern GI may include at least one of silicon oxide or a high-dielectric material. Herein, a high-dielectric material is defined as a material with a dielectric constant higher than that of silicon oxide. Each of the first gate capping pattern GC1 and the second gate capping pattern GC2 may include an insulating material. For example, the first gate capping pattern GC1 and the second gate capping pattern GC2 may include at least one of silicon oxide or silicon nitride.

[0057] The cut pattern CT may be situated between adjacent word lines WL in the first direction D1, and space the word lines WL apart. The cut pattern CT may extend along a third direction D3. For example, the cut pattern CT may include insulating material.

[0058] A back gate structure (BGS) can be disposed on the sidewall of a semiconductor pattern (SP). The back gate structure (BGS) can be located between adjacent semiconductor patterns (SP) along the first direction (D1). The back gate structure (BGS) and word lines (WL) can be spaced apart from each other along the first direction (D1), with the semiconductor pattern (SP) located between the back gate structure (BGS) and the word line (WL). The back gate structure (BGS) can extend along the second direction (D2) between adjacent semiconductor patterns (SP) along the first direction (D1). Multiple back gate structures (BGS) can be disposed. The back gate structures (BGS) can be spaced apart from each other along the first direction (D1).

[0059] When a back-gate structure (BGS) is configured, the threshold voltage of the transistor, including the semiconductor pattern SP, can be adjusted by applying a voltage to the BGS. Accordingly, adjusting the threshold voltage via the BGS is easier than adjusting it by implanting dopants into the semiconductor pattern SP. By adjusting the threshold voltage using the BGS, unnecessarily turning on the transistor can be prevented.

[0060] The back gate structure BGS may include a back gate electrode BGE, a first back gate capping pattern BGC1 on the top surface of the back gate electrode BGE, a second back gate capping pattern BGC2 on the bottom surface of the back gate electrode BGE, and a back gate insulating pattern BGI covering its sidewalls. For example, the back gate electrode BGE may include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), a metal silicide (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), or a metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). For example, the first back gate capping pattern BGC1 and the second back gate capping pattern BGC2 may include an insulating material. In some embodiments, the back gate insulating pattern BGI may include at least one of silicon oxide or a high-dielectric material.

[0061] An interlayer insulation layer 120 (e.g.,) can be set on the lower insulation layer LIL. Figure 7C (As shown). The interlayer insulating layer 120 may be located between adjacent semiconductor patterns SP in the second direction D2. For example, the interlayer insulating layer 120 may include an insulating material.

[0062] The interconnect structure CNS can be disposed on the semiconductor pattern SP. The interconnect structure CNS may include a memory node contact BC and a bonding pad LP. The memory node contact BC may be disposed on the top surface of the semiconductor pattern SP. The memory node contact BC may include a conductive material. For example, the memory node contact BC may include doped silicon. Multiple memory node contacts BC may be disposed. The memory node contacts BC may be spaced apart from each other in a first direction D1 and a second direction D2.

[0063] A bonding pad LP can be disposed on the memory node contact BC. The memory node contact BC and the bonding pad LP can vertically overlap each other. The sidewalls of the memory node contact BC and the sidewalls of the bonding pad LP can be aligned. The bonding pad LP can be connected to the semiconductor pattern SP through the memory node contact BC. The bonding pad LP can include a conductive material. For example, the bonding pad LP can include at least one of the following: doped semiconductor material (e.g., doped silicon, doped germanium, etc.), metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), metal silicide (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), or metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0064] Multiple bonding pads LP can be set. Bonding pads LP can be spaced apart from each other in the first direction D1 and the second direction D2. For example, in a planar view, bonding pads LP can be arranged in various shapes, such as zigzag, matrix, and honeycomb. For example, in a planar view, bonding pads LP can have various shapes, such as circular, elliptical, rectangular, square, rhomboid, and hexagonal.

[0065] An upper insulating layer (UIL) can be configured around the storage node contacts BC and bonding pads LP. The upper insulating layer (UIL) may include insulating material. The upper insulating layer (UIL) may be a single layer or a composite layer. The upper insulating layer (UIL) can space multiple storage node contacts BC apart from each other. The upper insulating layer (UIL) can separate multiple bonding pads LP from each other.

[0066] A data storage pattern DSP can be disposed on a bonding pad LP. The data storage pattern DSP can be connected to a semiconductor pattern SP via the bonding pad LP and the memory node contact BC. Multiple data storage pattern DSPs can be disposed. The data storage pattern DSPs can be spaced apart from each other in a first direction D1 and a second direction D2. The data storage pattern DSP can be connected to a reference. Figures 1 to 3 The data storage device DS described corresponds to this.

[0067] Data storage pattern DSPs can be, for example, capacitors comprising a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor device can be dynamic random access memory (DRAM). Data storage pattern DSPs can include, for example, magnetic tunnel junction patterns. In this case, the semiconductor device can be magnetic random access memory (MRAM). Data storage pattern DSPs can include phase change materials or variable resistance materials. In this case, the semiconductor device can be phase change random access memory (PRAM) or resistive random access memory (ReRAM). However, these are merely examples, and data storage pattern DSPs are not limited to these, but can include various suitable structures and / or materials capable of storing data.

[0068] In the following text, reference will be made to Figures 5 to 7D A more detailed description of the semiconductor pattern SP.

[0069] refer to Figure 5 and Figure 6A The semiconductor pattern SP can be located between the back gate electrode BGE and the gate electrode GE. The back gate insulating pattern BGI can be located between the semiconductor pattern SP and the back gate electrode BGE. The gate insulating pattern GI can be located between the semiconductor pattern SP and the gate electrode GE. The semiconductor pattern SP can be located between the back gate insulating pattern BGI and the gate insulating pattern GI. The gate insulating pattern GI can be in contact with the back gate insulating pattern BGI.

[0070] The semiconductor pattern SP may include a first outer wall OW1, a second outer wall OW2, a first sidewall SW1, and a second sidewall SW2. The first outer wall OW1 may be adjacent to the back gate electrode BGE and may extend parallel to the back gate electrode BGE. For example, as Figures 6A to 6C As shown, in the first direction D1, the first outer wall OW1 may be closer to the back gate electrode BGE than the second outer wall OW2. For example, the first outer wall OW1 may extend in the second direction D2. The first outer wall OW1 may contact the back gate insulating pattern BGI. The second outer wall OW2 may be the surface opposite to the first outer wall OW1 in the first direction D1. The second outer wall OW2 may be adjacent to the gate electrode GE and may extend in the second direction D2. For example, in the first direction D1, the second outer wall OW2 may be closer to the gate electrode GE than the first outer wall OW1. The second outer wall OW2 may contact the gate insulating pattern GI.

[0071] Each of the first sidewall SW1 and the second sidewall SW2 can be connected to the first outer wall OW1 and the second outer wall OW2. The first sidewall SW1 can be a surface opposite to the second sidewall SW2. The first sidewall SW1 and the second sidewall SW2 can be in contact with the gate insulating pattern GI. The first sidewall SW1 and the second sidewall SW2 can extend obliquely relative to the first direction D1 and the second direction D2.

[0072] The first angle θ1 between the first sidewall SW1 and the first outer wall OW1 can be an acute angle. For example, the first angle θ1 can be in the range of 40° to 80°. For example, the first angle θ1 can be less than 70°. The second angle θ2 between the first sidewall SW1 and the second outer wall OW2 can be an obtuse angle. For example, the second angle θ2 can be in the range of 100° to 140°. For example, the second angle θ2 can be greater than 110°.

[0073] The angle between the second sidewall SW2 and the first outer wall OW1 can be an acute angle. For example, the angle between the second sidewall SW2 and the first outer wall OW1 can be in the range of 40° to 80°. For example, the angle between the second sidewall SW2 and the first outer wall OW1 can be less than 70°. The angle formed by the second sidewall SW2 and the second outer wall OW2 can be an obtuse angle. For example, the angle between the second sidewall SW2 and the second outer wall OW2 can be in the range of 100° to 140°. For example, the angle between the second sidewall SW2 and the second outer wall OW2 can be greater than 110°.

[0074] The first outer wall OW1 may have a first length W1 in the second direction D2. The second outer wall OW2 may have a second length W2 in the second direction D2. The first length W1 may be greater than the second length W2. For example, the ratio of the first length W1 to the second length W2 may be in the range of 1.4 to 1.7.

[0075] The maximum width of the semiconductor pattern SP in the second direction D2 can be the same as the first length W1 of the first outer wall OW1. In other words, the semiconductor pattern SP can have a maximum width in the second direction D2 at the first outer wall OW1. The width of the semiconductor pattern SP in the second direction D2 can decrease as the distance from the first outer wall OW1 increases.

[0076] The minimum width of the semiconductor pattern SP in the second direction D2 can be the same as the second length W2 of the second outer wall OW2. In other words, the semiconductor pattern SP can have a minimum width in the second direction D2 at the second outer wall OW2. The width of the semiconductor pattern SP in the second direction D2 can increase as the distance from the second outer wall OW2 increases.

[0077] The second length W2 of the second outer wall OW2 can be greater than the width of the semiconductor pattern SP in the first direction D1. For example, the ratio of the maximum width of the semiconductor pattern SP in the first direction D1 to the second length W2 of the second outer wall OW2 can be in the range of 0.5 to 0.8.

[0078] Figure 6B and Figure 6C These are based on other examples. Figure 5A magnified view of section M. To simplify the description, details that overlap with the above will be omitted, and the main focus will be on the differences from the above.

[0079] refer to Figure 6B The first sidewall SW1 and the second sidewall SW2 can be curved surfaces that are recessed into the semiconductor pattern SP. The first angle θ1 can be the angle between the first sidewall SW1 and the first outer wall OW1. The second angle θ2 can be the angle between the first sidewall SW1 and the second outer wall OW2.

[0080] refer to Figure 6C The semiconductor pattern SP can have a hemispherical profile. In this case, the first sidewall SW1 and the second sidewall SW2 can be omitted, and the second outer wall OW2 can be directly connected to the first outer wall OW1. The second outer wall OW2 can be a curved surface protruding towards the gate electrode GE. In this case, the first angle θ1 can be the angle between the first outer wall OW1 and the second outer wall OW2.

[0081] Figure 7A , Figure 7C and Figure 7D This is a cross-sectional view showing an example of the active region CR of the element, and Figure 7B This is a cross-sectional view showing an example of the boundary region BR.

[0082] refer to Figure 4 , Figure 5 and Figures 7A to 7D The active region CR can be a region that includes memory cells. The active region CR can control bit lines BL. The boundary region BR can be adjacent to the edge region of the active region CR. The boundary region BR can surround the active region CR. Similar to the active region CR, the boundary region BR can include bit lines BL and word lines WL, and can connect the bit lines BL extending from the active region CR to... Figure 1 The sense amplifier 3 is located in the region. For example, the bit line BL of the boundary region BR can be connected to the sense amplifier 3 via a contact. As another example, the boundary region BR can be connected to... Figure 1 The region of line decoder 2. For example, the word line WL of the boundary region BR can be connected to line decoder 2 via a contact.

[0083] refer to Figures 7A to 7DThe bit line BL of the active region CR can extend on the boundary region BR. In the boundary region BR, a dummy insulating layer 110 can be disposed on a portion of the bit line BL. The dummy insulating layer 110 can include multiple insulating layers. The dummy insulating layer 110 can include an insulating material. The dummy insulating layer 110 can be spaced apart from the semiconductor pattern SP and word line WL of the boundary region BR in a first direction D1. The connection structure CNS and the data storage pattern DSP can be disposed on the dummy insulating layer 110. The bit line BL of the boundary region BR can be connected to the sense amplifier 3 via a contact portion. The contact portion connected to the bit line BL can be disposed in the lower insulating layer LIL.

[0084] The top surface of the semiconductor pattern SP on the active region CR can be located at a first horizontal level LV1. The top surface of the semiconductor pattern SP on the boundary region BR can also be located at the first horizontal level LV1. For example, the top surfaces of the semiconductor pattern SP on the active region CR and the semiconductor pattern SP on the boundary region BR can be located at the same horizontal level. The height of the semiconductor pattern SP on the active region CR can be the same as the height of the semiconductor pattern SP on the boundary region BR.

[0085] On the active region CR, the top surface of the semiconductor pattern SP can be coplanar with the top surface of the first back gate capping pattern BGC1. On the boundary region BR, the top surface of the semiconductor pattern SP can be coplanar with the top surface of the first back gate capping pattern BGC1. Therefore, the top surface of the first back gate capping pattern BGC1 on the active region CR can be at the same horizontal level as the top surface of the first back gate capping pattern BGC1 on the boundary region BR.

[0086] The height of the first back gate cap pattern BGC1 on the active region CR and boundary region BR can be in the range of 150 Å to 200 Å. The height of the first gate cap pattern GC1 can be in the range of 200 Å to 300 Å. The height of the first back gate cap pattern BGC1 can be 5% to 15% of the height of the back gate structure BGS. This is because, in the manufacturing method described later, by adjusting the height of the first back gate cap pattern BGC1, the height of the first back gate cap pattern BGC1 can be reduced, and the height of the back gate electrode BGE can be increased.

[0087] According to some embodiments, the angle between the first sidewall SW1 and the first outer wall OW1 adjacent to the back gate electrode BGE of the semiconductor pattern SP can be 40° to 80°. The first length W1 of the first outer wall OW1 of the semiconductor pattern SP can be greater than the second length W2 of the second outer wall OW2. This is because, in the manufacturing method described later, when the etch spacer SPC is etched to form the semiconductor pattern SP, the portion of the etch spacer SPC adjacent to the back gate insulating pattern BGI may not be etched (see...). Figure 12 ).

[0088] Furthermore, in some embodiments, the top surface of each of the semiconductor patterns SP on the active cell region CR and the boundary region BR can be located at the same horizontal level. That is, there may be no height difference between the semiconductor patterns SP on the active cell region CR and the boundary region BR. The height difference between the semiconductor patterns SP on the active cell region CR and the boundary region BR can be as small as 50 Å or less. Therefore, the height of the semiconductor patterns SP can be sufficiently ensured in both the active cell region CR and the boundary region BR. This improves the reliability and electrical characteristics of the semiconductor device.

[0089] Figures 8A to 18C This is a diagram illustrating an example of a method for manufacturing semiconductor devices. More specifically, Figure 8A , Figure 9A , Figure 11A , Figure 13A , Figure 14 , Figure 15A , Figure 16A , Figure 17A and Figure 18A They are along Figure 5 The cross-sectional view taken by line AA′ in the diagram. Figure 8B , Figure 9B , Figure 11B , Figure 15B , Figure 16B , Figure 17B and Figure 18B They are along Figure 5 The cross-sectional view taken from line BB′ in the diagram. Figure 9C , Figure 11C , Figure 13B , Figure 15C , Figure 16C , Figure 17C and Figure 18C They are along Figure 5 The cross-sectional view taken by line CC′ in the diagram. Figure 9D , Figure 11D , Figure 13C and Figure 15D They are along Figure 5 A cross-sectional view taken from the centerline DD′. Figure 10 and Figure 12yes Figure 5 An enlarged view of part M in the image.

[0090] refer to Figure 8A and Figure 8B A first substrate 100 can be fabricated. A preliminary semiconductor pattern SP_P can be formed on the first substrate 100. For example, the first substrate 100 and the preliminary semiconductor pattern SP_P can include semiconductor materials. A dummy insulating layer 110 adjacent to the preliminary semiconductor pattern SP_P in the first direction D1 can be formed on the first substrate 100 in the boundary region BR.

[0091] Then, by performing a patterning process on the preliminary semiconductor pattern SP_P, a first trench TR1 can be formed on the preliminary semiconductor pattern SP_P. The first trench TR1 can be formed to extend along the second direction D2. The preliminary semiconductor pattern SP_P can be separated into multiple preliminary semiconductor patterns SP_P by the first trench TR1.

[0092] A preliminary back gate structure BGS_P can be formed in the first trench TR1. For example, a preliminary back gate insulation pattern BGI_P can be formed to conformally cover the first trench TR1. A preliminary back gate electrode BGE_P can be formed to fill the lower part of the first trench TR1 on the preliminary back gate insulation pattern BGI_P. A first preliminary back gate capping pattern BGC1_P can be formed to fill the upper part of the first trench TR1 on the preliminary back gate electrode BGE_P.

[0093] The height of the initial semiconductor pattern SP_P can then be reduced by etching the upper portion of the initial semiconductor pattern SP_P. The top surface of the initial semiconductor pattern SP_P can be located at a level lower than the top surface of the initial back gate insulating pattern BGI_P and the top surface of the first initial back gate cap pattern BGC1_P. Pad patterns PAD can be formed on the initial semiconductor pattern SP_P. The pad pattern PAD can be a thin insulating layer. The pad pattern PAD can include an insulating material. For example, the pad pattern PAD can include silicon oxide.

[0094] Etched spacer structures (SPCs) can be formed on the pad pattern PAD. Forming the etched spacer SPCs may include conformally forming etched spacer layers on the pad pattern PAD, the initial back gate insulation pattern BGI_P, and the first initial back gate cap pattern BGC1_P. The etched spacer layers on the pad pattern PAD, except for the portion on the sidewalls of the initial back gate insulation pattern BGI_P, can be removed by an etching process. An etch-back process can be performed to remove the etched spacer layers on the top surface of the initial back gate insulation pattern BGI_P and the top surface of the first initial back gate cap pattern BGC1_P. Therefore, in some embodiments, the etched spacer SPCs may be disposed only on the sidewalls of the initial back gate insulation pattern BGI_P on the top surface of the pad pattern PAD.

[0095] The etch spacer SPC may include a material with etch selectivity relative to the first initial back gate cover pattern BGC1_P and the poly insulating layer POL. The etch spacer SPC may include a metal. For example, the etch spacer SPC may include TiN. Alternatively, the etch spacer SPC may include at least one of titanium nitride, metal oxide, tungsten, polysilicon, doped silicon, silicon nitride, or silicon oxide.

[0096] A polycrystalline insulating layer POL can be formed on the substrate 100. The polycrystalline insulating layer POL can cover the pad pattern PAD, the preliminary back gate insulating pattern BGI_P, the first preliminary back gate cap pattern BGC1_P, and the etch spacer SPC.

[0097] refer to Figures 9A to 9D An etching process can be performed on the polycrystalline insulating layer (POL). The etching process can be a chemical mechanical polishing (CMP) process. Therefore, the height of the polycrystalline insulating layer (POL) can be reduced. The polycrystalline insulating layer (POL) on the unit active region (CR) can be etched more than the polycrystalline insulating layer (POL) on the boundary region (BR). Since the boundary region (BR) is located at the edge of the unit active region (CR), the polycrystalline insulating layer (POL) in the boundary region (BR) can be etched less. Therefore, the top surface of the polycrystalline insulating layer (POL) on the unit active region (CR) is at a lower level than the top surface of the polycrystalline insulating layer (POL) on the boundary region (BR), and a height difference can occur.

[0098] When etching the polycrystalline insulating layer POL, the preliminary back gate insulation pattern BGI_P and the first preliminary back gate capping pattern BGC1_P on the cell active region CR can also be etched together. Therefore, the height of the preliminary back gate insulation pattern BGI_P and the first preliminary back gate capping pattern BGC1_P can also be reduced, such as... Figure 9AAs shown. After the etching process, the top surface of the polycrystalline insulating layer POL on the active region CR of the cell can be coplanar with the top surface of the preliminary back gate insulating pattern BGI_P, the top surface of the first preliminary back gate capping pattern BGC1_P, and the top surface of the etch spacer SPC.

[0099] On the other hand, such as Figure 9B As shown, the polycrystalline insulating layer POL on the boundary region BR can still cover the top surface of each of the preliminary back gate insulating pattern BGI_P, the first preliminary back gate capping pattern BGC1_P, and the etch spacer SPC. The height of each of the preliminary back gate insulating pattern BGI_P, the first preliminary back gate capping pattern BGC1_P, and the etch spacer SPC on the boundary region BR can remain unchanged. Therefore, the height of each of the preliminary back gate insulating pattern BGI_P, the first preliminary back gate capping pattern BGC1_P, and the etch spacer SPC on the boundary region BR can be greater than its height on the cell active region CR. That is, the first height HE1 of the preliminary back gate insulating pattern BGI_P in the cell active region CR can be less than the second height HE2 of the preliminary back gate insulating pattern BGI_P in the boundary region BR.

[0100] refer to Figures 10 to 11D A first mask pattern MP can be formed on the polycrystalline insulating layer POL. On the cell active region CR, the first mask pattern MP can cover the polycrystalline insulating layer POL, the etch spacer SPC, the preliminary back gate insulating pattern BGI_P, and the first preliminary back gate capping pattern BGC1_P. The first mask pattern MP can extend in a first direction D1. The first mask patterns MP can be spaced apart from each other in a second direction D2. The first mask pattern MP can be formed on the region forming the semiconductor pattern SP, which will be described later. The first mask pattern MP can include a material with etch selectivity relative to each of the first preliminary back gate capping pattern BGC1_P, the etch spacer SPC, and the polycrystalline insulating layer POL. The etch selectivity of the first mask pattern MP can be different for each of the first preliminary back gate capping pattern BGC1_P, the etch spacer SPC, and the polycrystalline insulating layer POL.

[0101] refer to Figures 12 to 13C An etching process using a first mask pattern MP as a mask can be performed. Through the etching process, the etch spacers SPC and polycrystalline insulating layer POL exposed by the first mask pattern MP can be removed. The upper portion of the first preliminary back gate cap pattern BGC1_P exposed by the first mask pattern MP can also be etched. Therefore, the height of the exposed first preliminary back gate cap pattern BGC1_P can be reduced from a first height H1 to a second height H2.

[0102] Through an etching process, the etched spacer SPC can have a trapezoidal profile. The portion of the etched spacer SPC adjacent to the initial back gate insulating pattern BGI_P can be retained without being etched. This is because the remaining portion is adjacent to both the initial back gate insulating pattern BGI_P and the first mask pattern MP, and therefore may not be completely removed. The remaining portion of the etched spacer SPC can decrease in size as it moves away from the initial back gate insulating pattern BGI_P. The etched spacer SPC can have a trapezoidal profile... Figure 6A The semiconductor pattern SP has the same outline. For example, the etch spacer SPC can include the same outline as... Figure 6A The first outer wall OW1 and the second outer wall OW2, as well as the first side wall SW1 and the second side wall SW2, of the semiconductor pattern SP are substantially the same outer wall and side wall.

[0103] According to some embodiments of this disclosure, over-etching of the exposed first preliminary back gate cover pattern BGC1_P can be prevented by using an etch spacer SPC. This is because the etch spacer SPC comprises a material that is etch-selective not only to the first mask pattern MP but also to the first preliminary back gate cover pattern BGC1_P. Therefore, in the process of removing the etch spacer SPC exposed by the first mask pattern MP1 (see...), Figure 13C The initial back gate insulating pattern BGI_P and the first initial back gate capping pattern BGC1_P can be etched relatively little. Therefore, the height of each of the initial back gate insulating pattern BGI_P and the first initial back gate capping pattern BGC1_P can be sufficiently high. By making the first initial back gate capping pattern BGC1_P sufficiently high, the heights of the first back gate capping pattern BGC1 and the back gate electrode BGE can be adjusted. Furthermore, by making the first initial back gate capping pattern BGC1_P sufficiently high, adjacent word lines WL can be prevented from crossing the first initial back gate capping pattern BGC1_P and contacting each other during word line WL formation.

[0104] refer to Figure 14 The first mask pattern MP can be removed. Therefore, the first preliminary back gate cap pattern BGC1_P, the preliminary back gate insulation pattern BGI_P, the etch spacer SPC, and the polycrystalline insulating layer POL can be exposed again. The dashed line indicates the height of the exposed first preliminary back gate cap pattern BGC1_P.

[0105] refer to Figures 15A to 15D An etching process can be performed to remove the polycrystalline insulating layer POL. For example, ammonia can be used to perform the etching process. The etching process allows the first preliminary back gate cap pattern BGC1_P, the preliminary back gate insulating pattern BGI_P, and the etch spacer SPC to be removed without removing them.

[0106] By removing the polysilicon insulating layer POL, the top surface of the pad pattern PAD can be exposed again. The polysilicon insulating layer POL can be removed from the pad pattern PADs of the cell active region CR and the boundary region BR. The pad pattern PADs of each of the cell active region CR and the boundary region BR can be located at the same level as each other. In other words, the height of the top surface of the initial semiconductor pattern SP_P of each of the cell active region CR and the boundary region BR can be located at substantially the same level (first level LV1).

[0107] refer to Figures 16A to 16C An etching process using an etch spacer SPC as an etch mask can be performed to etch the pad pattern PAD and the preliminary semiconductor pattern SP_P. The etching process etches the preliminary semiconductor pattern SP_P to form the semiconductor pattern SP. The semiconductor pattern SP can be formed on the sidewall of the preliminary back gate insulating pattern BGI_P. The semiconductor pattern SP can be a strip extending in the third direction D3. The etching process etches the upper portion of each of the first preliminary back gate cap pattern BGC1_P and the preliminary back gate insulating pattern BGI_P. Therefore, the height of each of the first preliminary back gate cap pattern BGC1_P and the preliminary back gate insulating pattern BGI_P can be reduced.

[0108] refer to Figures 17A to 17C An etching process can be performed to remove the spacer particles (SPCs). This etching process can be a wet etching process. Through this etching process, the SPCs can be selectively removed, and the semiconductor pattern (SP) will not be removed due to the pad pattern (PAD). In other words, the pad pattern (PAD) prevents the semiconductor pattern (SP) from being removed.

[0109] By removing the etch spacer SPC, the height of the semiconductor pattern SP in each of the cell active region CR and the boundary region BR can be substantially the same. Therefore, the top surface of the semiconductor pattern SP in each of the cell active region CR and the boundary region BR can be located at the same level as each other.

[0110] refer to Figures 18A to 18C Word lines WL can be formed between semiconductor patterns SP. Forming word lines WL may include: forming a gate insulating pattern GI covering the sidewalls of the semiconductor pattern SP, and sequentially forming a second gate capping pattern GC2, a gate electrode GE, and a first gate capping pattern GC1 on the gate insulating pattern GI. Subsequently, a cut pattern CT penetrating the gate electrode GE can be formed.

[0111] Memory node contacts BC and bonding pads LP can be formed sequentially on a semiconductor pattern SP. An upper insulating layer UIL can be formed around each of the memory node contacts BC and bonding pads LP. The upper insulating layer UIL can be formed at different times, whether before or after the formation of the memory node contacts BC and bonding pads LP. Then, a data storage pattern DSP can be formed on the bonding pads LP.

[0112] Next, the top and bottom surfaces of the first substrate 100 can be flipped to expose the bottom surface of the first substrate 100. The first substrate 100 can be removed until the bottom surface of the first preliminary back gate insulating pattern BGI_P is exposed. An etching process can be performed on the first preliminary back gate insulating pattern BGI_P to etch the bottom surface of the back gate electrode BGE and fill it with insulating material, thereby forming the second back gate capping pattern BGC2.

[0113] Refer again Figures 7A to 7D Bit line contacts (DCs) can be formed on the bottom surface of the semiconductor pattern SP. Bit lines (BLs) can be formed on the bit line contacts (DCs). A lower insulating layer (LIL) can be formed to cover the bit line contacts (DCs) and the bit lines (BLs). The lower insulating layer (LIL) can be formed at any different time during the manufacturing process, whether before or after the formation of the bit line contacts (DCs) and the bit lines (BLs).

[0114] Figure 19A and Figure 19B This is a diagram illustrating a method for manufacturing semiconductor devices without etched spacers (SPC). Figure 19A and Figure 19B respectively with Figure 13A and Figure 13C Correspondingly, to simplify the description, content that overlaps with the above will be omitted, and the main focus will be on the differences from the above.

[0115] refer to Figure 19A and Figure 19B The etch spacer SPC is omitted, and an oxide spacer 150 can be provided. The oxide spacer 150 can include a material that has no etch selectivity relative to the initial back gate insulating pattern BGI_P. For example, the oxide spacer 150 can include the same material as the initial back gate insulating pattern BGI_P. For example, the oxide spacer 150 can include silicon oxide. Furthermore, the pad pattern PAD can be omitted on the initial semiconductor pattern SP_P.

[0116] An etching process can be performed using a first mask pattern MP as an etching mask. The etching process removes the oxide spacers 150 exposed by the first mask pattern MP. Since the oxide spacers 150 comprise a material with no etch selectivity relative to the initial back gate insulating pattern BGI_P, the initial back gate insulating pattern BGI_P and the first initial back gate cap pattern BGC1_P can be etched together. Therefore, with... Figure 13C Different from Figure 13C In contrast, the preliminary back gate insulating pattern BGI_P exposed by the first mask pattern MP can be etched relatively more. Therefore, the height of the preliminary back gate insulating pattern BGI_P exposed after the etching process can be significantly reduced from the first height H1 to the third height H3. Consequently, the height of each of the preliminary back gate insulating pattern BGI_P and the first preliminary back gate capping pattern BGC1_P may be insufficient. Therefore, when forming word lines WL, there may be issues with adjacent word lines WL contacting each other, or insufficient height of the back gate electrode BGE.

[0117] Furthermore, omitting the pad pattern PAD results in the first back gate cap pattern BGC1 and the semiconductor pattern SP on the cell active region CR and boundary region BR having different heights, thus creating a height difference. As a result, the reliability and electrical characteristics of the semiconductor device may be compromised.

[0118] Figures 20A to 20D This is a diagram illustrating another example of a method for manufacturing a semiconductor device. For simplicity, descriptions that overlap with the above will be omitted, and the main focus will be on the differences from the above.

[0119] Figure 20A and Figure 20B respectively with Figure 13A and Figure 14 Correspondingly. Reference Figure 20A The pad pattern PAD can be omitted between the initial semiconductor pattern SP_P and the polysilicon insulating layer POL. The pad pattern PAD and etch spacer SPC can be formed on the initial semiconductor pattern SP_P, and then the pad pattern PAD exposed by the etch spacer SPC can be etched. The polysilicon insulating layer POL can be formed on the top surface of the initial semiconductor pattern SP_P where the pad pattern PAD has been removed. Therefore, the pad pattern PAD can be formed only between the initial semiconductor pattern SP_P and the etch spacer SPC.

[0120] refer to Figure 20B It can remove the first mask pattern MP and expose the polycrystalline insulating layer POL, the etch spacer SPC, the preliminary back gate insulating pattern BGI_P and the first preliminary back gate capping pattern BGC1_P.

[0121] refer to Figure 20CAn etching process using etch spacers (SPCs) as masks can be performed to simultaneously remove a portion of the polysilicon insulating layer (POL) and the initial semiconductor pattern (SP_P). For example, the entire polysilicon insulating layer (POL) can be removed by the etching process, and the initial semiconductor pattern (SP_P) exposed by the etch spacers (SPCs) can also be removed. Therefore, the removal of the polysilicon insulating layer (POL) and the formation of the semiconductor pattern (SP) can be completed in one step by the etching process. This is likely because the pad pattern (PAD) is omitted between the polysilicon insulating layer (POL) and the initial semiconductor pattern (SP_P). Furthermore, a relatively small portion of the etch spacers (SPCs) adjacent to the initial back gate insulating pattern (BGI_P) may be retained. Therefore, Figures 6A to 6C The first angle θ1 in the equation may increase relatively.

[0122] refer to Figure 20D This can remove the etch spacers (SPC). Removing the etch spacers (SPC) can be done in conjunction with a reference. Figures 17A to 17C The descriptions are basically the same.

[0123] Figures 21A to 21F This is a diagram illustrating another example of a method for manufacturing a semiconductor device. For simplicity, descriptions that overlap with the above will be omitted, and the main focus will be on the differences from the above.

[0124] refer to Figure 21A The materials of the polycrystalline insulating layer (POL) and the etch spacer SPC can be interchanged. The polycrystalline insulating layer (POL) may include a material that is etch-selective relative to the first initial back gate cover pattern (BGC1_P) and the polycrystalline insulating layer (POL). The polycrystalline insulating layer (POL) may include a metal. For example, the polycrystalline insulating layer (POL) may include at least one of titanium nitride, metal oxide, tungsten, polycrystalline silicon, doped silicon, silicon nitride, or silicon oxide. On the other hand, the etch spacer SPC may include an insulating material. For example, the etch spacer SPC may include polycrystalline silicon. However, the polycrystalline insulating layer (POL) and the etch spacer SPC may still include materials that are etch-selective relative to each other.

[0125] refer to Figure 21B The first mask pattern MP can cover the polycrystalline insulating layer POL, the etched spacer SPC, the preliminary back gate insulating pattern BGI_P, and the first preliminary back gate capping pattern BGC1_P. Figure 21B The first mask pattern MP in the reference can be compared with the reference. Figures 10 to 11D The first mask pattern MP is substantially the same as described. The first mask pattern MP may include materials that have etch selectivity relative to the polycrystalline insulating layer POL, the etch spacer SPC, and the initial back gate insulating pattern BGI_P.

[0126] refer to Figure 21C The etching process can be performed using the first mask pattern MP as a mask. Figure 21C The etching process can be compared with the reference. Figures 12 to 13C The etching process described is basically the same. Afterwards, the first mask pattern MP can be removed.

[0127] refer to Figure 21D After removing the first mask pattern MP, the exposed polycrystalline insulating layer POL can be removed. In this case, the pad pattern PAD can be used as an etch stop layer. Furthermore, the etch spacer SPC can be left unremoved.

[0128] refer to Figure 21E An oxidation process can be performed on the exposed etch spacer SPC. The oxidation process can be performed on both sidewalls and the top surface of the etch spacer SPC. Therefore, the etch spacer SPC can comprise a material that has no etch selectivity relative to the initial back gate insulation pattern BGI_P and the first initial back gate cap pattern BGC1_P.

[0129] refer to Figure 21F An oxidized etch spacer (SPC) can be used as a mask to perform an etching process to etch a portion of the initial semiconductor pattern SP_P, thereby forming the semiconductor pattern SP. Through the etching process, the initial back gate insulating pattern BGI_P and the first initial back gate capping pattern BGC1_P are not removed, allowing their respective heights to remain relatively high. Subsequent processes can be performed in conjunction with a reference... Figures 17A to 18C The described processes are basically the same.

[0130] Based on the embodiments described above, semiconductor patterns can be formed using etch spacers adjacent to the back gate insulating pattern. The etch spacers may comprise materials that are etch-selective for each of the back gate insulating pattern and the polycrystalline insulating layer. The height of the back gate capping pattern on the top surface of the back gate electrode can thus be maintained high to prevent adjacent gate electrodes from contacting each other. Furthermore, the angle between the first sidewall and the first outer wall adjacent to the back gate electrode of the semiconductor pattern can be in the range of 40° to 80°. The width of the first outer wall of the semiconductor pattern can be greater than the width of the second outer wall adjacent to the gate electrode. Furthermore, the top surfaces of each of the semiconductor patterns in the cell active region and the boundary region can be at the same level. The heights of the semiconductor patterns in the cell active region and the boundary region can be identical. Therefore, the height of the back gate electrode can be increased, and the reliability of the semiconductor device can be improved.

[0131] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of any claims. In a single embodiment, specific features described in the context of a standalone implementation of this disclosure may also be combined. Conversely, different features described in the context of a single implementation may also be implemented individually in multiple embodiments, or in appropriate sub-combinations. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination may be removed from the combination in some cases, and combinations may be for sub-combinations or variations thereof.

[0132] Although this disclosure has been described with reference to examples thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: The substrate includes the active unit region and the boundary region; Bit lines extend along a first direction parallel to the top surface of the substrate; A semiconductor pattern extends along a direction perpendicular to the top surface of the substrate, wherein the semiconductor pattern is disposed on the bit line; A back gate electrode extends along a second direction parallel to the top surface of the substrate, wherein the second direction intersects the first direction; and A gate electrode is spaced apart from the back gate electrode in the first direction, wherein the semiconductor pattern is located between the gate electrode and the back gate electrode in the first direction. The semiconductor pattern includes: The first outer wall extends in the second direction. The second outer wall is opposite to the first outer wall in the first direction, wherein, in the first direction, the first outer wall is closer to the back gate electrode than the second outer wall. The first sidewall connects the first outer wall and the second outer wall, and The angle between the first sidewall and the first outer wall is in the range of 40° to 80°.

2. The semiconductor device according to claim 1, wherein, The length of the first outer wall in the second direction is greater than the length of the second outer wall in the second direction.

3. The semiconductor device according to claim 1, wherein, The angle between the first sidewall and the second outer wall is in the range of 100° to 140°.

4. The semiconductor device of claim 1, comprising a gate insulating pattern between the semiconductor pattern and the gate electrode. in, In the first direction, the second outer wall is closer to the gate electrode than the first outer wall, and The gate insulating pattern is in contact with the first sidewall and the second outer wall.

5. The semiconductor device of claim 1, further comprising a back gate insulating pattern between the semiconductor pattern and the back gate electrode. in, The first outer wall is in contact with the back grid insulation pattern.

6. The semiconductor device according to claim 1, wherein, The ratio of the maximum width of the semiconductor pattern in the first direction to the length of the second outer wall in the second direction is in the range of 0.5 to 0.

8.

7. The semiconductor device according to claim 1, wherein, The maximum width of the semiconductor pattern in the second direction is the same as the length of the first outer wall in the second direction, and The width of the semiconductor pattern in the second direction decreases as the distance from the first outer wall increases.

8. The semiconductor device according to claim 1, wherein, The first sidewall includes a concave surface that curves inward toward the interior of the semiconductor pattern.

9. The semiconductor device according to claim 1, wherein, The active region of the unit includes a storage unit. The boundary region includes circuitry that connects the readout amplifier or line decoder to the active region of the unit. Wherein, the top surface of the semiconductor pattern on the active region of the cell is at the same level as the top surface of the semiconductor pattern on the boundary region.

10. The semiconductor device of claim 1, comprising a first back gate capping pattern on the top surface of the back gate electrode. in, The height of the first back grid cover pattern is in the range of 150 Å to 200 Å.

11. A semiconductor device, comprising: The substrate includes the active unit region and the boundary region; Bit lines extend along a first direction parallel to the top surface of the substrate; A semiconductor pattern extends along a direction perpendicular to the top surface of the substrate, wherein the semiconductor pattern is disposed on the bit line; A back gate electrode extends along a second direction parallel to the top surface of the substrate, wherein the second direction intersects the first direction; and A gate electrode is spaced apart from the back gate electrode in the first direction, wherein the semiconductor pattern is located between the gate electrode and the back gate electrode in the first direction. The active region of the unit includes a storage unit. The boundary region surrounds the active region of the cell and includes circuitry connecting the active region of the cell and the sense amplifier. Wherein, the top surface of the semiconductor pattern on the active region of the cell is at the same level as the top surface of the semiconductor pattern on the boundary region.

12. The semiconductor device of claim 11, comprising a first back gate capping pattern on the top surface of the back gate electrode. in, The height of the first back grid cover pattern is in the range of 150 Å to 200 Å.

13. The semiconductor device according to claim 12, wherein, The top surface of the first back gate cover pattern on the active region of the cell is at the same level as the top surface of the first back gate cover pattern on the boundary region.

14. The semiconductor device of claim 11, comprising a first gate capping pattern on the top surface of the gate electrode. in, The height of the first gate capping pattern is in the range of 200 Å to 300 Å.

15. The semiconductor device according to claim 11, wherein, The semiconductor pattern has a hemispherical outline in the planar view.

16. The semiconductor device according to claim 11, wherein, The height of the semiconductor pattern on the active region of the cell is the same as the height of the semiconductor pattern on the boundary region.

17. A semiconductor device, comprising: The substrate includes the active unit region and the boundary region; Bit lines extend along a first direction parallel to the top surface of the substrate; A semiconductor pattern extends along a direction perpendicular to the top surface of the substrate, wherein the semiconductor pattern is disposed on the bit line; A back gate electrode extends along a second direction parallel to the top surface of the substrate, wherein the second direction intersects the first direction; A gate electrode is spaced apart from the back gate electrode in the first direction, wherein the semiconductor pattern is located between the gate electrode and the back gate electrode in the first direction; A gate insulating pattern, between the semiconductor pattern and the gate electrode; and A back-gate insulating pattern is positioned between the semiconductor pattern and the back-gate electrode. The semiconductor pattern includes: The first outer wall extends in the second direction. The second outer wall is opposite to the first outer wall in the first direction, wherein, in the first direction, the first outer wall is closer to the back gate electrode than the second outer wall. The first sidewall connects the first outer wall and the second outer wall. Wherein, the length of the first outer wall in the second direction is greater than the length of the second outer wall in the second direction, and The ratio of the maximum width of the semiconductor pattern in the first direction to the length of the second outer wall in the second direction is in the range of 0.5 to 0.

8.

18. The semiconductor device according to claim 17, wherein, The maximum width of the semiconductor pattern in the second direction is the same as the length of the first outer wall in the second direction, and The width of the semiconductor pattern in the second direction decreases as the distance from the first outer wall increases.

19. The semiconductor device according to claim 17, wherein, The first sidewall includes a concave surface that curves inward toward the interior of the semiconductor pattern.

20. The semiconductor device according to claim 17, wherein, The ratio of the length of the first outer wall in the second direction to the length of the second outer wall in the second direction is in the range of 1.4 to 1.7.

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