Diode chip and method of manufacturing the same

Abstract

This invention discloses a diode chip and its fabrication method. The method includes: performing a first phosphorus diffusion at the four corners of both sides of a P-type substrate silicon wafer to form an N-type cutoff ring and a first silicon dioxide layer; photolithographically patterning both sides of the P-type substrate silicon wafer and forming a first hollow rectangle in the central region of both sides; and performing a second phosphorus diffusion on both sides of the P-type substrate silicon wafer to form a double-sided P-N junction. ‑ The process involves forming a junction and a second silicon dioxide layer; performing photolithography on both sides of the P-type substrate silicon wafer, and forming a circular matrix within the area of ​​the first hollowed-out rectangle; the circular matrix penetrates the second silicon dioxide layer; and performing three phosphorus diffusions to form P-N junctions on both sides of the P-type substrate silicon wafer. ‑ -N + The junction and a third silicon dioxide layer are formed; lead holes are etched on both sides of the P-type substrate silicon wafer, and metal electrodes are covered. The technical solution provided by the embodiments of the present invention improves the diode chip's withstand capability against lightning surges.

Description

Technical Field

[0001] This invention relates to the field of diode technology, and in particular to a diode chip and its fabrication method. Background Technology

[0002] Diodes are critical protection devices in electronic circuits, such as transient voltage suppressor diodes (TVS). They are widely used in consumer electronics, industrial control, and new energy equipment. Among them, bidirectional negative resistance TVS, with its symmetrical breakdown characteristics in both positive and negative directions, can adapt to bidirectional transient high-voltage interference scenarios and is one of the core components of current high-voltage, high-reliability protection circuits.

[0003] However, when current diodes are subjected to strong current and the electromagnetic pulses they generate, overvoltage will occur in the diode. When the overvoltage is transmitted along the power line or signal line, it will form a lightning surge. This transient process will generate a large number of electrons and release a lot of heat energy, which will damage the diode and other devices, causing the diode to burn out and lose its ability to protect the circuit. Summary of the Invention

[0004] This invention provides a diode chip and its fabrication method to solve the problem of poor withstand capability of diode chips against lightning surges.

[0005] According to one aspect of the present invention, a method for fabricating a diode chip is provided, comprising: A phosphorus diffusion is performed at the four corners of both sides of the P-type substrate silicon wafer to form an N-type stop ring and a first silicon dioxide layer. A double-sided photolithographic pattern is formed on the P-type substrate silicon wafer, and a first hollow rectangle is formed in the central region of both sides of the P-type substrate silicon wafer; the first hollow rectangle and the N-type cutoff ring do not overlap; Secondary phosphorus diffusion is performed on both sides of the P-type substrate silicon wafer to form a double-sided PN junction. - The junction and the second silicon dioxide layer; Photolithographic patterns are formed on both sides of the P-type substrate silicon wafer, and a circular matrix of cutouts is formed within the area of ​​the first cutout rectangle; the circular matrix penetrates the second silicon dioxide layer; Three phosphorus diffusion processes are performed to form PN junctions on both sides of the P-type substrate silicon wafer. - -N + The junction and a third silicon dioxide layer; the third silicon dioxide layer covers the second silicon dioxide layer; Leadholes are etched on both sides of the P-type substrate silicon wafer and covered with metal electrodes.

[0006] Optionally, during the three-stage phosphorus diffusion process, a PN junction is formed on both sides of the P-type substrate silicon wafer. - -N + Before the junction and the third silicon dioxide layer, it also includes: The doping concentration of phosphorus atoms in the third phosphorus diffusion is set; the doping concentration of phosphorus atoms in the second phosphorus diffusion is less than the doping concentration of phosphorus atoms in the third phosphorus diffusion.

[0007] Optionally, the step of performing phosphorus diffusion at the four corners of both sides of the P-type substrate silicon wafer to form an N-type stop ring and a first silicon dioxide layer includes: An initial silicon dioxide layer is formed on both sides of the P-type substrate silicon wafer; Photolithographic patterns are formed at the four corners of both sides of the P-type substrate silicon wafer, and a second hollow rectangle is formed at each corner, the second hollow rectangle penetrating the initial silicon dioxide layer; A phosphorus diffusion is performed on both sides of the P-type substrate silicon wafer, and the N-type cutoff ring and the first silicon dioxide layer are formed in the second hollow rectangular region.

[0008] Optionally, the thickness of the initial silicon dioxide layer is 11000-18000 Å, the thickness of the first silicon dioxide layer is 3000-8000 Å, and the width of the N-type stop ring is 40-70 μm.

[0009] Optionally, the step of etching lead holes on both sides of the P-type substrate silicon wafer and covering the metal electrodes includes: Photoresist is coated on both sides of the P-type substrate silicon wafer. Through exposure and development, lead holes are etched on both sides, penetrating the third silicon dioxide layer and the second silicon dioxide layer; the lead holes cover at least a portion of the P-type substrate silicon wafer. - -N + The area of ​​the knot; Metal electrodes are respectively covered on both sides of the lead hole.

[0010] Optionally, secondary phosphorus diffusion is performed on both sides of the P-type substrate silicon wafer to form a double-sided PN junction. - Before the junction and the second silicon dioxide layer, it also includes: Clean the P-type substrate silicon wafer and spin dry.

[0011] Optionally, before performing phosphorus diffusion at the four corners of both sides of the P-type substrate silicon wafer and forming the N-type stop ring and the first silicon dioxide layer, the process includes: The P-type substrate silicon wafer is polished and thinned by chemical etching; Clean the P-type substrate silicon wafer and spin dry.

[0012] Optionally, during the three-stage phosphorus diffusion process, a PN junction is formed on both sides of the P-type substrate silicon wafer. - -N + Before the junction and the third silicon dioxide layer, it also includes: Clean the P-type substrate silicon wafer and spin dry.

[0013] Optionally, the cleaning and spin-drying of the P-type substrate silicon wafer includes: The P-type substrate silicon wafer is cleaned by ultrasonic cleaning for the first cleaning time. The P-type substrate silicon wafer was cleaned with SC1 cleaning solution and SC2 cleaning solution respectively for a second cleaning time; Spin dry the P-type substrate silicon wafer.

[0014] According to another aspect of the present invention, a diode chip is provided, which is prepared using the diode chip preparation method described in any embodiment of the present invention.

[0015] The technical solution provided in this invention achieves N-type phosphorus diffusion by performing primary phosphorus diffusion, secondary phosphorus diffusion, photolithographically cut-out circular matrix patterning, and tertiary phosphorus diffusion on both sides of a P-type substrate silicon wafer. + -N - -PN - -N + Integration of diode chips with a specific structure. When N + -N - -PN - -N + When a lightning surge occurs inside the diode chip due to overvoltage, the N-type drift region can absorb the surge voltage, preventing voltage concentration on the surface of the P-type substrate silicon wafer and reducing leakage current. Furthermore, tertiary phosphorus diffusion can form a high concentration of N-type phosphorus. + The heavily doped region significantly reduces contact resistance. Large surge currents can be quickly discharged, preventing heat buildup between the surface of the P-type substrate silicon wafer and the metal electrodes, thus preventing localized high temperatures from burning out the diode chip. Therefore, N... + -N - -PN - -N + The diode structure significantly improves the chip's overall resistance to lightning surges by adjusting N. + The concentration of the heavily doped region can also be adjusted to regulate surge capability, playing an important role in protecting the overall circuit.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a method for fabricating a diode chip according to an embodiment of the present invention; Figure 2 This is a cross-sectional view of a diode chip provided according to an embodiment of the present invention; Figure 3 This is a top view of a diode chip provided according to an embodiment of the present invention; Figure 4 This is a flowchart of another method for fabricating a diode chip according to an embodiment of the present invention; Figure 5 This is a flowchart of another method for fabricating a diode chip according to an embodiment of the present invention; Figure 6 This is a flowchart of another method for fabricating a diode chip according to an embodiment of the present invention; Figure 7 This is a flowchart of another method for fabricating a diode chip according to an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] This invention provides a method for fabricating a diode chip. Figure 1 This is a flowchart illustrating a method for fabricating a diode chip according to an embodiment of the present invention. Figure 2 This is a cross-sectional view of a diode chip provided in an embodiment of the present invention. Figure 3 This is a top view of a diode chip provided in an embodiment of the present invention. (In conjunction with...) Figures 1-3 The fabrication methods for diode chips include: S110, phosphorus diffusion is performed at the four edges and corners of both sides of the P-type substrate silicon wafer to form an N-type stop ring and a first silicon dioxide layer.

[0022] During the dicing and high-temperature processing of the P-type substrate silicon wafer 1, various impurities such as copper, iron, and nickel are generated. These impurities significantly increase leakage current and dark current, and reduce breakdown voltage, thus decreasing the reliability of the diode chip. Furthermore, the edges of the P-type substrate silicon wafer 1 are geometrically sharp, and dislocations, microcracks, and dangling bonds generated during dicing also degrade the performance of the diode chip. Therefore, phosphorus diffusion is required at the four edges of both sides of the P-type substrate silicon wafer 1 to form N-type cutoff rings 5. That is, eight N-type cutoff rings 5 ​​are formed at the eight corners of both sides of the P-type substrate silicon wafer 1. The N-type cutoff rings 5 ​​have a gettering function, actively attracting and fixing impurities and lattice defects within the N-type cutoff rings 5, preventing them from further penetrating into the interior of the P-type substrate silicon wafer 1.

[0023] By forming N-type cutoff rings 5 ​​directly at the corners, impurities do not need to diffuse over long distances; they can be captured nearby by each N-type cutoff ring 5, preventing impurities from diffusing into the active region inside the P-type substrate silicon wafer 1. Simultaneously, because four N-type cutoff rings 5 ​​are provided on each of the two sides of the P-type substrate silicon wafer 1, diffusing impurities can be captured simultaneously on both sides of the P-type substrate silicon wafer 1, preventing the formation of impurity channels through longitudinal penetration of the P-type substrate silicon wafer 1.

[0024] For example, the first silicon dioxide layer ( Figure 2 The thickness of the (not shown) ring is 3000-8000 Å, and the width of the N-type stop ring is 40-70 μm.

[0025] S120. Photolithographic patterning on both sides of a P-type substrate silicon wafer, and forming a first hollow rectangle in the central region of both sides of the P-type substrate silicon wafer; the first hollow rectangle and the N-type cutoff ring do not overlap.

[0026] The first hollowed-out rectangle represents the active region of the P-type substrate silicon wafer. By restricting the position of the first hollowed-out rectangle, positional conflicts with the N-type cutoff ring 5 can be avoided. This ensures that impurities are confined outside the area of ​​the first hollowed-out rectangle, guaranteeing the purity of the active region.

[0027] S130. Secondary phosphorus diffusion is performed on both sides of a P-type substrate silicon wafer to form a double-sided PN junction. - The junction and the second silicon dioxide layer.

[0028] During the secondary phosphorus diffusion process, phosphorus atoms diffuse from both sides of the P-type substrate silicon wafer 1 into the interior of the P-type substrate silicon wafer 1, simultaneously forming N-drift regions 21 on both sides of the P-type substrate silicon wafer 1, thereby forming PN - Conclusion 2. During the secondary phosphorus diffusion process, a second silicon dioxide layer 42 is generated on the surface of the P-type substrate silicon wafer 1 due to the high-temperature oxidation effect.

[0029] For example, the thickness of the second silicon dioxide layer 42 can be between 3000-8000 Å, PN - The sheet resistance of the junction is between 0.5 and 2.5 ohms / sq.

[0030] S140. Photolithographic patterns are formed on both sides of the P-type substrate silicon wafer, and a hollowed-out circular matrix is ​​formed within the area of ​​the first hollowed-out rectangle; the circular matrix penetrates the second silicon dioxide layer.

[0031] After the secondary phosphorus diffusion is completed, a second silicon dioxide layer 42 is covered on both sides of the P-type substrate silicon wafer 1. The second silicon dioxide layer 42 can prevent phosphorus atoms from entering the P-type substrate silicon wafer. Therefore, it is necessary to remove part of the second silicon dioxide layer 42 so that phosphorus atoms can diffuse into the interior of the P-type substrate silicon wafer 1 from both sides during the subsequent secondary phosphorus diffusion.

[0032] By adopting a hollow circular matrix window arrangement, compared to opening and doping the entire area, the continuous electrode area can be divided into multiple dispersed circles, thereby dispersing the current, preventing the current from concentrating in a local position, alleviating the current congestion effect, avoiding excessive local temperature, and improving the diode's ability to withstand lightning surges.

[0033] S150, three phosphorus diffusion processes are performed to form PN junctions on both sides of the P-type substrate silicon wafer. - -N + The junction and the third silicon dioxide layer; the third silicon dioxide layer covers the second silicon dioxide layer.

[0034] In this process, because the second silicon dioxide layer 42 is removed only in a portion of the P-type substrate silicon wafer 1 during photolithography on both sides by using a circular matrix 31 for perforation, phosphorus atoms only diffuse into the interior of the P-type substrate silicon wafer 1 through the circular matrix 31 during the three-stage phosphorus diffusion process, thereby forming a PN junction. - -N + Region 3.

[0035] During the three-stage phosphorus diffusion process, a silicon dioxide layer, namely the third silicon dioxide layer 43, is generated again on the surface of the P-type substrate silicon wafer 1 through high-temperature oxidation.

[0036] By removing the second silicon dioxide layer 42 in the circular matrix 31 region and retaining the second silicon dioxide protective layer 42 in other regions, phosphorus atoms can only penetrate into the interior of the N drift region from the hollowed-out circular matrix 31 region, thereby forming PN. - -N + Conclusion 3.

[0037] High concentrations of N can be formed in region 31 of the circular matrix through tertiary phosphorus diffusion. + The heavily doped region has low contact resistance, resulting in high current density and strong conductivity during subsequent current path formation. In the event of surge current, the circular matrix 31 region effectively conducts the surge current, reducing electron accumulation and heat generation, thus ensuring the safe operation of the diode chip. Furthermore, the N-drift region 21 is still preserved outside the circular matrix 31 region, which helps maintain the breakdown voltage and ensures the withstand voltage remains constant.

[0038] For example, by adjusting the concentration of secondary phosphorus diffusion, it can be used to adjust N + The concentration of the heavily doped region is adjusted to regulate the surge capability.

[0039] Since both secondary and tertiary phosphorus diffusion are bifacial diffusion methods, PN junctions are formed on both sides of the P-type substrate silicon wafer. - -N + Conclusion 3, ultimately forming N + -N - -PN - -N + Diode chip with a specific structure.

[0040] For example, the thickness of the second silicon dioxide layer can be between 4000-7000 Å, PN - -N + The sheet resistance of the junction is between 0.5 and 1 ohm / sq.

[0041] S160. Etch lead holes on both sides of the P-type substrate silicon wafer and cover them with metal electrodes.

[0042] Since the second silicon dioxide layer 42 and the third silicon dioxide layer 43 are insulating materials, current cannot pass through them. Therefore, the second silicon dioxide layer 42 and the third silicon dioxide layer 43 at the corresponding positions need to be removed by etching the lead holes, so that the metal electrode 6 can directly contact the P-type substrate silicon wafer 1, thereby forming a conductive path.

[0043] For example, a dicing channel is provided between multiple P-type substrate silicon wafers, and the dicing channel may also be provided with lead holes, and the diode chip is a planar negative resistance TVS chip.

[0044] The technical solution provided in this invention achieves N-type phosphorus diffusion by performing primary phosphorus diffusion, secondary phosphorus diffusion, photolithographically cut-out circular matrix patterning, and tertiary phosphorus diffusion on both sides of a P-type substrate silicon wafer. + -N - -PN - -N + Integration of diode chips with a specific structure. When N + -N - -PN - -N + When a lightning surge occurs inside the diode chip due to overvoltage, the N-type drift region can absorb the surge voltage, preventing voltage concentration on the surface of the P-type substrate silicon wafer and reducing leakage current. Furthermore, tertiary phosphorus diffusion can form a high concentration of N-type phosphorus. + The heavily doped region significantly reduces contact resistance. Large surge currents can be quickly discharged, preventing heat buildup between the surface of the P-type substrate silicon wafer and the metal electrodes, thus preventing localized high temperatures from burning out the diode chip. Therefore, N... + -N - -PN - -N + The diode structure significantly improves the chip's overall resistance to lightning surges by adjusting N. + The concentration of the heavily doped region can also be adjusted to regulate surge capability, playing an important role in protecting the overall circuit.

[0045] Based on the above embodiments, optionally, a PN junction is formed on both sides of the P-type substrate silicon wafer after three phosphorus diffusion processes. - -N + Before the junction and the third silicon dioxide layer, the process also includes: setting the doping concentration of phosphorus atoms in the third phosphorus diffusion; the doping concentration of phosphorus atoms in the second phosphorus diffusion is less than the doping concentration of phosphorus atoms in the third phosphorus diffusion.

[0046] Secondary phosphorus diffusion is used to generate lightly doped N. - In the drift region, the surge voltage of the diode chip is mainly determined by N. - The drift region is crucial; if the doping concentration in this region is too high, it will reduce the breakdown voltage and fail to meet the withstand voltage requirements. Therefore, the doping concentration of phosphorus atoms during secondary phosphorus diffusion can be appropriately reduced.

[0047] The phosphorus doping concentration in the tertiary phosphorus diffusion process is negatively correlated with resistance. A higher phosphorus doping concentration reduces the internal resistance of the P-type substrate silicon wafer, thereby decreasing the contact resistance between the metal electrode and the P-type substrate silicon wafer. Conversely, a lower phosphorus doping concentration increases the internal resistance of the P-type substrate silicon wafer, thereby increasing the contact resistance between the metal electrode and the P-type substrate silicon wafer. Therefore, by adjusting the phosphorus doping concentration in the tertiary phosphorus diffusion process, the surge resistance of diode chips during lightning strikes can be adjusted.

[0048] Specifically, by increasing the phosphorus atom doping concentration, a high concentration of N can be formed through tertiary phosphorus diffusion. + Heavily doped regions can significantly reduce the contact resistance between the metal electrode and the P-type silicon substrate. Therefore, surge current in the diode chip can be smoothly discharged, preventing current accumulation and the generation of localized high temperatures, and improving the diode chip's ability to withstand lightning surges.

[0049] This invention, through different phosphorus atom doping concentrations in secondary and tertiary phosphorus diffusion, enables the diode chip to meet voltage withstand requirements while simultaneously enhancing its short-surge capability, particularly for 8 / 20μs short-surge pulses. Adjusting the phosphorus atom doping concentration allows for flexible adjustment of surge tolerance.

[0050] Figure 4 A flowchart illustrating another method for fabricating a diode chip according to an embodiment of the present invention. (See reference...) Figure 4 Based on the above embodiments, optionally, S110, performing a phosphorus diffusion at the four corners of both sides of the P-type substrate silicon wafer to form an N-type stop ring and a first silicon dioxide layer includes: S111. An initial silicon dioxide layer is formed on both sides of a P-type substrate silicon wafer.

[0051] S112. Photolithographic patterns are formed at the four corners of both sides of the P-type substrate silicon wafer, and a second hollow rectangle is formed at each corner, the second hollow rectangle penetrating the initial silicon dioxide layer.

[0052] Before phosphorus diffusion, an initial silicon dioxide layer needs to be simultaneously formed on both sides of the P-type substrate silicon wafer. This initial silicon dioxide layer is then patterned using photolithography and etching processes, exposing the P-type substrate silicon wafer by hollowing out the silicon dioxide at the four corners of its perimeter. This method allows for precise phosphorus diffusion at the corners of the perimeter.

[0053] For example, the initial silicon dioxide layer has a thickness of 11,000-18,000 Å.

[0054] S113. Perform phosphorus diffusion on both sides of the P-type substrate silicon wafer and form an N-type cutoff ring and a first silicon dioxide layer in the second hollowed-out rectangular region.

[0055] The second hollowed-out rectangle is the region of the N-type cutoff ring. Because the P-type substrate silicon wafer is covered with an initial silicon dioxide layer on both sides except for the second hollowed-out rectangle, during the first phosphorus diffusion, the initial silicon dioxide layer blocks the entry of phosphorus atoms, and an N-type cutoff ring is formed only in the second hollowed-out rectangle region. Due to the high temperature during the first phosphorus diffusion, a first silicon dioxide layer is also formed simultaneously.

[0056] In this embodiment of the invention, N-type cutoff rings are set at the four corners of the edges on both sides of the P-type substrate silicon wafer, forming multiple getter regions. This ensures that impurities do not penetrate into other regions, thus ensuring the quality and reliability of the diode chip.

[0057] Figure 5 This is a flowchart illustrating another method for fabricating a diode chip according to an embodiment of the present invention. (In conjunction with...) Figure 2 and Figure 5 Based on the above embodiments, optionally, in step S160, etching lead holes on both sides of the P-type substrate silicon wafer and covering the metal electrodes includes: S161. Photoresist is coated on both sides of a P-type substrate silicon wafer. Through exposure and development, lead holes are etched on both sides, penetrating the third and second silicon dioxide layers; the lead holes cover at least a portion of the P-type substrate silicon wafer. - -N + The region of the knot.

[0058] S162. Cover the lead holes on both sides with metal electrodes respectively.

[0059] Since the second silicon dioxide layer 42 and the third silicon dioxide layer 43 are insulating materials, current cannot pass through them. Therefore, it is necessary to remove the second silicon dioxide layer 42 and the third silicon dioxide layer 43 at the corresponding positions by etching the lead holes, so that the metal electrode 6 can directly contact the P-type substrate silicon wafer 1, thereby forming a conductive path. Therefore, the second silicon dioxide layer 42 and the third silicon dioxide layer 43 on the surface of the P-type substrate silicon wafer 1 can be etched by exposure, development, and wet etching, so that the metal electrode can directly contact the P-type substrate silicon wafer 1 through the lead holes.

[0060] Specifically, photoresist is uniformly coated on both the upper and lower surfaces of a P-type silicon substrate. The spin coater is used to control the rotation speed, ensuring that the photoresist thickness is uniform on both sides of the P-type silicon substrate. Afterward, a low-temperature pre-baking process can be performed to evaporate the internal solvent of the photoresist, allowing it to adhere tightly to the surface of the P-type silicon substrate and preventing it from peeling off, thus preparing it for subsequent exposure.

[0061] For example, a double-sided alignment photolithography process with an alignment accuracy of <10μm is used. The upper and lower surfaces of a P-type substrate silicon wafer are exposed to ultraviolet light according to a preset pattern. The photoresist in the area corresponding to the lead hole undergoes a photosensitive reaction after being irradiated by ultraviolet light. The photoresist in the exposed area is then dissolved using a developer, with the remaining photoresist acting as a protective barrier. At this point, a cutout pattern for the lead hole is formed on both sides of the silicon wafer, meaning only the third silicon dioxide layer 43 at the lead hole location is exposed, while the remaining areas are covered by photoresist, thus determining the position and size of the lead hole. The third silicon dioxide layer 43 and the covering second silicon dioxide layer 42 can be removed by wet etching.

[0062] For example, the metal electrode 6 can be electroless nickel plating or evaporated metal.

[0063] Figure 6 A flowchart illustrating another method for fabricating a diode chip according to an embodiment of the present invention. (See reference...) Figure 6 Based on the above embodiments, optionally, S110, before performing phosphorus diffusion at the four corners of both sides of the P-type substrate silicon wafer and forming the N-type stop ring and the first silicon dioxide layer, includes: S170. Polish and thin the P-type substrate silicon wafer by chemical etching.

[0064] S180, clean the P-type substrate silicon wafer and spin dry.

[0065] In particular, during the early cutting and mechanical polishing process, invisible microcracks will form on the silicon surface of P-type substrate silicon wafers. If the damaged layer remains, the cracks will extend further during subsequent diffusion and high-temperature sintering processes. When the diode chip is subjected to a large current impact, it is easy to cause damage to the diode chip.

[0066] Therefore, before phosphorus diffusion onto P-type substrate silicon wafers, surface treatment of the P-type substrate silicon wafers is required. Chemical etching can remove the mechanical damage layer and residual stress generated during the initial dicing process of the P-type substrate silicon wafers.

[0067] After polishing and thinning, a cell will form on the surface of the P-type substrate silicon wafer, which can be used to increase the surface area of ​​the P-type substrate silicon wafer and improve the mechanical bonding strength of the subsequent silicon dioxide layer.

[0068] For example, the thinning removal amount can be 60±5μm, and the corrosion temperature can be 95±5 degrees Celsius.

[0069] Figure 7 A flowchart illustrating another method for fabricating a diode chip according to an embodiment of the present invention. (See reference...) Figure 7Based on the above embodiments, optionally, in S130, secondary phosphorus diffusion is performed on both sides of the P-type substrate silicon wafer to form a double-sided PN junction. - Before the junction and the second silicon dioxide layer, the process also includes: S191, cleaning the P-type substrate silicon wafer and drying it.

[0070] Continue to refer to Figure 7 Based on the above embodiments, optionally, in S150, a third phosphorus diffusion is performed to form a PN junction on both sides of the P-type substrate silicon wafer. - -N + Before the junction and the third silicon dioxide layer, it also includes: S192, cleaning the P-type substrate silicon wafer and spin-drying it.

[0071] Optionally, cleaning and drying the P-type substrate silicon wafer includes: cleaning the P-type substrate silicon wafer by ultrasonic cleaning for a first cleaning time; cleaning the P-type substrate silicon wafer by SC1 cleaning solution and SC2 cleaning solution for a second cleaning time; and drying the P-type substrate silicon wafer by spin drying.

[0072] Before performing secondary and tertiary phosphorus diffusion, the P-type substrate silicon wafer needs to be cleaned to ensure the effectiveness of phosphorus diffusion.

[0073] Specifically, the P-type substrate silicon wafer is first cleaned using ultrasonic cleaning. Ultrasonic cleaning can remove silicon chips, particles and loose impurities from the surface of the P-type substrate silicon wafer, reducing the pressure of subsequent cleaning.

[0074] SC1 cleaning solution is prepared by mixing ammonia and hydrogen peroxide. It can be used to remove organic residues from the surface of P-type substrate silicon wafers and further remove particulate contaminants. SC2 cleaning solution is prepared by mixing hydrochloric acid and hydrogen peroxide. It can be used to remove metallic impurities such as iron and copper from the surface of P-type substrate silicon wafers, reducing the amount of metal residue.

[0075] For example, the first cleaning time can be 20 minutes, and the second cleaning time can be 10 minutes.

[0076] After cleaning the P-type substrate silicon wafer, it can be dried by high-speed centrifugation, which results in a high degree of cleanliness and good dryness.

[0077] Based on the above embodiments, optionally, the doping concentration of phosphorus atoms in the secondary phosphorus diffusion is less than the doping concentration of phosphorus atoms in the tertiary phosphorus diffusion.

[0078] This invention also provides a diode chip. The diode chip fabricated using the method provided in any embodiment of this invention has similar beneficial effects to other diode chip fabrication methods, and will not be described in detail here.

[0079] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and no limitation is imposed herein.

[0080] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for fabricating a diode chip, characterized in that, include: A phosphorus diffusion is performed at the four corners of both sides of the P-type substrate silicon wafer to form an N-type stop ring and a first silicon dioxide layer. A double-sided photolithographic pattern is formed on the P-type substrate silicon wafer, and a first hollow rectangle is formed in the central region of both sides of the P-type substrate silicon wafer; the first hollow rectangle and the N-type cutoff ring do not overlap; Secondary phosphorus diffusion is performed on both sides of the P-type substrate silicon wafer to form a double-sided PN junction. - The junction and the second silicon dioxide layer; Photolithographic patterns are formed on both sides of the P-type substrate silicon wafer, and a circular matrix of cutouts is formed within the area of ​​the first cutout rectangle; the circular matrix penetrates the second silicon dioxide layer; Three phosphorus diffusion processes are performed to form PN junctions on both sides of the P-type substrate silicon wafer. - -N + The junction and a third silicon dioxide layer; the third silicon dioxide layer covers the second silicon dioxide layer; Leadholes are etched on both sides of the P-type substrate silicon wafer and covered with metal electrodes.

2. The method for fabricating a diode chip according to claim 1, characterized in that, In the process of performing three phosphorus diffusions, PN junctions are formed on both sides of the P-type substrate silicon wafer. - -N + Before the junction and the third silicon dioxide layer, it also includes: The doping concentration of phosphorus atoms in the third phosphorus diffusion is set; the doping concentration of phosphorus atoms in the second phosphorus diffusion is less than the doping concentration of phosphorus atoms in the third phosphorus diffusion.

3. The method for fabricating a diode chip according to claim 1, characterized in that, The process of performing phosphorus diffusion at the four corners of both sides of the P-type substrate silicon wafer to form an N-type stop ring and a first silicon dioxide layer includes: An initial silicon dioxide layer is formed on both sides of the P-type substrate silicon wafer; Photolithographic patterns are formed at the four corners of both sides of the P-type substrate silicon wafer, and a second hollow rectangle is formed at each corner, the second hollow rectangle penetrating the initial silicon dioxide layer; A phosphorus diffusion is performed on both sides of the P-type substrate silicon wafer, and the N-type cutoff ring and the first silicon dioxide layer are formed in the second hollow rectangular region.

4. The method for fabricating a diode chip according to claim 3, characterized in that, The initial silicon dioxide layer has a thickness of 11,000-18,000 Å, the first silicon dioxide layer has a thickness of 3,000-8,000 Å, and the N-type stop ring has a width of 40-70 μm.

5. The method for fabricating a diode chip according to claim 1, characterized in that, The step of etching lead holes on both sides of the P-type substrate silicon wafer and covering the metal electrodes includes: Photoresist is coated on both sides of the P-type substrate silicon wafer. Through exposure and development, lead holes are etched on both sides, penetrating the third silicon dioxide layer and the second silicon dioxide layer; the lead holes cover at least a portion of the P-type substrate silicon wafer. - -N + The area of ​​the knot; Metal electrodes are respectively covered on both sides of the lead hole.

6. The method for fabricating a diode chip according to claim 1, characterized in that, Secondary phosphorus diffusion is performed on both sides of the P-type substrate silicon wafer to form a double-sided PN junction. - Before the junction and the second silicon dioxide layer, it also includes: Clean the P-type substrate silicon wafer and spin dry.

7. The method for fabricating a diode chip according to claim 1, characterized in that, Before performing phosphorus diffusion at the four corners of both sides of the P-type substrate silicon wafer and forming the N-type stop ring and the first silicon dioxide layer, the process includes: The P-type substrate silicon wafer is polished and thinned by chemical etching; Clean the P-type substrate silicon wafer and spin dry.

8. The method for fabricating a diode chip according to claim 1, characterized in that, In the process of performing three phosphorus diffusions, PN junctions are formed on both sides of the P-type substrate silicon wafer. - -N + Before the junction and the third silicon dioxide layer, it also includes: Clean the P-type substrate silicon wafer and spin dry.

9. The method for fabricating a diode chip according to claim 6, 7, or 8, characterized in that, The cleaning and drying of the P-type substrate silicon wafer includes: The P-type substrate silicon wafer is cleaned by ultrasonic cleaning for the first cleaning time. The P-type substrate silicon wafer was cleaned with SC1 cleaning solution and SC2 cleaning solution respectively for a second cleaning time; Spin dry the P-type substrate silicon wafer.

10. A diode chip, characterized in that, The diode chip is prepared using the method described in any one of claims 1-9.

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