A gallium nitride high electron mobility transistor device and method of manufacturing the same

Abstract

A gallium nitride high electron mobility transistor device and a manufacturing method thereof, the present application relates to the technical field of power semiconductor devices, in order to solve the problems of the prior art that the PSJ GaN HEMT structure and the enhancement characteristics are difficult to consider, the process is complex, the reliability is insufficient, the injection and extraction speed of holes is slow, the long p-type nitride semiconductor layer and the gate metal are used above the cover layer, the ohmic contact area of the p-type nitride semiconductor layer and the gate metal is expanded, the moving path of the holes in the 2DHG is changed from horizontal to vertical, the moving distance of the holes in the 2DHG to the gate is shortened, thereby the injection and extraction speed of the holes is accelerated, the formation and depletion process of the 2DHG is accelerated, and the switching performance of the device is improved.

Description

Technical Field

[0001] This invention relates to the technical field of power semiconductor devices, and in particular to a gallium nitride high electron mobility transistor device and its manufacturing method. Background Technology

[0002] Polarized superjunction (PSJ) technology is a method for realizing high-voltage GaN HEMT devices. This technology utilizes the spontaneous polarization and piezoelectric polarization effects in group III nitride materials to form a high-density positive and negative polarization charge in the barrier layer. These positive and negative polarization charges induce a two-dimensional electron gas (2DEG) and a two-dimensional hole gas (2DHG) at the heterojunction. In the off state, these positive and negative charges balance each other, achieving effective lateral charge balance and electric field distribution, thereby improving the breakdown voltage. In the on state, the 2DEG and 2DHG discharge through the drain and gate, respectively. This technology helps to shorten the gate-drain pitch, reduce cell size, and thus reduce chip area and manufacturing cost.

[0003] However, most existing PSJ GaN HEMT structures are depletion-mode devices, meaning they are in the on-state when no bias voltage is applied between the gate and source. An existing depletion-mode PSJ GaN HEMT structure is shown below. Figure 1 As shown, to enhance the polarization effect and form high-density 2DEG and 2DHG, this structure typically employs a thicker AlGaN barrier layer and introduces a GaN capping layer on top of the traditional enhancement-mode p-GaN HEMT structure. While this structure is beneficial for constructing the PSJ structure in GaN HEMTs, it also increases the distance between the upper p-GaN layer and the lower 2DEG channel, thereby weakening the gate's depletion capability of the 2DEG channel and hindering the realization of enhancement-mode devices. Simultaneously, simply thinning the AlGaN barrier layer reduces the polarization-induced charge density, further affecting the formation of 2DEG and 2DHG.

[0004] Existing solutions for implementing enhancement-mode PSJ GaN HEMT structures mainly include cascode structures, recessed gate structures, and p-GaN gate structures. Among these, the cascode structure requires a depletion-mode PSJ GaN HEMT to be connected to a low-voltage silicon-based enhancement-mode device via a cascode connection, thus introducing additional chip and packaging costs, as well as additional parasitic parameters and resistance, reducing device performance. Implementing enhancement-mode PSJ GaN HEMT structures using recessed gate structures and p-GaN gate structures typically requires local etching or thinning of the AlGaN barrier layer, which can easily introduce damage, defects, and leakage channels into the AlGaN barrier layer and interface, thereby affecting device reliability, dynamic performance, gate reliability, and threshold voltage consistency.

[0005] p-GaN gate structures typically require separate dual gate electrodes. An existing enhanced p-GaN gate PSJ GaNHEMT structure is shown below. Figure 2 As shown, the first type of gate 11 implements hole injection and extraction using an ohmic contact; the second type of gate 12 implements an enhancement-mode device using a Schottky contact to reduce leakage current from the p-GaN layer in the off state.

[0006] Furthermore, the first type gate 11 and the first p-GaN layer 21 are preferably designed above the GaN capping layer closer to the source. However, hole extraction and injection depend on the ohmic contact region below the first type gate 11. Therefore, during switching, holes in the 2DHG closer to the drain need to move a longer spatial distance. In addition, the mobility of holes is lower than that of electrons, resulting in slower hole injection and extraction speeds, which limits the switching speed of the device. Additionally, there is a local electric field peak in the edge region of the second type gate 12 closer to the drain, affecting the breakdown voltage of the device. Summary of the Invention

[0007] The present invention aims to provide an enhancement-mode polarized superjunction gallium nitride high electron mobility transistor and its manufacturing method, so as to solve the problems of difficulty in achieving both enhancement-mode characteristics, complex process, insufficient reliability, and slow hole injection and extraction speed in the prior art PSJ GaN HEMT structure.

[0008] A gallium nitride high electron mobility transistor device includes a substrate layer at the bottom of the transistor, a buffer layer above the substrate layer, a channel layer above the buffer layer, a first barrier layer above the channel layer, and a source metal, a second left barrier layer, a gate metal, a second right barrier layer, and a drain metal arranged sequentially from left to right above the first barrier layer. The source metal is connected to the second left barrier layer, and the second right barrier layer is connected to the drain metal. A capping layer is disposed above the second right barrier layer, and a p-type nitride semiconductor layer is disposed above the capping layer. A right thin dielectric layer is disposed above the drain metal, extending at least to the left and upward from the capping layer. Above the right side wall of the layer; a left thin dielectric layer is provided above the source metal, and the left thin dielectric layer extends to the right and upward at least to the left side wall of the capping layer; an opening is reserved between the left thin dielectric layer and the right thin dielectric layer; the gate metal is separated from the source metal, the second left barrier layer, the first barrier layer, the second right barrier layer and the capping layer through the left thin dielectric layer, the gate metal extends upward along the left thin dielectric layer to the opening and forms an ohmic contact with the p-type nitride semiconductor layer, a two-dimensional electron gas is formed at the heterojunction between the channel layer and the first barrier layer; a two-dimensional hole gas is formed at the heterojunction between the second right barrier layer and the capping layer.

[0009] Furthermore, the thickness of the first barrier layer is no greater than 8nm, and the thickness of the second left barrier layer and the second right barrier layer is no less than 20nm. The first barrier layer, the left thin dielectric layer, and the gate metal constitute an enhancement-type MIS gate structure.

[0010] Furthermore, the total length of the opening is less than the sum of the top width of the p-type nitride semiconductor layer, the height of the left side wall, and the height of the right side wall.

[0011] Furthermore, the left sidewall of the p-type nitride semiconductor layer and the capping layer contracts inward, causing the widths of the second right barrier layer, the capping layer, and the p-type nitride semiconductor layer to decrease sequentially, resulting in the gate metal near the left sidewall of the second right barrier layer, the capping layer, and the nitride semiconductor having an inclined or stepped structure.

[0012] Furthermore, between the left and right thin dielectric layers above the p-type nitride semiconductor layer, there is one or more uniformly spaced thin dielectric layers, thereby forming one or more uniformly spaced openings.

[0013] Furthermore, the upper surface of the p-type nitride semiconductor layer has one or more first groove structures extending along a first direction and periodically arranged along a second direction; and / or the upper surface of the p-type nitride semiconductor layer has a plurality of second groove structures extending along a second direction and periodically arranged along a first direction, wherein the gate metal is filled downward into the first groove structure and the second groove structure.

[0014] Furthermore, the first groove structure and / or the second groove structure are of the type that is smaller at the top and larger at the bottom.

[0015] Furthermore, a gate metal with more than one spaced interval is provided at the opening position above the p-type nitride semiconductor layer.

[0016] Furthermore, when the device is in the off state, the first gate metal located near the source metal has the same potential as the source metal, and the potentials of the other gate metals can be set to the same potential or increase sequentially, and the potentials of all gate metals are between the potentials of the source metal and the potentials of the drain metal.

[0017] Furthermore, a heavily doped p-type nitride semiconductor layer is provided at the opening location. The doping concentration of the heavily doped p-type nitride semiconductor layer is higher than that of the p-type nitride semiconductor layer, and its thickness is 3-10 nm.

[0018] A method for manufacturing a gallium nitride high electron mobility transistor device, the method comprising the following steps: The first step is to provide a substrate layer, and then form a buffer layer, a channel layer, a first barrier layer, a second left barrier layer, and a second right barrier layer sequentially from bottom to top on the substrate layer. The second step is to form a capping layer and a p-type nitride semiconductor layer sequentially from bottom to top on the second right barrier layer; The third step is to form source metal and drain metal at both ends of the device, in the region above the first barrier layer, respectively. The fourth step is to form a thin dielectric layer on top of the device; The fifth step is to form an opening between the thin dielectric layers above the p-type nitride semiconductor layer to form a left thin dielectric layer and a right thin dielectric layer; The sixth step is to form a gate metal over the left thin dielectric layer and the opening to form a gallium nitride high electron mobility transistor device.

[0019] This invention employs ultrathin barrier technology to form a multilayer barrier structure without relying on etching to thin the barrier layer. The first barrier layer is thinner than the second barrier layer, and together with the thin dielectric layer, it constitutes an enhancement-mode MIS (Metal-Insulator-Semiconductor) gate structure. This structure avoids barrier layer damage and interface defects caused by etching, thereby reducing the risk of gate leakage current caused by etching damage and improving device reliability. The second barrier layer is thick. By optimizing the thicknesses of the first and second barrier layers, the polarization effect is enhanced, and high-density 2DEG and 2DHG are formed to achieve a high-voltage PSJ structure.

[0020] This invention achieves enhancement mode by introducing a thin dielectric layer to form a MIS gate structure. It eliminates the need for Schottky contacts and only requires the formation of ohmic contacts, thereby realizing an integrated gate structure. Compared with the existing enhancement-mode p-GaN gate PSJ GaN HEMT structure with dual gate electrodes, it can reduce process steps and thus reduce process costs.

[0021] At the same time, the MIS gate structure helps to increase the threshold voltage, expand the gate voltage operating window, and improve gate reliability and threshold voltage consistency.

[0022] Furthermore, although PSJ devices can achieve a relatively uniform electric field distribution, local electric field peaks still exist in the gate edge region closer to the drain. This invention, by introducing a stepped structure or field plate structure, can further uniformize the drain-side electric field distribution, reduce the gate-side peak electric field, thereby improving the breakdown voltage and device reliability.

[0023] The beneficial effects of this invention are as follows: This invention employs a long p-type nitride semiconductor layer and gate metal above the capping layer to expand the ohmic contact area of ​​the p-type nitride semiconductor layer and gate metal, thereby changing the movement path of holes in the 2DHG from horizontal to vertical, shortening the movement distance of holes from the 2DHG to the gate, thereby accelerating the hole injection and extraction speed, accelerating the formation and depletion process of the 2DHG, and thus improving the switching performance of the device. Attached Figure Description

[0024] Figure 1 This is a schematic cross-sectional view of an existing depletion-type PSJ GaN HEMT device.

[0025] Figure 2 This is a schematic cross-sectional view of an existing enhancement-type p-GaN gate PSJ GaN HEMT device.

[0026] Figure 3 This is a cross-sectional schematic diagram of the first embodiment of the device of the present invention.

[0027] Figure 4 This is a cross-sectional schematic diagram of a second embodiment of the device of the present invention.

[0028] Figure 5 This is a cross-sectional schematic diagram of the third embodiment of the device of the present invention.

[0029] Figure 6 This is a cross-sectional schematic diagram of the fourth embodiment of the device of the present invention.

[0030] Figure 7 This is a cross-sectional schematic diagram of the fifth embodiment of the device of the present invention.

[0031] Figure 8 This is a cross-sectional schematic diagram of the sixth embodiment of the device of the present invention.

[0032] Figure 9 This is a cross-sectional schematic diagram of the seventh embodiment of the device of the present invention.

[0033] Figure 10 This is a cross-sectional schematic diagram of the eighth embodiment of the device of the present invention.

[0034] Figure 11 This is a cross-sectional schematic diagram of the ninth embodiment of the device of the present invention.

[0035] Figure 12 This is a cross-sectional schematic diagram of the tenth embodiment of the device of the present invention.

[0036] Figures 13 to 17 This is a key step in the manufacturing process of one embodiment of the present invention. Detailed Implementation

[0037] To facilitate understanding of the present invention, the present invention will be described in more detail below with reference to the accompanying drawings and specific embodiments.

[0038] The term “and / or” as used in this specification includes any and all combinations of one or more of the associated listed items.

[0039] It should be noted that the devices in the accompanying drawings are not necessarily drawn to scale. The straight lines showing the boundaries of the doped regions and trenches in the drawings, as well as the sharp corners formed by these boundaries, are generally not straight lines or precise angles in practical applications.

[0040] It should be noted that the corresponding positional terms used in this document, such as "up," "down," "left," "right," "front," "back," "middle," "vertical," "horizontal," "vertical," "inner," and "outer," correspond to the relative positions shown in the reference diagrams. In practice, there is no fixed orientation; the terminology and similar expressions used in this specification are for illustrative purposes only.

[0041] It should be noted that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, and a second component may be referred to as a first component.

[0042] It should be noted that when a component is described as "connected" to another component, it may be directly connected to the other component, or there may be one or more intermediate components in between.

[0043] The doping concentrations described in this specification are for illustrative purposes only. Specific doping concentrations can be flexibly adjusted based on the actual application scenario, device parameters, and process technology. Furthermore, the actual doping concentration is not necessarily uniform; variations in concentration and distribution are permissible due to design requirements or process limitations.

[0044] The layers and / or regions described in this specification are characterized as having an conductivity type such as n-type or p-type, which refers to multiple carrier types in the layer and / or region. n-type materials include a balance excess of electrons, while p-type materials include a balance excess of holes. Some materials may be indicated by "+" or "-" (e.g., n+, n-, p+, p-, heavily doped p-type) to indicate a relatively large (+) or small (-) concentration of multiple carriers compared to another layer or region. This notation does not represent a specific concentration of carriers.

[0045] It should be noted that the materials, doping concentration, length, and thickness of this embodiment do not limit the scope of protection of this invention. These parameters can be adaptively optimized according to the needs of the application.

[0046] The term "Group III nitrides" as used in this text refers to compound semiconductors containing nitrogen (N) and at least one Group III element (aluminum Al, gallium Ga, indium In, boron B), including but not limited to their various alloys, such as aluminum boron nitride, (Al... x B (1-x) N), aluminum gallium nitride (Al) x Ga (1-x) N), Indium gallium nitride (In) y Ga (1-y) N), aluminum indium gallium nitride (Al) x In y Ga (1-x-y) N), gallium arsenide phosphide (GaAs) a PbN (1-a-b) ) and aluminum indium gallium arsenide phosphide alloy (Al x In y Ga (1-x-y) As a PbN (1-a-b) ), etc., among which aluminum gallium nitride (AlGaN) alloy has the chemical formula Al x Ga (1-x) N, 0 <x<1。

[0047] The “enhancement-mode (E-mode)” device described in the text is in the off state when no bias voltage is applied between the gate (G) and the source (S) (VGS=0V). The “depletion-mode (D-mode)” device refers to the device in the on state when no bias voltage is applied between the gate (G) and the source (S) (VGS=0V), but a conductive channel already exists between the source and the drain.

[0048] It should be noted that although each diagram shows only a single unit cell, it should be understood that the structure shown can be repeated multiple times in actual semiconductor devices.

[0049] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0050] It should be noted that, in conjunction with the attached figures, the first direction referred to below is the Y direction in the attached figures; the second direction is the X direction in the attached figures (the direction from the source metal 209 to the drain metal 210); and the third direction is the Z direction in the attached figures (the direction perpendicular to the substrate layer 200). The X, Y, and Z directions are the three directions of a standard three-dimensional coordinate axis. Example 1

[0051] Figure 3 This is a cross-sectional schematic diagram of a first embodiment of the device of the present invention, the structure of which includes: Substrate layer 200 located at the bottom of the device; Buffer layer 201 located above substrate layer 200; Channel layer 202 located above buffer layer 201; The first barrier layer 203 is located above the channel layer 202; The gate metal 208, source metal 209, and drain metal 210 are located above the first barrier layer 203; in the horizontal direction, the source metal 209 and drain metal 210 are located at both ends of the device, and the gate metal 208 is located between the source metal 209 and drain metal 210.

[0052] The second left barrier layer 2041 is located above the first barrier layer 203, between the gate metal 208 and the source metal 209; the left side of the second left barrier layer 2041 is connected to the source metal 209.

[0053] A second right barrier layer 2042 is located above the first barrier layer 203, between the source metal 209 and the drain metal 210. The second left barrier layer 2041 and the second right barrier layer 2042 are typically formed simultaneously in the same process step and are collectively referred to as the second barrier layer 204 in this invention. The second left barrier layer 2041 and the second right barrier layer 2042 are isolated by the gate metal 208, and the right side of the second right barrier layer 2042 is connected to the drain metal 210. The second right barrier layer 2042 is wider than the second left barrier layer 2041.

[0054] The capping layer 205 is located above the second right barrier layer 2042; A two-dimensional electron gas (2DEG) 101 is formed at the heterogeneous interface (referred to as the 202 / 203 interface) between the channel layer 202 and the first barrier layer 203; Two-dimensional cavitation gas (2DHG) 102 is formed at the heterogeneous interface (referred to as the 2042 / 205 interface) between the second right barrier layer 2042 and the capping layer 205; p-type nitride semiconductor layer 206 located above capping layer 205; A left thin dielectric layer 2071 and a right thin dielectric layer 2072 are located above the device; the left thin dielectric layer 2071 covers the source metal 209, the second left barrier layer 2041, and the first barrier layer 203 between the second left barrier layer 2041 and the second right barrier layer 2042, and extends upward along the left side wall of the capping layer 205 and the p-type nitride semiconductor layer 206. Figure 3In the middle, the left thin dielectric layer 2071 covers upward to the upper surface of the p-type nitride semiconductor layer 206; the right thin dielectric layer 2072 covers the drain metal 210 and the second right barrier layer 2042 between the drain metal 210 and the capping layer 205, and extends upward along the right sidewall of the capping layer 205 and the p-type nitride semiconductor layer 206. Figure 3 In the middle, the right thin dielectric layer 2072 extends upward to cover the upper surface of the p-type nitride semiconductor layer 206. An opening 301 is reserved above the p-type nitride semiconductor layer 206 and between the left thin dielectric layer 2071 and the right thin dielectric layer 2072; The gate metal 208 is isolated from the group III nitride semiconductor layers (203 / 204 / 205) by the left thin dielectric layer 2071 and is connected to the p-type nitride semiconductor layer 206 only through the opening 301.

[0055] The gate metal 208 is isolated from the source metal 209 and the drain metal 210 by a dielectric layer.

[0056] The contact between the gate metal 208 and the p-type nitride semiconductor layer 206 is an ohmic contact, which is beneficial for hole extraction and injection.

[0057] Typically, the contact between the source metal 209 and the drain metal 210 and the first barrier layer 203 is an ohmic contact.

[0058] Typically, the substrate 200 is made of silicon, but it may also be made of materials such as gallium nitride, silicon carbide, or sapphire.

[0059] The buffer layer 201 is composed of group III nitride materials and may include multiple material layer combinations such as aluminum gallium nitride, aluminum nitride, gallium nitride, and aluminum boron nitride. These material layer combinations may contain impurities such as carbon, iron, manganese, and magnesium.

[0060] The thickness of buffer layer 201 is based on the required vertical withstand voltage design. The higher the vertical withstand voltage requirement, the thicker the layer. Specifically, in a 1200V device, the thickness of buffer layer 201 is not less than 5µm.

[0061] The channel layer 202 and the capping layer 205 are composed of group III nitride materials, which may be composed of materials such as aluminum gallium nitride, aluminum nitride, aluminum indium nitride, and boron nitride, but are usually gallium nitride.

[0062] Optionally, the channel layer 202 and the capping layer 205 may be undoped, doped, or unintentionally doped, usually unintentionally doped, and may contain impurities such as silicon, oxygen, and magnesium.

[0063] The thickness of the channel layer 202 is typically between 300 nm and 1 μm; the capping layer 205 is typically between 10 nm and 30 nm.

[0064] The band gaps of the first barrier layer 203 and the second barrier layer 204 are narrower than those of the channel layer 202 and the cap layer 205. The first barrier layer 203 and the second barrier layer 204 are made of III-nitride materials, which may be aluminum gallium nitride, aluminum nitride, aluminum indium nitride, boron nitride and other materials, and are usually aluminum gallium nitride.

[0065] Optionally, the first barrier layer 203 and the second barrier layer 204 may be undoped, doped or unintentionally doped, and are usually unintentionally doped. The unintentionally doped layer may contain impurities such as silicon, oxygen, and magnesium.

[0066] Typically, the first barrier layer 203 is a thin layer of Al with a thickness no greater than 8 nm x Ga (1-x) N, 0<x≤1, the thickness depends on the aluminum content x, with a typical value of 6 nm and x=0.2; Typically, the second barrier layer 204 is Al with a thickness no less than 20 nm y Ga (1-y) N, 0<y≤1, the thickness depends on the aluminum content y and the target concentration of 2DHG 102, with a typical value of 40 nm and y=0.2.

[0067] The p-type nitride semiconductor layer 206 is made of a doped III-nitride material, which may be p-AlGaN, p-AlN, p-InGaN, p-BN, p-NiO or other materials, and is usually p-GaN.

[0068] In the above structure, the doping material of the p-type nitride semiconductor layer 206 includes magnesium (Mg) or other suitable p-type doping elements.

[0069] In a specific embodiment, the p-type nitride semiconductor layer 206 is made of p-GaN material, with a doping concentration of 1e19 cm -3 -1e20cm -3 in between, with a typical value of 5e19cm -3 .

[0070] Optionally, the thickness of the p-type nitride semiconductor layer 206 is 10 nm-20 nm, with a typical value of 10 nm.

[0071] Optionally, the left thin dielectric layer 2071 and the right thin dielectric layer 2072 are usually made of oxide or nitride materials, for example, may be Ta2O5, HfO2, SiO2, Si3N4, ZrO2, Al2O3, etc., and may also be a combination of a plurality of the above material layers.

[0072] Typically, the thicknesses of the left thin dielectric layer 2071 and the right thin dielectric layer 2072 are between 5nm and 50nm, with the specific thickness depending on the different materials and the required gate voltage value.

[0073] Optionally, the gate metal 208, source metal 209, and drain metal 210 may be composed of a single metal material or a metal compound. This metal material may include, but is not limited to, metals such as titanium, nickel, tungsten, aluminum, and gold, and their metal compounds.

[0074] Typically, in the second direction, the width of the second right barrier layer 2042 is wider than that of the capping layer 205 and the p-type nitride semiconductor layer 206.

[0075] Typically, in the second direction, the capping layer 205 and the p-type nitride semiconductor layer 206 have the same width.

[0076] Typically, in the second direction, the width of the opening 301 is the same as the width of the p-type nitride semiconductor layer 206.

[0077] Typically, the capping layer 205 and the p-type nitride semiconductor layer 206 are vertically aligned on the side closer to the drain metal 210.

[0078] In this embodiment, a multilayer barrier structure is formed, wherein the first barrier layer 203 is a thin layer, and together with the left thin dielectric layer 2071, it constitutes an enhancement-mode MIS gate structure. This structure can avoid barrier layer damage and interface defects caused by etching, thereby reducing the risk of gate leakage current caused by etching damage and improving device reliability.

[0079] The second barrier layers (2041 and 2042) are thick layers. By optimizing the thickness of the first barrier layer 203 and the second barrier layer, the polarization effect is enhanced and high-density 2DEG and 2DHG are formed to achieve a high-voltage-resistant PSJ structure.

[0080] The present invention achieves enhancement by introducing a thin dielectric layer 2071 to form a MIS gate structure, which eliminates the need for Schottky contacts and only requires the formation of ohmic contacts, thereby realizing an integrated gate structure.

[0081] Compared to existing technologies, the p-type nitride semiconductor layer 206 covers the entire capping layer 205, and both have the same width and length, increasing the contact area between the p-type nitride semiconductor layer 206 and the capping layer 205. Similarly, the gate metal 208 is also increased in length and width. By providing a long opening 301 above the p-type nitride semiconductor layer 206, the contact area between the gate metal 208 and the p-type nitride semiconductor layer 206 is also increased. The width of the opening 301 is at least 1 / 2 of the width of the p-type nitride semiconductor layer 206.

[0082] Furthermore, the present invention employs a long p-type nitride semiconductor layer 206 and a long gate metal 208 above the capping layer to expand the ohmic contact area of ​​the p-type nitride semiconductor layer 206 and the gate metal 208, thereby changing the movement path of holes in the 2DHG from horizontal to vertical, shortening the movement distance of holes from the gate in the 2DHG, thereby accelerating the hole injection and extraction speed, accelerating the formation and depletion process of the 2DHG, and thus improving the switching performance of the device. Example 2

[0083] In some embodiments, in the second direction, the width of the p-type nitride semiconductor layer 206 is narrower than that of the capping layer 205, so that the second right barrier layer 2042, the capping layer 205, and the p-type nitride semiconductor layer 206 form a stepped structure 302 on the side closer to the source metal 209. Correspondingly, this also forms a stepped gate metal structure, such as... Figure 4 As shown.

[0084] Although the PSJ GaN HEMT device can achieve a relatively uniform electric field distribution through the PSJ structure, local electric field peaks still exist in the edge region of the gate metal 208, which is closer to the source metal 209. By introducing a stepped structure 302, the drain-side electric field distribution can be further homogenized, the gate-side peak electric field can be reduced, thereby improving the breakdown voltage and device reliability.

[0085] In addition, field plate structures can be introduced to reduce the peak electric field at the gate edge, thereby increasing the breakdown voltage and improving device reliability. Example 3

[0086] In some embodiments, in the second direction, the width of the p-type nitride semiconductor layer 206 is narrower than that of the capping layer 205, so that the second right barrier layer 2042, the capping layer 205, and the p-type nitride semiconductor layer 206 form an inclined structure 303 on the side closer to the source metal 209, and correspondingly also become an inclined gate metal, such as... Figure 5 As shown.

[0087] While PSJ GaN HEMT devices can achieve a relatively uniform electric field distribution through the PSJ structure, local electric field peaks still exist in the edge region of the gate metal 208, which is closer to the source metal 209. Compared to the stepped structure 302, the tilted structure 303 can further uniformize the drain-side electric field distribution, reduce the gate-side peak electric field, thereby improving the breakdown voltage and device reliability. Example 4

[0088] In some embodiments, based on Embodiment 1, the opening 301 extends to the sidewalls (left sidewall and / or right sidewall) of the p-type nitride semiconductor layer 206, such as... Figure 6As shown (extending to the left side wall), the left thin dielectric layer 2071 extends upward only slightly above the left side wall of the capping layer 205. Similarly, in some embodiments, the right thin dielectric layer 2072 may also extend upward only slightly above the right side wall of the capping layer 205.

[0089] When the opening 301 extends to the left and right walls respectively, the total length of the opening 301 is less than the sum of the top width d of the p-type nitride semiconductor layer 206, the height h1 of the left wall and the height h2 of the right wall.

[0090] The width of the opening 301 is the contact window area between the gate metal 208 and the p-type nitride semiconductor layer 206. The opening 301 is not limited to the upper surface of the p-type nitride semiconductor layer 206. Compared with the existing enhancement p-GaN gate PSJ GaN HEMT structure with dual gate electrodes, the opening 301 extends to the sidewall of the p-type nitride semiconductor layer 206, which can increase the ohmic contact area and shorten the hole movement distance from the gate in the 2DHG, which is beneficial to the hole extraction and injection speed. Example 5

[0091] In some embodiments, based on Example 1, two or more thin dielectric layers (2073, 2074...207n) are further provided above the p-type nitride semiconductor layer 206. Correspondingly, a plurality of openings 301 are formed between these thin dielectric layers, and the plurality of openings 301 are uniformly spaced. These thin dielectric layers and their fabrication processes and materials are consistent with those of the left thin dielectric layer 2071 and the right thin dielectric layer 2072, such as... Figure 7 As shown. Example 6

[0092] In some embodiments, based on Embodiment 1, the upper surface of the p-type nitride semiconductor layer 206 is provided with a plurality of first groove structures 400 extending along a first direction and periodically arranged along a second direction, such as... Figure 8 As shown. Compared with the existing enhanced p-GaN gate PSJ GaN HEMT structure with dual gate electrodes, this structure can increase the ohmic contact area, shorten the hole-to-gate movement distance in the 2DHG, which is beneficial to the hole extraction and injection speed, and can reduce the on-resistance of the device, thereby improving the device performance.

[0093] Furthermore, in some embodiments, the depth of the first groove structure 400 can reach the upper surface of the capping layer 205, and the p-type nitride semiconductor layer 206 is spaced out along the second direction. This structure helps to further reduce the on-resistance of the device.

[0094] Furthermore, in some embodiments, the first groove structure 400 can be a structure that is smaller at the top and larger at the bottom. This structure can further increase the ohmic contact area and shorten the movement distance of holes from the gate in the 2DHG, which is beneficial to the extraction and injection speed of holes. Example 7

[0095] In some embodiments, based on Embodiment 1, the upper surface of the p-type nitride semiconductor layer 206 is provided with a plurality of second groove structures 401 extending along the second direction (X) and periodically arranged along the first direction (Y), such as... Figure 9 As shown. Compared with the existing enhanced p-GaN gate PSJ GaN HEMT structure with dual gate electrodes, this structure can increase the ohmic contact area, shorten the hole-to-gate movement distance in the 2DHG, which is beneficial to the hole extraction and injection speed, and can reduce the on-resistance of the device, thereby improving the device performance.

[0096] Furthermore, in some embodiments, the depth of the second groove structure 401 can reach the upper surface of the capping layer 205, and the p-type nitride semiconductor layer 206 is spaced out along the first direction. This structure helps to further reduce the on-resistance of the device. Example 8

[0097] In some embodiments, based on embodiment 7, the second groove structure 401 has a structure that is smaller at the top and larger at the bottom, such as... Figure 10 As shown. Compared with Example 7, this structure can further increase the ohmic contact area and shorten the hole-to-gate movement distance in the 2DHG, which is beneficial to the hole extraction and injection speed. Example 9

[0098] In some embodiments, the number of gate metal 208 segments is more than one.

[0099] like Figure 11 As shown, n gate metals are set, from left to right as the first gate metal 2081...the nth gate metal 208n, where n is a positive integer greater than 1 (n>1); the n gate metals (2081 to 208n) are distributed at intervals in the second direction.

[0100] When the device is in the off state, the first gate metal 2081 and the source metal 209 have the same potential. For the remaining second gate metals 2082 to the nth gate metal 208n, their potentials can be the same, partially the same, partially different, or all different.

[0101] Gate metals at different potentials are electrically isolated from each other; gate metals at the same potential are electrically connected to each other.

[0102] Preferably, when the device is in the off state, if there is a potential difference between the second gate metal 2082 and the nth gate metal 208n, its potential is between the potential of the first gate metal 2081 (i.e., the potential of the source metal 209) and the potential of the drain metal 210. Furthermore, starting from the side closer to the source metal 209 and moving towards the side closer to the drain metal 210, the potentials of the other gate metals can be set to the same potential or sequentially increased. This sequential increase means that the potential of the gate metal 208(n-1) closer to the source metal 209 is successively lower than the potential of the adjacent gate metal 208(n) closer to the drain metal 210. This arrangement helps to homogenize the electric field distribution and improve the device's withstand voltage. Example 10

[0103] In some embodiments, based on Embodiment 1, a heavily doped p-type nitride semiconductor layer 211 is further provided between the p-type nitride semiconductor layer 206 and the gate metal 208 at the opening 301. The doping concentration of the heavily doped p-type nitride semiconductor layer 211 is higher than that of the p-type nitride semiconductor layer 206, and its thickness is 3-10 nm. Figure 12 As shown.

[0104] The heavily doped p-type nitride semiconductor layer 211 is composed of doped group III nitride materials, which may be composed of heavily doped p-type AlGaN, heavily doped p-type AlN, heavily doped p-type InGaN, heavily doped p-type BN, heavily doped p-type NiO or other materials, typically heavily doped p-type GaN.

[0105] Typically, magnesium is used as the p-type impurity in heavily doped p-type nitride semiconductor layers 211.

[0106] In one specific embodiment, the heavily doped p-type nitride semiconductor layer 211 is composed of heavily doped p-type GaN material, and the concentration of the heavily doped p-type nitride semiconductor layer 211 is greater than 1e20cm⁻¹. -3 The thickness is 3-20nm.

[0107] Adding a heavily doped p-type nitride semiconductor layer 211 can reduce ohmic contact resistance, which is beneficial to accelerate hole extraction and injection speed, and speed up the switching speed of the device. Example 11

[0108] Figures 13 to 17 The key steps of the manufacturing process of one embodiment of the present invention are shown.

[0109] The first step involves providing a substrate layer 200, on which a buffer layer 201, a channel layer 202, a first barrier layer 203, and a second barrier layer 204 are sequentially formed from bottom to top, as follows: Figure 13 As shown.

[0110] Typically, the aforementioned layers can be grown using chemical vapor deposition, hydride vapor phase epitaxy (HVPE), atomic layer deposition (MBE), or other suitable epitaxial processes.

[0111] The first barrier layer 203 is formed using an ultra-thin barrier process. The first barrier layer 203 is a thin layer, and its thickness is configured to, together with the subsequently formed left thin dielectric layer 2071, constitute the gate structure of an enhancement-mode MIS (Metal-Insulator-Semiconductor). This structure achieves an enhancement-mode MIS gate structure without relying on etching to thin the barrier layer, avoiding barrier layer damage and interface defects caused by etching, reducing the risk of gate leakage current, and improving device reliability.

[0112] The second barrier layer 204 is formed using a selective regrowth process. The specific formation process may be as follows: first, a first hard mask material layer 501 is formed on the upper surface of the device, and the first hard mask material layer 501 is patterned to form a window region; then, a second left barrier layer 2041 and a second right barrier layer 2042 are selectively grown in the window region.

[0113] The first hard mask material layer 501 may be composed of oxide or nitride materials, such as SiO2, TiN, SiN, etc., or it may be a combination of multiple material layers mentioned above.

[0114] The first hard mask material layer 501 may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.

[0115] Patterning processes may include steps such as forming a hard mask, photolithography, planarization, etching, cleaning, and heat treatment.

[0116] The second barrier layer 204 is a thick layer. By optimizing the thickness and material parameters of the first barrier layer 203 and the second barrier layer 204, the polarization effect can be enhanced and high-density 2DEG 101 and 2DHG 102 can be formed at the corresponding heterojunction interface, thereby constructing a high-voltage-resistant PSJ structure.

[0117] The second step involves forming a capping layer 205 and a p-type nitride semiconductor layer 206 sequentially from bottom to top on the second right barrier layer 2042, as follows: Figure 14 As shown.

[0118] The capping layer 205 and the p-type nitride semiconductor layer 206 can be formed using a selective regrowth process. Specifically, the formation process may involve: first, forming a second hard mask material layer 502 on the upper surface of the device, and then patterning the second hard mask material layer 502 to form a window region; then, selectively growing the capping layer 205 in the window region. The formation process of the p-type nitride semiconductor layer 206 can be the same as that of the capping layer 205, or epitaxial growth can continue after the capping layer 205 is formed.

[0119] The second hard mask material layer 502 may be composed of oxide or nitride materials, such as SiO2, TiN, SiN, etc., or it may be a combination of multiple material layers mentioned above.

[0120] The second hard mask material layer 502 may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.

[0121] Typically, the formation of the p-type nitride semiconductor layer 206 includes a p-GaN annealing activation process to activate Mg impurity acceptors. For example, a rapid thermal annealing (RTA) process can be used to anneal the p-type nitride semiconductor layer 206 within an appropriate temperature range to increase the hole concentration and improve electrical properties.

[0122] Patterning processes include steps such as forming a hard mask, photolithography, planarization, etching, cleaning, and heat treatment.

[0123] The third step involves forming source metal 209 and drain metal 210 at both ends of the device, in the regions above the first barrier layer 203, respectively. Figure 15 As shown.

[0124] Typically, the source metal 209 and drain metal 210 and the first barrier layer 203 located below them form an ohmic contact.

[0125] Specifically, the steps for forming the source metal 209 and the drain metal 210 may be as follows: first, a third hard mask material layer 503 is formed on the upper surface of the device and patterned to form window regions at both ends of the device; then, the source metal 209 and the drain metal 210 are formed in the window regions respectively.

[0126] Patterning processes include steps such as forming a hard mask, photolithography, planarization, etching, cleaning, and heat treatment.

[0127] The fourth step is to form a thin dielectric layer 207 on top of the device, such as... Figure 16 As shown.

[0128] In some embodiments, a thin dielectric layer 207 may be formed by chemical vapor deposition or other suitable deposition methods.

[0129] In some embodiments, after the thin dielectric layer 207 is formed, a planarization process may be performed to reduce surface roughness and improve interface quality.

[0130] Fifth step: An opening 301 is formed above the thin dielectric layer 207 above the p-type nitride semiconductor layer 206, and a left thin dielectric layer 2071 and a right thin dielectric layer 2072 are formed on both sides of the opening 301, as follows. Figure 17 As shown.

[0131] The method for forming opening 301 may employ anisotropic dry etching.

[0132] In some embodiments, a combination of anisotropic dry etching and isotropic wet etching processes can also be used for etching.

[0133] An opening 301 is formed by etching the thin dielectric layer 207 and exposing the upper surface of the p-type nitride semiconductor layer 206, so that the gate metal 208 formed subsequently can form an ohmic contact with the p-type nitride semiconductor layer 206.

[0134] Step 6: A gate metal 208 is formed above the left thin dielectric layer 2071 and the opening 301, forming a structure as shown in the figure. Figure 3 The device shown.

[0135] The gate metal 208 may be formed by processes such as evaporation and sputtering, and patterned by processes such as photolithography, dry etching or wet etching to form the required gate pattern.

[0136] Those skilled in the art will understand that the above manufacturing steps only list the key steps and do not show the complete process for forming the device. Specific, detailed manufacturing steps can be derived from common manufacturing processes and general knowledge, and can be appropriately added to, subtracted from, or modified.

[0137] In some embodiments, such as in the second step, a functional layer, such as an AlN layer, may be inserted as needed between the channel layer 202 and the first barrier layer 203, and / or between the second right barrier layer 2042 and the capping layer 205, to increase the concentration of 2DEG.

[0138] In some embodiments, such as the manufacturing method of Embodiment 6, an additional step may be added after the third step to selectively etch the p-type nitride semiconductor layer 206 to form a first groove structure 400, and then remove the residual thin dielectric layer 207 on the mesa between the upper surfaces of the first groove structure 400.

[0139] Those skilled in the art should understand that the structural features and process details mentioned in the various embodiments of the present invention described above can be combined to form more embodiment device structures and manufacturing processes. It should be noted that the relevant process steps in the above embodiments can be appropriately increased or decreased to achieve the same effect. Those skilled in the art should recognize that the embodiments of the present invention described above are not limiting but exemplary, and the present invention can be implemented in a wider range than the above embodiments.

Claims

1. A gallium nitride high electron mobility transistor device, the device comprising a substrate layer at the bottom of the transistor device, a buffer layer above the substrate layer, a channel layer above the buffer layer, a first barrier layer above the channel layer, and a source metal, a second left barrier layer, a gate metal, a second right barrier layer, and a drain metal disposed sequentially from left to right above the first barrier layer, wherein the source metal is connected to the second left barrier layer, and the second right barrier layer is connected to the drain metal, characterized in that... A capping layer is provided above the second right barrier layer, and a p-type nitride semiconductor layer is provided above the capping layer. A right thin dielectric layer is provided above the drain metal, and the right thin dielectric layer extends to the left and upward at least to the right side wall of the capping layer. A left thin dielectric layer is provided above the source metal, and the left thin dielectric layer extends to the right and upward at least to the left side wall of the capping layer. An opening is reserved between the left and right thin dielectric layers. The gate metal is separated from the source metal, the second left barrier layer, the first barrier layer, the second right barrier layer, and the capping layer by the left thin dielectric layer. The gate metal extends upward along the left thin dielectric layer to the opening and forms an ohmic contact with the p-type nitride semiconductor layer. A two-dimensional electron gas is formed at the heterojunction between the channel layer and the first barrier layer. A two-dimensional hole gas is formed at the heterojunction between the second right barrier layer and the capping layer. The thickness of the left and right thin dielectric layers is between 5 nm and 50 nm. The upper surface of the p-type nitride semiconductor layer has one or more first groove structures extending along a first direction and periodically arranged along a second direction; and / or the upper surface of the p-type nitride semiconductor layer has a plurality of second groove structures extending along a second direction and periodically arranged along a first direction, and the gate metal is filled downward into the first groove structure and the second groove structure. The first groove structure and / or the second groove structure are of the type that is smaller at the top and larger at the bottom.

2. The gallium nitride high electron mobility transistor device as described in claim 1, characterized in that, The thickness of the first barrier layer is no greater than 8nm, and the thickness of the second left barrier layer and the second right barrier layer is no less than 20nm. The first barrier layer, the left thin dielectric layer and the gate metal constitute an enhancement-type MIS gate structure.

3. The gallium nitride high electron mobility transistor device as described in claim 1, characterized in that, The total length of the opening is less than the sum of the top width, the height of the left side wall, and the height of the right side wall of the p-type nitride semiconductor layer.

4. A gallium nitride high electron mobility transistor device as described in claim 1, characterized in that, The left side wall of the capping layer contracts inward, causing the widths of the second right barrier layer, the capping layer, and the p-type nitride semiconductor layer to decrease sequentially, resulting in the gate metal near the left side wall of the second right barrier layer, the capping layer, and the p-type nitride semiconductor having an inclined or stepped structure.

5. A gallium nitride high electron mobility transistor device as described in claim 1, characterized in that, Between the left and right thin dielectric layers above the p-type nitride semiconductor layer, there is one or more uniformly spaced thin dielectric layers, thereby forming one or more uniformly spaced openings.

6. A gallium nitride high electron mobility transistor device as described in claim 1, characterized in that, Above the opening of the p-type nitride semiconductor layer, there is also a gate metal with more than one spaced interval.

7. A gallium nitride high electron mobility transistor device as described in claim 6, characterized in that, When the device is in the off state, the first gate metal closest to the source metal has the same potential as the source metal, and then the potentials of the other gate metals are the same or increase sequentially, and the potentials of all the gate metals are between the potentials of the source metal and the drain metal.

8. A gallium nitride high electron mobility transistor device as described in claim 1, characterized in that, The opening is provided with a heavily doped p-type nitride semiconductor layer. The doping concentration of the heavily doped p-type nitride semiconductor layer is higher than that of the p-type nitride semiconductor layer, and its thickness is 3-10 nm.

9. A method for manufacturing a gallium nitride high electron mobility transistor device according to any one of claims 1 to 8, characterized in that, The manufacturing method includes the following steps: The first step is to provide a substrate layer, and then form a buffer layer, a channel layer, a first barrier layer, a second left barrier layer, and a second right barrier layer sequentially from bottom to top on the substrate layer. The second step is to form a capping layer and a p-type nitride semiconductor layer sequentially from bottom to top on the second right barrier layer; The third step is to form source metal and drain metal at both ends of the device, in the region above the first barrier layer, respectively. The fourth step is to form a thin dielectric layer on top of the device; The fifth step is to form an opening between the thin dielectric layers above the p-type nitride semiconductor layer to form a left thin dielectric layer and a right thin dielectric layer; The sixth step involves forming a gate metal over the left thin dielectric layer and the opening to form a gallium nitride high electron mobility transistor device.

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