An SOI_MOSFET device suitable for high temperature environment

Abstract

An SOI_MOSFET device suitable for high temperature environment, from bottom to top, a substrate layer, a back gate layer, a buried oxygen layer and a top silicon layer are sequentially arranged; the top silicon layer comprises source / drain doped extension region two, source / drain doped extension region one and channel region, source / drain doped extension region two and source / drain doped extension region one are located on both sides of the channel region; a gate dielectric layer is located on the top of the channel region, and a gate electrode is arranged on the top of the gate dielectric layer; the gate dielectric layer is symmetrically arranged with gate side wall one and gate side wall two on both sides of the gate electrode; the gate side wall one is in contact with the source / drain doped extension region two, and the gate side wall two is in contact with the source / drain doped extension region one. The application synchronously and significantly improves the threshold voltage stability, off-state leakage current and breakdown characteristic parameters of the device under high temperature without increasing additional process modules.

Description

Technical Field

[0001] This invention belongs to the field of SOI_MOSFET device technology, and specifically relates to an SOI_MOSFET device suitable for high-temperature environments. Background Technology

[0002] Fully Depleted Silicon-On-Insulator (FDSOI) technology, with its unique buried oxide layer isolation structure, can effectively suppress short-channel effects, reduce parasitic capacitance, improve device speed and latch-up resistance, and has good compatibility with mainstream silicon-based processes, making it a promising core device technology for the aforementioned high-end applications.

[0003] However, FDSOI devices are often used in harsh physical environments characterized by extreme temperatures, high radiation, and high power consumption. Especially under extreme high-temperature operating conditions of approximately 175°C (about 450K) and above, while FDSOI devices possess structural advantages, their electrical performance still faces the risk of severe systemic and synergistic degradation. Therefore, there is an urgent need for an FDSOI device structure scheme based on a collaborative optimization design approach for extreme high-temperature operating environments, along with a corresponding efficient performance evaluation method. This would enable the rapid design and accurate evaluation of high-performance, high-reliability FDSOI devices in high-temperature environments, thereby meeting the increasingly urgent needs of various fields for high-temperature semiconductor core devices.

[0004] Existing technologies primarily rely on iterative optimization based on traditional design rules. The core approach involves using TCAD (Technical Computer-Aided Design) simulation tools to simulate electrical characteristics at both room temperature (e.g., 300K) and high temperature (e.g., 450K) to assess performance degradation. For specific performance bottlenecks (e.g., high leakage current at high temperatures), single or a few parameters are adjusted independently and sequentially, resulting in a compromised design after multiple iterations. This approach depends on complex trade-offs between multiple degradation mechanisms, making it difficult to simultaneously achieve breakthroughs in multiple mutually constraining objectives such as high-temperature threshold stability, extremely low off-state leakage current, reliable breakdown, and high drive capability.

[0005] Current high-temperature performance issues of FDSOI devices are mainly addressed through independent parameter adjustments. For example, an FDSOI device and its manufacturing method disclosed in CN115498024A involves independent / single parameter adjustments, focusing only on the buried oxide layer thickness without coordinating optimization of the top silicon layer thickness, the concentration gradient of the lightly doped extension region, and the back gate doping. This results in a trade-off between self-heating effects and threshold voltage stability, as well as off-state current and breakdown characteristics at high temperatures. Furthermore, it cannot simultaneously suppress high-temperature multi-path leakage, such as inter-junction tunneling, subthreshold leakage, and source / drain edge leakage. It fails to systematically consider the inherent correlation and synergistic effects of different structural parameters in dealing with multiple physical effects at high temperatures. As a result, it heavily relies on engineer experience. Under the traditional design framework, the high-temperature performance improvement obtained through parameter fine-tuning is limited, making it difficult to overcome the comprehensive bottleneck of "synchronous degradation of various performance characteristics at high temperatures." This fails to meet the stringent requirements of "high stability, low power consumption, high reliability, and strong drive" for extreme high-temperature applications. Summary of the Invention

[0006] To overcome the shortcomings of the existing technology, the present invention aims to provide an SOI_MOSFET device suitable for high-temperature environments. This device is suitable for extreme high-temperature environments of about 450K. By synergistically and systematically setting the top silicon layer thickness, lightly doped extended region (LDD) doping profile, buried oxide layer thickness and back gate, a new electro-thermal balance is constructed at the device physical level. This simultaneously and significantly improves the threshold voltage stability, off-state leakage current and breakdown characteristics of the device at high temperatures without the need to add additional process modules.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows: An SOI_MOSFET device suitable for high-temperature environments, comprising a substrate layer, a back gate layer, a buried oxide layer, and a top silicon layer arranged sequentially from bottom to top; The top silicon layer includes a second source / drain doped extension region, a first source / drain doped extension region, and a channel region, with the second source / drain doped extension region and the first source / drain doped extension region located on both sides of the channel region. A grid electrode is installed above the channel region; Two grid sidewalls, namely, grid sidewall one and grid sidewall two, are symmetrically arranged on both sides of the grid electrode. The first gate sidewall is in contact with the second source / drain doped extension region, and the second gate sidewall is in contact with the first source / drain doped extension region.

[0008] A gate dielectric layer is disposed at the top of the channel region, and a gate electrode is disposed at the top of the gate dielectric layer. The gate dielectric layer includes an upper high dielectric constant gate dielectric layer and a lower gate oxide layer, wherein the material of the high dielectric constant gate dielectric layer is HfO2 and the material of the gate oxide layer is SiO2. The gate dielectric layer thickness is 2nm; The material of the first and second gate sidewalls is Si3N4 (silicon nitride); the thickness is 26nm.

[0009] The source / drain doped extension region 2 and source / drain doped extension region 1 are composed of a lightly doped extension region (LDD) and a heavily doped source / drain region (S / D). The doping distributions of the heavily doped source / drain region and the lightly doped extension region partially overlap in space, forming a doping concentration gradient structure away from the channel region: the region closer to the channel region is the lightly doped extension region with a lower concentration, and the region farther away from the channel region is the heavily doped source / drain region with a higher concentration.

[0010] The lightly doped extension region is located between the channel region and the heavily doped source / drain region. The doping concentration follows a Gaussian distribution, and the doping type is arsenic (As, n-type), with a peak concentration of 1 × 10⁻⁶. 20 cm -3 Vertically, its peak concentration is located at the interface between the top silicon layer and the gate dielectric layer (i.e., the silicon surface), and remains constant from this position down to the bottom of the gate dielectric layer, with a concentration of 1×10⁻⁶. 20 cm -3 Subsequently, the concentration decreases in a Gaussian distribution from that location towards the interface between the silicon layer and the buried oxide layer, dropping to 1×10 near the interface between the top silicon layer and the buried oxide layer. 15 cm -3 .

[0011] The heavily doped source / drain region is located outside the lightly doped extension region, i.e., on the side furthest from the channel region. The doping concentration follows a Gaussian distribution, the conductivity type is arsenic (As, n-type), and the peak concentration is higher than that of the lightly doped extension region (LDD), with a peak concentration of 4 × 10⁻⁶. 20 cm -3 .

[0012] The top silicon layer material is a boron-doped silicon layer with a concentration of 1×10⁻⁶. 14 cm -3 The thickness is 7-10 nm, and the boron to silicon doping ratio is 1:5×10⁻⁶. 8 The top silicon layer includes source / drain doped extension region II, source / drain doped extension region I, and the channel region, all of which are composed of the same boron-doped silicon layer, but functional partitioning is achieved through different doping concentrations.

[0013] The top silicon layer thickness is 8.5nm. The thickness of the top silicon layer is to ensure that the channel is always in a fully depleted state at high temperatures above 450K, suppressing the body effect and parasitic bipolar transistor conduction. If the thickness is too large, the threshold voltage Vth will drift severely, and if the thickness is too small, the drive current will decrease significantly.

[0014] The buried oxide layer is SiO2 with a thickness of 12-18 nm. The thickness of the buried oxide layer is to achieve a balance between high-temperature self-heating benefits, leakage current isolation and back gate coupling control. If the thickness is too small, the leakage current will increase, and if the thickness is too large, the heat accumulation will be serious.

[0015] The back gate layer is a boron-doped silicon layer with a boron doping concentration of 1×10⁻⁶. 18 cm -3 Up to 5×10 18 cm -3 The thickness is 25nm. The back gate layer of the present invention forms a stable built-in potential through a specific doping concentration, which is used to construct a dual potential constraint structure in conjunction with the front gate. This design avoids leakage and drift problems of the back gate bias circuit at high temperature and improves the reliability of high temperature applications.

[0016] The substrate is a boron-doped silicon layer with a boron doping concentration of 1×10⁻⁶. 14 cm -3 The thickness is 150nm.

[0017] The beneficial effects of this invention are: This invention is applicable to extreme high temperatures of 450K and realizes multiple degradation mechanisms at high temperatures.

[0018] In this invention, the buried oxide layer insulation cuts off the leakage path between the source / drain region and the substrate. At high temperatures, the concentration of intrinsic carriers will increase sharply. Typical bulk silicon devices will fail due to reverse leakage at the source / drain-substrate junction. However, in this application, the FDSOI device does not have this junction, thus fundamentally eliminating the largest leakage path.

[0019] The ultrathin top silicon layer in this invention has a full depletion characteristic. The 8.5nm top silicon layer keeps the channel region in a depleted state at all times, which largely eliminates the body effect. This means that the threshold voltage is not sensitive to the back gate bias and suppresses the conduction of parasitic bipolar transistors.

[0020] In this invention, the front gate and back gate work together to enhance the control of the channel region. The back gate layer in the FDOSI structure is equivalent to a dual potential constraint structure with front gate and back gate working together, which enhances the gate's control over the channel region. At high temperatures, the channel is less prone to punch-through effect, thus maintaining good short-channel effect suppression capability.

[0021] In this invention, the lightly doped extended region (LDD) is a physical gradient that reduces the junction electric field and junction leakage current. The doping concentration changes gradually from the edge of the channel region to the source / drain end, with the peak value close to the surface. This causes the peak electric field of the junction depletion region to decrease, thereby suppressing field-enhanced tunneling and thermal emission leakage and reducing junction leakage current.

[0022] In this invention, the lightly doped channel region reduces threshold voltage temperature drift and avoids the floating body effect, which is the physical support for achieving high-temperature threshold voltage stability and reducing off-state current.

[0023] The FDSOI structure fundamentally improves the high-temperature reliability of the device from a physical structure perspective. This is because the ultrathin fully depleted top silicon layer limits the longitudinal expansion of the high electric field region at the drain end within the silicon film, thereby shortening the acceleration distance of carriers in a strong electric field and reducing the probability of them acquiring enough energy to trigger impact ionization. The gradient doping and light doping extension regions reduce the peak electric field at the source / drain junction edge, the buried oxide layer cuts off the junction path and limits the expansion of the depletion layer, and the back gate region enhances the dual-gate potential constraint. These factors physically suppress the generation of impact ionization and avalanche multiplication feedback under high temperature and high bias. Therefore, it effectively suppresses the impact ionization effect that leads to a decrease in breakdown voltage and degradation of hot carriers at high temperatures, enabling the device to still have a wide safe operating area and stable "hard" breakdown characteristics at 450K. This FDSOI structure limits the longitudinal expansion of the high electric field region at the drain end within the silicon film through an ultrathin fully depleted top silicon layer. This shortens the acceleration distance of carriers in a strong electric field, reducing the probability that they will acquire enough energy to trigger impact ionization. The gradient doping and light doping extension regions reduce the peak electric field at the source / drain junction edge. The buried oxide layer cuts off the junction path and limits the expansion of the depletion layer. The back gate region enhances the dual-gate potential constraint. These measures physically suppress the generation of impact ionization and avalanche multiplication feedback under high temperature and high bias. Therefore, it effectively suppresses the impact ionization effect that leads to a decrease in breakdown voltage and degradation of hot carriers at high temperatures, enabling the device to still have a wide safe operating area and stable "hard" breakdown characteristics at 450K.

[0024] This invention also possesses excellent process compatibility and industrialization potential, requiring no additional non-standard or complex process modules, and is easily integrated into the design and manufacturing processes of modern integrated circuits, exhibiting strong industrial application reliability and promotional value. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of an NMOS FDSOI device.

[0026] Figure 2 This is a schematic diagram comparing the transfer characteristics at 300K and 450K.

[0027] Figure 3 This is a diagram comparing the breakdown characteristics at 300K and 450K.

[0028] Figure 4 This is the simulation circuit diagram for the FDSOI device. Detailed Implementation

[0029] The present invention will now be described in further detail with reference to the accompanying drawings.

[0030] This invention discloses an SOI_MOSFET device suitable for high-temperature environments, with reference to... Figure 1 This is a schematic cross-sectional view of the FDSOI MOSFET device of the present invention. The device includes: a gate electrode 7, a first gate sidewall 5, a second gate sidewall 6, a gate dielectric layer 3, a high dielectric constant gate dielectric layer 4, a top silicon layer, a channel region 8, a second source / drain doped extension region 2, a first source / drain doped extension region 1, a buried oxide layer 9, a back gate layer 10, and a substrate 11.

[0031] Among them, gate sidewall 5 and gate sidewall 6 are made of Si3N4 with a thickness of 26 nm; the gate dielectric layer is made of HfO2+SiO2 with a thickness of 2 nm; and the top silicon layer is a boron-doped silicon layer with a concentration of 1×10⁻⁶. 14 cm -3 The thickness is 8.5 nm; the lightly doped extended region (LDD) material is an arsenic (As) implanted silicon-arsenic (As) implanted Gaussian doping distribution with the peak located on the silicon surface, a junction depth of 3 nm, and a peak concentration of 1 × 10⁻⁶. 20 cm -3 At a depth of 3 nm, the concentration decreased to 1 × 10⁻⁶. 15 cm -3 This forms lightly doped extension regions, where source / drain doped extension region 2 and source / drain doped extension region 1 are defined as silicon material, with a default silicon atom concentration of 5 × 10⁻⁶. 22 cm -3 In this LDD structure, the arsenic to silicon doping ratio is 1:500 at the doping peak, decreasing to 1:5×10 at a depth of 3 nm. 7 The heavily doped source / drain regions (S / D) are implanted with As (As) silicon, with a peak doping concentration of 4 × 10⁻⁶. 20 cm -3 The doping ratio of arsenic to silicon is 1:125. The material of the buried oxide layer 9 is SiO2, which is usually high-purity SiO2 obtained by thermal oxidation or deposition. Its main function is electrical isolation and stress transfer, so it is undoped and has a thickness of 15nm. The back gate layer 10 is a boron-doped silicon layer with a concentration of 2 × 10⁻⁶. 18 cm -3 The thickness is 25nm; the doping ratio of boron to silicon is 1:25000. Substrate 11 is a boron-doped silicon layer with a concentration of 1×10⁻⁶. 14 cm -3 The thickness is 150 nm, and the boron to silicon doping ratio is 1:5 × 10⁻⁶. 8 .

[0032] The above parameters are all optimized preferred values. In actual processes, the silicon layer thickness can be 7–10 nm, the buried oxide layer 9 thickness can be 12–18 nm, and the back gate layer 10 doping can be 1×10¹. 8 –5×10¹ 8 cm - Adjustments within the range of 3 can still achieve the high-temperature synergistic optimization effect of this invention.

[0033] refer to Figure 2 This is a schematic diagram comparing the transfer characteristics (Ids-Vg) of the FDSOI MOSFET device of the present invention at 300K and 450K; the horizontal axis represents the gate voltage, and the vertical axis represents the drain current, demonstrating the temperature stability of the saturation current. Figure 2 As shown, the saturation current I of this device increases with temperature over a wide temperature range from 300K to 450K. sat It shows a slight downward trend, decreasing from 2.757mA to 2.39mA, with a total attenuation of 13.3%, corresponding to a temperature coefficient of -887ppm / K.

[0034] refer to Figure 3 This is a schematic diagram comparing the breakdown characteristics of the FDSOI MOSFET device of the present invention at 300K and 450K; the horizontal axis represents the drain voltage and the vertical axis represents the drain current, clearly showing the stability of the breakdown voltage and the controlled increase of the breakdown current. like Figure 3 Within a wide temperature range from room temperature (300K) to high temperature (450K), the breakdown voltage of the device remains at around 58V with a drift of only 1.8%. Compared to the significant drop in breakdown voltage that traditional bulk silicon devices typically exhibit at high temperatures, this device effectively solves the technical problem of device withstand voltage reliability degradation under high temperature conditions. At the same time, the breakdown current exhibits a controlled linear increase with increasing temperature, ensuring the robustness of the device under different ambient temperatures.

[0035] Figure 4 The simulation circuit diagram used for this device in the Sentaurus simulation tool is used to study its transfer characteristic curve and transfer characteristic curve by adopting the form of fixed gate voltage of FDSOI device. The source and substrate of the FDSOI device are grounded, and the gate-source voltage is set to a fixed value, with a fixed scan from 0V to 5V. A load resistor is connected in series between the drain and ground to simulate normal device operation, and the initial internal temperature of the device is set to 300K. The simulation target is the electrical parameter characteristics of the device, and the specific results are as follows. Figure 2 , Figure 3 As shown.

[0036] The thickness of the top silicon layer is set to approximately 8.5 nm, and the channel region is lightly doped or intrinsically doped. The synergistic effect of this design is that the ultra-thin thickness (8.5 nm) ensures that the channel remains in a fully depleted state at high temperatures, effectively suppressing the negative threshold voltage drift and subthreshold slope degradation caused by the increase in intrinsic carrier concentration; at the same time, the low intrinsic doping minimizes ionized impurity scattering, which helps maintain a high carrier mobility at high temperatures and alleviates drive current degradation.

[0037] The lightly doped source / drain extension regions have specific doping profiles, with a peak doping concentration of approximately 1 × 10⁻⁶. 20 cm -3 The junction depth is approximately 3 nm. Despite a high peak concentration, it rapidly decays to 1 × 10⁻⁶ within 3 nm. 15 cm -3 This creates a steep doping gradient, which physically mitigates the junction electric field. The key to this design lies in the heavily doped source / drain regions in source / drain doping extension regions 2 and 1, which serve as the primary carrier supply regions. Their extremely high doping concentration ensures low ohmic contact resistance, avoiding high-voltage thermal effects caused by excessive series resistance and guaranteeing the device's thermal stability under high current. The adjacent lightly doped extension region absorbs most of the source-drain voltage drop, effectively blocking the direct transmission of the drain potential to the channel. This is because the smooth doping concentration gradient between the heavily and lightly doped regions significantly alleviates the electric field concentration near the drain. At high temperatures, this effectively reduces the generation rate of high-energy carriers and impact ionization effects, thereby simultaneously improving the stability of off-state leakage current and breakdown voltage, preventing "soft breakdown."

[0038] The thickness of the buried oxide layer 9 is optimized to approximately 15 nm. This thickness is the result of a trade-off between self-heating effects (heat dissipation), suppression of parasitic bipolar transistor effects, and substrate coupling. Too thick a layer hinders heat dissipation, while too thin a layer reduces isolation effectiveness. Meanwhile, the back gate layer 10 has a doping concentration of approximately 2 × 10⁻⁶. 18 cm -3 The highly doped silicon layer. Due to the smooth doping gradient design in the source / drain doping extension region 2 and source / drain doping extension region 1, the depletion-mode distribution below the channel region 8 will be more uniform. If an independent bias voltage is applied to the back gate layer 10, the electric field can pass through the buried oxide layer 9 uniformly and shift the Fermi level in the channel region 8, thereby achieving continuous fine-tuning of the threshold voltage without affecting the distortion of the local electric field. This will ensure that the switching voltage window of the device remains consistent at 300K and 450K, solving the problem of increased leakage current at high temperatures.

[0039] The gate dielectric layer is preferably made of a high-k material (such as HfO2), with an equivalent oxide layer thickness (EOT) of about 1 nm, to enhance gate control capability and further suppress short-channel effects and leakage current.

[0040] This invention provides a method for optimizing the structure of FDSOI devices in extreme high-temperature environments of 450K. By collaboratively setting key parameters such as top silicon layer thickness, lightly doped extended region (LDD) doping profile, buried oxide layer thickness, and back gate concentration, the method systematically and synchronously improves the device's threshold voltage stability, off-state characteristics, breakdown reliability, and drive current retention rate at high temperatures. This method provides a clear optimization path and parameter benchmark for the design of FDSOI devices for high-temperature and high-reliability applications.

[0041] This invention proposes a set of optimized combinations of specific structural parameters, including: an ultrathin and lightly doped / intrinsically doped top silicon channel of approximately 8.5 nm, and a peak concentration of approximately 1 × 10⁻⁶. 18 cm -3 Furthermore, it has a gradient lightly doped extension region (LDD) with a junction depth of approximately 3 nm, a buried oxide layer 9 with a thickness of approximately 15 nm, and a doping concentration of approximately 2 × 10⁻⁶. 18 cm -3 The back gate layer 10. This combination aims to physically synergistically suppress multiple degradation effects such as intrinsic carrier surge, electric field concentration, and intensified collisional ionization at high temperatures, and is the intrinsic core for achieving high performance at high temperatures.

[0042] This invention provides a method for designing the structure of an FDSOI MOSFET device suitable for extreme high-temperature environments of 450K, through a specific optimized combination of structural parameters (approximately 8.5nm ultrathin intrinsic / lightly doped channel, approximately 1×10⁻⁶…). 20 cm -3 A gradient LDD of approximately 3 nm, a buried oxide layer of approximately 15 nm, and approximately 2 × 10⁻⁶ nm. 18 cm -3 For the back gate, the above parameters are optimized preferred values. In actual processes, the top silicon layer thickness can be 7-10 nm, the buried oxide layer thickness can be 12-18 nm, and the back gate layer doping can be 1×10⁻⁶. 18 cm -3 Up to 5×10 18 cm -3 Adjustments can be made within a certain range to still achieve the high-temperature synergistic optimization effect of this invention.

[0043] Through the aforementioned collaborative optimization design, this invention enables FDSOI devices to achieve a breakthrough improvement in overall performance at a high temperature of 450K. Specifically, this is manifested in: a significant reduction in threshold voltage drift (approximately -0.153V) while maintaining enhancement mode; and an extremely low off-state current (Ioff) (approximately 7.02 × 10⁻⁶). -8(A / μm); breakdown characteristics maintain "hard" breakdown behavior with good stability; low saturation drive current degradation rate (approximately 13.3%). This effectively solves the problem of insufficient performance in traditional compromise designs, providing a highly reliable device foundation for high-temperature integrated circuits.

Claims

1. An SOI_MOSFET device suitable for high-temperature environments, characterized in that, The substrate layer (11), back gate layer (10), buried oxide layer (9) and top silicon layer are arranged sequentially from bottom to top; The top silicon layer includes a second source / drain doped extension region (2), a first source / drain doped extension region (1), and a channel region (8). The second source / drain doped extension region (2) and the first source / drain doped extension region (1) are located on both sides of the channel region (8). The gate electrode (7) above the channel region (8); The grid electrode (7) is symmetrically arranged with grid sidewall 1 (5) and grid sidewall 2 (6) on both sides. The first gate sidewall (5) is in contact with the second source / drain doped extension region (2), and the second gate sidewall (6) is in contact with the first source / drain doped extension region (1).

2. The SOI_MOSFET device suitable for high-temperature environments according to claim 1, characterized in that, The top of the channel region (8) is provided with a gate dielectric layer, and the gate electrode (7) is provided on the top of the gate dielectric layer. The gate dielectric layer includes an upper high dielectric constant gate dielectric layer (4) and a lower gate oxide layer (3), wherein the material of the high dielectric constant gate dielectric layer (4) is HfO2, and the material of the gate oxide layer (3) is SiO2. The gate dielectric layer thickness is 2nm; The material of the first gate sidewall (5) and the second gate sidewall (6) is Si3N4; the thickness is 26nm.

3. The SOI_MOSFET device suitable for high-temperature environments according to claim 1, characterized in that, The source / drain doped extension region two (2) and the source / drain doped extension region one (1) are composed of a lightly doped extension region and a heavily doped source / drain region. The doping distribution of the heavily doped source / drain region and the lightly doped extension region partially overlaps in space, forming a doping concentration gradient structure away from the channel region (8): the region close to the channel region (8) is the lightly doped extension region with a lower concentration, and the region away from the channel region (8) is the heavily doped source / drain region with a higher concentration.

4. The SOI_MOSFET device suitable for high-temperature environments according to claim 3, characterized in that, The lightly doped extension region is located between the channel region (8) and the heavily doped source / drain region. The doping concentration follows a Gaussian distribution, the doping type is arsenic, and the peak concentration is 1×10⁻⁶. 20 cm -3 Vertically, its peak concentration is located at the interface between the top silicon layer and the gate dielectric layer, and remains constant from this position down to the bottom of the gate dielectric layer, with a concentration of 1×10⁻⁶. 20 cm -3 Subsequently, the concentration decreases in a Gaussian distribution from that location towards the interface between the silicon layer and the buried oxide layer, dropping to 1×10 near the interface between the top silicon layer and the buried oxide layer. 15 cm -3 .

5. The SOI_MOSFET device suitable for high-temperature environments according to claim 3, characterized in that, The heavily doped source / drain region is located outside the lightly doped extension region, i.e., on the side away from the channel region (8). The doping concentration follows a Gaussian distribution, the conductivity type is arsenic, and the peak concentration is higher than that of the lightly doped extension region, with a peak concentration of 4 × 10⁻⁶. 20 cm -3 .

6. The SOI_MOSFET device suitable for high-temperature environments according to claim 1, characterized in that, The top silicon layer material is a boron-doped silicon layer with a concentration of 1×10⁻⁶. 14 cm -3 The thickness is 7-10 nm, and the boron to silicon doping ratio is 1:5×10. 8 .

7. The SOI_MOSFET device suitable for high-temperature environments according to claim 6, characterized in that, The thickness of the top silicon layer is 8.5 nm.

8. The SOI_MOSFET device suitable for high-temperature environments according to claim 1, characterized in that, The buried oxide layer (9) is SiO2 with a thickness of 12-18 nm.

9. The SOI_MOSFET device suitable for high-temperature environments according to claim 1, characterized in that, The back gate layer (10) is a boron-doped silicon layer with a boron doping concentration of 1×10⁻⁶. 18 cm -3 Up to 5×10 18 cm -3 The thickness is 25nm.

10. The SOI_MOSFET device suitable for high-temperature environments according to claim 1, characterized in that, The substrate (11) is a boron-doped silicon layer with a boron doping concentration of 1×10⁻⁶. 14 cm -3 The thickness is 150nm.

Images