Power device and manufacturing method, power module, power conversion circuit, and vehicle

Abstract

The application provides a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The power device comprises: a semiconductor body comprising a well region, a first region and a second region, and a first surface provided with a gate trench; the first region is of a first conductivity type and is located at the first surface; the second region is of a second conductivity type; the second region extends from the bottom of the gate trench to the sidewall of the gate trench and covers part of the sidewall; the second region comprises an inclined portion arranged at a corner of the gate trench, the inclined portion is arranged obliquely relative to the sidewall of the gate trench, and the inclined portion comprises a first end adjacent to the first surface and a second end adjacent to a second surface, and in a first direction, the second end is farther away from the sidewall of the gate trench than the first end. The application can improve the breakdown voltage of the device and improve the reliability of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a power device and its fabrication method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) have evolved from planar to trench types. By improving the gate structure, the direction of current flow on the gate has changed from planar to vertical. However, due to the poor protection of the gate by the gate oxide layer, the gate oxide electric field is very strong in the blocking state, which can easily lead to device breakdown and affect long-term reliability. Summary of the Invention

[0003] This application provides a power device and its fabrication method, a power module, a power conversion circuit, and a vehicle, to improve the breakdown voltage of the device and enhance its reliability.

[0004] According to one aspect of this application, a power device is provided, comprising: A semiconductor body includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region, a first region, and a second region. The first surface is provided with a gate trench. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. The second region is configured with a second conductivity type. The second region extends from the bottom of the gate trench to the sidewall of the gate trench, covering a portion of the sidewall of the gate trench. The second region includes an inclined portion disposed at a corner of the gate trench. The inclined portion is inclined relative to the sidewall of the gate trench, and the inclined portion includes a first end adjacent to the first surface and a second end adjacent to the second surface. Along a first direction, the second end is further away from the sidewall of the gate trench than the first end. Along the first direction, the well region is disposed on one or both sides of the gate trench, and the first conductivity type and the second conductivity type are different. The gate is located within the gate trench; A source electrode is located on the first surface, and the source electrode is connected to the first region; The drain electrode is located on the second surface.

[0005] Optionally, the second region further includes a first main body portion and a connecting portion, wherein the first main body portion extends from the bottom of the gate trench to the sidewall of the gate trench, covering a portion of the sidewall of the gate trench; and the connecting portion extends from the first surface to the sidewall of the gate trench and is connected to the first main body portion.

[0006] Optionally, the semiconductor body further includes a third region, the third region being configured with a first conductivity type, the third region being disposed within the second region, and / or disposed within the region enclosed by the second region and the gate trench.

[0007] Optionally, the second region includes a second main body and a connecting portion, the second main body extending from the bottom of the gate trench to the sidewall of the gate trench, covering a portion of the sidewall of the gate trench; the connecting portion extending from the first surface to the sidewall of the gate trench and connected to the second main body. The semiconductor body further includes a third region, which is configured with a first conductivity type; the third region is disposed within the second main body portion, and / or within the area enclosed by the second main body portion and the gate trench.

[0008] Optionally, the third region and the connecting portion are arranged alternately along the second direction; wherein the second direction is perpendicular to the first direction and the third direction, and the third direction is the direction from the first surface to the second surface.

[0009] Optionally, the second region includes a first sub-region and a second sub-region that are interconnected, and the third region includes a third sub-region and a fourth sub-region; The first sub-region is located at the corner of the gate trench, and the second sub-region is located at the bottom of the gate trench; the first sub-region is the inclined portion. The third sub-region is located within the area enclosed by the first sub-region and the corner of the gate trench; the fourth sub-region is located within the second sub-region.

[0010] Optionally, the angle between the line connecting the geometric centers of the first sub-region and the third sub-region and the sidewall of the gate trench is greater than 0, and along the first direction, the geometric center of the first sub-region is farther away from the gate trench than the geometric center of the third sub-region.

[0011] Optionally, the first main body includes a first preset sub-region and a second preset sub-region that are interconnected; the first preset sub-region covers the corner of the gate trench, and the second preset sub-region is disposed at the bottom of the gate trench; the first preset sub-region is the inclined portion.

[0012] According to another aspect of this application, a power module is provided, including a substrate and at least one power device as described in any embodiment of this application, wherein the substrate is used to carry the power device.

[0013] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one power device as described in any embodiment of this application, the power device being electrically connected to the circuit board.

[0014] According to another aspect of this application, a vehicle is provided, including a load and a power conversion circuit as described in any embodiment of this application, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0015] According to another aspect of this application, a method for fabricating a power device is provided, comprising: A semiconductor body is provided, the semiconductor body being configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other, the semiconductor body further including a well region, a first region, and a second region, the first surface being provided with a gate trench; the first region being configured with a first conductivity type and located on the first surface; the well region being configured with a second conductivity type and located on the side of the first region away from the first surface; the second region being configured with a second conductivity type; the second region extending from the bottom of the gate trench to the sidewall of the gate trench, covering a portion of the sidewall of the gate trench; the second region including an inclined portion disposed at a corner of the gate trench, the inclined portion being inclined relative to the sidewall of the gate trench, and the inclined portion including a first end adjacent to the first surface and a second end adjacent to the second surface, the second end being further away from the sidewall of the gate trench relative to the first end along a first direction; wherein, along the first direction, the well region is disposed on one or both sides of the gate trench, and the first conductivity type and the second conductivity type are different; A gate is disposed within the gate trench; A source electrode is disposed on the first surface; wherein the source electrode is connected to the first region; A drain electrode is provided on the second surface.

[0016] Optionally, a semiconductor body is provided, including: A semiconductor structure layer is provided, wherein the semiconductor structure layer includes the well region and the first region, and the first surface of the semiconductor structure layer is further provided with the gate trench; A first mask layer is disposed within the gate trench and on the first surface of the semiconductor structure layer; wherein the first mask layer encloses a first sub-layer and a second sub-layer, the first sub-layer covers the first surface of the semiconductor structure layer, and the second sub-layer is disposed on the sidewall of the gate trench, extending from the first surface of the semiconductor structure layer to a first predetermined position on the sidewall of the gate trench; A first preset sub-region and a third sub-region with the opposite conductivity type to the first preset sub-region are formed at the corner of the gate trench. The portion of the first preset sub-region that is retained after the formation of the third sub-region is the first sub-region. A second preset sub-region and a fourth sub-region with the opposite conductivity type to the second preset sub-region are formed at the bottom of the gate trench. The portion of the second preset sub-region that is retained after the fourth sub-region is formed is called the second sub-region. The second region includes the first sub-region and the second sub-region that are connected to each other. The first sub-region is the inclined portion. The third region includes the third sub-region and the fourth sub-region. The third sub-region is located in the region enclosed by the first sub-region and the trench corner of the gate trench. The fourth sub-region is located within the second sub-region. Remove the first mask layer; A first predetermined sub-region and a third sub-region with the opposite conductivity type to the first predetermined sub-region are formed at the corner of the gate trench, including: The first preset sub-region is formed by doping the trench corner of the gate trench using a halo implantation process; The third sub-region is formed by doping the region adjacent to the gate trench of the first preset sub-region using a halo implantation process.

[0017] Optionally, a first mask layer is formed within the gate trench and on the first surface of the semiconductor structure layer, including: A first sublayer is formed on the first surface of the semiconductor structure layer; An intermediate layer is formed at the bottom of the gate trench, the intermediate layer extending from the bottom of the gate trench to a first predetermined position on the sidewall of the gate trench; A second sublayer is formed on the sidewall of the gate trench; Remove the intermediate layer.

[0018] Optionally, a semiconductor body is provided, including: A semiconductor structure layer is provided, wherein the semiconductor structure layer includes the well region and the first region, and the first surface of the semiconductor structure layer is further provided with the gate trench; A second mask layer is disposed within the gate trench and on the first surface of the semiconductor structure layer; wherein the second mask layer includes a first sub-layer and a fourth sub-layer, the first sub-layer covers the first surface of the semiconductor structure layer, the fourth sub-layer is disposed on the sidewall of the gate trench, extending from the first surface to a first predetermined position on the sidewall of the gate trench, the fourth sub-layer includes at least one opening, the opening exposing a predetermined area of ​​the sidewall of the gate trench, the predetermined area extending from the first surface of the semiconductor structure layer to the bottom of the gate trench; A first preset sub-region and a connecting portion are formed at the corner and sidewall of the gate trench; wherein, the first preset sub-region is disposed at the corner of the gate trench, and the connecting portion extends from the first surface to the sidewall of the gate trench and is connected to the first preset sub-region. A second preset sub-region is formed at the bottom of the gate trench; wherein the second region includes a first main body and a connecting part, the first main body includes the first preset sub-region and the second preset sub-region connected to each other; the first preset sub-region is the inclined part; Remove the second mask layer; A first predetermined sub-region and the connecting portion are formed at the corner and sidewall of the gate trench, including: The gate trench corners and sidewalls are doped using a halo implantation process to form a first preset sub-region and the connection portion.

[0019] Optionally, a second mask layer is formed within the gate trench and on the first surface of the semiconductor structure layer, including: A first sublayer is formed on the first surface of the semiconductor structure layer; An intermediate layer is formed at the bottom of the gate trench, the intermediate layer extending from the bottom of the gate trench to a first predetermined position on the sidewall of the gate trench; A second sublayer is formed on the sidewall of the gate trench; The second sublayer is patterned to form the fourth sublayer; Remove the intermediate layer. The semiconductor body of this embodiment includes a well region, a first region, and a second region. A gate trench is formed on the first surface. The second region is configured with a second conductivity type. The second region extends from the bottom of the gate trench to the sidewall of the gate trench. The second region includes an inclined portion disposed at the corner of the gate trench. The inclined portion is inclined relative to the sidewall of the gate trench. Along the first direction, the second end is further away from the sidewall of the gate trench than the first end, allowing the second region to cover more of the sidewall of the gate trench. When the device is reverse-biased, the second region can suppress the high electric field at the bottom and corner of the gate trench, preventing local breakdown of the gate insulating layer, increasing the breakdown voltage of the device, and improving the reliability of the device.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a three-dimensional schematic diagram of a power device provided in an embodiment of this application.

[0023] Figure 2 This is a cross-sectional schematic diagram of a power device provided in an embodiment of this application.

[0024] Figure 3 This is a cross-sectional schematic diagram of another power device provided in an embodiment of this application.

[0025] Figure 4 This is a top view schematic diagram of a semiconductor device provided in an embodiment of this application.

[0026] Figure 5 This is a flowchart of a method for fabricating a power device according to an embodiment of this application.

[0027] Figures 6-10 This is a diagram illustrating the formation process of a semiconductor structure layer.

[0028] Figures 11-13 This is a schematic diagram of the formation of the first mask layer.

[0029] Figure 14 This is a schematic diagram of the formation of the second preset sub-region.

[0030] Figure 15 This is a schematic diagram of the formation of the third sub-region.

[0031] Figure 16 This is a schematic diagram of the formation of the fourth sub-region.

[0032] Figure 17 This is a schematic diagram after the first mask layer has been removed.

[0033] Figure 18 This is a schematic diagram after the insulating layer and gate are formed.

[0034] Figure 19 This is a schematic diagram of the formation of the interlayer medium layer.

[0035] Figure 20 This is a schematic diagram of the source electrode formation.

[0036] Figure 21 This is a top view of the gate trench and the fourth sublayer.

[0037] Figure 22 yes Figure 21 A cross-sectional view along section line CC.

[0038] Figure 23 This is a schematic diagram of the formation of the second preset sub-region.

[0039] Figure 24 This is a schematic diagram after the second mask layer has been removed. Detailed Implementation

[0040] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0041] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0042] This application provides a power device. Figure 1 This is a three-dimensional schematic diagram of a power device provided in an embodiment of this application. Figure 2 This is a cross-sectional schematic diagram of a power device provided in an embodiment of this application. Figure 3 This is a cross-sectional schematic diagram of another power device provided in an embodiment of this application, with reference to... Figures 1-3 Power devices include: The semiconductor body 10, configured for a first conductivity type, includes a first surface 101 and a second surface 102 disposed opposite to each other. The semiconductor body also includes a well region 15, a first region 11, and a second region 12. The first surface 101 has a gate trench 16. The first region 11 is configured for the first conductivity type and is located on the first surface 101. The well region 15 is configured for the second conductivity type and is located on the side of the first region 11 away from the first surface 101. The second region 12 is configured for the second conductivity type and extends from the bottom of the gate trench 16 to the gate. The sidewall of the trench 16 covers a portion of the sidewall of the gate trench 16; the second region 12 includes an inclined portion 1, which is disposed at the corner of the gate trench 16. The inclined portion 1 is inclined relative to the sidewall of the gate trench 16, and the inclined portion 1 includes a first end adjacent to the first surface 101 and a second end adjacent to the second surface 102. Along the first direction X, the second end is further away from the sidewall of the gate trench 16 than the first end; wherein, along the first direction X, the well region 15 is disposed on one or both sides of the gate trench 16, and the first conductivity type and the second conductivity type are different.

[0043] Gate 20 is located within gate trench 16.

[0044] Source electrode 30 is located on the first surface 101 and is connected to the first region 11.

[0045] Drain 40 is located on the second surface 102.

[0046] The power device can be a metal-oxide-semiconductor field-effect transistor (MOSFET) device. One of the first conductivity type and the second conductivity type is N-type and the other is P-type. If the device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, the well region 15 can be a P-type well region, the first region 11 can be an N+ source region, the second region 12 can be a P-region, and the third region 13 can be an N-region. If the device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type. The semiconductor body 10 can be made of silicon carbide (SiC), and the power device in this embodiment can be a SiC MOSFET device. The gate 20 can be made of polysilicon, and the source 30 and drain 40 can be made of metal materials; for example, the metal material includes aluminum. The first direction X is the width direction of the gate trench 16.

[0047] Specifically, the inclined portion 1 is inclined relative to the sidewall of the gate trench 16, and along the first direction X, the second end is further away from the sidewall of the gate trench 16 than the first end, so that the inclined portion 1 can cover more of the sidewall of the gate trench 16. When the voltage difference between the source 30 and the gate 20 meets the conduction condition, a conductive channel is formed in the area where the well region 15 contacts the gate trench 16, and the device is forward-conducting. When the voltage difference between the source 30 and the gate 20 does not meet the conduction condition, the device is reverse-blocked. The second region 12 extends from the bottom of the gate trench 16 to the sidewall of the gate trench 16. The second region 12 can suppress the high electric field at the bottom and corner of the gate trench 16, avoid local breakdown of the gate insulating layer, and improve the breakdown voltage of the device.

[0048] The semiconductor body of this application embodiment includes a well region 15, a first region 11, and a second region 12. A gate trench 16 is provided on the first surface 101. The second region 12 is configured with a second conductivity type. The second region 12 extends from the bottom of the gate trench 16 to the sidewall of the gate trench 16. The second region 12 includes an inclined portion 1, which is disposed at the corner of the gate trench 16. The inclined portion 1 is inclined relative to the sidewall of the gate trench 16. Along the first direction X, the second end is further away from the sidewall of the gate trench 16 than the first end, so that the second region 12 can cover more of the sidewall of the gate trench 16. When the device is reverse blocked, the second region 12 can suppress the high electric field at the bottom and corner of the gate trench 16, avoid local breakdown of the gate insulating layer, improve the breakdown voltage of the device, and improve the reliability of the device.

[0049] Based on the above embodiments, optionally, refer to Figure 1 and Figure 2 The semiconductor body 10 also includes a third region 13, which is configured with a first conductivity type; the third region 13 is disposed within the second region 12, and / or disposed within the region enclosed by the second region 12 and the gate trench 16.

[0050] Specifically, the second region 12 and the third region 13 completely cover the bottom and corners of the gate trench 16. The third region 13 is used for carrier interaction with the second region 12, such as receiving holes from the second region 12 or providing holes to the second region 12, to maintain the stability and reliability of the device. For example, when the potential of the drain 40 is higher than the potential of the source 30, the holes in the second region 12 and the electrons in the third region 13 form electron-hole pairs, thereby suppressing hole accumulation and avoiding excessive local electric field; when the potential of the source 30 is higher than the potential of the drain 40, the electrons in the third region 13 are separated through electron-hole pairs, sending the holes back to the second region 12, thereby maintaining the charge balance of the second region 12, preventing charge drift or potential shift, and thus maintaining the stability and reliability of the device.

[0051] refer to Figure 3 Based on the above embodiments, optionally, the second region 12 includes a first main body 02 and a connecting part 17. The first main body 02 extends from the bottom of the gate trench 16 to the sidewall of the gate trench 16, covering part of the sidewall of the gate trench 16. The connecting part 17 extends from the first surface 101 to the sidewall of the gate trench 16 and is connected to the first main body 02.

[0052] Specifically, the connection portion 17 can be a P-region. When the semiconductor body 10 includes the connection portion 17, the connection portion 17 extends through the sidewall of the gate trench 16 to the first surface 101 and is connected to the source 30. The first body portion 02 covers the bottom and corners of the gate trench 16. When the device is reverse blocked, the potential of the source 30 is zero, and the first body portion 02 is connected to the source 30 through the connection portion 17. The potentials of the connection portion 17 and the first body portion 02 are zero (grounded), avoiding complex manufacturing processes and the instability of the device caused by the ungrounded second region 12. At the same time, it protects the gate insulating layer at the corners and bottom of the gate trench 16, preventing premature breakdown of the device due to strong electric fields, improving the reliability of the device, and maintaining the stability and reliability of the device.

[0053] Each gate trench 16 may have a connection portion 17 on one or two sidewalls, and one or more connection portions 17 may be provided on the same sidewall. For example, a gate trench 16 may have only one connection portion 17 on one sidewall to avoid the connection portion 17 covering too large an area of ​​the gate trench 16, which would affect the channel on-resistance.

[0054] Figure 4 This is a top view schematic diagram of a semiconductor device provided in an embodiment of this application. Optionally, based on the above embodiments, refer to... Figures 2-4 The second region 12 includes a second main body 03 and a connecting portion 17. The second main body 03 extends from the bottom of the gate trench 16 to the sidewall of the gate trench 16, covering part of the sidewall of the gate trench 16. The connecting portion 17 extends from the first surface 101 to the sidewall of the gate trench 16 and is connected to the second main body 03. The semiconductor body 10 also includes a third region 13, which is configured with a first conductivity type; the third region 13 is disposed within the second main body portion 03, and / or disposed within the area enclosed by the second main body portion 03 and the gate trench 16.

[0055] Specifically, in the semiconductor device of this embodiment, the second region 12 includes a connection portion 17, and the semiconductor body 10 includes a third region 13. A cross-section is taken at different positions of the gate trench 16 along the length direction (second direction Y) of the gate trench 16, and the cross-section is perpendicular to the length direction of the gate trench 16. Figure 2 The sectional view corresponding to section line AA is shown. Figure 3The sectional view corresponding to section line BB is shown.

[0056] The semiconductor body 10 includes a third region 13, which has a different conductivity type than the second region 12. The third region is disposed within the second main body portion 03, and / or within the area enclosed by the second main body portion 03 and the gate trench 16. The third region 13 can recombine and separate electron-hole pairs with the second region 12, which can suppress hole accumulation, avoid excessive local electric field, and maintain the stability and reliability of the device. The second region 12 includes a connection portion 17, which is connected to the source 30. When the device is reverse blocked, the potential of the source 30 is zero, and the potential of the second region 12 is zero (grounded), which can better maintain the stability and reliability of the device.

[0057] Based on the above embodiments, optionally, refer to Figures 1-4 Along the second direction Y, the third region 13 and the connecting part 17 are arranged alternately; wherein, the second direction Y is perpendicular to the first direction X and the third direction Z, and the third direction X is the direction from the first surface 101 to the second surface 102.

[0058] This configuration can better suppress hole accumulation, avoid excessive local electric field, and maintain the stability and reliability of the device.

[0059] Based on the above embodiments, optionally, refer to Figure 1 and Figure 2 When the semiconductor body includes the third region 13, the second region 12 includes the first sub-region 121 and the second sub-region 122 that are interconnected, and the third region 13 includes the third sub-region 131 and the fourth sub-region 132. The first sub-region 121 is located at the corner of the gate trench 16, and the second sub-region 122 is located at the bottom of the gate trench 16; the first sub-region 121 is an inclined portion 1; The third sub-region 131 is located within the area enclosed by the first sub-region 121 and the trench corner of the gate trench 16; the fourth sub-region 132 is located within the second sub-region 122.

[0060] Specifically, the first sub-region 121 and the third sub-region 131 cover the corners of the gate trench 16. For example, the first sub-region 121 and the third sub-region 131 are in contact with the insulating layer 50 within the gate trench 16. Covering the corners of the gate trench 16 with the first sub-region 121 and the third sub-region 131 can better suppress the high electric field at the corners of the gate trench 16. The second sub-region 122 is disposed at the bottom of the gate trench 16, covering the bottom region of the adjacent gate trench 16. For example, the second sub-region 122 is in contact with the insulating layer 50 within the gate trench 16, and the second sub-region 122 can better suppress the high electric field at the bottom of the gate trench 16. By setting the third sub-region 131 and the fourth sub-region 132 in the first sub-region 121 and the second sub-region 122 respectively, the third region 13 can better interact with the second region 12 for charge carriers, thereby better maintaining the stability and reliability of the device.

[0061] Based on the above embodiments, optionally, the angle A between the line connecting the geometric centers of the first sub-region 121 and the third sub-region 131 and the sidewall of the gate trench 16 is greater than 0, and along the first direction X, the geometric center of the first sub-region 121 is farther away from the gate trench 16 than the geometric center of the third sub-region 131.

[0062] Specifically, the first sub-region 121 and the third sub-region 131 are inclined relative to the sidewall of the gate trench 16. Along the first direction X, the end of the first sub-region 121 adjacent to the second surface 102 is inclined away from the gate trench 16. The first sub-region 121 and the third sub-region 131 can be formed using a halo implantation process. By adjusting parameters such as the implantation angle, dose, and energy, the first sub-region 121 and the third sub-region 131 with different tilt angles can be formed. The process is flexible and can better cover the trench corner of the gate trench 16.

[0063] Based on the above embodiments, optionally, refer to Figure 3 When the semiconductor body 10 includes the connecting portion 17, the first main body portion 02 includes a first preset sub-region 123 and a second preset sub-region 124 that are connected to each other; the first preset sub-region 123 covers the corner of the gate trench 16, the second preset sub-region 124 is disposed at the bottom of the gate trench 16, and the first preset sub-region 123 is an inclined portion 1.

[0064] Specifically, the first preset sub-region 123 covers the corner of the gate trench 16, that is, the first preset sub-region 123 covers part of the bottom and part of the sidewall of the corner of the gate trench 16, which can better suppress the high electric field at the corner. For example, the first preset sub-region 123 is in contact with the insulating layer 50 located at the corner of the gate trench 16. The second preset sub-region 124 covers the bottom region of the adjacent gate trench 16, which can better suppress the high electric field at the bottom of the gate trench 16. For example, the second preset sub-region 124 is in contact with the insulating layer 50 located at the bottom of the trench in the gate trench 16.

[0065] Based on the above embodiments, optionally, the two first preset sub-regions 123 at the two corners of the same gate trench 16 are in a figure-eight shape. The first preset sub-region 123 includes a first end 1231 adjacent to the gate trench 16 and a second end 1232 away from the gate trench 16. The line length connecting the second ends 1232 of the two first preset sub-regions 123 of the same gate trench 16 is greater than the line length connecting the first ends 1231 of the two first preset sub-regions 123.

[0066] That is, the first preset sub-region 123 is inclined relative to the sidewall of the gate trench 16. The first preset sub-region 123 can be formed by halo injection process. By adjusting parameters such as injection angle, dose and energy, the first preset sub-region 123 with different tilt angles can be formed. The process is flexible and can better cover the trench corner of the gate trench 16.

[0067] Based on the above embodiments, optionally, the semiconductor body 10 further includes a fourth region 14, which is configured as a second conductivity type and located on the first surface 101, and the fourth region 14 is connected to the well region 15 and the first region 11.

[0068] Power devices also include: An insulating layer 50 is located within the gate trench 16. The insulating layer 50 is located on the side of the gate 20 adjacent to the second surface 102. The insulating layer 50 covers the bottom of the gate trench 16 and the sidewall of the gate trench 16. Interlayer dielectric layer 60 is located on the side of gate 20 away from the second surface 102; interlayer dielectric layer 60 covers gate 20 and part of first region 11; source 30 is located on the side of interlayer dielectric layer 60 away from the second surface 102, and source 30 covers part of first region 11.

[0069] The fourth region 14 can be the source P-polarity+ region. The insulating layer 50 is a gate insulating layer, and its material includes silicon oxide or silicon nitride. The insulating layer 50 is located between the gate 20 and the gate trench 16, and it isolates the gate 20 to prevent device leakage. The interlayer dielectric layer 60 isolates the gate 20 and the source 30. The interlayer dielectric layer 60 exposes a portion of the first region 11, allowing the source 30 to contact a portion of the first region 11. The interlayer dielectric layer 60 can also be made of silicon oxide or silicon nitride.

[0070] Based on the above embodiments, this application also provides a power module, including a substrate and the power devices described in any embodiment of this application, wherein the substrate is used to support the power devices.

[0071] The power modules provided in the embodiments of this application and the power devices described in any embodiment of this application have the same beneficial effects.

[0072] Based on the above embodiments, this application also provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and the power device described in any embodiment of this application, and the power device is electrically connected to the circuit board.

[0073] The power conversion circuit provided in the embodiments of this application and the power device described in any embodiment of this application have the same beneficial effects.

[0074] Based on the above embodiments, this application also provides a vehicle, including a load and the power conversion circuit described in any embodiment of this application. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0075] The vehicle provided by the technical solution of this application embodiment and the power device described in any embodiment of this application have the same beneficial effects.

[0076] This application also provides a method for fabricating a power device. Figure 5 This is a flowchart of a method for fabricating a power device according to an embodiment of this application, see reference. Figure 5 The fabrication methods for power devices include: S110. A semiconductor body is provided, the semiconductor body being configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other, the semiconductor body also including a well region, a first region and a second region, the first surface being provided with a gate trench; the first region being configured with the first conductivity type and located on the first surface; the well region being configured with the second conductivity type and located on the side of the first region away from the first surface; the second region being configured with the second conductivity type, the second region extending from the bottom of the gate trench to the sidewall of the gate trench, covering part of the sidewall of the gate trench; the second region including an inclined portion, the inclined portion being disposed at the corner of the gate trench, the inclined portion being inclined relative to the sidewall of the gate trench, and the inclined portion including a first end adjacent to the first surface and a second end adjacent to the second surface, along the first direction, the second end being further away from the sidewall of the gate trench relative to the first end; wherein, along the first direction, the well region is disposed on one or both sides of the gate trench, and the first conductivity type and the second conductivity type are different.

[0077] S120. A gate is disposed in the gate trench.

[0078] S130, A source electrode is disposed on the first surface; wherein the source electrode is connected to the first region; S140, A drain electrode is provided on the second surface.

[0079] The semiconductor body of this application embodiment includes a well region, a first region, and a second region. A gate trench is formed on the first surface. The second region is configured with a second conductivity type and is located on the side of the gate trench adjacent to the second surface. The second region extends from the bottom of the gate trench to the sidewall of the gate trench. The second region includes an inclined portion, which is located at the corner of the gate trench. The inclined portion is inclined relative to the sidewall of the gate trench. Along the first direction, the second end is further away from the sidewall of the gate trench than the first end, so that the second region can cover more of the sidewall of the gate trench. When the device is reverse blocked, the second region can suppress the high electric field at the bottom and corner of the gate trench, avoid local breakdown of the gate insulating layer, improve the breakdown voltage of the device, and improve the reliability of the device.

[0080] Figures 6-16 To illustrate the process of forming the semiconductor body, based on the above embodiments, optionally, refer to... Figures 5-16 S110, providing a semiconductor body, including: A semiconductor structure layer 100 is provided, wherein the semiconductor structure layer 100 includes a well region 15 and a first region 11, and a gate trench 16 is further provided on the first surface of the semiconductor structure layer 100. A first mask layer is disposed within the gate trench 16 and on the first surface of the semiconductor structure layer 100; wherein the first mask layer includes a first sub-layer 71 and a second sub-layer 72, the first sub-layer 71 covers the first surface of the semiconductor structure layer 100, and the second sub-layer 72 is disposed on the sidewall of the gate trench 16, extending from the first surface of the semiconductor structure layer 100 to a first predetermined position on the sidewall of the gate trench 16. A first preset sub-region 123 is formed at the corner of the gate trench 16, and a third sub-region 131 with the opposite conductivity type to the first preset sub-region 123 is formed. The portion of the first preset sub-region 123 that is retained after the third sub-region 131 is formed is the first sub-region 121. A second preset sub-region 124 is formed at the bottom of the gate trench 16; and a fourth sub-region 132 with the opposite conductivity type to the second preset sub-region 124 is formed. The portion of the second preset sub-region 124 that is retained after the formation of the fourth sub-region 132 is called the second sub-region 122. The second region 12 includes a first sub-region 121 and a second sub-region 122 that are connected to each other. The first sub-region 121 is an inclined portion. The third region 13 includes a third sub-region 131 and a fourth sub-region 132. The third sub-region 131 is disposed in the region enclosed by the first sub-region 121 and the trench corner of the gate trench 16. The fourth sub-region 132 is disposed within the second sub-region 122. Remove the first mask layer.

[0081] Specifically, Figures 6-10 This is a diagram illustrating the formation process of semiconductor structure layer 100, for reference. Figure 6 A first epitaxial layer 011 is grown on a substrate 01, where the substrate 01 can be an N-type substrate and the first epitaxial layer 011 can be an N-type epitaxial layer. (Reference) Figure 7 A Pwell layer 02 is grown on the first epitaxial layer 011. (Reference) Figure 8 A fourth region 14 is formed by localized P-doping on the Pwell layer 02. This fourth region 14 can serve as a source P+ region. (Reference) Figure 9 N-doping is performed on the Pwell layer 02 to form the first region 11, i.e., the source N+ region, while the undoped Pwell layer forms the well region 15. (Reference) Figure 10 A mask 701 is deposited on the surfaces of the first region 11 and the fourth region 14, and gate trenches 16 are etched to form a semiconductor structure layer 100. The mask 701 can be made of silicon oxide material. A silicon oxide layer can be deposited first, and then the silicon oxide layer can be dry etched to form silicon to form the mask 701.

[0082] Figures 11-13 This is a schematic diagram of the formation of the first mask layer. (See reference) Figures 11-13The first sub-layer 71 can be a mask 701 used in the process of forming the gate trench 16. The second sub-layer 72 covers the opening sidewall of the first sub-layer 71 and extends from the opening sidewall of the first sub-layer 71 to the bottom of the gate trench 16, extending to a first preset position. The first preset position is located on the sidewall of the gate trench 16 and has a certain distance from the bottom of the gate trench 16, exposing part of the sidewall, so that the second region formed under the shielding of the second sub-layer 72 can cover the corner of the gate trench 16.

[0083] Continue to refer to Figure 13 After forming the first mask layer, tilted implantation is performed on the corner of the gate trench 16 to form a first preset sub-region 123. For example, halo implantation is performed to form the first preset sub-region 123. Figure 14 This is a schematic diagram of the formation of the second preset sub-region, for reference. Figure 14 Ions are vertically implanted at the bottom of the gate trench 16 to form a second preset sub-region 124. For example, P-type ions are vertically implanted at the bottom of the gate trench 16 to form the second preset sub-region 124.

[0084] Figure 15 This is a schematic diagram of the formation of the third sub-region. (See reference) Figure 15 Then, tilted implantation is performed again at the corner of the gate trench 16 to form the third sub-region 131. For example, halo implantation is performed, and N-type ions are implanted at low energy to form N-islands at the corner, i.e., the third sub-region 131. Figure 16 This is a schematic diagram of the formation of the fourth sub-region. (See reference) Figure 16 Vertical implantation is performed at the bottom of the gate trench 16 to form a fourth sub-region 132. For example, N-type ions are vertically implanted at the bottom of the gate trench 16 to form a bottom N-island, which forms the fourth sub-region 132. Figure 17 This is a schematic diagram after removing the first mask layer. (See reference) Figure 17 The first mask layer is removed by wet etching.

[0085] Figure 18 This is a schematic diagram after the insulating layer and gate are formed. (See reference) Figure 18 An insulating layer 50 and a gate 20 are fabricated within the gate trench 16. The gate 20 can be made of polysilicon. Figure 19 This is a schematic diagram of the formation of the interlayer dielectric layer. (See reference) Figure 19 An interlayer dielectric layer 60 is deposited on the first surface of the semiconductor body 10. Figure 20 This is a schematic diagram of the source electrode formation, see reference. Figure 20 and Figure 1 Source 30 and drain 40 are fabricated on the first and second surfaces, respectively.

[0086] In this embodiment, by setting a first mask layer including a first sub-layer 71 and a second sub-layer 72, the first sub-layer 71 covers the first surface of the semiconductor structure layer 100, and the second sub-layer 72 covers part of the sidewall of the gate trench 16, the doping of the corner position of the gate trench 16 can be achieved by tilted ion implantation to form the first sub-region 121 and the third sub-region 131, thereby reducing the process difficulty.

[0087] Based on the above embodiments, optionally, a first mask layer is formed within the gate trench 16 and on the first surface of the semiconductor structure layer 100, including: A first sublayer 71 is formed on the first surface of the semiconductor structure layer 100; An intermediate layer 73 is formed at the bottom of the gate trench 16, and the intermediate layer 73 extends from the bottom of the gate trench 16 to a first predetermined position on the sidewall of the gate trench 16. A second sublayer 72 is formed on the sidewall of the gate trench 16; Remove the intermediate layer 73.

[0088] For details, please refer to Figure 11 A polysilicon layer is deposited to fill the gate trench 16, and dry etching is performed to the bottom of the gate trench 16 to form an intermediate layer 73. (Reference) Figure 12 SiN is deposited on the sidewalls of the gate trench 16 to form sidewalls, i.e., to form the second sub-layer 72, which is in contact with the intermediate layer 73. (Reference) Figure 13 The intermediate layer 73 at the bottom of the gate trench 16 is removed by wet etching to form a first mask layer. By first setting the intermediate layer 73 and then forming the second sub-layer 72 on the sidewall of the gate trench 16, the intermediate layer 73 can limit the cutoff position of the second sub-layer 72. Removing the intermediate layer 73 can form a second sub-layer 72 with a suitable coverage area, which is a simple process.

[0089] Optionally, the first sublayer 71 and the second sublayer 72 are made of different materials than the intermediate layer 73. This arrangement can prevent damage to the first sublayer 71 and the second sublayer 72 when the intermediate layer 73 is etched away.

[0090] Based on the above embodiments, optionally, refer to Figures 14-16 A first preset sub-region 123 and a third sub-region 131 with the opposite conductivity type to the first preset sub-region 123 are formed at the corner of the gate trench 16, including: The first preset sub-region 123 is formed by doping the trench corner of the gate trench 16 using a halo implantation process; The third sub-region 131 is formed by doping the region adjacent to the gate trench 16 in the first preset sub-region 123 through a halo implantation process.

[0091] Specifically, using halo injection can improve the positional accuracy of the first preset sub-region 123 and the third sub-region 131, better cover the corner of the gate trench 16, better protect the corner, and avoid high electric field breakdown.

[0092] Figures 21-24 This is another process diagram for forming the second region. Optionally, based on the above embodiments, refer to... Figures 21-24 Provides a semiconductor body, including: A semiconductor structure layer is provided, wherein the semiconductor structure layer includes a well region 15 and a first region 11, and a gate trench 16 is further provided on the first surface of the semiconductor structure layer. A second mask layer is disposed within the gate trench 16 and on the first surface of the semiconductor structure layer; wherein the second mask layer includes a first sub-layer 71 and a fourth sub-layer 74, the first sub-layer 71 covers the first surface of the semiconductor structure layer, the fourth sub-layer 74 is disposed on the sidewall of the gate trench 16, extends from the first surface 101 of the semiconductor structure layer to a first predetermined position on the sidewall of the gate trench 16, and the fourth sub-layer 74 includes at least one opening 741, the opening 741 exposing a predetermined area of ​​the sidewall of the gate trench 16, the predetermined area extending from the first surface 101 of the semiconductor structure layer to the bottom of the gate trench 16; A first preset sub-region 123 and a connecting portion 17 are formed at the corner and sidewall of the gate trench 16; wherein, the first preset sub-region 123 is disposed at the corner of the gate trench 16, and the connecting portion 17 extends from the first surface to the sidewall of the gate trench 16 and is connected to the first preset sub-region 123. A second preset sub-region 124 is formed at the bottom of the gate trench 16; wherein, the second region 12 includes a first main body and a connecting part, the first main body includes a first preset sub-region 123 and a second preset sub-region 124 connected to each other; the first preset sub-region is an inclined part; Remove the second mask layer.

[0093] Specifically, Figure 21 This is a top view of the gate trench and the fourth sublayer. Figure 22 yes Figure 21 A cross-sectional view along section line CC, see reference. Figure 21 and Figure 22The fourth sublayer 74 includes an opening 741 that exposes a portion of the sidewall of the gate trench 16, i.e., a predetermined region of exposed sidewalls. This predetermined region extends from the first surface of the semiconductor structure layer to the bottom of the gate trench 16. Ion implantation of the exposed sidewalls forms a first predetermined sub-region 123, and ion implantation of the exposed sidewalls forms a connection portion 17 connected to the first predetermined sub-region 123. By including the opening 741 in the fourth sublayer 74, the first predetermined sub-region 123 and the connection portion 17 can be formed simultaneously in a single implantation process, reducing process steps. For example, the first predetermined sub-region 123 and the connection portion 17 can be formed first using a halo implantation process. Figure 23 This is a schematic diagram of the formation of the second preset sub-region. (See reference) Figure 23 Then, vertical ion implantation is performed on the bottom of the gate trench 16 to form the second preset sub-region 124. Figure 24 This is a schematic diagram after removing the second mask layer. (See reference) Figure 23 and Figure 24 After etching away the first sublayer 71 and the fourth sublayer 74, a semiconductor body is formed.

[0094] refer to Figures 10-12 ,as well as Figures 21-22 Based on the above embodiments, optionally, a second mask layer is formed within the gate trench 16 and on the first surface of the semiconductor structure layer 100, including: A first sublayer 71 is formed on the first surface of the semiconductor structure layer; An intermediate layer 73 is formed at the bottom of the gate trench 16, and the intermediate layer 73 extends from the bottom of the gate trench 16 to a first predetermined position on the sidewall of the gate trench 16. A second sublayer 72 is formed on the sidewall of the gate trench 16; The patterned second sublayer 72 forms the fourth sublayer 74; Remove the intermediate layer 73.

[0095] Specifically, a photoresist layer can be formed on the surface of the second sub-layer 72. After patterning the photoresist layer, the second sub-layer 72 is etched to form a fourth sub-layer 74 with an opening 741, and then the intermediate layer 73 is etched away.

[0096] Based on the above embodiments, optionally, a first preset sub-region 123 and a connecting portion 17 are formed at the trench corner and sidewall of the gate trench 16, including: The gate trench 16 is doped at the corners and sidewalls to form the first preset sub-region 123 and the connection portion 17 by a halo implantation process.

[0097] Specifically, the halo injection process can improve the positional accuracy of the first preset sub-region 123 and the connection portion 17, so that the first preset sub-region 123 can better cover the corner of the gate trench 16, better protect the corner, and avoid high electric field breakdown.

[0098] It should be noted that when the semiconductor body includes a third region 13 and the second region 12 includes a connection portion 17, a second mask layer can be used to form a second region 12 with a connection portion 17. Then, a mask layer is used to cover the opening 741 where the connection portion 17 is formed and the bottom of the gate trench 16 adjacent to the opening 741. Then, ion implantation is performed to form the third region 13 and the final second region 12.

[0099] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0100] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A power device, characterized in that, include: A semiconductor body includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region, a first region, and a second region. The first surface is provided with a gate trench. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. The second region is configured with a second conductivity type. The second region extends from the bottom of the gate trench to the sidewall of the gate trench, covering a portion of the sidewall of the gate trench. The second region includes an inclined portion disposed at a corner of the gate trench. The inclined portion is inclined relative to the sidewall of the gate trench, and the inclined portion includes a first end adjacent to the first surface and a second end adjacent to the second surface. Along a first direction, the second end is further away from the sidewall of the gate trench than the first end. Along the first direction, the well region is disposed on one or both sides of the gate trench, and the first conductivity type and the second conductivity type are different. The gate is located within the gate trench; A source electrode is located on the first surface, and the source electrode is connected to the first region; The drain electrode is located on the second surface; The second region includes a second main body portion and a connecting portion. The second main body portion extends from the bottom of the gate trench to the sidewall of the gate trench, covering a portion of the sidewall of the gate trench. The connecting portion extends from the first surface to the sidewall of the gate trench and is connected to the second main body portion. The semiconductor body further includes a third region, which is configured with a first conductivity type; the third region is disposed within the second main body portion, and / or within the area enclosed by the second main body portion and the gate trench; Along the second direction, the third region and the connecting portion are arranged alternately; wherein, the second direction is perpendicular to the first direction and the third direction, and the third direction is the direction from the first surface to the second surface.

2. The power device according to claim 1, characterized in that: The second region includes a first sub-region and a second sub-region that are interconnected, and the third region includes a third sub-region and a fourth sub-region; The first sub-region is located at the corner of the gate trench, and the second sub-region is located at the bottom of the gate trench; the first sub-region is the inclined portion. The third sub-region is located within the area enclosed by the first sub-region and the corner of the gate trench; the fourth sub-region is located within the second sub-region.

3. The power device according to claim 2, characterized in that: The angle between the line connecting the geometric centers of the first sub-region and the third sub-region and the sidewall of the gate trench is greater than 0, and along the first direction, the geometric center of the first sub-region is farther away from the gate trench than the geometric center of the third sub-region.

4. The power device according to claim 1, characterized in that: The second main body includes a first preset sub-region and a second preset sub-region that are interconnected; the first preset sub-region covers the corner of the gate trench, and the second preset sub-region is disposed at the bottom of the gate trench; the first preset sub-region is the inclined portion.

5. A power module, characterized in that, It includes a substrate and at least one power device as described in any one of claims 1-4, wherein the substrate is used to carry the power device.

6. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one power device as described in any one of claims 1-4, wherein the power device is electrically connected to the circuit board.

7. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 6, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

8. A method for fabricating a power device, characterized in that, include: A semiconductor body is provided, the semiconductor body being configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other, the semiconductor body further including a well region, a first region, and a second region, the first surface being provided with a gate trench; the first region being configured with the first conductivity type and located on the first surface; the well region being configured with the second conductivity type and located on the side of the first region away from the first surface; the second region being configured with the second conductivity type; the second region extending from the bottom of the gate trench to the sidewall of the gate trench, covering a portion of the sidewall of the gate trench; the second region including an inclined portion disposed at a corner of the gate trench, the inclined portion being inclined relative to the sidewall of the gate trench, and the inclined portion including a first end adjacent to the first surface and a second end adjacent to the second surface, the second end being further away from the first end along a first direction. The sidewall of the gate trench; wherein, along the first direction, the well region is disposed on one or both sides of the gate trench, and the first conductivity type and the second conductivity type are different; the second region includes a second main body and a connecting portion, the second main body extending from the bottom of the gate trench to the sidewall of the gate trench, covering part of the sidewall of the gate trench; the connecting portion extending from the first surface to the sidewall of the gate trench and connected to the second main body; the semiconductor body further includes a third region, the third region being configured with the first conductivity type; the third region is disposed within the second main body, and / or, disposed within the region enclosed by the second main body and the gate trench; along the second direction, the third region and the connecting portion are arranged alternately; wherein, the second direction is perpendicular to the first direction and the third direction, the third direction being the direction from the first surface to the second surface; A gate is disposed within the gate trench; A source electrode is disposed on the first surface; wherein the source electrode is connected to the first region; A drain electrode is provided on the second surface.

9. The method for fabricating a power device according to claim 8, characterized in that, Provide semiconductor bodies, including: A semiconductor structure layer is provided, wherein the semiconductor structure layer includes the well region and the first region, and the first surface of the semiconductor structure layer is further provided with the gate trench; A first mask layer is disposed within the gate trench and on the first surface of the semiconductor structure layer; wherein the first mask layer includes a first sub-layer and a second sub-layer, the first sub-layer covers the first surface of the semiconductor structure layer, and the second sub-layer is disposed on the sidewall of the gate trench, extending from the first surface of the semiconductor structure layer to a first predetermined position on the sidewall of the gate trench; A first preset sub-region and a third sub-region with the opposite conductivity type to the first preset sub-region are formed at the corner of the gate trench. The portion of the first preset sub-region that is retained after the formation of the third sub-region is the first sub-region. A second preset sub-region and a fourth sub-region with the opposite conductivity type to the second preset sub-region are formed at the bottom of the gate trench. The portion of the second preset sub-region that is retained after the fourth sub-region is formed is called the second sub-region. The second region includes the first sub-region and the second sub-region that are connected to each other. The first sub-region is the inclined portion. The third region includes the third sub-region and the fourth sub-region. The third sub-region is located in the region enclosed by the first sub-region and the trench corner of the gate trench. The fourth sub-region is located within the second sub-region. Remove the first mask layer; A first predetermined sub-region and a third sub-region with the opposite conductivity type to the first predetermined sub-region are formed at the corner of the gate trench, including: The first preset sub-region is formed by doping the trench corner of the gate trench using a halo implantation process; The third sub-region is formed by doping the region adjacent to the gate trench of the first preset sub-region using a halo implantation process.

10. The method for fabricating a power device according to claim 9, characterized in that, A first mask layer is formed within the gate trench and on the first surface of the semiconductor structure layer, including: A first sublayer is formed on the first surface of the semiconductor structure layer; An intermediate layer is formed at the bottom of the gate trench, the intermediate layer extending from the bottom of the gate trench to a first predetermined position on the sidewall of the gate trench; A second sublayer is formed on the sidewall of the gate trench; Remove the intermediate layer.

11. The method for fabricating a power device according to claim 8, characterized in that, Provide semiconductor bodies, including: A semiconductor structure layer is provided, wherein the semiconductor structure layer includes the well region and the first region, and the first surface of the semiconductor structure layer is further provided with the gate trench; A second mask layer is disposed within the gate trench and on the first surface of the semiconductor structure layer; wherein the second mask layer includes a first sub-layer and a fourth sub-layer, the first sub-layer covers the first surface of the semiconductor structure layer, the fourth sub-layer is disposed on the sidewall of the gate trench, extending from the first surface to a first predetermined position on the sidewall of the gate trench, the fourth sub-layer includes at least one opening, the opening exposing a predetermined area of ​​the sidewall of the gate trench, the predetermined area extending from the first surface of the semiconductor structure layer to the bottom of the gate trench; A first preset sub-region and a connecting portion are formed at the corner and sidewall of the gate trench; wherein, the first preset sub-region is disposed at the corner of the gate trench, and the connecting portion extends from the first surface to the sidewall of the gate trench and is connected to the first preset sub-region. A second preset sub-region is formed at the bottom of the gate trench; wherein, the second main body includes the first preset sub-region and the second preset sub-region connected to each other; the first preset sub-region is the inclined portion; Remove the second mask layer; A first preset sub-region and the connecting portion are formed at the corner and sidewall of the gate trench, including: The gate trench corners and sidewalls are doped using a halo implantation process to form a first preset sub-region and the connection portion.

12. The method for fabricating a power device according to claim 11, characterized in that, A second mask layer is disposed within the gate trench and on the first surface of the semiconductor structure layer, including: A first sublayer is formed on the first surface of the semiconductor structure layer; An intermediate layer is formed at the bottom of the gate trench, the intermediate layer extending from the bottom of the gate trench to a first predetermined position on the sidewall of the gate trench; A second sublayer is formed on the sidewall of the gate trench; The second sublayer is patterned to form the fourth sublayer; Remove the intermediate layer.

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