A split-gate trench silicon carbide MOSFET device

Abstract

The application discloses a kind of split gate trench silicon carbide MOSFET devices, belong to semiconductor power device technical field.The application sets up split gate trench structure and integrates multiple kinds of schottky diode in the center of split gate trench and source area, P-type buried layer that is shorted with source electrode is set in the bottom of split gate trench, and the device includes: N-type substrate, N-type epitaxial layer, P body area, N+ source area, P+ source area, P-type buried layer, oxide layer medium, polysilicon, source metal, drain metal.The P buried layer is set below split gate trench in the application, and P buried layer is shorted with source electrode by the separation P-type area of both sides of trench, the complexity of preparation process of new structure can be simplified;On the premise that new structure effectively improves the first, third quadrant static, dynamic performance of device, reliability problems such as device gate oxide quality, body diode bipolar degradation, short-circuit and surge current capacity can be simultaneously improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, and relates to a gate trench silicon carbide MOSFET device, specifically a novel gate trench silicon carbide MOSFET structure with multi-region integrated hybrid PiN / Schottky diodes. Background Technology

[0002] Silicon carbide (SiC), as a representative of third-generation wide-bandgap semiconductor materials, possesses excellent properties such as high breakdown field strength, high thermal conductivity, and high chemical stability. Its bandgap is three times that of silicon, and its thermal conductivity is more than three times that of silicon, enabling stable operation under extreme environments such as high temperature, high frequency, and high voltage. Silicon carbide is widely used in electric drive systems and charging piles for new energy vehicles, significantly improving energy conversion efficiency. It also plays a crucial role in high-end fields such as photovoltaic power generation, 5G communication RF devices, smart grids, and aerospace. Compared to traditional silicon-based devices, silicon carbide devices have lower energy consumption and smaller size, making them an important fundamental material for driving technological upgrades. SiC MOSFETs are a typical device made of silicon carbide wide-bandgap materials and are currently widely used in medium- and high-voltage applications such as traction inverters for new energy vehicles, photovoltaics, energy storage, smart grids, and rail transit. The planar gate structure was the first commercially available SiC MOSFET form, where the gate, source, and drain are all arranged on the chip surface, and the channel region is parallel to the substrate direction. The biggest advantage of this structure is its mature process and high fault tolerance. However, an inherent drawback of planar structures is the presence of a JFET region—a narrow N-type region formed between two adjacent P-body regions. Current is forced to contract here, generating additional JFET resistance, making it difficult to further reduce the specific on-resistance. Simultaneously, the planar gate has a large parasitic capacitance, limiting improvements in high-frequency switching performance.

[0003] To overcome the performance bottlenecks of planar structures, trench gate structures were developed. Trench gate SiC MOSFETs embed the gate in a vertically extending trench within the semiconductor, with the channel direction perpendicular to the substrate, thus completely eliminating the JFET region. This vertically conductive topology allows current to flow directly from the source region through the channel to the vertical drain, significantly reducing on-resistance and switching losses. Higher channel mobility and smaller parasitic capacitance give trench structures significant advantages in high-frequency, high-efficiency applications such as on-board chargers, DC-DC converters, and photovoltaic inverters.

[0004] However, trench structures face severe manufacturing challenges. SiC has a hardness of up to 9.5, and dry etching to form smooth, vertical trench sidewalls requires extremely high process precision. Any slight sidewall roughness or micro-trench effect can lead to channel mobility degradation or even gate oxide breakdown. Even more serious are the reliability challenges in practical applications: Firstly, under high-voltage blocking conditions, severe electric field concentration occurs at the bottom corner of the trench, where the electric field strength can reach 2-3 times that of planar structures. This creates long-term stress on the gate oxide layer, causing threshold voltage drift or even premature failure. This is a critical bottleneck determining device lifespan and reliability. Therefore, in practical applications, the drive circuit of trench-gate SiC MOSFETs needs to strictly control gate voltage overshoot, negative voltage turn-off, and set a reasonable gate resistance to balance the device's gate oxide stress and switching losses. On the other hand, the body diode undergoes bipolar degradation when bipolar current is conducting. This is due to the parasitic BJT effect within the device. When the body diode is forward-biased and minority carriers (holes) are injected, the energy released by electron-hole recombination causes pre-existing basal dislocations in the drift layer to expand into stacking faults. These stacking faults act as recombination centers, leading to a gradual increase in on-resistance and a rise in the forward voltage drop of the body diode. Simultaneously, the reverse recovery characteristics deteriorate. The degree of degradation intensifies with increasing accumulated current stress and temperature, and is particularly significant in high-current-density switching applications. These two main reliability issues directly affect the long-term stability and lifespan of the device.

[0005] Silicon carbide (SiC) Schottky diodes are among the first wide-bandgap power semiconductor devices to replace silicon-based devices, offering advantages such as low on-resistance, high breakdown voltage, and near-ideal reverse recovery characteristics, making them promising for high-frequency power electronics applications. As unipolar devices, SiC Schottky diodes do not exhibit the electron-hole recombination process found in bipolar PN junctions during conduction, allowing for the integration of Schottky diodes into SiC MOSFETs to address the bipolar degradation problem of body diodes. However, existing SiC Schottky diodes still suffer from several issues. First, under high voltage conditions, the reverse tunneling current is significant, reaching tens of microamps, due to the barrier reduction effect, material surface defects, and metal puncture at the Schottky contact, resulting in a low breakdown voltage and limiting their application in high-voltage fields. Second, SiC Schottky diodes have limited surge current resistance, requiring additional protection or derating in high-surge applications such as input rectifier bridges in power electronics. Therefore, developing a novel SiC MOSFET structure that can simultaneously address these issues is of great importance. Summary of the Invention

[0006] To address the aforementioned issues, this invention discloses a gate trench silicon carbide MOSFET device, which features a gate trench structure and integrates a unipolar Schottky diode in the center of the gate trench. A P-type buried layer, shorted to the source, is located at the bottom of the gate trench.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows:

[0008] A gate trench silicon carbide MOSFET device includes a unipolar Schottky diode integrated in the center of the gate trench and a P-type buried layer at the bottom of the gate trench. The device comprises: an N-type substrate; an N-type epitaxial layer above the N-type substrate; a P-type body region, an N+ source region, and a P+ source region on top of the N-type epitaxial layer; a P-type buried layer at the bottom of the gate trench; an oxide dielectric layer inside the gate trench and above the N-type epitaxial layer; polysilicon in the center of the oxide dielectric layer; a source metal above the N-type epitaxial layer and the oxide dielectric layer; and a drain metal below the N-type substrate. The N+ source region, P+ source region, and P-type buried layer are shorted by the source metal.

[0009] Furthermore, it also includes: two separate P-type regions located on the central sidewall of the gate trench, with the top of the separate P-type regions shorted to the source metal, and a unipolar junction barrier Schottky diode integrated in the center of the gate trench.

[0010] Furthermore, the two separated P-type regions are short-connected to the P-type buried layer.

[0011] Furthermore, it also includes: multiple separated P-type regions located on the central sidewall of the gate trench, two of which are located on the sidewall of the gate trench and shorted to the P-type buried layer at the bottom, and another separated P-type region is located between the gate trenches and shorted to the source metal at the top. A unipolar hybrid PiN / Schottky diode is integrated in the center of the gate trench.

[0012] Furthermore, the P+ source region is selectively injected, and the device source region integrates a unipolar junction barrier Schottky diode.

[0013] Furthermore, the source region is provided with multiple separate P+ source regions, and hybrid PiN / Schottky diodes are integrated in the center of the gate trench and the source region, respectively.

[0014] Furthermore, the device source region is trenched, with the P+ source region located at the bottom of the source trench, and a unipolar junction barrier Schottky diode integrated at the bottom of the source trench.

[0015] Furthermore, each source trench has two separate P+ source regions at the bottom, and a hybrid PiN / Schottky diode is integrated at the bottom of the source trench.

[0016] Furthermore, the P-type buried layer is short-circuited to the source metal through an opening in the cell-terminal junction area.

[0017] Furthermore, the P-body region, N+ source region, P+ source region, and P-type buried layer are formed by ion implantation, and the size of the P-type buried layer is adjusted by multiple epitaxy and ion implantation processes.

[0018] The beneficial effects of this invention are as follows:

[0019] 1. This invention provides a P-type buried layer below the gate trench and short-circuits the P-type buried layer to the source electrode through the separated P-type regions on both sides of the trench. This simplifies the process, shortens the source signal transmission delay, and the P-type buried layer can effectively suppress the electric field strength at the trench corner, improve the long-term reliability of the gate oxide dielectric and the device, and reduce the device switching loss. By adjusting the size of the P-type buried layer at the bottom of the gate trench, the short-circuit withstand capability of the device can be optimized, and the short-circuit reliability of the device can be improved.

[0020] 2. This invention forms multiple separate P-type regions in the center of the gate trench through ion implantation, and integrates various Schottky diodes such as unipolar Schottky diodes (SBD), unipolar junction barrier Schottky diodes (JBS), and hybrid PiN / Schottky diodes (MPS) in the center of the gate through source metal shorting. This solves the bipolar degradation effect of the body diode of trench SiC MOSFET, reduces device leakage current, increases device breakdown voltage, and improves device surge current resistance.

[0021] 3. The present invention forms multiple P+ source regions through selective ion implantation at the source of the device, and integrates various Schottky diodes such as unipolar Schottky diode (SBD), unipolar junction barrier Schottky diode (JBS), and hybrid PiN / Schottky diode (MPS) at the source of the device, so as to further increase the area of ​​the integrated Schottky diode, reduce the diode forward voltage drop, better solve the bipolar degradation effect of the body diode, reduce the device leakage current, and improve the device's surge current resistance.

[0022] 4. This invention proposes a dual-gate trench silicon carbide MOSFET structure with multi-region integrated Schottky diodes. A trench structure is set at the source of the device, and a P-type buried layer is injected at the bottom of the source trench to optimize the short-circuit withstand capability of the MOSFET and reduce the process difficulty of adjusting the size of the P-type buried layer at the bottom of the gate trench. The thickness of the Schottky diode epitaxial layer formed by ion implantation after etching the source trench is reduced, which can further reduce the on-resistance of the integrated Schottky diode.

[0023] 5. This invention addresses the shortcomings of segmented-gate trench silicon carbide MOSFETs in terms of device performance, structural design, and reliability by innovatively proposing several novel structures for segmented-gate trench silicon carbide MOSFET devices that integrate different types of Schottky diodes. By cleverly setting a buried P-layer and separating the P-type region and the trench source P-type region, the complexity of the fabrication process for the new structure is simplified, and the reliability of trench silicon carbide MOSFETs can be improved while enhancing device performance. Compared to existing segmented-gate trench silicon carbide MOSFETs, the new structure can effectively improve the device's static and dynamic performance in the first and third quadrants, while simultaneously improving reliability issues such as gate oxide quality, body diode bipolar degradation, short-circuit withstand capability, and surge current capability. It overcomes the technical bias of existing technologies that preclude both high performance and high reliability, providing a feasible technical path for the domestic production and commercial application of segmented-gate trench silicon carbide MOSFET devices. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a gate trench silicon carbide MOSFET device structure with a centrally integrated unipolar Schottky diode (SBD) proposed in Example 1, where A and B are schematic diagrams of P-type buried layers of different sizes;

[0025] Figure 2 This is a schematic diagram of a gate trench silicon carbide MOSFET device structure with a centrally integrated unipolar junction barrier Schottky diode (JBS) proposed in Embodiment 2 of the present invention, wherein A and B are schematic diagrams of P-type buried layers of different sizes.

[0026] Figure 3 This is a schematic diagram of a gate trench silicon carbide MOSFET device with a short-circuit structure and a centrally integrated unipolar junction barrier Schottky diode (JBS) proposed in Embodiment 3 of the present invention, wherein A and B are schematic diagrams of P-type buried layers of different sizes;

[0027] Figure 4 This is a schematic diagram of a gate trench silicon carbide MOSFET device structure with a centrally integrated hybrid PiN / Schottky diode (MPS) proposed in Embodiment 4 of the present invention, wherein A and B are schematic diagrams of P-type buried layers of different sizes;

[0028] Figure 5 This is a schematic diagram of a gate trench silicon carbide MOSFET device structure with multi-region integrated hybrid PiN / Schottky diode (MPS) and unipolar junction barrier Schottky diode (JBS) proposed in Embodiment 5 of the present invention, wherein A and B are schematic diagrams of P-type buried layers of different sizes;

[0029] Figure 6This is a schematic diagram of a gate trench silicon carbide MOSFET device structure with multi-region integrated hybrid PiN / Schottky diode (MPS) proposed in Embodiment 6 of the present invention, wherein A and B are schematic diagrams of P-type buried layers of different sizes;

[0030] Figure 7 This is a schematic diagram of a dual-gate trench silicon carbide MOSFET device structure with multi-region integrated hybrid PiN / Schottky diode (MPS) and unipolar junction barrier Schottky diode (JBS) proposed in Embodiment 7 of the present invention, wherein A and B are schematic diagrams of buried layers of P+ source regions with different sizes;

[0031] Figure 8 This is a schematic diagram of a dual-gate trench silicon carbide MOSFET device structure with multi-region integrated hybrid PiN / Schottky diode (MPS) proposed in Embodiment 8 of the present invention, where A and B are schematic diagrams of buried layers of P+ source regions of different sizes.

[0032] List of identifiers in attached diagrams:

[0033] 1-N-type substrate, 2-N-type epitaxial layer, 3-P-body region, 4-N+ ​​source region, 5-P+ source region, 6-P-type buried layer, 7-separated P-type region, 8-oxide dielectric, 9-polysilicon, 10-source metal, 11-drain metal. Detailed Implementation

[0034] The technical solutions provided by the present invention will be described in detail below with reference to specific embodiments. It should be understood that the following specific embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention.

[0035] The following examples all use a single cell as an example to illustrate the gate trench silicon carbide MOSFET device.

[0036] Example 1:

[0037] Figure 1 The diagram shows the structure of the first type of gate trench silicon carbide MOSFET device with a centrally integrated unipolar Schottky diode (SBD) proposed in this invention. The unipolar Schottky diode (SBD) is integrated in the center of the gate trench of the device. A P-type buried layer is provided at the bottom of the trench. The short-circuit withstand capability of the device can be optimized by adjusting the size of the P-type buried layer.

[0038] like Figure 1As shown, the MOSFET device includes an N-type substrate 1, an N-type epitaxial layer 2, a P-type body region 3, an N+ source region 4, a P+ source region 5, a P-type buried layer 6, an oxide dielectric layer 8, polysilicon 9, a source metal 10, and a drain metal 11. The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-type body region 3, N+ source region 4, and P+ source region 5 are located on top of the N-type epitaxial layer 2; and the P-type buried layer 6 is located at the bottom of the gate trench. The P-type body region 3, N+ source region 4, P+ source region 5, and P-type buried layer 6 are formed by ion implantation. Figure 1 A and B in the diagram represent two typical P-type buried layer design methods. Figure 1 In A, the width of the P-type buried layer 6 is slightly larger than the width of the trench. Figure 1 In section B, the P-type buried layer 6 extends to both sides, with a width much larger than the trench width. The length of the P-type buried layer 6 extending to both sides can be adjusted as needed. The size of the P-type buried layer 6 can be adjusted through multiple epitaxial layers and ion implantation. The oxide dielectric 8 is located inside the gate trench above the N-type epitaxial layer 2; the polysilicon 9 is located in the center of the oxide dielectric 8; the source metal 10 is located above the N-type epitaxial layer 2 and the oxide dielectric 8; and the drain metal 11 is located below the N-type substrate 1. The N+ source region 4, P+ source region 5, and P-type buried layer 6 are shorted by the source metal 10, wherein the P-type buried layer 6 is shorted to the source metal 10 through an opening in the cell-terminal junction region. In embodiment 1 of this invention, the N-type substrate 1, N-type epitaxial layer 2, P-body region 3, N+ source region 4, source metal 10, and drain metal 11 are used for conductivity.

[0039] This embodiment, on the one hand, transforms the gate-drain capacitance of the device into drain-source capacitance by setting a segmented gate trench structure, reducing Miller capacitance, increasing the device switching frequency, and reducing device switching losses. Secondly, by setting a P-type buried layer at the bottom of the segmented gate trench, the electric field strength at the trench corner can be effectively suppressed, improving the long-term reliability of the gate oxide and the device; the P-type buried layer being shorted to the source can further reduce drain-source capacitance and device switching losses; and the short-circuit withstand capability of the device can be optimized by adjusting the size of the P-type buried layer at the bottom of the segmented gate trench, improving the device's short-circuit reliability. Thirdly, by integrating a unipolar Schottky diode in the center of the segmented gate trench, the bipolar degradation effect of the device's body diode in forward conduction or freewheeling states is improved, increasing the device switching frequency and reducing switching losses.

[0040] Example 2:

[0041] Example 1: A P-type buried layer shorted to the source electrode is disposed at the bottom of a trench-grooved silicon carbide MOSFET. This effectively suppresses the electric field strength of the gate oxide layer at the trench corner, improving the long-term reliability of the gate oxide dielectric and the device. A unipolar Schottky diode is integrated in the center of the trench, which can improve the bipolar degradation effect of the device's body diode. However, the device still suffers from the barrier reduction effect under high voltage, resulting in a large reverse tunneling current and a small breakdown voltage, limiting its application in high-voltage fields. To solve the above problems, this invention proposes... Figure 2 The second type of gate trench silicon carbide MOSFET device structure shown is a gate trench silicon carbide MOSFET device with a centrally integrated unipolar junction barrier Schottky diode (JBS). The unipolar junction barrier Schottky diode (JBS) is integrated in the center of the gate trench. A P-type buried layer is provided at the bottom of the device trench. The short-circuit withstand capability of the device can be optimized by adjusting the size of the P-type buried layer.

[0042] The structure includes an N-type substrate 1, an N-type epitaxial layer 2, a P-type body region 3, an N+ source region 4, a P+ source region 5, a P-type buried layer 6, a split P-type region 7, an oxide dielectric layer 8, polysilicon 9, a source metal 10, and a drain metal 11. The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-type body region 3, N+ source region 4, and P+ source region 5 are located on top of the N-type epitaxial layer 2; the P-type buried layer 6 is located at the bottom of the gate trench; two split P-type regions 7 are disposed on the central sidewall of the gate trench, with their tops shorted to the source metal 10. In this example, the split P-type regions 7 do not contact the P-type buried layer 6. The P-type body region 3, N+ source region 4, P+ source region 5, P-type buried layer 6, and two split P-type regions 7 are formed by ion implantation. Figure 2 A and B in the diagram represent two typical P-type buried layer design methods. Figure 2 In A, the width of the P-type buried layer 6 is slightly larger than the width of the trench. Figure 2 In embodiment B, the P-type buried layer 6 extends to both sides, with a width much larger than the trench width. The length of the P-type buried layer 6 extending to both sides can be adjusted as needed. The size of the P-type buried layer 6 can be adjusted through multiple epitaxial layers and ion implantation. The oxide dielectric 8 is located inside the gate trench and above the N-type epitaxial layer 2; the polysilicon 9 is located in the center of the oxide dielectric 8. The source metal 10 is located above the N-type epitaxial layer 2 and the oxide dielectric 8, and the drain metal 11 is located below the N-type substrate 1. The N+ source region 4, P+ source region 5, P-type buried layer 6, and two separate P-type regions 7 are shorted by the source metal 10, wherein the P-type buried layer 6 is shorted to the source metal 10 through an opening in the cell-terminal junction area. In embodiment 2 of this invention, the N-type substrate 1, N-type epitaxial layer 2, P-body region 3, N+ source region 4, source metal 10, and drain metal 11 are used for conductivity.

[0043] In this example, two separate P-type regions are formed in the center of the gate of a trench silicon carbide MOSFET through ion implantation, and a unipolar junction barrier Schottky diode (JBS) is integrated in the center of the gate trench. This structure also possesses the following advantages of Example 1: the trench gate structure reduces the Miller capacitance of the device, increases the switching frequency, and reduces switching losses; by placing a P-type buried layer at the bottom of the trench, the electric field strength at the trench corner can be effectively suppressed, improving the long-term reliability of the gate oxide and the device; the P-type buried layer is shorted to the source, further reducing drain-source capacitance and lowering switching losses; the short-circuit withstand capability of the device can be optimized and its short-circuit reliability improved by adjusting the size of the P-type buried layer at the bottom of the trench. Meanwhile, this example integrates a unipolar junction barrier Schottky diode (JBS) by forming two separate P-type regions in the center of the gate trench through ion implantation. On the one hand, this can improve the bipolar degradation effect of the device body diode in the forward conduction or freewheeling state; on the other hand, it can reduce the device leakage current and improve the device breakdown voltage. Furthermore, by adjusting the spacing and size of the two separate P-type regions in the center of the gate trench, the surge current resistance of the device can be improved.

[0044] Example 3:

[0045] Example 2 integrates a unipolar junction barrier Schottky diode (JBS) in the center of a trench silicon carbide MOSFET, which can effectively improve the bipolar degradation effect of the body diode, reduce leakage current, and improve the breakdown voltage and surge current resistance. However, the P-type buried layer at the bottom of the trench is shorted to the source electrode through a separate opening in the cell-terminal junction region, which is complex and causes source signal transmission delay. To solve the above problems, this invention proposes... Figure 3 The third type of gate trench silicon carbide MOSFET device structure shown is a gate trench silicon carbide MOSFET device with a short-circuit structure and a centrally integrated junction barrier Schottky diode (JBS). A P-type buried layer is provided at the bottom of the device trench, and a unipolar junction barrier Schottky diode (JBS) is integrated in the center of the gate trench. The separated P-type region of the unipolar junction barrier Schottky diode (JBS) is short-circuited to the P-type buried layer at the bottom of the trench.

[0046] The structure includes an N-type substrate 1, an N-type epitaxial layer 2, a P-body region 3, an N+ source region 4, a P+ source region 5, a P-type buried layer 6, a separated P-type region 7, an oxide dielectric layer 8, polysilicon 9, a source metal 10, and a drain metal 11. The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-body region 3, N+ source region 4, and P+ source region 5 are located on top of the N-type epitaxial layer 2; and the P-type buried layer 6 is located at the bottom of the gate trench. Two separated P-type regions 7 are disposed on the central sidewall of the gate trench, and the separated P-type regions 7 are shorted to the P-type buried layer 6. The P-body region 3, N+ source region 4, P+ source region 5, P-type buried layer 6, and two separated P-type regions 7 are formed by ion implantation. Figure 3A and B in the diagram represent two typical P-type buried layer design methods. Figure 3 In A, the width of the P-type buried layer 6 is slightly larger than the width of the trench. Figure 3 In section B, the P-type buried layer 6 extends to both sides, with a width much larger than the trench width. The length of the P-type buried layer 6 extending to both sides can be adjusted as needed. The size of the P-type buried layer 6 can be adjusted through multiple epitaxial layers and ion implantation. The oxide dielectric 8 is located inside the gate trench and above the N-type epitaxial layer 2; the polysilicon 9 is located in the center of the oxide dielectric 8; the source metal 10 is located above the N-type epitaxial layer 2 and the oxide dielectric 8; the drain metal 11 is located below the N-type substrate 1; the N+ source region 4, the P+ source region 5, and the two separated P-type regions 7 are shorted through the source metal 10, with the P-type buried layer 6 shorted to the source metal 10 through the two separated P-type regions 7. In this example, the N-type substrate 1, the N-type epitaxial layer 2, the P-body region 3, the N+ source region 4, the source metal 10, and the drain metal 11 are used for conductivity.

[0047] In this example, two separate P-type regions shorted to the buried P-layer are formed in the center of the gate of a trench silicon carbide MOSFET through ion implantation. A unipolar junction barrier Schottky diode (JBS) is integrated in the center of the gate trench. This structure also has the following advantages of Example 2: the trench structure reduces the Miller capacitance of the device, increases the switching frequency, and reduces the switching loss; by setting the P-type buried layer at the bottom of the trench, the electric field strength at the trench corner can be effectively suppressed, improving the gate oxide dielectric and the long-term reliability of the device; the integration of the unipolar junction barrier Schottky diode (JBS) in the center of the trench can improve the bipolar degradation effect of the body diode, reduce the leakage current, increase the breakdown voltage, and improve the surge current resistance by adjusting the spacing and size of the two separate P-type regions in the center of the trench. Secondly, in this example, two separate P-type regions shorted to the buried P-type layer are formed by ion implantation. The buried P-type layer is directly shorted to the source electrode through the two separate P-type regions, which can simplify the process, shorten the source signal transmission delay, and more effectively suppress the electric field strength at the trench corner, reduce the drain-source capacitance, and reduce the device switching loss. It can also better optimize the device's short-circuit withstand capability and improve the device's short-circuit reliability.

[0048] Example 4:

[0049] Examples 2 and 3 integrate a unipolar junction barrier Schottky diode (JBS) in the center of a trench silicon carbide MOSFET, which can effectively improve the bipolar degradation effect of the body diode, reduce leakage current, and improve the breakdown voltage and surge current withstand capability. However, problems still exist, such as large reverse tunneling current under high voltage conditions and limited improvement in breakdown voltage and surge current withstand capability. To solve the above problems, this invention proposes... Figure 4The fourth type of gate trench silicon carbide MOSFET device structure shown is a gate trench silicon carbide MOSFET device structure with a centrally integrated hybrid PiN / Schottky diode (MPS). A unipolar hybrid PiN / Schottky diode (MPS) is integrated in the center of the gate trench, and a P-type buried layer is provided at the bottom of the device trench. The short-circuit withstand capability of the device can be optimized by adjusting the size of the P-type buried layer. The separated P-type regions on both sides of the trench sidewall are shorted to the P-type buried layer at the bottom of the trench.

[0050] The structure includes an N-type substrate 1, an N-type epitaxial layer 2, a P-body region 3, an N+ source region 4, a P+ source region 5, a P-type buried layer 6, a split P-type region 7, an oxide dielectric layer 8, polysilicon 9, a source metal 10, and a drain metal 11. The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-body region 3, N+ source region 4, and P+ source region 5 are located on top of the N-type epitaxial layer 2; the P-type buried layer 6 is located at the bottom of the gate trench; multiple split P-type regions 7 are disposed in the center of the gate trench, two of which are located on the sidewalls of the gate trench and their bottoms are in contact with the P-type buried layer 6, and another split P-type region 7 is located in the center of the gate trench. The tops of all three split P-type regions are in contact with the source metal 10. The P-body region 3, N+ source region 4, P+ source region 5, P-type buried layer 6, and multiple split P-type regions 7 are formed by ion implantation. Figure 4 A and B in the diagram represent two typical P-type buried layer design methods. Figure 4 In section A, the width of the P-type buried layer 6 is slightly larger than the width of the trench. More specifically, in this example, the inner side of the P-type buried layer 6 is longitudinally flush with the inner side of the separated P-type zone 7. Figure 1 In section B, the P-type buried layer 6 extends to both sides, with a width much larger than the trench width. The length of the P-type buried layer 6 extending to both sides can be adjusted as needed. The size of the P-type buried layer 6 can be adjusted through multiple epitaxial growths and ion implantations. The oxide dielectric 8 is located inside the gate trench and above the N-type epitaxial layer 2; the polysilicon 9 is located in the center of the oxide dielectric 8. The source metal 10 is located above the N-type epitaxial layer 2 and the oxide dielectric 8; the drain metal 11 is located below the N-type substrate 1. The N+ source region 4, P+ source region 5, and multiple separated P-type regions 7 are shorted by the source metal 10, wherein the P-type buried layer 6 is shorted to the source metal 10 through the separated P-type regions 7 on both sides of the trench sidewall. In embodiment 4 of this invention, the N-type substrate 1, N-type epitaxial layer 2, P-body region 3, N+ source region 4, source metal 10, and drain metal 11 are used for conductivity.

[0051] This example integrates a hybrid PiN / Schottky diode (MPS) in the center of the gate of a trench silicon carbide MOSFET, where the separated P-type regions on both sides of the trench sidewalls are shorted to the P-type buried layer at the bottom of the trench. This structure also possesses the following advantages of Example 3: the trench gate structure reduces the device's Miller capacitance and increases the device's switching frequency; the P-type buried layer at the bottom of the trench suppresses the electric field strength at the trench corners, improving the long-term reliability of the gate oxide and the device; the P-buried layer is directly shorted to the source electrode through two separate P-type regions, simplifying the process, shortening the source signal transmission delay, better optimizing the device's short-circuit withstand capability, and improving the device's short-circuit reliability. Furthermore, integrating the hybrid PiN / Schottky diode (MPS) in the center of the trench in this example can improve the bipolar degradation effect of the device's body diode, further reducing leakage current and improving the device's breakdown voltage and surge current withstand capability.

[0052] Example 5:

[0053] Example 4 integrates a hybrid PiN / Schottky diode (MPS) in the center of the gate of a trench silicon carbide MOSFET. The separated P-type regions on both sides of the trench sidewalls are shorted to the P-type buried layer at the bottom of the trench, effectively solving the bipolar degradation problem of the body diode, further reducing leakage current, and improving the breakdown voltage and surge current withstand capability. However, the integrated hybrid PiN / Schottky diode (MPS) has a relatively large forward voltage drop. To solve the above problems, this invention proposes... Figure 5 The fifth type of gate trench silicon carbide MOSFET device structure shown is a gate trench silicon carbide MOSFET device structure with multi-region integrated hybrid PiN / Schottky diode (MPS) and unipolar junction barrier Schottky diode (JBS). The source region integrates a unipolar junction barrier Schottky diode (JBS), and the hybrid PiN / Schottky diode (MPS) is integrated in the center of the gate trench. The separated P-type regions on both sides of the trench sidewall are shorted to the P-type buried layer at the bottom of the trench. The short-circuit withstand capability of the device can be optimized by adjusting the size of the P-type buried layer at the bottom of the trench.

[0054] The structure includes an N-type substrate 1, an N-type epitaxial layer 2, a P-type body region 3, an N+ source region 4, a P+ source region 5, a P-type buried layer 6, a separated P-type region 7, an oxide dielectric layer 8, polysilicon 9, a source metal 10, and a drain metal 11. The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-type body region 3, N+ source region 4, and P+ source region 5 are located on top of the N-type epitaxial layer 2; and the P-type buried layer 6 is located at the bottom of the gate trench. Multiple separated P-type regions 7 are disposed in the center of the gate trench, and their structural design is the same as in Example 4. The P-type body region 3, N+ source region 4, P+ source region 5, P-type buried layer 6, and multiple separated P-type regions 7 are formed by ion implantation. Figure 5In the examples A and B, two typical P-type buried layer 6 designs with different widths are shown, and their width design concept is the same as in Example 4. The size of the P-type buried layer 6 can be adjusted through multiple epitaxial growths and ion implantations. Unlike Example 4, the P+ source region 5 is narrower, and an N-type epitaxial layer 2 is provided on its outer side. The oxide dielectric 8 is located inside the gate trench and above the N-type epitaxial layer 2; the polysilicon 9 is located in the center of the oxide dielectric 8. The source metal 10 is located above the N-type epitaxial layer 2 and the oxide dielectric 8; the drain metal 11 is located below the N-type substrate 1. The N+ source region 4, P+ source region 5, and multiple separated P-type regions 7 are shorted through the source metal 10, wherein the P-type buried layer 6 is shorted to the source metal 10 through the separated P-type regions 7 on both sides of the trench sidewall, and the P+ source region 5 is selectively implanted. In this embodiment of the invention, the N-type substrate 1, N-type epitaxial layer 2, P-body region 3, N+ source region 4, source metal 10, and drain metal 11 are used for conductivity.

[0055] This example integrates a hybrid PiN / Schottky diode (MPS) in the center of the gate of a trench silicon carbide MOSFET. The separated P-type regions on both sides of the trench sidewalls are shorted to the buried P-type layer at the bottom of the trench. A unipolar junction barrier Schottky diode (JBS) is integrated in the source region. This structure also possesses the following advantages of Example 4: the trench gate structure reduces the device's Miller capacitance and increases the device's switching frequency; the buried P-type layer at the bottom of the trench suppresses the electric field strength at the trench corners, improving the long-term reliability of the gate oxide and the device; the buried P-type layer is directly shorted to the source electrode through two separate P-type regions, simplifying the process, shortening the source signal transmission delay, better optimizing the device's short-circuit withstand capability, and improving the device's short-circuit reliability; the integration of the hybrid PiN / Schottky diode (MPS) in the center of the trench improves the bipolar degradation effect of the device's body diode, further reducing leakage current and improving the device's breakdown voltage and surge current withstand capability. Furthermore, this example demonstrates how integrating a junction barrier Schottky diode (JBS) in the source region of the device can increase the area of ​​the integrated Schottky diode and reduce its forward voltage drop.

[0056] Example 6:

[0057] Example 5 integrates a hybrid PiN / Schottky diode (MPS) in the center of the gate of a trench silicon carbide MOSFET and a unipolar junction barrier Schottky diode (JBS) in the source region. This effectively solves the bipolar degradation problem of the body diode and increases the area of ​​the integrated Schottky diode, reducing its forward voltage drop. However, the unipolar junction barrier Schottky diode (JBS) integrated in the source region has a large leakage current and weak surge capability. To solve the above problems, this invention proposes... Figure 6The sixth type of gate trench silicon carbide MOSFET device structure shown is a gate trench silicon carbide MOSFET device with multi-region integrated hybrid PiN / Schottky diodes (MPS). Hybrid PiN / Schottky diodes (MPS) are integrated in the center of the gate trench and the source region, respectively. The separated P-type regions on both sides of the trench sidewall are shorted to the P-type buried layer at the bottom of the trench. The short-circuit withstand capability of the device can be optimized by adjusting the size of the P-type buried layer at the bottom of the trench.

[0058] The structure includes an N-type substrate 1, an N-type epitaxial layer 2, a P-body region 3, an N+ source region 4, a P+ source region 5, a P-type buried layer 6, separated P-type regions 7, an oxide dielectric layer 8, polysilicon 9, a source metal 10, and a drain metal 11. The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-body region 3, N+ source region 4, and P+ source region 5 are located on top of the N-type epitaxial layer 2. Unlike the previous embodiment, the source region is provided with multiple separated P+ source regions 5. The P-type buried layer 6 is located at the bottom of the gate trench; multiple separated P-type regions 7 are provided in the center of the gate trench, and their structural design is the same as in embodiments 4 and 5. The P-body region 3, N+ source region 4, P+ source region 5, P-type buried layer 6, and multiple separated P-type regions 7 are formed by ion implantation. Figure 6 In Example 6, A and B represent two typical P-type buried layer 6 designs with different widths, and their width design principles are the same as in Examples 4 and 5. The size of the P-type buried layer 6 can be adjusted through multiple epitaxial growths and ion implantations. The oxide layer dielectric 8 is located inside the gate trench and above the N-type epitaxial layer 2; the polysilicon 9 is located in the center of the oxide layer dielectric 8. The source metal 10 is located above the N-type epitaxial layer 2 and the oxide layer dielectric 8; the drain metal 11 is located below the N-type substrate 1. The N+ source region 4, P+ source region 5, and multiple separated P-type regions 7 are shorted through the source metal 10, wherein the P-type buried layer 6 is shorted to the source metal 10 through the separated P-type regions 7 on both sides of the trench sidewall, and the P+ source region 5 is selectively implanted. In Example 6 of this invention, the N-type substrate 1, N-type epitaxial layer 2, P-body region 3, N+ source region 4, source metal 10, and drain metal 11 are used for conductivity.

[0059] This example integrates a hybrid PiN / Schottky diode (MPS) in the center and source regions of a trench silicon carbide MOSFET, with the separated P-type regions on both sides of the trench sidewalls shorted to the P-type buried layer at the bottom of the trench. This structure also has the following advantages of Example 5: the trench structure reduces the Miller capacitance of the device and increases the switching frequency; the P-type buried layer at the bottom of the trench suppresses the electric field strength at the trench corner, improving the long-term reliability of the gate oxide and the device; the P-buried layer is directly shorted to the source electrode through two separate P-type regions, simplifying the process, shortening the source signal transmission delay, better optimizing the device's short-circuit withstand capability, and improving the device's short-circuit reliability. In this example, the integration of a hybrid PiN / Schottky diode (MPS) in the center and source regions of the trench increases the area of ​​the integrated Schottky diode, reduces its on-state voltage drop, and improves the bipolar degradation effect of the body diode, further reducing leakage current and improving the device's breakdown voltage and surge current withstand capability.

[0060] Example 7:

[0061] Example 6 integrates a hybrid PiN / Schottky diode (MPS) in the center of the gate and the source region of a trench silicon carbide MOSFET. This effectively solves the problems of large leakage current and weak surge capability of unipolar junction barrier Schottky diodes (JBS) integrated in the source region. However, adjusting the size of the P-type buried layer at the bottom of the trench requires multiple epitaxial growth and ion implantation, resulting in multiple epitaxial biasing processes, complex overall process, and high cost. Furthermore, the on-resistance of the hybrid PiN / Schottky diode (MPS) integrated in the source region remains relatively high. To address these issues, this invention proposes... Figure 7 The seventh type of gate trench silicon carbide MOSFET device structure shown is a dual-gate trench silicon carbide MOSFET device with a multi-region integrated hybrid PiN / Schottky diode (MPS) and a unipolar junction barrier Schottky diode (JBS). The hybrid PiN / Schottky diode (MPS) is integrated in the center of the gate trench, wherein the separated P-type regions on both sides of the trench sidewall are shorted to the P-type buried layer at the bottom of the trench; a trench is dug in the source region of the device, and a unipolar junction barrier Schottky diode (JBS) is integrated at the bottom of the source region trench.

[0062] The structure includes an N-type substrate 1, an N-type epitaxial layer 2, a P-type body region 3, an N+ source region 4, a P+ source region 5, a P-type buried layer 6, a separated P-type region 7, an oxide dielectric layer 8, polysilicon 9, a source metal 10, and a drain metal 11. The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-type body region 3, N+ source region 4, and P+ source region 5 are located on top of the N-type epitaxial layer 2, and the P+ source region 5 is located at the bottom of the source trench. The P+ source region 5 serves as a buried layer to suppress the electric field strength at the bottom of the source trench; the P-type buried layer 6 is located at the bottom of the gate trench. Multiple separated P-type regions 7 are provided in the center of the gate trench, and their structural design is the same as in embodiments 4-6. The P-type body region 3, N+ source region 4, P+ source region 5, P-type buried layer 6, and multiple separated P-type regions 7 are formed by ion implantation. Figure 7 In the diagram, A and B represent two different design schemes for the P+ source region 5 with varying widths. Figure 7 In A, the inner side of the P+ source region 5 is flush with the inner side of the source trench. Figure 7 In section B, the inner side of the P+ source region 5 extends beyond the inner side of the source trench and laterally towards the gate trench. The oxide dielectric 8 is located inside the gate trench and above the N-type epitaxial layer 2; the polysilicon 9 is located in the center of the oxide dielectric 8. The source metal 10 is located above the N-type epitaxial layer 2 and the oxide dielectric 8 and inside the source trench; the drain metal 11 is located below the N-type substrate 1. The N+ source region 4, P+ source region 5, and multiple separated P-type regions 7 are shorted through the source metal 10, wherein the P-type buried layer 6 is shorted to the source metal 10 through the separated P-type regions 7 on both sides of the trench sidewall, and the P+ source region 5 is selectively implanted. In this example, the N-type substrate 1, N-type epitaxial layer 2, P-body region 3, N+ source region 4, source metal 10, and drain metal 11 are used for conductivity.

[0063] This example integrates a hybrid PiN / Schottky diode (MPS) in the center of a gate trench, where the separated P-type regions on both sides of the trench sidewalls are shorted to the P-type buried layer at the bottom of the trench. A trench is created in the source region of the device, and a unipolar junction barrier Schottky diode (JBS) is integrated at the bottom of the source trench. This structure also has the following advantages of Example 6: the gate trench structure reduces the device Miller capacitance and increases the device switching frequency; the P-type buried layer at the bottom of the gate trench suppresses the electric field strength at the trench corner, improving the long-term reliability of the gate oxide and the device; the P-buried layer is directly shorted to the source electrode through two separate P-type regions, simplifying the process, shortening the source signal transmission delay, better optimizing the device's short-circuit withstand capability, and improving the device's short-circuit reliability. In this example, a hybrid PiN / Schottky diode (MPS) is integrated in the center of the gate trench, and a unipolar junction barrier Schottky diode (JBS) is integrated at the bottom of the source trench. On the one hand, the short-circuit withstand capability of the MOSFET structure can be optimized by the P-type buried layer implanted at the bottom of the source trench, reducing the process difficulty of adjusting the size of the P-type buried layer at the bottom of the gate trench. On the other hand, the epitaxial layer thickness of the source unipolar junction barrier Schottky diode (JBS) formed by ion implantation after the source trench is etched is reduced, which can further reduce the on-resistance of the integrated Schottky diode.

[0064] Example 8:

[0065] Example 7 integrates a hybrid PiN / Schottky diode (MPS) in the center of the gate of a trench silicon carbide MOSFET. A trench is created in the source region of the device, and a unipolar junction barrier Schottky diode (JBS) is integrated at the bottom of the trench. This simplifies the fabrication of the P-type buried layer at the bottom of the trench, reduces the epitaxial layer thickness of the integrated unipolar junction barrier Schottky diode (JBS) in the source region, and lowers the on-resistance of the Schottky diode. However, the unipolar junction barrier Schottky diode (JBS) integrated in the trench source region has a large leakage current and weak surge capability. To solve the above problems, this invention proposes... Figure 8 The eighth type of split-gate trench silicon carbide MOSFET device structure shown is a dual split-gate trench silicon carbide MOSFET device with a multi-region integrated hybrid PiN / Schottky diode (MPS). The hybrid PiN / Schottky diode (MPS) is integrated in the center of the split-gate trench, wherein the separated P-type regions on both sides of the trench sidewall are shorted to the P-type buried layer at the bottom of the trench; a trench is dug in the source region of the device, and the hybrid PiN / Schottky diode (MPS) is integrated at the bottom of the source region trench.

[0066] The structure includes: an N-type substrate 1, an N-type epitaxial layer 2, a P-body region 3, an N+ source region 4, a P+ source region 5, a P-type buried layer 6, a separated P-type region 7, an oxide dielectric layer 8, polysilicon 9, a source metal 10, and a drain metal 11. The N-type epitaxial layer 2 is located above the N-type substrate 1; the P-body region 3, N+ source region 4, and P+ source region 5 are located on top of the N-type epitaxial layer 2. The P+ source region 5 is located at the bottom of the source trench; the P-type buried layer 6 is located at the bottom of the gate trench. Multiple separated P-type regions 7 are provided in the center of the gate trench, and their structural design is the same as in Examples 4-7. The P-body region 3, N+ source region 4, P+ source region 5, P-type buried layer 6, and multiple separated P-type regions 7 are formed by ion implantation. In this example, each source trench has two separated P+ source regions 5 at its bottom, and the size of the P+ source region 5 near the gate trench can be adjusted as needed. Figure 8 In the diagram, A and B represent two different design schemes for the P+ source region 5 with varying widths. Figure 8 In A, the inner side of the P+ source region 5 is flush with the inner side of the source trench. Figure 8 In section B, the inner side of the P+ source region 5 extends beyond the inner side of the source trench and laterally towards the gate trench. The oxide dielectric 8 is located inside the gate trench and above the N-type epitaxial layer 2; the polysilicon 9 is located in the center of the oxide dielectric 8. The source metal 10 is located above the N-type epitaxial layer 2 and the oxide dielectric 8 and inside the source trench; the drain metal 11 is located below the N-type substrate 1. The N+ source region 4, P+ source region 5, and multiple separated P-type regions 7 are shorted through the source metal 10, wherein the P-type buried layer 6 is shorted to the source metal 10 through the separated P-type regions 7 on both sides of the trench sidewall, and the P+ source region 5 is selectively implanted. In this example, the N-type substrate 1, N-type epitaxial layer 2, P-body region 3, N+ source region 4, source metal 10, and drain metal 11 are used for conductivity.

[0067] In this example, a hybrid PiN / Schottky diode (MPS) is integrated at the center of the gate trench and at the bottom of the source trench, with the separated P-type regions on both sides of the trench sidewalls shorted to the P-type buried layer at the bottom of the trench. This structure also has the following advantages of Example 7: the gate trench structure reduces the Miller capacitance of the device and increases the switching frequency; the P-type buried layer at the bottom of the gate trench suppresses the electric field strength at the trench corner, improving the long-term reliability of the gate oxide and the device; the P-type buried layer is directly shorted to the source electrode through two separated P-type regions, simplifying the process, shortening the source signal transmission delay, better optimizing the short-circuit withstand capability of the device, and improving the short-circuit reliability of the device; the P-type buried layer implanted at the bottom of the source trench optimizes the short-circuit withstand capability of the MOSFET structure and reduces the process difficulty of adjusting the size of the P-type buried layer at the bottom of the gate trench; the thickness of the Schottky diode epitaxial layer formed by ion implantation after the source trench is reduced, which can further reduce the on-resistance of the integrated Schottky diode. The device integrates a hybrid PiN / Schottky diode (MPS) at the center of the gate trench and the bottom of the source trench. On the one hand, this can increase the area of ​​the integrated Schottky diode and reduce the forward voltage drop of the Schottky diode. On the other hand, it can improve the bipolar degradation effect of the body diode, further reduce the leakage current of the device, and improve the breakdown voltage and surge current resistance of the device.

[0068] It should be noted that the above content merely illustrates the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. For those skilled in the art, various improvements and modifications can be made without departing from the principle of the present invention, and all such improvements and modifications fall within the scope of protection of the claims of the present invention.

Claims

1. A gate trench silicon carbide MOSFET device, characterized in that, A unipolar Schottky diode is integrated in the center of the gate trench, and a P-type buried layer (6) is disposed at the bottom of the gate trench. The device includes: an N-type substrate (1); an N-type epitaxial layer (2) located above the N-type substrate (1); a P-type body region (3), an N+ source region (4), and a P+ source region (5) located on top of the N-type epitaxial layer (2); a P-type buried layer (6) located at the bottom of the gate trench; and an oxide dielectric layer (8) located inside the gate trench and above the N-type epitaxial layer (2). Polycrystalline silicon (9) in the center of oxide medium (8); source metal (10) above N-type epitaxial layer (2) and oxide medium (8); two separate P-type regions (7) on the central sidewall of the gate trench; the N+ source region (4), P+ source region (5) and P-type buried layer (6) are shorted by the source metal (10); the top of the two separate P-type regions (7) is shorted to the source metal (10), and a unipolar junction barrier Schottky diode is integrated in the center of the gate trench.

2. The gate trench silicon carbide MOSFET device according to claim 1, characterized in that, The two separate P-type zones (7) are short-connected to the P-type buried layer (6).

3. A gate-trench silicon carbide MOSFET device, characterized in that, A unipolar Schottky diode is integrated in the center of the gate trench, and a P-type buried layer (6) is disposed at the bottom of the gate trench. The device includes: an N-type substrate (1); an N-type epitaxial layer (2) located above the N-type substrate (1); a P-type body region (3), an N+ source region (4), and a P+ source region (5) located on top of the N-type epitaxial layer (2); a P-type buried layer (6) located at the bottom of the gate trench; an oxide dielectric layer (8) located inside the gate trench and above the N-type epitaxial layer (2); a polysilicon (9) located in the center of the oxide dielectric layer (8); and a dielectric layer (9) located between the N-type epitaxial layer (2) and the oxide dielectric layer. Source metal (10) above the substrate (8); drain metal (11) below the N-type substrate (1); multiple separate P-type regions (7) located on the central sidewall of the gate trench; the N+ source region (4), P+ source region (5), and P-type buried layer (6) are shorted by the source metal (10); two of the separate P-type regions (7) are located on the sidewall of the gate trench and shorted at the bottom to the P-type buried layer (6), and another separate P-type region (7) is located between the gate trenches and shorted at the top to the source metal (10). A unipolar hybrid PiN / Schottky diode is integrated in the center of the gate trench.

4. The gate trench silicon carbide MOSFET device according to claim 3, characterized in that, The P+ source region (5) is selectively injected, and the source region of the device integrates a unipolar junction barrier Schottky diode.

5. The gate trench silicon carbide MOSFET device according to claim 3, characterized in that, The source region is provided with multiple separate P+ source regions (5), and hybrid PiN / Schottky diodes are integrated in the center of the gate trench and the source region respectively.

6. The gate trench silicon carbide MOSFET device according to claim 3, characterized in that, The device source region is trenched, and the P+ source region (5) is located at the bottom of the source trench. A unipolar junction barrier Schottky diode is integrated at the bottom of the source trench.

7. The gate trench silicon carbide MOSFET device according to claim 3, characterized in that, Each source trench has two separate P+ source regions (5) at the bottom, and a hybrid PiN / Schottky diode is integrated at the bottom of the source trench.

8. The gate trench silicon carbide MOSFET device according to claim 1 or 3, characterized in that, The P-type buried layer (6) is short-circuited to the source metal (10) through an opening in the cell-terminal junction area.

9. The gate trench silicon carbide MOSFET device according to claim 1 or 3, characterized in that, The P-body region (3), N+ source region (4), P+ source region (5), and P-type buried layer (6) are formed by ion implantation. The size of the P-type buried layer (6) is adjusted by multiple epitaxy and ion implantation.

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