A bidirectional DTSCR electrostatic protection device and semiconductor device

Abstract

The embodiment of the application discloses a bidirectional DTSCR electrostatic protection device and a semiconductor device. The first semiconductor region group and the second semiconductor region group are arranged on the second conductive type well in parallel. The first conductive type semiconductor region and the second conductive type semiconductor region on the first semiconductor region group are arranged alternately with the first conductive type semiconductor region and the second conductive type semiconductor region on the second semiconductor region group. The first electrostatic protection structure is arranged below the first semiconductor region group, and the second electrostatic protection structure is arranged below the second semiconductor region group. The anode-cathode distance can be effectively shortened, the on-resistance of the device can be reduced, the failure current can be improved, the area of the bidirectional diode trigger thyristor can be reduced, and the limitation on the application range of the device can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a bidirectional DTSCR electrostatic discharge protection device and a semiconductor device. Background Technology

[0002] A thyristor is a semiconductor device that has the characteristics of controllable conduction and cutoff. It mainly consists of two main electrodes, an anode and a cathode (some types also include a trigger electrode). Unidirectional trigger thyristors can only achieve unidirectional conduction. When bidirectional conduction is required, bidirectional diode-triggered silicon-controlled thyristors (DTSCRs) become a good choice.

[0003] A bidirectional diode-triggered thyristor typically includes a P-type substrate, an N-type deep well, an N-well, and a P-well, as well as an anode and a cathode extending from the N-well and P-well. In related technologies, to ensure isolation between the P-type substrate and the P-well in a bidirectional diode-triggered thyristor, an N-type deep well layer is generally introduced, resulting in a large area for the bidirectional diode-triggered thyristor and severely limiting its application range. Summary of the Invention

[0004] This application provides a bidirectional DTSCR electrostatic discharge protection device and a semiconductor device to solve the technical problem in the related art where the N-type deep well causes a large area of ​​the bidirectional diode-triggered thyristor, which seriously limits the application range of the device. It can effectively reduce the area of ​​the bidirectional diode-triggered thyristor and reduce the limitation on the application range of the device.

[0005] In a first aspect, embodiments of this application provide a bidirectional DTSCR electrostatic discharge protection device, comprising: A first conductivity type substrate and a second conductivity type well, wherein the second conductivity type well is located on the first conductivity type substrate; A first semiconductor region group and a second semiconductor region group are arranged side-by-side on a second conductivity type well. The first semiconductor region group includes a plurality of alternating first conductivity type semiconductor regions and second conductivity type semiconductor regions. The second semiconductor region group includes a plurality of alternating second conductivity type semiconductor regions and first conductivity type semiconductor regions. The first conductivity type semiconductor regions and second conductivity type semiconductor regions on the first semiconductor region group are arranged alternately with the first conductivity type semiconductor regions and second conductivity type semiconductor regions on the second semiconductor region group. The second conductivity type semiconductor region in the middle of the first semiconductor region group is short-circuited with the first conductivity type semiconductor region in the middle of the second semiconductor region group. A first anode structure and a second anode structure, wherein the first anode structure is disposed on a first conductivity type semiconductor region at a first end of the first semiconductor region group, and the second anode structure is disposed on a second conductivity type semiconductor region at a second end of the second semiconductor region group; A first cathode structure and a second cathode structure, wherein the first cathode structure is disposed on a first conductivity type semiconductor region at the second end of the first semiconductor region group, and the second cathode structure is disposed on a second conductivity type semiconductor region at the first end of the second semiconductor region group; A first electrostatic discharge (ESD) protection structure and a second ESD protection structure are arranged below the first semiconductor region group.

[0006] Furthermore, the first electrostatic discharge (ESD) protection structure includes a first ESD protection substructure and a second ESD protection substructure. The first ESD protection substructure is disposed below a first conductivity type semiconductor region at the first end of the first semiconductor region group, and the second ESD protection substructure is disposed below a first conductivity type semiconductor region at the second end of the first semiconductor region group.

[0007] Furthermore, the first semiconductor region group includes two semiconductor regions of a first conductivity type and one semiconductor region of a second conductivity type, and the second semiconductor region group includes one semiconductor region of a first conductivity type and two semiconductor regions of a second conductivity type.

[0008] Furthermore, it also includes: A first blocking structure and a second blocking structure, wherein the first blocking structure is disposed between a first conductivity type semiconductor region and a second conductivity type semiconductor region on the first semiconductor region group, and the second blocking structure is disposed between a first conductivity type semiconductor region and a second conductivity type semiconductor region on the second semiconductor region group.

[0009] Furthermore, the first and second barrier structures are silicide barrier layers.

[0010] Furthermore, the second conductivity type semiconductor region in the middle of the first semiconductor region group is shorted to the first conductivity type semiconductor region in the middle of the second semiconductor region group by a metal.

[0011] Furthermore, the first conductivity type is P-type, and the second conductivity type is N-type.

[0012] Furthermore, the first semiconductor region group includes a first conductivity type semiconductor region, a second conductivity type semiconductor region, and a first conductivity type semiconductor region arranged in sequence, and the second semiconductor region group includes a second conductivity type semiconductor region, a first conductivity type semiconductor region, and a second conductivity type semiconductor region arranged in sequence, and the second conductivity type semiconductor region in the first semiconductor region group and the first conductivity type semiconductor region in the second semiconductor region group are short-circuited.

[0013] Furthermore, the second conductivity type trap has trenches arranged on both sides of the first semiconductor region group and on both sides of the second semiconductor region group.

[0014] In a second aspect, embodiments of this application provide a semiconductor device including a bidirectional DTSCR electrostatic discharge protection device as described in any of the first aspects.

[0015] This embodiment of the application arranges a first semiconductor region group and a second semiconductor region group side by side on a second conductivity type well. The first conductivity type semiconductor regions on the first semiconductor region group and the second conductivity type semiconductor regions on the second semiconductor region group are arranged alternately. The second conductivity type semiconductor region in the middle of the first semiconductor region group is short-circuited with the first conductivity type semiconductor region in the middle of the second semiconductor region group. A first anode structure is arranged on the first conductivity type semiconductor region at the first end of the first semiconductor region group, and a second anode structure is arranged on the second conductivity type semiconductor region at the second end of the second semiconductor region group. A first cathode structure is arranged on the first conductivity type semiconductor region at the second end of the first semiconductor region group, and a second cathode structure is arranged on the second conductivity type semiconductor region at the first end of the second semiconductor region group. The first electrostatic discharge (ESD) protection structure is arranged below the first semiconductor region group, and the second ESD protection structure is arranged below the second semiconductor region group. This can effectively shorten the anode-cathode distance, reduce the device on-resistance, and increase the failure current. At the same time, the P-well setting is eliminated, which can effectively reduce the area of ​​the bidirectional diode-triggered thyristor and reduce the limitation on the application range of the device. Attached Figure Description

[0016] Figure 1 This is a cross-sectional schematic diagram of a bidirectional DTSCR electrostatic discharge protection device based on a related technology. Figure 2 This is a top view of a bidirectional DTSCR electrostatic discharge protection device based on a related technology. Figure 3 This is a top view schematic diagram of a bidirectional DTSCR electrostatic discharge protection device provided in an embodiment of this application; Figure 4 It is along Figure 3A schematic cross-sectional view of line AA' in the middle; Figure 5 It is along Figure 3 A cross-sectional schematic diagram of the middle BB' line; Figure 6 It is along Figure 3 A cross-sectional view of the CC' line; Figure 7 It is along Figure 3 A schematic cross-sectional view of the DD' line; Figure 8 It is along Figure 3 A cross-sectional schematic diagram of the EE' line in the middle; Figure 9 This is a schematic diagram of the forward operating current flow provided in an embodiment of this application; Figure 10 This is a schematic diagram of the reverse working current flow provided in an embodiment of this application.

[0017] Reference numerals: 11, substrate of first conductivity type; 12, well of second conductivity type; 21, first semiconductor region group; 22, second semiconductor region group; 31, first anode structure; 32, second anode structure; 41, first cathode structure; 42, second cathode structure; 51, first electrostatic discharge (ESD) protection structure; 511, first ESD protection substructure; 512, second ESD protection substructure; 52, second ESD protection structure; 61, first barrier structure; 62, second barrier structure. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, specific embodiments of this application will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure.

[0019] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. Spatial relation terms such as "below," "under," "below," "below," "above," "over," etc., can be used herein to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as "below" or "under" or "below" other elements or features would be oriented "on" other elements or features. Therefore, the exemplary terms "below" and "under" can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0021] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, they identify the presence of features, integers, steps, operations, elements, and / or parts, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0022] like Figure 1 A cross-sectional schematic diagram of a bidirectional DTSCR electrostatic discharge protection device of related technology is provided, and as follows: Figure 2A top view of a bidirectional DTSCR electrostatic discharge (ESD) protection device is provided. Bidirectional DTSCR ESD protection devices are commonly used in advanced low-voltage processes. In related technologies, bidirectional DTSCR ESD protection devices include a P-type substrate and an N-type deep well arranged from bottom to top, with N-wells, P-wells, and N-wells interleaved on the N-type deep well. Multiple P+ semiconductor regions and multiple N+ semiconductor regions are respectively formed on the N-wells and P-wells, and anodes and cathodes are led out from the P+ and N+ semiconductor regions. To meet the isolation requirements of the P-well and P-type substrate, an N-type deep well layer is required, resulting in a large area for the bidirectional diode-triggered thyristor, severely limiting the device's application range. Furthermore, this arrangement results in a large distance between the cathode and anode, leading to a high on-resistance, low failure current, and unstable operation. Therefore, this application provides a bidirectional DTSCR ESD protection device to solve the above-mentioned technical problems.

[0023] Figure 3 A top view schematic diagram of a bidirectional DTSCR electrostatic discharge protection device provided in an embodiment of this application is given. Figure 4 For bidirectional DTSCR electrostatic protection devices along Figure 3 A cross-sectional view of line AA' in the middle. Figure 5 For bidirectional DTSCR electrostatic protection devices along Figure 3 A cross-sectional view of the middle BB' line. Figure 6 For bidirectional DTSCR electrostatic protection devices along Figure 3 A cross-sectional view of the CC' line. Figure 7 For bidirectional DTSCR electrostatic protection devices along Figure 3 A cross-sectional schematic diagram of the DD' line. Figure 8 For bidirectional DTSCR electrostatic protection devices along Figure 3 A schematic diagram of the cross section of the EE' line.

[0024] For example, refer to Figures 3-6 The bidirectional DTSCR electrostatic discharge protection device includes a first conductivity type substrate 11 (e.g., a P-type substrate in the figure) and a second conductivity type trap 12 (e.g., an NW in the figure), a first semiconductor region group 21 and a second semiconductor region group 22, a first anode structure 31 and a second anode structure 32, a first cathode structure 41 and a second cathode structure 42, and a first electrostatic discharge protection structure 51 and a second electrostatic discharge protection structure 52.

[0025] The second conductivity type well 12 is located on the first conductivity type substrate 11. In one possible embodiment, the first conductivity type can be P-type and the second conductivity type can be N-type; in other possible embodiments, the first conductivity type can be N-type and the second conductivity type can be P-type.

[0026] Optionally, the substrate material corresponding to the first conductivity type substrate 11 can be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or other III-V compounds, as well as multilayer structures composed of the aforementioned semiconductor materials. Furthermore, it can also be silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked germanium (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or double-side polished wafers (DSP), etc., which are not limited in this embodiment. The second conductivity type well 12 can be a highly doped thin layer pre-doped on the substrate surface, doped with donor impurities phosphorus or arsenic.

[0027] The first semiconductor region group 21 and the second semiconductor region group 22 provided in this application are arranged side by side on a second conductivity type well 12 (the top layer of the second conductivity type well 12 away from the first conductivity type substrate 11). The first semiconductor region group 21 includes a plurality of alternating first conductivity type semiconductor regions and second conductivity type semiconductor regions (i.e., adjacent semiconductor regions of different conductivity types). The second semiconductor region group 22 includes a plurality of alternating second conductivity type semiconductor regions and first conductivity type semiconductor regions (i.e., adjacent semiconductor regions of different conductivity types). For example, the first semiconductor region group 21 includes three or more semiconductor regions, adjacent semiconductor regions of different conductivity types, and semiconductor regions of the same conductivity type at both ends of the first semiconductor region group 21; the second semiconductor region group 22 includes three or more semiconductor regions, adjacent semiconductor regions of different conductivity types, and semiconductor regions of the same conductivity type at both ends of the second semiconductor region group 22.

[0028] In this arrangement, the first conductivity type semiconductor region and the second conductivity type semiconductor region on the first semiconductor region group 21 are arranged alternately with the first conductivity type semiconductor region and the second conductivity type semiconductor region on the second semiconductor region group 22. The first semiconductor region group 21 and the second semiconductor region group 22 are arranged opposite to each other, and the semiconductor regions at the opposite positions of the first semiconductor region group 21 and the second semiconductor region group 22 are of different conductivity types.

[0029] The second conductivity type semiconductor region in the middle of the first semiconductor region group 21 is short-circuited with the first conductivity type semiconductor region in the middle of the second semiconductor region group 22. In one embodiment, the second conductivity type semiconductor region in the middle of the first semiconductor region group 21 and the first conductivity type semiconductor region in the middle of the second semiconductor region group 22 are short-circuited by a metal, so that the trigger current can flow smoothly from the second conductivity type semiconductor region in the middle of the first semiconductor region group 21 to the first conductivity type semiconductor region in the middle of the second semiconductor region group 22, ensuring the correct conduction of the bidirectional DTSCR electrostatic discharge protection device.

[0030] The first anode structure 31 provided in this application is disposed on a first conductivity type semiconductor region at the first end of the first semiconductor region group 21, and the second anode structure 32 is disposed on a second conductivity type semiconductor region at the second end of the second semiconductor region group 22. Optionally, the first anode structure 31 and the second anode structure 32 can be shorted by a metal connection to jointly lead out as the anode of the bidirectional DTSCR electrostatic discharge protection device. The anode structure can be a port where ESD current flows into the device, connected to a high potential during a positive ESD pulse and a low potential during a reverse ESD pulse.

[0031] The first cathode structure 41 provided in this application is disposed on a first conductivity type semiconductor region at the second end of the first semiconductor region group 21, and the second cathode structure 42 is disposed on a second conductivity type semiconductor region at the first end of the second semiconductor region group 22. Optionally, the first cathode structure 41 and the second cathode structure 42 can be shorted by a metal connection to jointly lead out as the cathode of a bidirectional DTSCR electrostatic discharge protection device. The cathode structure can be the port where ESD current flows out of the device, connected to a low potential during a positive ESD pulse and a high potential during a reverse ESD pulse. It can be seen that, at this time, the first anode structure 31 and the second cathode structure 42 are arranged adjacent to each other, and the second anode structure 32 and the first cathode structure 41 are arranged adjacent to each other, with a short distance between the anode and cathode, which can effectively reduce the on-resistance of the device and increase the failure current.

[0032] In one possible embodiment, the first semiconductor region group 21 provided in this application includes two first conductivity type semiconductor regions and one second conductivity type semiconductor region, wherein the first conductivity type semiconductor region, the second conductivity type semiconductor region, and the first conductivity type semiconductor region are arranged sequentially. The second semiconductor region group 22 includes one first conductivity type semiconductor region and two second conductivity type semiconductor regions, wherein the second conductivity type semiconductor region, the first conductivity type semiconductor region, and the second conductivity type semiconductor region are arranged sequentially.

[0033] In one embodiment, this application describes an example where the first conductivity type is P-type and the second conductivity type is N-type. The first semiconductor region group 21 includes a first conductivity type semiconductor region, a second conductivity type semiconductor region, and a first conductivity type semiconductor region arranged sequentially. The second semiconductor region group 22 includes a second conductivity type semiconductor region, a first conductivity type semiconductor region, and a second conductivity type semiconductor region arranged sequentially. The second conductivity type semiconductor region in the first semiconductor region group 21 and the first conductivity type semiconductor region in the second semiconductor region group 22 are short-circuited. For example, the first conductivity type semiconductor region, the second conductivity type semiconductor region, and the first conductivity type semiconductor region in the first semiconductor region group 21 are arranged as P+, N+, and P+ regions, respectively. The second conductivity type semiconductor region (N+) in the first semiconductor region group 21 and the first conductivity type semiconductor region (P+) in the second semiconductor region group 22 are arranged as N+, P+, and N+ regions, respectively. The second conductivity type semiconductor region (N+) in the first semiconductor region group 21 and the first conductivity type semiconductor region (P+) in the second semiconductor region group 22 are metal-short-circuited. The above arrangement results in an alternating distribution of conductivity types among the semiconductor regions in the relative positions of the first semiconductor region group 21 and the second semiconductor region group 22, which greatly reduces the distance between the positive and negative electrodes, effectively reducing the on-resistance of the device and increasing the failure current.

[0034] This application provides an electrostatic discharge (PESD) protection structure in the second conductivity type well 12, below the semiconductor region group, eliminating the need for the P-well design in related technologies and avoiding the need to isolate the first conductivity type substrate 11. The PESD protection structure provided in this application includes a first PESD protection structure 51 and a second PESD protection structure 52. The second conductivity type well 12 has trenches (STIs) arranged on both sides of the first semiconductor region group 21 and on both sides of the second semiconductor region group 22. In the figure, the first semiconductor region group 21 and the second semiconductor region group 22 share the same trench. The first PESD protection structure 51 is arranged below the first semiconductor region group 21 and between the corresponding trenches on both sides of the first semiconductor region group 21, and the second PESD protection structure 52 is arranged below the second semiconductor region group 22 and between the corresponding trenches on both sides of the second semiconductor region group 22.

[0035] In the bidirectional DTSCR electrostatic discharge (ESD) device, when the ESD pulse is applied to the anode and the cathode is grounded during forward operation, the diode trigger path, consisting of the first anode structure 31, the first ESD protection structure 51, the second conductivity type trap 12, the short-circuited position of the middle of the first semiconductor region group 21 and the middle of the second semiconductor region group 22, the second ESD protection structure 52, and the second cathode structure 42, firstly conducts and discharges the ESD current. As the ESD pulse current increases, a voltage drop is generated across the resistor of the second conductivity type trap 12 in the diode trigger path, enabling the parasitic PNP or parasitic NPN to conduct. The parasitic PNP and parasitic NPN enter the positive feedback loop, ultimately making the SCR path consisting of the first anode structure 31, the first ESD protection structure 51, the second conductivity type trap 12, the second ESD protection structure 52, and the second cathode structure 42 fully conduct. The bidirectional DTSCR electrostatic discharge (ESD) device exhibits symmetry in both reverse and forward operation. For instance, in reverse operation, when an ESD pulse is applied to the cathode and the anode is grounded, the diode trigger path, composed of the first cathode structure 41, the first ESD protection structure 51, the second conductivity type trap 12, the short-circuited position of the middle of the first semiconductor region group 21 and the middle of the second semiconductor region group 22, the second ESD protection structure 52, and the second anode structure 32, firstly conducts and discharges the ESD current. As the ESD pulse current increases, a voltage drop is generated across the resistor of the second conductivity type trap 12, causing the parasitic PNP or parasitic NPN to conduct. The parasitic PNP and parasitic NPN enter the positive feedback loop, ultimately making the SCR path composed of the first cathode structure 41, the first ESD protection structure 51, the second conductivity type trap 12, the second ESD protection structure 52, and the second anode structure 32 fully conduct.

[0036] In one possible embodiment, combining Figure 3 , Figure 7 and Figure 8 The first electrostatic discharge (ESD) protection structure 51 provided in this application is divided into two parts: a first ESD protection substructure 511 and a second ESD protection substructure 512. The first ESD protection substructure 511 is arranged below the first conductive type semiconductor region at the first end of the first semiconductor region group 21. The second ESD protection substructure 512 is arranged below the first conductive type semiconductor region at the second end of the first semiconductor region group 21. The second ESD protection substructure 512 is arranged below the first conductive type semiconductor region. The second ESD protection structure 52 is arranged below the second conductive type semiconductor region, the first conductive type semiconductor region, and the second conductive type semiconductor region.

[0037] In this design, a first electrostatic discharge (ESD) protection structure 51 is disposed below the first semiconductor region group 21, and a second ESD protection structure 52 is disposed below the second semiconductor region group 22. The area of ​​the second ESD protection structure 52 is greater than or equal to the area of ​​the second semiconductor region group 22. The area of ​​the first ESD protection substructure 511 is greater than or equal to the area of ​​the first conductive type semiconductor region at the first end of the first semiconductor region group 21, and the area of ​​the second ESD protection substructure 512 is greater than or equal to the area of ​​the first conductive type semiconductor region at the second end of the first semiconductor region group 21. This application isolates and protects the first conductive type semiconductor region of the first semiconductor region group 21 using the first ESD protection substructure 511 and the second ESD protection substructure 512, eliminating the need for the P-well design in related technologies, reducing the isolation of the first conductive type substrate 11, and decreasing the area of ​​the bidirectional diode-triggered thyristor.

[0038] Combination Figure 3 , Figure 7 and Figure 8 The bidirectional DTSCR electrostatic protection device provided in this application also has a barrier structure (SAB) on the second conductivity type well 12 (the top layer of the second conductivity type well 12 away from the first conductivity type substrate 11). The barrier structure includes a barrier structure 61 and a second barrier structure 62, and the first barrier structure 61 and the second barrier structure 62 are silicide barrier layers.

[0039] The first blocking structure 61 is disposed between a first conductivity type semiconductor region and a second conductivity type semiconductor region on the first semiconductor region group 21. For example, a first blocking structure 61 is disposed between P+ and N+ regions arranged sequentially on the first semiconductor region group 21, and between N+ and P+ regions respectively (see...). Figure 7 The second barrier structure 62 is disposed between the first conductivity type semiconductor region and the second conductivity type semiconductor region on the second semiconductor region group 22. For example, a second barrier structure 62 is disposed between N+ and P+ regions arranged sequentially on the second semiconductor region group 22, and between P+ and N+ regions respectively (see...). Figure 8 Through the above configuration, an effective barrier isolation is formed between the first conductivity type semiconductor region and the second conductivity type semiconductor region within the same semiconductor region group, effectively improving the electrical performance of the bidirectional DTSCR electrostatic discharge protection device. Furthermore, the bidirectional DTSCR electrostatic discharge protection device provided in this application, through the above configuration, has only PN junction capacitance and small parasitic capacitance, making it suitable for low-voltage, high-speed applications below 1.4V, thus broadening its application range.

[0040] like Figure 9As shown in the schematic diagram of the forward operating current flow, when the bidirectional DTSCR electrostatic discharge protection device provided in this application is operating in the forward direction, the ESD pulse is applied to the anode of the bidirectional DTSCR electrostatic discharge protection device and the cathode is grounded. The diode triggering path, which is composed of the first conductive type semiconductor region P+ connected to the anode, the first electrostatic discharge protection substructure PESD, the second conductive type trap, the metal-short-circuited second conductive type semiconductor region N+, and the first conductive type semiconductor region P+, the second electrostatic discharge protection substructure PESD, and the cathode-connected second conductive type semiconductor region N+, first conducts and discharges the ESD current. The diode triggering current path is shown as L11 in the figure. As the ESD pulse current increases, a voltage drop is generated across the NW resistor of the second conductivity type trap in the diode trigger path, enabling the parasitic PNP or parasitic NPN to conduct. The parasitic PNP and parasitic NPN enter the positive feedback loop, ultimately making the SCR path composed of the anode P+, ​​the first electrostatic protection substructure PESD, NW, the second electrostatic protection substructure PESD, and the cathode N+ completely conduct. The current path after conduction is shown in L12 in the figure. In the figure, the diode trigger current path L11 and the conduction current path L12 are represented by different types of line segments.

[0041] like Figure 10 As shown in the schematic diagram of the reverse operating current flow, when the bidirectional DTSCR electrostatic discharge device provided in this application is operating in reverse, an ESD pulse is applied to the cathode of the bidirectional DTSCR electrostatic discharge device and the anode is grounded. The diode trigger path, composed of the first conductive type semiconductor region P+ connected to the cathode, the first electrostatic discharge protection substructure PESD, the metal-short-circuited second conductive type semiconductor region N+, and the first conductive type semiconductor region P+, the second electrostatic discharge protection substructure PESD, and the anode-connected second conductive type semiconductor region N+, firstly conducts to discharge the ESD current, as shown in L21 in the figure. As the ESD pulse current increases, a voltage drop is generated across the second conductive type well NW resistor in the diode trigger path, conducting the parasitic PNP or parasitic NPN. The parasitic PNP and parasitic NPN enter the positive feedback loop, ultimately making the SCR path composed of the cathode P+, ​​the first electrostatic discharge protection substructure PESD, NW, the second electrostatic discharge protection substructure PESD, and the anode N+ fully conduct, as shown in L22 in the figure. In the figure, the diode trigger current path L21 and the conduction current path L22 are represented by different types of line segments.

[0042] As described above, by arranging the first semiconductor region group 21 and the second semiconductor region group 22 side by side on the second conductivity type well 12, the first conductivity type semiconductor regions and the second conductivity type semiconductor regions on the first semiconductor region group 21 are arranged alternately with the first conductivity type semiconductor regions and the second conductivity type semiconductor regions on the second semiconductor region group 22, the second conductivity type semiconductor region in the middle of the first semiconductor region group 21 is short-circuited with the first conductivity type semiconductor region in the middle of the second semiconductor region group 22, the first anode structure 31 is arranged on the first conductivity type semiconductor region at the first end of the first semiconductor region group 21, and the second anode structure 32 is arranged on the second half of the first semiconductor region group 21. On the second conductivity type semiconductor region at the second end of the conductor region group 22, a first cathode structure 41 is arranged on the first conductivity type semiconductor region at the second end of the first semiconductor region group 21, and a second cathode structure 42 is arranged on the second conductivity type semiconductor region at the first end of the second semiconductor region group 22. The first electrostatic protection structure 51 is arranged below the first semiconductor region group 21, and the second electrostatic protection structure 52 is arranged below the second semiconductor region group 22. This can effectively shorten the anode-cathode spacing, reduce the device on-resistance and increase the failure current. At the same time, the P-well setting is eliminated, which can effectively reduce the area of ​​the bidirectional diode-triggered thyristor and reduce the limitation on the application range of the device.

[0043] This application also provides a semiconductor device, which is provided with a bidirectional DTSCR electrostatic discharge protection device as provided in any embodiment of this application. The technical effects that the bidirectional DTSCR electrostatic discharge protection device provided in this application can achieve can also be achieved by this semiconductor device, and will not be repeated here.

[0044] The above description is merely a preferred embodiment and the technical principles employed in this application. This application is not limited to the specific embodiments provided herein, and various obvious changes, readjustments, and substitutions that can be made by those skilled in the art will not depart from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the claims.

Claims

1. A bidirectional DTSCR electrostatic discharge protection device, characterized in that, include: A first conductivity type substrate and a second conductivity type well, wherein the second conductivity type well is located on the first conductivity type substrate; A first semiconductor region group and a second semiconductor region group are arranged side-by-side on a second conductivity type well. The first semiconductor region group includes a plurality of alternating first conductivity type semiconductor regions and second conductivity type semiconductor regions. The second semiconductor region group includes a plurality of alternating second conductivity type semiconductor regions and first conductivity type semiconductor regions. The first conductivity type semiconductor regions and second conductivity type semiconductor regions on the first semiconductor region group are arranged alternately with the first conductivity type semiconductor regions and second conductivity type semiconductor regions on the second semiconductor region group. The second conductivity type semiconductor region in the middle of the first semiconductor region group is short-circuited with the first conductivity type semiconductor region in the middle of the second semiconductor region group. A first anode structure and a second anode structure, wherein the first anode structure is disposed on a first conductivity type semiconductor region at a first end of the first semiconductor region group, and the second anode structure is disposed on a second conductivity type semiconductor region at a second end of the second semiconductor region group; A first cathode structure and a second cathode structure, wherein the first cathode structure is disposed on a first conductivity type semiconductor region at the second end of the first semiconductor region group, and the second cathode structure is disposed on a second conductivity type semiconductor region at the first end of the second semiconductor region group; A first electrostatic discharge (ESD) protection structure and a second ESD protection structure are arranged below the first semiconductor region group.

2. The bidirectional DTSCR electrostatic discharge protection device according to claim 1, characterized in that, The first electrostatic discharge (ESD) protection structure includes a first ESD protection substructure and a second ESD protection substructure. The first ESD protection substructure is disposed below a first conductivity type semiconductor region at the first end of the first semiconductor region group, and the second ESD protection substructure is disposed below a first conductivity type semiconductor region at the second end of the first semiconductor region group.

3. The bidirectional DTSCR electrostatic discharge protection device according to claim 1, characterized in that, The first semiconductor region group includes two semiconductor regions of a first conductivity type and one semiconductor region of a second conductivity type, and the second semiconductor region group includes one semiconductor region of a first conductivity type and two semiconductor regions of a second conductivity type.

4. The bidirectional DTSCR electrostatic discharge protection device according to claim 1, characterized in that, Also includes: A first blocking structure and a second blocking structure, wherein the first blocking structure is disposed between a first conductivity type semiconductor region and a second conductivity type semiconductor region on the first semiconductor region group, and the second blocking structure is disposed between a first conductivity type semiconductor region and a second conductivity type semiconductor region on the second semiconductor region group.

5. The bidirectional DTSCR electrostatic discharge protection device according to claim 4, characterized in that, The first and second barrier structures are silicide barrier layers.

6. The bidirectional DTSCR electrostatic discharge protection device according to claim 1, characterized in that, The second conductivity type semiconductor region in the middle of the first semiconductor region group is shorted to the first conductivity type semiconductor region in the middle of the second semiconductor region group by a metal.

7. The bidirectional DTSCR electrostatic discharge protection device according to any one of claims 1-6, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type.

8. The bidirectional DTSCR electrostatic discharge protection device according to claim 7, characterized in that, The first semiconductor region group includes a first conductivity type semiconductor region, a second conductivity type semiconductor region, and a first conductivity type semiconductor region arranged in sequence. The second semiconductor region group includes a second conductivity type semiconductor region, a first conductivity type semiconductor region, and a second conductivity type semiconductor region arranged in sequence. The second conductivity type semiconductor region in the first semiconductor region group and the first conductivity type semiconductor region in the second semiconductor region group are short-circuited.

9. The bidirectional DTSCR electrostatic discharge protection device according to claim 1, characterized in that, The second type of conductive well has trenches arranged on both sides of the first semiconductor region group and on both sides of the second semiconductor region group.

10. A semiconductor device, characterized in that, Includes the bidirectional DTSCR electrostatic discharge protection device as described in any one of claims 1-9.

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