Method of manufacturing an image sensor

Abstract

The application provides a manufacturing method of an image sensor. In the manufacturing method, a silicon oxide material layer is formed on a second hard mask material layer, and the silicon oxide material layer covers the second hard mask material layer; a part of the thickness of the silicon oxide material layer is removed by grinding, so that the silicon oxide material layer is flat away from the top surface of the second hard mask material layer; a photoresist is coated on the silicon oxide material layer to form a second photoresist layer, the second photoresist layer is exposed and developed to form a patterned second photoresist layer; the patterned second photoresist layer is used as a mask to etch the silicon oxide material layer and the second hard mask material layer and stop on a substrate; and the second hard mask material layer is used as a mask to etch the substrate to form a groove accommodating a vertical transfer gate. In this way, the deposition and grinding of the silicon oxide material layer can expand the photolithography process window of the vertical transfer gate in the image sensor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for manufacturing an image sensor. Background Technology

[0002] CIS chips refer to CMOS image sensor chips, which are indispensable core components in modern digital cameras, mobile phones, tablets, and other electronic products. Shallow Trench Isolation (STI) technology is frequently used in CIS processes. This involves etching shallow trenches on a silicon wafer and then filling them with silicon oxide to form an electrically isolated shallow trench isolation structure. With the miniaturization of devices, image sensor pixels are becoming increasingly dense while their size is decreasing, requiring a corresponding reduction in the size of the transfer gates that contact the photodiodes. However, reducing the size of the transfer gates leads to a decrease in the pixel fill power, resulting in more noise in the image sensor. The transfer gates of image sensors are typically located below the photodiodes. Changing the transfer gate structure from horizontal to vertical allows for the formation of deeper photodiodes within the pixel, enabling more electrons to pass through the transfer gates to the floating diffusion nodes, achieving the goal of capturing more electrons in a smaller space. This is known as Vertical Transfer Gate (VTG) technology. The typical design of a vertical transfer gate involves creating holes in the silicon substrate at the edge of the STI (Self-Transfer Gate). Since the STI protrudes a certain height on the substrate surface, it affects the photolithography window of the vertical transfer gate. Summary of the Invention

[0003] One of the purposes of this application is to provide a method for fabricating an image sensor that can expand the photolithography process window of the vertical transmission gate in the image sensor.

[0004] To achieve the above objectives, the method for fabricating an image sensor provided in this application includes: providing a substrate having an isolation structure, the top surface of the isolation structure protruding from the top surface of the substrate; forming a second hard mask material layer on the substrate, the second hard mask material layer covering the substrate and the isolation structure; forming a silicon oxide material layer on the second hard mask material layer, the silicon oxide material layer covering the second hard mask material layer; grinding away a portion of the thickness of the silicon oxide material layer, making the top surface of the silicon oxide material layer flat away from the second hard mask material layer; coating photoresist on the silicon oxide material layer to form a second photoresist layer; exposing and developing the second photoresist layer to form a patterned second photoresist layer; using the patterned second photoresist layer as a mask, etching the silicon oxide material layer and the second hard mask material layer and stopping on the substrate; and using the second hard mask material layer as a mask, etching the substrate to form a groove accommodating a vertical transmission gate.

[0005] Optionally, the second hard mask material layer may be formed using a low-pressure chemical vapor deposition process, an atomic layer deposition process, or a plasma-enhanced chemical vapor deposition process.

[0006] Optionally, the second hard mask material layer includes a silicon nitride layer.

[0007] Optionally, in the step of forming a silicon oxide material layer on the second hard mask material layer, the thickness of the silicon oxide material layer is set according to the height of the top surface of the isolation structure protruding from the top surface of the substrate.

[0008] Optionally, the silicon oxide material layer is removed after etching the silicon oxide material layer and the second hard mask material layer and before etching the substrate.

[0009] Optionally, the method for fabricating the image sensor further includes: after forming the groove, removing the second hard mask material layer; forming a gate oxide layer on the inner surface of the groove; and filling the groove with polysilicon to form a vertical transmission gate.

[0010] Optionally, after forming the groove to accommodate the vertical transmission gate and before removing the second hard mask material layer, ion implantation is performed on the substrate of the groove sidewalls and bottom surface.

[0011] Optionally, a wet etching process can be used to remove the patterned second hard mask layer.

[0012] Optionally, the method of forming an isolation structure in the substrate includes: forming a patterned first hard mask layer on the substrate; etching the substrate to form trenches using the patterned first hard mask layer as a mask; depositing an isolation material on the substrate, the isolation material covering the patterned first hard mask layer and filling the trenches; grinding away the isolation material above the patterned first hard mask layer and stopping at the patterned first hard mask layer, retaining the isolation material in the trenches; and removing the patterned first hard mask layer to form an isolation structure with its top surface protruding from the top surface of the substrate.

[0013] Optionally, a pad oxide layer is formed on the substrate before the first hard mask layer is formed; after the patterned first hard mask layer is removed, the pad oxide layer is removed to form an isolation structure with its top surface protruding from the top surface of the substrate.

[0014] In the image sensor fabrication method provided in this application, a silicon oxide material layer is formed on a second hard mask material layer, the silicon oxide material layer covering the second hard mask material layer; then, a portion of the thickness of the silicon oxide material layer is removed by grinding, making the top surface of the silicon oxide material layer flat away from the second hard mask material layer; next, photoresist is coated on the silicon oxide material layer to form a second photoresist layer, the second photoresist layer is exposed and developed to form a patterned second photoresist layer; then, using the patterned second photoresist layer as a mask, the silicon oxide material layer and the second hard mask material layer are etched and stopped on the substrate; using the second hard mask material layer as a mask, the substrate is etched to form a groove accommodating a vertical transmission gate. This application adds a silicon oxide material layer on the second hard mask material layer, and then grinds the silicon oxide material layer flat. This allows subsequent photolithography to be performed on the flat surface of the silicon oxide material layer, and the thickness of each region of the second photoresist layer is uniform, which helps to expand the photolithography process window of the vertical transfer gate. In addition, since silicon oxide has a good grinding rate, and both silicon oxide deposition and grinding are mature processes in the semiconductor field, the silicon oxide material layer deposition and grinding process added before photoresist coating in this application is easy to implement and has low process difficulty, and does not require additional equipment, thus having a small impact on manufacturing costs.

[0015] Furthermore, this application removes the silicon oxide material layer after etching the silicon oxide material layer and the hard mask material layer, but before etching the substrate, so that the silicon oxide material layer will not affect the subsequent etching process for forming grooves on the substrate. Attached Figure Description

[0016] Figures 1 to 4 This is a step-by-step structural diagram of an image sensor fabrication method.

[0017] Figure 5 This is a schematic flowchart illustrating a method for manufacturing an image sensor according to an embodiment of this application.

[0018] Figures 6 to 13 This is a step-by-step structural diagram of a method for manufacturing an image sensor according to an embodiment of this application.

[0019] Explanation of reference numerals in the attached figures: 1-substrate; 2-shallow trench isolation structure; 3-silicon nitride material layer; 4-photoresist layer; 100-substrate; 101-isolation structure; 102-second hard mask material layer; 103-silicon oxide material layer; 104a-second photoresist layer; 104-patterned second photoresist layer; 105-groove; 106-gate oxide layer; 107-vertical transport gate. Detailed Implementation

[0020] Figures 1 to 4This is a schematic diagram illustrating the step-by-step structure of a method for fabricating an image sensor. Related technology provides a method for fabricating an image sensor, which includes the following steps: (Refer to...) Figure 1 As shown, a silicon nitride material layer 3 is formed on a substrate 1 having a shallow trench isolation structure 2, and the silicon nitride material layer 3 covers the substrate 1 and the shallow trench isolation structure 2; Reference Figure 2 As shown, photoresist is coated onto silicon nitride material layer 3 to form photoresist layer 4; Reference Figure 3 As shown, the photoresist layer 4 is exposed and developed to complete the patterning process of the photoresist layer 4; Reference Figure 3 and Figure 4 As shown, using photoresist layer 4 as a mask, silicon nitride material layer 3 is etched to complete the patterning of silicon nitride material layer 3; then, using silicon nitride material layer 3 as a mask, substrate 1 is etched to form a groove to accommodate the vertical transmission gate.

[0021] However, since the top surface of the shallow trench isolation structure 2 protrudes from the top surface of the substrate 1, a slope will be formed on the surface of the silicon nitride material layer 3 after it is formed. When photoresist is coated on the slope, although the surface of the resulting photoresist layer 4 is flat, due to the existence of the slope, some areas of the photoresist layer 4 are thicker and some areas are thinner. Since the exposure energy required for the thinner areas is less and the exposure energy required for the thicker areas is more, it is necessary to ensure that both the thin and thick areas have a good profile, resulting in a smaller lithography window. This is especially true for higher node processes, where the original window is already small. Therefore, a better method is needed to improve the lithography process window.

[0022] In the image sensor fabrication method provided in this application, a silicon oxide material layer is formed on the second hard mask material layer, and then the top surface of the silicon oxide material layer is ground flat. This allows subsequent photolithography to be performed on the flat surface of the silicon oxide material layer, making the thickness of the second photoresist layer uniform in all areas. This helps to expand the photolithography process window of the vertical transfer gate. In addition, since silicon oxide has a good grinding rate, and the deposition and grinding of silicon oxide are mature processes in the semiconductor field, the deposition and grinding of the silicon oxide material layer added before the photolithography process of the vertical transfer gate in this application is easy to implement and has low process difficulty. It does not require additional equipment and has little impact on manufacturing costs.

[0023] Furthermore, in this application, after etching the silicon oxide material layer and the hard mask material layer and before etching the substrate to form a groove, the silicon oxide material layer is removed, so that the silicon oxide material layer does not affect the subsequent etching process of etching the substrate to form a groove.

[0024] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present application.

[0025] For ease of description, some embodiments of this application may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence. It should be understood that these terms, as used, may be replaced where appropriate.

[0026] Figure 5 This is a schematic flowchart illustrating a method for fabricating an image sensor according to an embodiment of this application. (Reference) Figure 5 As shown, the method for manufacturing an image sensor provided in this embodiment includes:

[0027] Step S1: Provide a substrate having an isolation structure, the top surface of the isolation structure protruding from the top surface of the substrate;

[0028] Step S2: A second hard mask material layer is formed on the substrate, the second hard mask material layer covering the substrate and the isolation structure;

[0029] Step S3: A silicon oxide material layer is formed on the second hard mask material layer, the silicon oxide material layer covering the second hard mask material layer;

[0030] Step S4: Grinding removes part of the thickness of the silicon oxide material layer, making the top surface of the silicon oxide material layer flat away from the second hard mask material layer;

[0031] Step S5: Coat the silicon oxide material layer with photoresist to form a second photoresist layer, expose and develop the second photoresist layer to form a patterned second photoresist layer.

[0032] Step S6: Using the patterned second photoresist layer as a mask, etch the silicon oxide material layer and the second hard mask material layer and stop on the substrate;

[0033] Step S7: Using the second hard mask material layer as a mask, the substrate is etched to form a groove for accommodating the vertical transmission gate.

[0034] Figures 6 to 13 This is a step-by-step structural diagram illustrating a method for fabricating an image sensor according to an embodiment of this application. The following is in conjunction with... Figure 5 , Figures 6 to 13 The method for manufacturing the image sensor in this embodiment will be described.

[0035] refer to Figure 6 As shown, the substrate 100 provided in step S1 has an isolation structure 101, the top surface of which protrudes from the top surface of the substrate 100.

[0036] For example, the substrate 100 may be any suitable substrate known in the art, such as at least one of the following materials: silicon, germanium, silicon germanium, silicon carbide, silicon germanium carbide, indium arsenide, gallium arsenide, indium phosphide, or other III / V compound semiconductors, and may also include multilayer structures composed of these semiconductors, or silicon on insulator, germanium on insulator, and silicon germanide on insulator, etc.

[0037] For example, the isolation structure 101 may be a shallow trench isolation structure (STI). For example, a method of forming the isolation structure 101 in the substrate 100 may include: forming a first hard mask material layer (not shown) on the substrate 100, the first hard mask material layer covering the top surface of the substrate 100; forming a patterned first photoresist layer (not shown) on the first hard mask material layer; etching the first hard mask material layer using the patterned first photoresist layer as a mask to form a patterned first hard mask layer; removing the patterned first photoresist layer; etching the substrate 100 using the patterned first hard mask layer as a mask to form a trench; depositing an isolation material on the substrate 100, the isolation material covering the patterned first hard mask layer and filling the trench; grinding away the isolation material above the patterned first hard mask layer and stopping at the patterned first hard mask layer, retaining the isolation material within the trench; removing the patterned first hard mask layer to form an isolation structure 101 with its top surface protruding from the top surface of the substrate 100.

[0038] In one embodiment of this application, a pad oxide layer is formed on the substrate 100 before the first hard mask material layer is formed; after the patterned first hard mask layer is removed, the pad oxide layer is removed to form an isolation structure 101 with its top surface protruding from the top surface of the substrate.

[0039] In this embodiment, the isolation structure 101 can be used to electrically isolate photodiodes and MOS transistors on both sides of the isolation structure 101.

[0040] In step S2, refer to Figure 6 As shown, a second hard mask material layer 102 is formed on the substrate 100, the second hard mask material layer 102 covering the substrate 100 and the isolation structure 101. Figure 6 As shown, the top surface of the second hard mask material layer 102 undulates with the protrusion of the isolation structure 101.

[0041] In this embodiment, the second hard mask material layer 102 can be a silicon nitride layer. In other embodiments, the second hard mask material layer 102 can also be a stacked structure formed by stacking different material layers, such as including a silicon oxide layer and a silicon nitride layer located on the silicon oxide layer, but is not limited thereto.

[0042] For example, the second hard mask material layer 102 is formed using a low-pressure chemical vapor deposition (LPCVD) process, an atomic layer deposition (ALD) process, or a plasma-enhanced chemical vapor deposition (PECVD) process.

[0043] Because the reactant gas in the low-pressure chemical vapor deposition process has a large mean free path, slow flow rate, and is dominated by molecular diffusion, the precursor is uniformly spread across the entire wafer surface without large-area local accumulation and erosion, resulting in good step coverage. In a preferred embodiment, a second hard mask material layer 102 can be formed on the substrate 100 using the low-pressure chemical vapor deposition process, so that the surface of the second hard mask material layer 102 covering the substrate 100 and the isolation structure 101 has small undulations and is relatively smooth. This can reduce the thickness and grinding amount of the subsequent silicon oxide material layer 103.

[0044] For example, the low-pressure chemical vapor deposition process is carried out in a furnace tube, and the pressure inside the furnace tube can be greater than or equal to 180 mtorr and less than or equal to 200 mtorr, for example, 190 mtorr; the reaction gases used in the low-pressure chemical vapor deposition process may include dichlorosilane (DCS) and ammonia (NH3), the flow rate of the dichlorosilane can be greater than or equal to 114 sccm and less than or equal to 126 sccm; the flow rate of the ammonia can be greater than or equal to 456 sccm and less than or equal to 504 sccm, but is not limited thereto. During the formation of the second hard mask material layer 102, the substrate 100 (i.e., the wafer) can be placed in the middle region of the furnace tube, that is, the edge region of the furnace tube can be used for production without placing the wafer. Since the stability of the middle region of the furnace tube is better, placing the substrate 100 in the middle region of the furnace tube helps to reduce the step difference on the surface of the second hard mask material layer 102.

[0045] In this embodiment, the temperature of the low-pressure chemical vapor deposition process can be greater than or equal to 580°C and less than or equal to 800°C, for example, 760°C. Forming the second hard mask material layer 102 at a temperature below 800°C helps to reduce the step difference on the surface of the second hard mask material layer 102.

[0046] In step S3, refer to Figure 7 As shown, a silicon oxide material layer 103 is formed on the second hard mask material layer 102, and the silicon oxide material layer 103 covers the second hard mask material layer 102.

[0047] For example, the silicon oxide material layer 103 can be formed by methods such as atmospheric pressure chemical vapor deposition (APCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), low pressure chemical vapor deposition, or plasma-enhanced chemical vapor deposition.

[0048] It should be noted that in this application, if Figure 7 As shown, the top surface of the silicon oxide material layer 103 undulates with the undulation of the second hard mask material layer 102, and the top surface of the second hard mask material layer 102 undulates with the protrusion of the isolation structure 101 on the top surface of the substrate 100. Therefore, the thickness of the silicon oxide material layer 103 can be set according to the height of the top surface of the isolation structure 101 protruding from the top surface of the substrate 100. More specifically, it can be set according to the height difference between the top surfaces of the second hard mask material layer 102 directly above the isolation structure 101 and the second hard mask material layer 102 on the side of the isolation structure 101. Preferably, the silicon oxide material layer 103 can cover the second hard mask material layer 102 after the top surface is ground flat. In this way, only silicon oxide is ground during the grinding process of the silicon oxide material layer 103, without the difference in the grinding selectivity of different materials, resulting in better surface flatness after grinding.

[0049] In step S4, refer to Figure 8 As shown, grinding removes part of the thickness of the silicon oxide material layer 103, making the top surface of the silicon oxide material layer 103 flat away from the second hard mask material layer 102.

[0050] In this embodiment, a portion of the thickness of the silicon oxide material layer 103 can be removed using a chemical mechanical polishing (CMP) process. During the polishing of the silicon oxide material layer 103, polishing can be stopped within the silicon oxide material layer 103, ensuring that the top surface of the silicon oxide material layer 103 is polished flat, resulting in a smooth surface after polishing; alternatively, polishing can be stopped precisely on the surface of the protruding second hard mask material layer 102.

[0051] In step S5, refer to Figure 9 As shown, a second photoresist layer 104a is formed by coating photoresist onto the silicon oxide material layer 103, with reference to... Figure 10 As shown, the second photoresist layer 104a is exposed and developed to form a patterned second photoresist layer 104.

[0052] In this embodiment, since a silicon oxide material layer 103 is formed on the second hard mask material layer 102 and the top surface of the silicon oxide material layer 103 is planarized, the thickness uniformity of each region of the second photoresist layer 104a formed on the silicon oxide material layer 103 is good. As a result, the exposure energy of the second photoresist layer 104a is less restricted by the thickness difference of the second photoresist layer 104a, thereby expanding the photolithography process window.

[0053] In step S6, refer to Figure 10 and Figure 11 As shown, using the patterned second photoresist layer 104 as a mask, the silicon oxide material layer 103 and the second hard mask material layer 102 are etched and the etching stops on the substrate 100, leaving the second hard mask material layer 102 as the patterned second hard mask layer.

[0054] For example, the silicon oxide material layer 103 and the second hard mask material layer 102 can be etched by a dry etching process, but it is not limited thereto.

[0055] Afterwards, refer to Figure 11 As shown, the patterned second photoresist layer 104 can be removed by an ashing process, and the wafer can be wet-cleaned after the patterned second photoresist layer 104 is removed.

[0056] In step S7, refer to Figure 12 As shown, the substrate 100 is etched using the second hard mask material layer 102 as a mask to form a groove 105 for accommodating the vertical transmission gate.

[0057] In this embodiment, a dry etching process can be used to etch the substrate 100 to form the groove 105.

[0058] In this embodiment, reference Figure 12 As shown, after the patterning of the second hard mask material layer 102 is completed and before the substrate 100 is etched to form the groove 105, the remaining silicon oxide material layer 103 on the second hard mask material layer 102 can be removed. This way, the silicon oxide material layer 103 will not affect the subsequent etching process for forming the groove on the substrate, allowing the etching gas to pass through the second hard mask material layer 102 to etch the substrate 100. Of course, in some embodiments, the remaining silicon oxide material layer 103 and the second hard mask material layer 102 can be removed sequentially after the groove 105 is formed.

[0059] In this embodiment, the groove 105 is located on the side of the isolation structure 101 and is disposed close to the isolation structure 101.

[0060] refer to Figure 13 As shown, after forming the groove 105, the second hard mask material layer 102 is removed; then, a gate oxide layer 106 is formed on the inner surface of the groove 105. For example, the gate oxide layer 106 can be formed by a process such as thermal oxidation, and the material of the gate oxide layer 106 includes, but is not limited to, silicon oxide; then, polysilicon is filled into the groove 105 to form a vertical transport gate 107. The gate oxide layer 106 may also cover the substrate surface on the side of the groove 105, but is not limited thereto.

[0061] In this embodiment, after forming the groove 105 and before forming the gate oxide layer 106, the substrate 100 can be pre-cleaned to avoid the influence of natural oxides and impurities on the quality of the gate oxide layer 106.

[0062] In this embodiment, the second hard mask material layer 102 can be removed by a wet etching process, but it is not limited to this.

[0063] In some embodiments, after forming the groove 105 that accommodates the vertical transmission gate 107 and before removing the second hard mask material layer 102, ion implantation can be performed on the substrate of the sidewalls and bottom surface of the groove 105, followed by heat treatment of the substrate 100. This allows for doping adjustment of the substrate 100, which helps to improve the performance of the image sensor.

[0064] In this embodiment, the image sensor also includes a photodiode and a floating diffusion node. The substrate around the vertical transmission gate can contact the photodiode, and the electrons generated by the photodiode can be moved to the floating diffusion node under the control of the vertical transmission gate 107.

[0065] It should be noted that the deposition and polishing of the silicon oxide material layer 103 added in the image sensor fabrication method of this application is easy to implement and has low process difficulty. It does not require additional materials or equipment and has little impact on manufacturing costs.

[0066] In the image sensor fabrication method provided in this application, a silicon oxide material layer 103 is formed on a second hard mask material layer 102, the silicon oxide material layer 103 covering the second hard mask material layer 102; then, grinding removes a portion of the thickness of the silicon oxide material layer 103, making the top surface of the silicon oxide material layer 103 flat away from the second hard mask material layer 102; next, photoresist is coated on the silicon oxide material layer 103 to form a second photoresist layer 104a, the second photoresist layer 104a is exposed and developed to form a patterned second photoresist layer 104; then, using the patterned second photoresist layer 104 as a mask, the silicon oxide material layer 103 and the second hard mask material layer 102 are etched and stopped on the substrate 100; using the second hard mask material layer 102 as a mask, the substrate 100 is etched to form a groove 105 accommodating a vertical transmission gate 107. In this application, a silicon oxide material layer 103 is formed on the second hard mask material layer 102, and then the silicon oxide material layer 103 is polished flat. This allows subsequent photolithography to be performed on the flat surface of the silicon oxide material layer 103, and the thickness of each region of the second photoresist layer 104a is consistent, which helps to expand the photolithography process window of the vertical transfer gate. In addition, since silicon oxide has a good polishing rate, and both silicon oxide deposition and polishing are mature processes in the semiconductor field, the silicon oxide material layer deposition and polishing process added in this application is easy to implement and has low process difficulty, and does not require additional equipment, thus having a small impact on manufacturing costs.

[0067] The above description is merely a description of preferred embodiments of this application and is not intended to limit the scope of the claims of this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A method for manufacturing an image sensor, characterized in that, include: A substrate is provided having an isolation structure, the top surface of which protrudes from the top surface of the substrate; A second hard mask material layer is formed on the substrate, the second hard mask material layer covering the substrate and the isolation structure; A silicon oxide material layer is formed on the second hard mask material layer, the silicon oxide material layer covering the second hard mask material layer; Grinding removes a portion of the thickness of the silicon oxide material layer, making the top surface of the silicon oxide material layer flat away from the second hard mask material layer; A second photoresist layer is formed by coating photoresist onto the silicon oxide material layer, and the second photoresist layer is exposed and developed to form a patterned second photoresist layer. Using the patterned second photoresist layer as a mask, the silicon oxide material layer and the second hard mask material layer are etched and the etching stops on the substrate; Using the second hard mask material layer as a mask, the substrate is etched to form a groove that accommodates the vertical transmission gate.

2. The method for manufacturing an image sensor as described in claim 1, characterized in that, The second hard mask material layer is formed using low-pressure chemical vapor deposition, atomic layer deposition, or plasma-enhanced chemical vapor deposition.

3. The method for manufacturing an image sensor as described in claim 1, characterized in that, The second hard mask material layer includes a silicon nitride layer.

4. The method for manufacturing an image sensor as described in claim 1, characterized in that, In the step of forming a silicon oxide material layer on the second hard mask material layer, the thickness of the silicon oxide material layer is set according to the height of the top surface of the isolation structure protruding from the top surface of the substrate.

5. The method for manufacturing an image sensor as described in claim 1, characterized in that, The silicon oxide material layer is removed after etching the silicon oxide material layer and the second hard mask material layer and before etching the substrate.

6. The method for manufacturing an image sensor as described in claim 1, characterized in that, Also includes: After the groove is formed, the second hard mask material layer is removed; A gate oxide layer is formed on the inner surface of the groove; as well as Polysilicon is filled into the groove to form a vertical transmission gate.

7. The method for manufacturing an image sensor as described in claim 6, characterized in that, After forming the groove to accommodate the vertical transmission gate and before removing the second hard mask material layer, ion implantation is performed on the substrate of the groove sidewalls and bottom surface.

8. The method for manufacturing an image sensor as described in claim 6, characterized in that, The patterned second hard mask layer is removed using a wet etching process.

9. The method for manufacturing an image sensor as described in claim 1, characterized in that, The method of forming an isolation structure in the substrate includes: A patterned first hard mask layer is formed on the substrate; Using the patterned first hard mask layer as a mask, the substrate is etched to form trenches; An isolation material is deposited on the substrate, the isolation material covering the patterned first hard mask layer and filling the trench; Grinding removes the insulating material above the patterned first hard mask layer and stops at the patterned first hard mask layer, retaining the insulating material within the trench; and Remove the patterned first hard mask layer to form an isolation structure with its top surface protruding from the top surface of the substrate.

10. The method for manufacturing an image sensor as described in claim 9, characterized in that, Before forming the first hard mask layer, a pad oxide layer is also formed on the substrate; after removing the patterned first hard mask layer, the pad oxide layer is removed to form an isolation structure with its top surface protruding from the top surface of the substrate.

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