A method and system for vertical eight-layer package of a mass storage chip

Abstract

The application discloses a vertical eight-layer stack packaging method and system of a large-capacity storage chip, relates to the technical field of electronic storage devices, and comprises the following steps: calculating a target deviation by subtracting the measured thickness of a storage chip original wafer from a target thickness, and inputting the grinding of a thinning machine; the chip is thinned to 60 mu m, the fifth layer chip is thickened to 100 mu m, the initial vacuum degree is set according to the chip area and the suction nozzle size after grinding, the chip picking is completed, the target offset is calculated by combining the chip length-width ratio and the solidification shrinkage of the DAF film, the first to fourth layer chips are stacked with a misplacement and a lead bonding gap is reserved, the lead bonding is completed, and secondary lead bonding is carried out for reinforcement, the fifth layer chip with a thickness of 100 mu m is attached as a suspended bearing substrate, the sixth to eighth layer chips are stacked and subjected to hot-pressing curing treatment, and the pad is corrected to complete the top layer lead bonding. The embodiment solves the problems of eight-layer stack suspension stress, space interference and ultra-thin chip cracking.

Description

Technical Field

[0001] This application relates to the field of electronic storage device technology, specifically to a vertical eight-layer stacked packaging method, system, electronic device, and computer-readable storage medium for a large-capacity storage chip. Background Technology

[0002] Traditional four-chip stacked packaging can no longer meet the growing demand for high capacity. A single packaged chip needs to carry a larger capacity. Within the same package area and limited space, the capacity needs to be increased by increasing the number of chips. The evolution from conventional four-chip stacking to eight-chip stacking aims to break through the stacking space limitation through process optimization while keeping the package thickness unchanged.

[0003] To address the industry's pain points at their root and achieve a large-capacity upgrade of memory chips, while overcoming the technical challenges brought about by high stacking, the key breakthrough lies in solving the structural stress problem in the high stacking structure, especially the suspended area between the fifth and eighth chips, where mechanical stress can cause the chips to crack. Summary of the Invention

[0004] To address the issues of spatial interference and stress in suspended structures during high-density stacked packaging, this application aims to provide a method, system, electronic device, and computer-readable storage medium for vertical eight-layer stacked packaging of high-capacity memory chips.

[0005] In a first aspect, the present application describes a method for vertical eight-layer stacked packaging of a large-capacity memory chip, comprising:

[0006] The difference between the original wafer thickness and the target thickness of the memory chip is calculated as the target deviation of the wafer thickness, and the target deviation is input into the thinning machine for thinning.

[0007] The first to fourth layers of the chip are thinned to 60μm, and the fifth layer of the chip is thickened to 100μm to counteract the suspended stress generated by the stacking of the sixth to eighth layers of the chip.

[0008] After thinning, the chip bottom area is calculated based on the chip length and chip width. The initial vacuum level is calculated in combination with the nozzle size of the ejector mechanism. The vacuum level and pick-up force are corrected by predicting the deformation of the chip peeling through a regression model to obtain the chip to be mounted.

[0009] The target offset is calculated by combining the aspect ratio of the chip and the curing shrinkage of the DAF film. The first to fourth layers of 60μm chips are stacked in a staggered manner, with gaps reserved for wire bonding between adjacent chips, to obtain a stepped stacked assembly.

[0010] First, complete all wire bonding for the first to fourth layers of the chip, and then perform secondary wire bonding reinforcement based on the arc value of the wire bonding and the power value to obtain the target bottom layer bonding structure.

[0011] A 100μm fifth-layer chip is mounted on the target bottom bonding structure to form a suspended bearing substrate;

[0012] The sixth to eighth layers of chips are stacked sequentially on the suspended support substrate, and after DAF alignment and hot pressing, a uniform thermosetting process is performed to obtain the target eight-layer stacked component.

[0013] After correcting the pad coordinates of the target eight-layer stacked component, the top layer wire bonding is completed. After verifying that the curvature value of the bonding line is qualified, pre-encapsulation baking is performed.

[0014] Preferably, the difference between the original measured thickness of the computing memory chip wafer and the target thickness is used as the target deviation of the wafer thickness. The target deviation is input into a thinning machine for thinning processing, including:

[0015] Obtain the original thickness of the original wafer and the preset target thickness, perform difference calculation, and obtain the target deviation of the wafer thickness;

[0016] The target deviation amount drives the thinning machine to perform a thinning process on the original wafer.

[0017] Preferably, after the thinning process, the chip bottom area is calculated based on the chip length and width, and the initial vacuum level is calculated in conjunction with the nozzle size of the ejector mechanism. The vacuum level and pickup force are corrected by predicting the deformation of the chip during peeling using a regression model, and the chip to be mounted is obtained, including:

[0018] Extract the chip length and chip width, perform calculations, and obtain the chip bottom area;

[0019] The initial deformation is obtained by extracting the chip's bottom area and the preset nozzle size;

[0020] The initial deformation is determined to obtain the target vacuum level;

[0021] The initial picking force is obtained based on the target vacuum level and the preset peeling speed;

[0022] The initial pickup force is processed to obtain the target pickup force;

[0023] The target picking force and the preset mounting force are calculated to obtain control commands;

[0024] The control commands drive the pick-and-place machine to pick up chips according to the target vacuum level and the target pickup force, thereby obtaining the chips to be mounted.

[0025] Preferably, the step of calculating the target offset by combining the aspect ratio of the chip and the curing shrinkage of the DAF film, and stacking the first to fourth layers of 60μm chips in a staggered manner, with gaps reserved for wire bonding between adjacent chips, to obtain a stepped stacked assembly, includes:

[0026] Calculate the chip length and chip width to obtain the chip's aspect ratio;

[0027] The initial offset of the chip is obtained based on the aspect ratio of the chip and the preset edge distance.

[0028] The initial offset and the preset DAF film thickness are obtained, and prediction processing is performed to obtain the target offset of the chip.

[0029] Based on the target offset, interleaved positioning processing is performed on the first to fourth layer chips to obtain the stepped stacked components of the first to fourth layer chips.

[0030] Preferably, the step of first completing all wire bonding for the first to fourth layers of the chip, and then performing secondary wire bonding reinforcement based on the arc value of the wire bonding and matching the power value, to obtain the target bottom layer bonding structure, includes:

[0031] Extract the pad spacing of the stepped stacked components of the first to fourth layers of chips, and obtain the initial bonding wires based on the pad spacing and the preset wire diameter.

[0032] The initial bonding line is predicted to obtain the target bonding line;

[0033] Wire bonding is performed on the stepped stacked assembly via the target bonding wire;

[0034] Perform secondary wire bonding reinforcement processing to obtain the target underlying bonding structure.

[0035] Preferably, obtaining the target eight-layer stacked component includes:

[0036] A 100μm fifth-layer chip is mounted onto the target bottom bonding structure to form a suspended support substrate;

[0037] The suspended support substrate is thinned to obtain a thinned wafer;

[0038] The thinned wafer is subjected to DAF lamination and DAF simultaneous dicing to prepare a DAF pre-bonded thinned chip with a solid adhesive film on the bottom surface.

[0039] Using the DAF pre-bonded thinned chip as a substrate, the sixth to eighth layers of chips are placed in sequence and aligned and hot-pressed. The DAF hot-pressing melts and wets the chip interface to obtain the initial eight-layer stacked assembly.

[0040] Perform a thermosetting process on the initial eight-layer stacked assembly to obtain the target eight-layer stacked assembly.

[0041] Preferably, the step of performing pad coordinate correction on the target eight-layer stacked component, completing top-layer wire bonding, and verifying the curvature value of the bonding wires to be qualified before performing pre-molding baking includes:

[0042] The target eight-layer stacked component is cleaned to obtain the component to be bonded;

[0043] The pads of the component to be bonded are identified to obtain the pad positions;

[0044] The offset of the pad position is obtained by comparing it with the preset standard coordinates.

[0045] The offset of the pad position is determined to obtain the target component to be bonded;

[0046] The top four chips of the target component to be bonded are wire bonded using gold wire to obtain bonding wires;

[0047] The bonding line is scanned to obtain the radian value;

[0048] If the radian value is within the preset radian value range, then pre-sealing baking is performed.

[0049] Secondly, the vertical eight-layer stacked packaging system for a large-capacity memory chip described in this application includes:

[0050] The wafer data module calculates the difference between the original measured thickness of the memory chip wafer and the target thickness as the target deviation of the wafer thickness, and inputs the target deviation into the thinning machine for thinning processing.

[0051] After thinning, the pick-up processing module calculates the chip bottom area based on the chip length and width, calculates the initial vacuum level in combination with the nozzle size of the ejector actuator, and corrects the vacuum level and pick-up force by predicting the deformation of chip peeling through a regression model to obtain the chip to be mounted.

[0052] The target offset module calculates the target offset by combining the aspect ratio of the chip and the curing shrinkage of the DAF film, and stacks the first to fourth layers of 60μm chips in a staggered manner, leaving gaps for wire bonding between adjacent chips to obtain a stepped stacked assembly.

[0053] The wire bonding module first completes all wire bonding for the first to fourth layers of the chip, and then performs secondary wire bonding reinforcement based on the arc value of the wire bonding and the power value, to obtain the target bottom layer bonding structure.

[0054] The DAF pre-bonding module mounts a 100μm fifth-layer chip onto the target bottom bonding structure to form a suspended bearing substrate.

[0055] The sixth to eighth layers of chips are stacked sequentially on the suspended support substrate, and after DAF alignment and hot pressing, a uniform thermosetting process is performed to obtain the target eight-layer stacked component.

[0056] The molding process module performs pad coordinate correction on the target eight-layer stacked component, completes the top layer wire bonding, and performs pre-molding baking after verifying that the arc value of the bonding line is qualified.

[0057] Thirdly, this application also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor causes the processor to perform the steps of the vertical eight-layer stacked packaging method for a large-capacity memory chip as described in the first aspect.

[0058] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the vertical eight-layer stacked packaging method for a high-capacity storage chip as described in the first aspect.

[0059] Implementing this embodiment addresses the shortcomings of traditional four-layer stacking (insufficient capacity), eight-layer stacking (prone to suspending stress causing chip cracking), unified wire bonding after all stacking layers (prone to wedge interference), easy breakage during ultra-thin chip handling, and numerous voids due to DAF overflow during layer-by-layer bonding in the prior art. This application offers the following advantages:

[0060] The first to fourth layers of the chip are thinned to 60μm, and the fifth layer is thickened to 100μm to support the upper layer chip, which offsets the suspended bending stress and solves the problem of warping and cracking of high-stacked chips. The bottom four layers of the chip are first stacked in a step and then reinforced with wire bonding to avoid interference with the upper layer mounting space, which greatly improves the bonding yield.

[0061] Simultaneous dicing and prefabrication of adhesive-coated chips at the wafer-level DAF lamination simplifies the process, reduces adhesive overflow and interlayer voids, and the entire process of grinding, picking, and stacking is controlled by a closed-loop algorithm to reduce the breakage rate of ultra-thin chips.

[0062] Eight-layer chip integration is achieved within a limited packaging space, doubling the storage capacity compared to four-layer stacking, while meeting the mass production requirements of miniaturization and high capacity. Attached Figure Description

[0063] Figure 1 This is a flowchart of a vertical eight-layer stacked packaging method for a high-capacity memory chip as described in this application;

[0064] Figure 2This is a schematic diagram of the structural composition of a vertical eight-layer stacked packaging system for a high-capacity memory chip as described in this application;

[0065] Figure 3 This is a frame diagram of the terminal device provided in the embodiments of this application;

[0066] Figure 4 This is a schematic diagram of the vertical eight-layer stacked packaging structure provided in the embodiments of this application. Detailed Implementation

[0067] Example 1

[0068] like Figure 1 As shown, the vertical eight-layer stacked packaging method for a high-capacity memory chip described in this application includes:

[0069] S101. Calculate the difference between the original wafer thickness and the target thickness of the memory chip as the target deviation of the wafer thickness, and input the target deviation into the thinning machine for thinning.

[0070] The first to fourth layers of the chip are thinned to 60μm, and the fifth layer of the chip is thickened to 100μm to counteract the suspended stress generated by the stacking of the sixth to eighth layers of the chip.

[0071] S102. After thinning, calculate the chip bottom area based on the chip length and chip width, calculate the initial vacuum degree in combination with the nozzle size of the ejector mechanism, and correct the vacuum degree and pick-up force by predicting the deformation of chip peeling through regression model to obtain the chip to be mounted.

[0072] S103. Calculate the target offset by combining the aspect ratio of the chip and the curing shrinkage of the DAF film. Stack the first to fourth layers of 60μm chips in a staggered manner, leaving gaps for wire bonding between adjacent chips, to obtain a stepped stacked assembly.

[0073] S104. First, complete all wire bonding for the first to fourth layers of the chip, and then perform secondary wire bonding reinforcement based on the arc value of the wire bonding and the power value to obtain the target bottom layer bonding structure.

[0074] S105. Mount the 100μm fifth-layer chip onto the target bottom bonding structure to form a suspended support substrate;

[0075] The sixth to eighth layers of chips are stacked sequentially on the suspended support substrate, and after DAF alignment and hot pressing, a uniform thermosetting process is performed to obtain the target eight-layer stacked component.

[0076] S106. After correcting the pad coordinates of the target eight-layer stacked component, complete the top layer lead bonding. After verifying that the curvature value of the bonding line is qualified, perform pre-encapsulation baking.

[0077] It should be noted that the suspended support substrate is the upper chip support structure formed by thickening the fifth chip layer.

[0078] Stepped stacked assembly: The first to fourth layers of chips are stacked in a staggered manner to form a lower stack with exposed pad gaps;

[0079] Target bottom layer bonding structure: After the first to fourth layers of chips are stacked in a staggered manner according to the target offset to form a stepped stacked component, the first gold wire bonding is completed on all four layers of chips, and the ultrasonic power is matched according to the curvature of the bonding wire arc to perform secondary wire bonding reinforcement, resulting in a bottom four-layer interconnected semi-finished product.

[0080] DAF pre-bonded thinning chip: The thinning memory chip (fifth layer chip) is integrally laminated with DAF film on the back and synchronously diced, with solid bonding film on the bottom surface.

[0081] Target component to be bonded: a qualified eight-layer chip stack semi-finished product after pad coordinate correction;

[0082] The target eight-layer stacked component is a complete eight-layer chip stacked semi-finished product obtained by DAF hot pressing of the sixth to eighth layers of chips and overall high-temperature curing.

[0083] Furthermore, S101 includes:

[0084] Obtain the original thickness of the original wafer and the preset target thickness, perform difference calculation, and obtain the target deviation of the wafer thickness;

[0085] The target deviation is predicted to obtain the initial grinding force;

[0086] Calculate the initial grinding force to obtain the basic feed rate;

[0087] Based on the basic feed rate and the spindle speed of the thinning machine, the material removal rate is obtained through calculation.

[0088] The material removal rate is determined to obtain the target feed rate;

[0089] Based on the target feed rate, control commands are generated and the thinning machine is driven to perform thinning processing on the original wafer.

[0090] In a specific embodiment, the original thickness of the original wafer and the preset target thickness are obtained, and the target deviation is obtained by calculating the difference between the original thickness and the target thickness.

[0091] The initial grinding force is obtained by inputting the target deviation into the support vector machine regression model for prediction.

[0092] The initial grinding force is processed by a proportional-integral-derivative controller to obtain the basic feed rate.

[0093] The basic feed rate and the spindle speed of the thinning machine are obtained, and the material removal rate is determined by multiplication.

[0094] If the material removal rate is greater than the preset removal rate threshold, the base feed rate is multiplied by the attenuation coefficient to obtain the target feed rate.

[0095] Based on the target feed rate, control instructions are generated, and the thinning machine is driven to perform a thinning process on the original wafer to obtain a wafer of the target thickness.

[0096] Surface cleaning is performed on the wafer of the target thickness, and a stacking assembly process is performed to obtain the target stacked layer.

[0097] Specifically, in S101, the wafer thinning process is performed by a laser interferometric thickness measurement system to scan the original wafer globally and generate an initial thickness distribution matrix. The system analysis shows that the average thickness is 100.05 μm.

[0098] The central control system calls the Preston material removal rate algorithm model to calculate the processing parameters required to achieve the target thickness, and dynamically adjusts the actuator of the thinning machine through the proportional integral derivative control algorithm.

[0099] During the rough grinding stage, the system sets the spindle speed to 3500 r / min, maintains the downward load at 45.5 N, and simultaneously activates real-time closed-loop monitoring.

[0100] The first to fourth layers of the chip are thinned to 60μm, and the fifth layer of the chip is thickened to 100μm to counteract the suspended stress generated by the stacking of the sixth to eighth layers of the chip.

[0101] When the online sensor detects that the wafer thickness has dropped to 65μm, the control system automatically switches to fine grinding mode and smoothly reduces the rotation speed to 1200r / min until the thickness feedback value reaches 60.02μm, which meets the error threshold of ±0.1μm, and then automatically stops the machine.

[0102] After thinning, a three-dimensional morphology analysis algorithm is used to perform mesh modeling of the wafer, and the theoretical thickness of the single-layer wafer combined with the preset adhesive layer is calculated to be 62.5 μm.

[0103] The system runs an eight-layer stacked space simulation model and calculates that the total thickness of the eight-layer stack is 500μm. Compared with the available height of 520μm inside the package shell, the remaining tolerance margin of 20μm is analyzed and confirmed, thus verifying the sufficiency of the physical space conditions, and automatically triggering instructions to transfer the wafer to the subsequent packaging process.

[0104] Specifically, in S101, in the total thickness deviation removed during wafer grinding:

[0105] ;

[0106] in, The thickness deviation that needs to be removed by overall grinding of the wafer, in μm; The measured average thickness of the original wafer, in μm; The target wafer thickness is expressed in μm.

[0107] In the Preston material removal rate-based model:

[0108] ;

[0109] in, The thickness of wafer material removed per unit time, in μm / s; The Preston process constant (calibrated by the grinding fluid and grinding disc material); The grinding load applied by the thinning machine, in N; The rotational speed of the grinding disc spindle is expressed in r / min. Grinding time, in seconds;

[0110] In the feed rate decay correction (when the removal rate exceeds the limit):

[0111] ;

[0112] in, The corrected target feed rate, in μm / s; The base feed rate output by the PID controller, in μm / s; The feed attenuation coefficient is 0 < ηfeed < 1, and is automatically adjusted when the removal rate exceeds the threshold.

[0113] In verifying the total theoretical thickness of an eight-layer stack:

[0114] ;

[0115] in, The theoretical total height of an 8-layer chip stack plus a bonding layer, in μm;

[0116] N is the total number of stacked chip layers, N=8; The thickness of a single thinned wafer plus the adhesive layer is expressed in μm; Substitute the values: =8×62.5=500μm;

[0117] In the internal height margin verification of the package:

[0118] ;

[0119] in, This refers to the remaining safety tolerance margin inside the package housing, in μm. The maximum permissible height inside the encapsulation cavity, in μm; The theoretical thickness of the eight-layer stack is given in μm; Substitute the values: =520-500=20μm, which meets the stacking space requirements;

[0120] In the thickness error determination logic:

[0121] ;

[0122] in, Real-time measured wafer thickness using laser interferometry, unit: μm; The target thickness for the process is expressed in μm. The thickness tolerance threshold is expressed in μm; grinding is stopped if the inequality holds true.

[0123] Furthermore, S102 includes:

[0124] Extract the chip length and chip width, perform calculations, and obtain the chip bottom area;

[0125] Extraction is performed based on the chip's bottom area and the preset nozzle size to obtain the initial vacuum level;

[0126] Obtain the initial vacuum level and the preset ejector height, perform prediction processing on the initial vacuum level and ejector height, and obtain the initial deformation.

[0127] Determine the initial deformation and obtain the target vacuum level;

[0128] The initial picking force is obtained based on the target vacuum level and the preset peeling speed;

[0129] The initial pickup force is processed to obtain the target pickup force;

[0130] Calculate the target picking force and the preset mounting force to obtain control commands;

[0131] By controlling the chip mounter to perform pick-and-place processing on the thinned chip according to the target vacuum level and target pick-up force, the chip to be mounted is obtained.

[0132] In a specific embodiment, after the thinning process, the chip length and chip width of the thinned chip are extracted, and the chip bottom area is obtained by multiplication. The chip bottom area and the preset nozzle size are then extracted to determine the initial vacuum level.

[0133] The initial vacuum level and the preset pin height are obtained. The initial vacuum level and pin height are then predicted using a random forest regression model to obtain the initial deformation variables.

[0134] Obtain the initial deformation and the preset deformation threshold. If the initial deformation is greater than the deformation threshold, perform a multiplication of the attenuation coefficient on the initial vacuum level to obtain the target vacuum level.

[0135] The initial pickup force is determined based on the target vacuum level and the preset peeling speed, and the initial pickup force is subjected to smoothing filtering to obtain the target pickup force;

[0136] The target picking force and the preset mounting force are obtained, and the mechanical ratio is obtained through ratio calculation. Control commands are generated based on the mechanical ratio.

[0137] By controlling the chip mounter to perform pick-up processing on the thinned chip according to the target vacuum level and target pick-up force, the chip to be mounted is obtained, and the chip to be mounted is then subjected to mounting processing to obtain the target mounting assembly.

[0138] Specifically, in S102, after the system reads data that the thickness of the chip to be processed is 60μm, it automatically triggers the chip thinning anti-crack safety protocol.

[0139] The central control unit calls the finite element stress distribution algorithm to perform mechanical modeling of the chip stripping process and calculates that a multi-pin collaborative stripping strategy is required to disperse local stress.

[0140] The control system sends multi-stage motion commands to the ejector actuator through a proportional-integral-derivative algorithm, sets the first-stage lifting speed to 2.5 mm / s, and precisely controls the target lifting height at 0.85 mm. At the same time, the piezoelectric sensor is activated to monitor stress at the microsecond level.

[0141] When the underlying system analysis confirms that the peak peel stress at the bottom of the chip does not exceed the safety threshold of 12.5MPa, the fluid dynamics model simultaneously calculates the optimal adsorption parameters of the nozzle, instructs the nozzle to contact the chip surface with a tiny contact force of 0.15N, and instantly applies a vacuum negative pressure of -68.5kPa to complete the pickup.

[0142] During the transfer and mounting stage, the machine vision positioning algorithm generates a high-precision coordinate compensation matrix, guiding the mounting head to descend smoothly at a speed of 1.2 mm / s. When the laser rangefinder reports a distance of 0.05 mm from the substrate surface, the system dynamically adjusts the mounting force to 0.25 N and holds it for 0.5 seconds. Finally, the pressure decay curve analysis confirms that there are no abnormal stress changes during the mounting process. Then, the vacuum is released and the robotic arm is driven to reset to execute the next cycle.

[0143] Specifically, in S102, the chip bottom area is:

[0144] ;

[0145] in, Chip bottom area, unit: mm2 ; Chip length, unit: mm; Chip width, unit: mm;

[0146] In the pressure decay curve analysis (deformation exceeding the limit):

[0147] ;

[0148] in, To safely pick up the target vacuum negative pressure, unit: kPa; The initial vacuum level is calculated based on the chip area and nozzle size, in kPa. This is the vacuum attenuation coefficient (the value is less than 1 when the deformation is greater than the threshold, reducing negative pressure to prevent deformation and cracking).

[0149] In the matching ratio of pickup force:

[0150] ;

[0151] in, For picking or mounting mechanical matching coefficients; The target pickup force after smoothing filtering, in N; The preset standard placement pressure, in N, is used to generate motion control commands for the pick-and-place machine.

[0152] In determining the safety of chip peel stress:

[0153] ;

[0154] in, The maximum local stress during the chip stripping process was obtained using finite element simulation, in MPa. The stress safety threshold for preventing silicon chips from cracking is expressed in MPa. Vacuum pickup can only be performed if the inequality is satisfied.

[0155] Furthermore, S103 includes:

[0156] Calculate the chip length and chip width to obtain the chip's aspect ratio;

[0157] The initial offset of the chip is obtained based on the chip's aspect ratio and the preset edge distance.

[0158] The initial offset and the preset DAF film thickness are obtained, and prediction processing is performed to obtain the target offset of the chip.

[0159] Based on the target offset, perform staggered positioning processing on the first to fourth layer chips to obtain the stepped stacked components of the first to fourth layer chips.

[0160] In a specific embodiment, the chip length and chip width of the first layer chip are obtained, the aspect ratio is obtained through ratio calculation, and the initial offset is determined based on the aspect ratio and the preset edge distance.

[0161] The initial offset and the preset DAF film thickness are obtained. The target offset is obtained by using a support vector machine model to predict the initial offset and the DAF film thickness.

[0162] Based on the target offset, perform staggered positioning processing on the first to fourth layer chips to obtain a stepped stacked assembly;

[0163] Obtain the exposed area size of the stepped stacked component. If the exposed area size is smaller than the preset bonding area threshold, perform coordinate translation processing on the stepped stacked component to obtain the corrected stacked component.

[0164] Obtain the step difference of the corrected stacked components, determine the initial pressing force based on the step difference and the preset pressure value, and perform a weighted summation on the initial pressing force to obtain the target pressing force;

[0165] The target stacked structure is obtained by hot-pressing and curing the DAF adhesive layer on the bottom surface of each chip with the target pressing force.

[0166] Specifically, in S103, after the system receives the four-layer staircase stacking instruction, it starts the three-dimensional coordinate system reconstruction module;

[0167] The machine vision system identifies optical reference marks on the substrate by using a normalized cross-correlation algorithm and establishes a global absolute coordinate system;

[0168] In this solution, all bottom-layer stacked chips are pre-laminated with DAF (Die Attach Film) and simultaneously diced with DAF. Each die has a solid DAF film on its bottom surface. The mounting head directly picks up the DAF pre-attached thinned chip and places it at the reference coordinates. A laser interferometer confirms that the vertical axis height is 0.12mm.

[0169] The spatial geometric planning algorithm calculates that the second layer needs to be offset by 150μm in the positive direction of the horizontal axis and 150μm in the positive direction of the vertical axis;

[0170] The system combines the hot-pressing melting and spreading characteristics of DAF film to generate the second layer of chip offset stacking coordinates. The vision servo system guides the placement head to place the second DAF pre-bonded thinned chip at a relative coordinate of 15mm in the horizontal direction and 20.15mm in the vertical direction.

[0171] The system calls the Markov chain prediction model to analyze the curing shrinkage of the DAF film, calculates the curing shrinkage compensation offset of the DAF film, and calculates that the third layer chip needs to be offset 300μm in the opposite direction of the lateral axis.

[0172] The mounting mechanism directly picks up the third-layer chip with its own DAF adhesive layer to complete the alignment and placement, without the need for additional liquid colloid coating, and achieves interlayer bonding by relying on DAF hot-pressing and melting.

[0173] The 3D topography scanner collects the cumulative tilt data of the first three layers of the chip in real time, and the tilt compensation angle is fitted to be 0.03° by the least squares method;

[0174] Based on this, the control system corrected the mounting posture of the fourth DAF pre-bonded thinned chip, placing it at a coordinate position of 15.15mm horizontally and 20.15mm vertically. The confocal color difference sensor scan confirmed that the edge spacing of the four-layer chip steps was maintained at 150μm, and the DAF bonding layer had no excess adhesive covering the pads, meeting the requirements for reserved space for wire bonding.

[0175] Specifically, in S103, the aspect ratio of the chip is as follows:

[0176] ;

[0177] in, This is the scaling factor for the chip's aspect ratio; Chip length; This is the chip width, used for calculating the initial lateral offset in the SVM model;

[0178] In multi-layer stacked coordinate offset correction:

[0179] ;

[0180] in, Output the target XY axis offset for the SVM model, in μm; Initial offset calculated from aspect ratio and edge allowance: unit: μm; To predict weight coefficients for support vector machines; The offset for compensating for curing shrinkage of the DAF membrane, in μm;

[0181] In the weighted calculation of the compressive force of stepped stacking:

[0182] ;

[0183] in, The target bonding force for hot-pressing and curing of four-layer DAF pre-bonded thinned chips, in N; The weighting coefficients corresponding to the step height of the i-th chip layer; To accommodate the initial pressing force of a single layer during DAF film fusion bonding, unit: N;

[0184] In the verification of the step edge spacing:

[0185] ;

[0186] in, The measured distance between the exposed edges of adjacent DAF pre-bonded thinned chips for confocal sensors is in μm. The minimum gap threshold reserved for wire bonding is in μm. In this embodiment, it is 150 μm. This gap can prevent the DAF film from blocking the pads after melting.

[0187] Furthermore, S104 includes:

[0188] Extract the pad spacing of the stepped stacked components of the first to fourth layers of chips, and obtain the initial bonding wires based on the pad spacing and the preset wire diameter.

[0189] Predictive processing is performed on the initial bond line to obtain the target bond line;

[0190] By performing wire bonding on the ladder-like stacked components using the target bonding wire, the bottom layer bonding component can be obtained.

[0191] Determine the underlying bonding components and obtain the corrected bonding components;

[0192] Obtain the radian value of the modified bonding component, and determine the initial power value based on the radian value and the preset gap distance;

[0193] Calculate the initial power value to obtain the target power value;

[0194] By using the target power value, a secondary wire bonding reinforcement process is performed on the modified bonding component to obtain the target underlying bonding structure.

[0195] In a specific embodiment, a stepped stacked assembly of the first to fourth layer chips is obtained, the pad spacing of the stepped stacked assembly is obtained, and the initial bonding wire is determined according to the pad spacing and the preset wire diameter.

[0196] The initial bond line is predicted using the random forest algorithm to obtain the target bond line;

[0197] The bottom layer bonding component is obtained by performing wire bonding on the ladder-like stacked components using the target bonding wire;

[0198] Obtain the vertical distance of the underlying bonding component. If the vertical distance is less than the preset gap threshold, perform arc flattening processing on the underlying bonding component to obtain the corrected bonding component.

[0199] Obtain the radian value of the modified bonding component, and determine the initial power value based on the radian value and the preset gap distance;

[0200] The target power value is obtained by performing a weighted summation on the initial power value;

[0201] The target underlying bonding structure is obtained by performing secondary wire bonding reinforcement on the modified bonding component using the target power value.

[0202] Specifically, in S104, after the manufacturing execution system receives the signal that the four-layer chip stacking is complete, it triggers the wire bonding anti-interference control module.

[0203] The 3D bounding box collision detection algorithm performs spatial topology analysis on the current working area and calculates that if the fifth layer chip is directly mounted, the movement trajectory of the cleaver will interfere with the structure above. The system then locks the vertical safety clearance threshold to 250μm and issues a priority wire bonding command.

[0204] The machine vision module uses an edge gradient orientation histogram feature extraction algorithm to scan 64 input and output pads in the exposed areas of the first to fourth chip steps, generating an absolute coordinate point cloud containing depth information.

[0205] The trajectory planning engine calls the cubic B-spline curve interpolation algorithm to construct a three-dimensional spatial path of the lead wire, starting from the first layer chip pad and ending at the substrate pin, and strictly limits the highest point of the arc to within 120μm to reserve space for subsequent stacking.

[0206] The wire bonding control system drives the piezoelectric ceramic transducer to output 125mW of ultrasonic power, applies an initial bonding pressure of 15g to the first solder joint, and the cleaver stretches out a gold wire with a diameter of 18μm at a speed of 45mm / s according to the planned path and completes the crimping of the second solder joint.

[0207] A white light interferometer performs a tomographic scan along the vertical axis on the completed bonding wire array, extracts the coordinate data of the arc vertices, and compares and analyzes to confirm that the maximum vertical height of all leads is maintained at 118.5 μm, which meets the requirements for unobstructed movement trajectory of subsequent chip stacking.

[0208] Specifically, in S104, the wire arc height safety constraint for wire bonding is as follows:

[0209] ;

[0210] in, The measured vertical height of the lead arc apex using a white light interferometer, in μm. The maximum allowable arc height for non-interference of upper-layer chip stacking, in μm;

[0211] In the weighted solution of secondary wire bonding power:

[0212] ;

[0213] in, Ultrasonic power for secondary reinforcement of wire bonding target, unit: mW; The base power is determined by the radian value of the arc, in mW. The compensation power is determined by the vertical gap between the chips, in mW. , The weighting coefficients are for radians and gaps.

[0214] In 3D bounding box collision detection:

[0215] ;

[0216] in, The vertical clearance from the top of the current stack to the lowest trajectory of the moving chopper, in μm; The minimum safe vertical clearance for interference-free equipment movement is specified in μm. If this requirement is not met, upper-layer stacking is prohibited, and wire bonding must be performed first.

[0217] In the height constraint of the B-spline lead trajectory:

[0218] ;

[0219] in, Let be the arc height function of the leader line at spatial coordinates (x, y); Given the cubic B-spline interpolation trajectory equation, the output arc height at any position does not exceed a threshold.

[0220] Furthermore, S105 includes:

[0221] A 100μm fifth-layer chip is mounted onto the target bottom bonding structure to form a suspended support substrate.

[0222] Thinning treatment is performed on the suspended substrate to obtain a thinned wafer;

[0223] DAF lamination was performed on the thinned wafer, and DAF simultaneous dicing was performed to prepare a DAF pre-bonded thinned chip with a solid adhesive film on the bottom surface.

[0224] Using DAF pre-bonded thinned chip as a substrate, the sixth to eighth layers of chips are placed sequentially and aligned and hot-pressed. DAF hot-pressing melts and wets the chip interface to obtain the initial eight-layer stacked assembly.

[0225] Perform thermosetting on the initial eight-layer stacked component to obtain the target eight-layer stacked component.

[0226] In a specific embodiment, a 100μm fifth-layer chip is mounted onto a target bottom bonding structure to obtain a suspended support substrate;

[0227] The target mechanical force is obtained by using a support vector machine algorithm to predict the stress on the suspended bearing base.

[0228] Obtain the target mechanical force. If the target mechanical force is greater than the preset stress threshold, perform a thinning process on the wafer corresponding to the suspended bearing substrate according to the target mechanical force to obtain a thinned wafer.

[0229] The back side of the thinned wafer is integrally hot-pressed and laminated with DAF (Die Attach Film), and integrated with a UV-cut support film. The DAF adhesive layer is completely adhered to the back side of the entire wafer by rolling at 80-130℃.

[0230] After lamination is completed, wafer synchronous dicing is performed to cut the silicon substrate and DAF adhesive layer at one time. Then, UV exposure is used to reduce the adhesion of the support film and pick up the DAF pre-bonded thinned chip with a solid adhesive film of the same size on the bottom surface.

[0231] Obtain the DAF pre-bonded thinned chip, and place the sixth, seventh and eighth layer chips on top of the DAF pre-bonded thinned chip to perform alignment hot pressing. The hot pressing temperature is controlled at 100-150℃. The DAF solid adhesive film melts evenly under heat and fully wets the bonding interface of the upper and lower chips. There is no side overflow or local missing adhesive, resulting in the initial eight-layer stacked assembly.

[0232] The initial eight-layer stacked assembly is subjected to overall thermosetting treatment at 170-200℃ to completely cross-link and cure the DAF film, forming a uniform thickness and low-void interlayer adhesive layer, thus obtaining the target eight-layer stacked assembly.

[0233] Specifically, in S105, the system confirms that the bottom wire bonding process is completed and activates the upper floating stack control program.

[0234] For the suspended feature of the fifth-layer chip, the stress analysis engine calls the finite element mesh generation algorithm to perform mechanical modeling on the region with a suspended length of 1250.5μm. It calculates that the maximum principal stress under the standard 60μm thickness will exceed the yield threshold of silicon material. The system then sets the processing thickness parameter of the wafer that matches the fifth-layer chip to 100μm.

[0235] By using a closed-loop controlled chemical mechanical polishing process, the original wafer is precisely ground to a target thickness of 100μm to obtain a thinned wafer;

[0236] After the DAF lamination station is started, the integrated DDAF (Dicing and Die-Attach Film, DDAF) film is hot-pressed onto the back of the thinned wafer, and the rolling pressure is evenly distributed across the entire wafer to ensure that the DAF adhesive layer thickness tolerance is controlled within ±1μm.

[0237] The silicon wafer and the underlying DAF adhesive layer are cut simultaneously using a stealth laser, and the DAF adhesive film is independently retained at the bottom of each die;

[0238] After cutting, UV irradiation is performed to de-adhede the chip, weakening the adhesion of the underlying support film. During pickup, only the chip and DAF adhesive layer are taken away, and there will be no DAF residue or chip adhesive loss.

[0239] The picking device grabs the fifth-layer chip with its own DAF pre-bonding layer and presses it down onto the surface of the bottom bonding structure at a descent speed of 15mm / s. At the moment of contact, a holding pressure of 0.85N is applied to complete the positioning.

[0240] The interlayer alignment system uses a normalized cross-correlation image matching algorithm, taking the reference mark of the fifth layer chip as the coordinate origin, to calculate the offset compensation amount in the horizontal plane.

[0241] The motion control card drives the linear motor to sequentially align and place the sixth, seventh, and eighth layer chips on the DAF adhesive surface according to the setting of an incremental 50μm offset for each layer, and simultaneously apply heat and pressure to melt and spread the DAF interface.

[0242] After all the chips are stacked, they are sent to an oven for high-temperature curing. The DAF adhesive layer is completely hardened. The three-dimensional X-ray tomography module performs perspective reconstruction on the final eight-layer vertical stacked structure. The voxel-level analysis algorithm extracts the parallel deviation data and void rate data of each DAF bonding interface layer by layer. The interface void rate is controlled within 3%. It is confirmed that the vertical tilt angle of the overall structure is kept within 0.02° and there is no excess adhesive covering the chip pads.

[0243] Specifically, in S105, the maximum principal stress model for the suspended region is as follows:

[0244] ;

[0245] in, The maximum principal bending stress in the suspended region of the fifth chip, in MPa;

[0246] The bending moment of the suspended section is expressed in N·μm. The thickness of the fifth chip's silicon wafer, in μm; The moment of inertia of the chip cross section (μm) 4 ;

[0247] Decision logic: At that time, the chip thickness was changed from 60μm to 100μm to improve bending resistance;

[0248] In multi-layered stacked coordinate recursive offset:

[0249] ;

[0250] in, This represents the XY axis offset for the nth layer (n=6, 7, 8), in μm.

[0251] The reference offset coordinates for the fifth chip, in μm; The incrementing step offset for each level, in μm;

[0252] In the overall stack tilt angle verification:

[0253] ;

[0254] in, The vertical tilt angle of the eight stacked layers was measured by tomography, in degrees.

[0255] Maximum allowable tilt angle threshold for encapsulation, in degrees;

[0256] Under the constraints of DAF hot-press bonding process:

[0257] The hot-pressing temperature range is 100-150℃, and the holding time is 0.3-0.8s, which ensures that the DAF film melts and fully wets the interface without causing the colloid to overflow.

[0258] The final curing temperature range is 170-200℃, and the holding time is 60-90min, which allows the epoxy component of the DAF film to be fully cross-linked. After curing, it can withstand the high temperature of 260℃ reflow soldering, and the adhesive layer thickness is uniform and without undulation.

[0259] Furthermore, S106 includes:

[0260] Clean the target eight-layer stacked components to obtain the parts to be bonded;

[0261] Identify the pads of the component to be bonded and obtain the pad positions;

[0262] The offset of the pad position is obtained by comparing it with the preset standard coordinates.

[0263] Determine the pad offset to obtain the target component to be bonded;

[0264] The top four chips of the target component to be bonded are wire bonded using gold wire to obtain the bonding wire;

[0265] Scan the bond line to obtain the radian value;

[0266] If the curvature value is within the preset curvature range, then pre-sealing baking is performed.

[0267] In a specific embodiment, the surface cleanliness of the target eight-layer stacked component is obtained. If the surface cleanliness is less than a preset cleanliness threshold, plasma cleaning is performed on the target eight-layer stacked component according to the surface cleanliness to obtain the component to be bonded.

[0268] A convolutional neural network model is used to identify the pads of the components to be bonded, thereby obtaining the pad positions.

[0269] The offset is obtained by performing a comparison process based on the pad position and the preset standard coordinates.

[0270] If the offset is greater than the preset offset threshold, position compensation processing is performed on the part to be bonded based on the offset to obtain the target part to be bonded.

[0271] The top four chips of the target component to be bonded are wire bonded using gold wire to obtain bonding wires;

[0272] A three-dimensional topography scan was performed on the bond line to obtain the radian value;

[0273] If the radian value is within the preset radian range, then pre-bonding baking is performed on the target component to be bonded.

[0274] Specifically, in S106, the machine vision module calls the Canny edge detection operator combined with the sub-pixel interpolation algorithm to identify the center of the aluminum pads of the fifth to eighth layers of the chip, and extracts the coordinates with an accuracy of 0.05μm.

[0275] The 3D routing engine is based on a spline curve fitting algorithm to plan the bonding trajectory from the top chip pad to the substrate pin. The maximum lead span of the gold wire is set to 3250.25μm, and the highest point of the arc is 120.5μm from the chip surface to avoid step edge interference.

[0276] The piezoelectric ceramic actuator controls the cleaver to descend at a speed of 25 mm / s, applying an initial bonding force of 0.45 N at the moment of contact with the pad, and simultaneously outputting ultrasonic energy at a frequency of 120 kHz and a power of 65.5 mW, which lasts for 15 ms to complete the first solder joint interconnection.

[0277] After the bonding process is completed, the automated material handling system moves the substrate to the vacuum chamber. The radio frequency generator calculates the breakdown voltage according to Paschen's Law. In an argon-oxygen mixed gas environment of 45 Pa, 350W of radio frequency power is applied to excite the plasma and continuously bombard the surface for 120 seconds to remove the organic contaminants remaining in the bonding process.

[0278] Specifically, in S106, the pad coordinate offset compensation amount is:

[0279] ;

[0280] in, Total planar offset between the CNN-identified pads and the standard template, in μm;

[0281] , The XY coordinates of the pad center are shown in the actual image, in μm. , Reference coordinates for standard pads, unit: μm; Judgment: Platform location compensation is performed in a timely manner;

[0282] In ultrasonic energy:

[0283] ;

[0284] in, Total ultrasonic bonding energy at a single weld point, unit: mW·ms; The output power of the top-bonded ultrasound is expressed in mW. The duration of ultrasound waves, measured in milliseconds (ms).

[0285] In the simplified process formula for plasma breakdown voltage according to Paschen's law:

[0286] ;

[0287] in, The breakdown voltage of argon-oxygen mixed gas plasma, in V; The pressure of the gas inside the vacuum chamber, in Pa; This refers to the distance between the RF electrode and the substrate, in mm, used to match the RF power for surface plasma cleaning.

[0288] In determining the compliance range of the arc height:

[0289] ;

[0290] in, The height of the top bonding line arc in a 3D scan, in μm; The minimum safe height threshold for the arc, in μm; The maximum arc length that does not touch the molding die is measured in μm. Within this range, the product can directly proceed to the baking process.

[0291] In the total energy input for plasma cleaning:

[0292] ;

[0293] in, Total radio frequency energy for plasma cleaning, unit: W·s; The output power of the radio frequency generator, in watts (W). The duration of plasma bombardment cleaning is expressed in seconds (s).

[0294] Example 2

[0295] like Figure 2 As shown, a vertical eight-layer stacked packaging system for high-capacity memory chips includes:

[0296] Wafer data module 1 calculates the difference between the original measured thickness of the memory chip wafer and the target thickness as the target deviation of the wafer thickness, and inputs the target deviation into the thinning machine for thinning processing.

[0297] Pick-up processing module 2, after thinning, calculates the bottom area of ​​the chip based on the chip length and width, calculates the initial vacuum degree in combination with the nozzle size of the ejector actuator, and corrects the vacuum degree and pick-up force by predicting the deformation of chip peeling through regression model, and obtains the chip to be mounted.

[0298] The target offset module 3 calculates the target offset by combining the aspect ratio of the chip and the curing shrinkage of the DAF film, and stacks the first to fourth layers of 60μm chips in a staggered manner, leaving gaps for wire bonding between adjacent chips to obtain a stepped stacked assembly.

[0299] The wire bonding module 4 first completes all wire bonding for the first to fourth layers of the chip, and then performs secondary wire bonding reinforcement based on the arc value of the wire bonding and the power value, to obtain the target bottom layer bonding structure.

[0300] DAF pre-bonding module 5, attaches a 100μm fifth layer chip to the target bottom bonding structure to form a suspended bearing substrate;

[0301] The sixth to eighth layers of chips are stacked sequentially on the suspended support substrate, and after DAF alignment and hot pressing, a uniform thermosetting process is performed to obtain the target eight-layer stacked component.

[0302] The molding process module 6 performs pad coordinate correction on the target eight-layer stacked component, completes the top layer lead bonding, and performs pre-molding baking after verifying that the arc value of the bonding line is qualified.

[0303] Example 3

[0304] like Figure 3 As shown, this embodiment provides a terminal device 30, including a processor 300 and a memory 301;

[0305] The memory 301 is used to store the computer program 302 and to transfer the computer program 302 to the processor 300;

[0306] The processor 300 is used to execute the steps in the above-described vertical eight-layer stacked packaging method for high-capacity memory chips according to the instructions in the computer program 302.

[0307] For example, computer program 302 may be divided into one or more modules / units; one or more modules / units are stored in memory 301 and executed by processor 300 to complete this application; one or more modules / units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution process of computer program 302 in terminal device 30.

[0308] Terminal device 30 may be a desktop computer, laptop, handheld computer, cloud server, or other computing device; terminal device 30 may include, but is not limited to, processor 300 and memory 301.

[0309] Those skilled in the art will understand that Figure 3 This is merely an example of terminal device 30 and does not constitute a limitation on terminal device 30. It may include more or fewer components than shown, or combine certain components, or different components. For example, terminal device 30 may also include input / output devices, network access devices, buses, etc.

[0310] The processor 300 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0311] The memory 301 can be an internal storage unit of the terminal device 30, such as a hard disk or memory of the terminal device 30; the memory 301 can also be an external storage device of the terminal device 30, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc. equipped on the terminal device 30.

[0312] Example 4

[0313] This embodiment provides a computer-readable storage medium storing a computer program; when the computer program is executed by a processor, it implements all the steps of the vertical eight-layer stacked packaging method for a large-capacity memory chip as described in Embodiment 1.

[0314] Computer-readable storage media include, but are not limited to: ROM, RAM, disk, optical disc, USB flash drive, solid-state drive, cloud storage media; the program can be run by being loaded into any electronic device.

[0315] For those skilled in the art, various other corresponding changes and modifications can be made based on the technical solutions and concepts described above, and all such changes and modifications should fall within the protection scope of the claims of this application.

[0316] Example 5

[0317] like Figure 4 As shown in the diagram, this embodiment provides a schematic diagram of a vertical eight-layer stacked packaging structure. Figure 4 All structural dimensions, thickness values, number of layers, size ratios, marking size parameters, and component arrangement numbers are merely illustrative examples and do not constitute a limitation on the scope of protection of this application or the packaging structure parameters. Packaging process engineers in the field can make routine process adjustments, structural modifications, and size adaptations based on chip specifications, heat dissipation requirements, reliability indicators, and packaging pattern requirements.

[0318] All numerical dimensions, number of structural layers, and component specifications in the structural diagrams and illustrations accompanying this embodiment are only used to clearly illustrate the core connection structure and protection structure of the chip packaging of this invention, and are not intended to limit the features of the claims. Conventional adaptive modifications made by those skilled in the art to the packaging shape, thickness of each layer, conductive structure dimensions, and number of components based on the core technical concept of this invention all fall within the protection scope of this application.

Claims

1. A method for vertical eight-layer stacked packaging of a high-capacity memory chip, characterized in that, include: The difference between the original wafer thickness and the target thickness of the memory chip is calculated as the target deviation of the wafer thickness, and the target deviation is input into the thinning machine for thinning. The first to fourth layers of the chip are thinned to 60μm, and the fifth layer of the chip is thickened to 100μm to counteract the suspended stress generated by the stacking of the sixth to eighth layers of the chip. After thinning, the chip bottom area is calculated based on the chip length and chip width. The initial vacuum level is calculated in combination with the nozzle size of the ejector mechanism. The vacuum level and pick-up force are corrected by predicting the deformation of the chip peeling through a regression model to obtain the chip to be mounted. The target offset is calculated by combining the aspect ratio of the chip and the curing shrinkage of the DAF film. The first to fourth layers of 60μm chips are stacked in a staggered manner, with gaps reserved for wire bonding between adjacent chips, to obtain a stepped stacked assembly. First, complete all wire bonding for the first to fourth layers of the chip, and then perform secondary wire bonding reinforcement based on the arc value of the wire bonding and the power value to obtain the target bottom layer bonding structure. A 100μm fifth-layer chip is mounted on the target bottom bonding structure to form a suspended bearing substrate; The sixth to eighth layers of chips are stacked sequentially on the suspended support substrate, and after DAF alignment and hot pressing, a uniform thermosetting process is performed to obtain the target eight-layer stacked component. After correcting the pad coordinates of the target eight-layer stacked component, the top layer wire bonding is completed. After verifying that the curvature value of the bonding line is qualified, pre-encapsulation baking is performed.

2. The vertical eight-layer stacked packaging method for high-capacity memory chips according to claim 1, characterized in that, The difference between the measured thickness of the original wafer and the target thickness of the computing memory chip is used as the target deviation of the wafer thickness. The target deviation is input into a thinning machine for thinning processing, including: Obtain the original thickness of the original wafer and the preset target thickness, perform difference calculation, and obtain the target deviation of the wafer thickness; The target deviation amount drives the thinning machine to perform a thinning process on the original wafer.

3. The vertical eight-layer stacked packaging method for high-capacity memory chips according to claim 1, characterized in that, After the thinning process, the chip bottom area is calculated based on the chip length and width. The initial vacuum level is calculated using the nozzle size of the ejector mechanism. The vacuum level and pickup force are corrected by predicting the chip peeling deformation using a regression model, thus obtaining the chip to be mounted. Extract the chip length and chip width, perform calculations, and obtain the chip bottom area; The initial deformation is obtained by extracting the chip's bottom area and the preset nozzle size; The initial deformation is determined to obtain the target vacuum level; The initial picking force is obtained based on the target vacuum level and the preset peeling speed; The initial pickup force is processed to obtain the target pickup force; The target picking force and the preset mounting force are calculated to obtain control commands; The control commands drive the pick-and-place machine to pick up chips according to the target vacuum level and the target pickup force, thereby obtaining the chips to be mounted.

4. The vertical eight-layer stacked packaging method for high-capacity memory chips according to claim 1, characterized in that, The target offset is calculated by combining the aspect ratio of the chip and the curing shrinkage of the DAF film. The first to fourth layers of 60μm chips are stacked in a staggered manner, with gaps reserved for wire bonding between adjacent chips, to obtain a stepped stacked assembly, including: Calculate the chip length and chip width to obtain the chip's aspect ratio; The initial offset of the chip is obtained based on the aspect ratio of the chip and the preset edge distance. The initial offset and the preset DAF film thickness are obtained, and prediction processing is performed to obtain the target offset of the chip. Based on the target offset, interleaved positioning processing is performed on the first to fourth layer chips to obtain the stepped stacked components of the first to fourth layer chips.

5. The vertical eight-layer stacked packaging method for high-capacity memory chips according to claim 1, characterized in that, The process involves first completing all wire bonding for the first to fourth layers of the chip, and then performing secondary wire bonding reinforcement based on the arc value of the wire bonding and the matching power value to obtain the target bottom layer bonding structure, including: Extract the pad spacing of the stepped stacked components of the first to fourth layers of chips, and obtain the initial bonding wires based on the pad spacing and the preset wire diameter. The initial bonding line is predicted to obtain the target bonding line; Wire bonding is performed on the stepped stacked assembly via the target bonding wire; Perform secondary wire bonding reinforcement processing to obtain the target underlying bonding structure.

6. The vertical eight-layer stacked packaging method for high-capacity memory chips according to claim 1, characterized in that, The acquisition of the target eight-layer stacked component includes: A 100μm fifth-layer chip is mounted onto the target bottom bonding structure to form a suspended support substrate; The suspended support substrate is thinned to obtain a thinned wafer; The thinned wafer is subjected to DAF lamination and DAF simultaneous dicing to prepare a DAF pre-bonded thinned chip with a solid adhesive film on the bottom surface. Using the DAF pre-bonded thinned chip as a substrate, the sixth to eighth layers of chips are placed in sequence and aligned and hot-pressed. The DAF hot-pressing melts and wets the chip interface to obtain the initial eight-layer stacked assembly. Perform a thermosetting process on the initial eight-layer stacked assembly to obtain the target eight-layer stacked assembly.

7. The vertical eight-layer stacked packaging method for high-capacity memory chips according to claim 1, characterized in that, The process of performing pad coordinate correction on the target eight-layer stacked component, completing top-layer wire bonding, verifying the curvature value of the bond wires to be qualified, and then performing pre-molding baking includes: The target eight-layer stacked component is cleaned to obtain the component to be bonded; The pads of the component to be bonded are identified to obtain the pad positions; The offset of the pad position is obtained by comparing it with the preset standard coordinates. The offset of the pad position is determined to obtain the target component to be bonded; The top four chips of the target component to be bonded are wire bonded using gold wire to obtain bonding wires; The bonding line is scanned to obtain the radian value; If the radian value is within the preset radian value range, then pre-sealing baking is performed.

8. A vertical eight-layer stacked packaging system for high-capacity memory chips, characterized in that, include: The wafer data module calculates the difference between the original measured thickness of the memory chip wafer and the target thickness as the target deviation of the wafer thickness, and inputs the target deviation into the thinning machine for thinning processing. After thinning, the pick-up processing module calculates the chip bottom area based on the chip length and width, calculates the initial vacuum level in combination with the nozzle size of the ejector actuator, and corrects the vacuum level and pick-up force by predicting the deformation of chip peeling through a regression model to obtain the chip to be mounted. The target offset module calculates the target offset by combining the aspect ratio of the chip and the curing shrinkage of the DAF film, and stacks the first to fourth layers of 60μm chips in a staggered manner, leaving gaps for wire bonding between adjacent chips to obtain a stepped stacked assembly. The wire bonding module first completes all wire bonding for the first to fourth layers of the chip, and then performs secondary wire bonding reinforcement based on the arc value of the wire bonding and the power value, to obtain the target bottom layer bonding structure. The DAF pre-bonding module mounts a 100μm fifth-layer chip onto the target bottom bonding structure to form a suspended bearing substrate. The sixth to eighth layers of chips are stacked sequentially on the suspended support substrate, and after DAF alignment and hot pressing, a uniform thermosetting process is performed to obtain the target eight-layer stacked component. The molding process module performs pad coordinate correction on the target eight-layer stacked component, completes the top layer wire bonding, and performs pre-molding baking after verifying that the arc value of the bonding line is qualified.

9. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor causes the processor to perform the steps of the vertical eight-layer stacked packaging method for a high-capacity memory chip as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the vertical eight-layer stacked packaging method for a large-capacity memory chip as described in any one of claims 1 to 7.

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