Programmable slew rate control for cascode power devices

Abstract

A slew rate controller for a cascode device is disclosed. A slew rate controller according to one aspect of the disclosure can include a cascode device including a first device and a second device coupled cascode with the first device. A charge storage device can be coupled between the first device and the second device. The charge storage device can control a slew rate of the cascode device.

Description

[0001] Cross-reference of related applications This application claims priority to U.S. Patent Application Serial No. 63 / 608,010, entitled “PROGRAMMABLE SLEW RATECONTROL OF CASCODE POWER DEVICES”, filed on December 8, 2023, and claims all rights derived from that priority filing date in all jurisdictions. Technical Field

[0002] This invention relates generally to slew rate control in power converters, and more specifically to programmable slew rate control in cascode power devices. Background Technology

[0003] Because of their high efficiency, small size, and light weight, switch-mode power converters are commonly used to power modern electronic devices from conventional wall outlets. According to switch-mode power converter practice, a high-voltage AC (AC) input is converted to a well-regulated DC (DC) output via energy transfer elements, such as transformers. Switch-mode power converter controllers typically provide output regulation by sensing one or more inputs representing one or more output quantities and controlling the output in a closed loop. During operation, the desired output is provided by using switches to change the duty cycle (typically the ratio of the switch's on-time to the total switching cycle), changing the switching frequency, or changing the number of pulses per unit time of the switches in the switch-mode power converter.

[0004] One type of switch-mode power converter is the resonant converter, which includes a resonant circuit (e.g., an inductor and a capacitor) as part of the power stage. The resonant circuit can advantageously improve power conversion efficiency by utilizing zero-current and / or zero-voltage switching.

[0005] A subset of resonant converters—the series inductor-inductor-capacitor (LLC) converter—uses a resonant circuit with two inductors and one capacitor connected in series to form an LLC resonant circuit. Typically, the power stage of an LLC converter is controlled such that the power stage switches (e.g., high-side and low-side devices) undergo zero-voltage switching (ZVS).

[0006] Other embodiments of the converter topology include a three-phase AC input active front-end (AFE) topology and a bridgeless totem pole power factor correction (PFC) topology. Unlike resonant converter topologies, the three-phase AC input AFE topology and the bridgeless totem pole PFC topology undergo hard switching. Attached Figure Description

[0007] The following figures illustrate a non-limiting and non-exhaustive embodiment of slew rate control for a common-source cascode power device, wherein, unless otherwise stated, the same reference numerals refer to the same parts in all the various views.

[0008] Figure 1A An example is illustrated of a (half-bridge LLC) power converter including a variable gate driver circuit according to one embodiment.

[0009] Figure 1B An example is illustrated of a flyback power converter including a variable gate driver circuit according to another embodiment.

[0010] Figure 1C An example is illustrated of a three-phase AC input active front end (AFE) including a variable gate driver circuit according to another embodiment.

[0011] Figure 1D An example is illustrated of a bridgeless totem-pole PFC input stage including a variable gate driver circuit according to another embodiment.

[0012] Figure 2 An example of a common-source cascode power device according to one embodiment is shown.

[0013] Figure 3 An example of a common-source cascode power device according to one embodiment is shown.

[0014] Figure 4A A cross-section of a depletion-type NFET according to one embodiment is illustrated.

[0015] Figure 4B Examples are given corresponding to Figure 4A The implementation scheme of the charge storage element.

[0016] Figure 5 Examples are given based on Figures 4A-4B The implementation scheme features a partially metallized layout for a depletion-type NFET.

[0017] Figure 6 Examples are given based on Figure 5 The top-view metallization layout of the depletion-type NFET implementation scheme.

[0018] In all the views of the accompanying drawings, corresponding reference characters indicate corresponding parts. Those skilled in the art will understand that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to others to help improve understanding of various embodiments of slew rate control for cascode power devices. Furthermore, common but easily understood elements that are useful or necessary in commercially viable embodiments are generally not depicted to facilitate viewing of these embodiments with less hindrance to the teachings herein. Detailed Implementation

[0019] In the following description, numerous specific details are set forth to provide a thorough understanding of slew rate control for cascode power devices. However, it will be apparent to those skilled in the art that the specific details are not required to practice the teachings herein. In other instances, well-known materials, components, and / or methods have not been described in detail to avoid obscuring this disclosure.

[0020] Throughout this specification, references to "one embodiment," "an embodiment," "one example," or "an example" mean that a specific feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment," "an embodiment," "one example," or "an example" appearing in various places throughout this specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Specific features, structures, or characteristics can be included in integrated circuits, electronic circuits, combinational logic circuits, or other suitable components that provide the described functionality. Additionally, it should be understood that the accompanying drawings are for illustrative purposes to those skilled in the art and are not necessarily drawn to scale.

[0021] In the context of this application, when a transistor is in an "off state" or "off-mode," it blocks current and / or conducts essentially no current. Conversely, when a transistor is in an "on state" or "on-mode," it conducts current significantly. For example, in one embodiment, the high-voltage transistor includes an N-channel field-effect transistor (FET); the N-channel FET may be a metal-oxide-semiconductor field-effect transistor (MOSFET), wherein a high voltage is borne between a first terminal, i.e., the drain, and a second terminal, i.e., the source. In another embodiment, the FET may be a junction field-effect transistor (JFET)—a depletion-type device in which transport is primarily carried out by majority carriers. Alternatively and additionally, the FET may be a gallium nitride (GaN) FET and / or a GaN high electron mobility transport (HEMT) FET device.

[0022] In some implementations, an integrated controller circuit can be used to drive the power switch when regulating the energy supplied to the load.

[0023] Additionally, for the purposes of this disclosure, “ground” or “ground potential” refers to a reference voltage or potential relative to which all other voltages or potentials of an electronic circuit or integrated circuit (IC) are defined or measured.

[0024] As described above, one type of switch-mode power converter is the resonant converter, which uses a resonant circuit (also known as a resonant network or "tank") with inductance and capacitance as part of the power conversion process. Compared to non-resonant switch-mode power converters, resonant converters can have several advantages, such as soft switching (e.g., zero-voltage switching), generally higher efficiency, lower losses at higher frequencies, and lower harmonic content in the switching waveform. These, in turn, can reduce packaging and component costs by allowing the use of smaller magnetic components and smaller electromagnetic interference (EMI) filters.

[0025] Resonant converters typically include a half-bridge circuit. The half-bridge circuit may include low-side devices (i.e., low-side switches) and high-side devices (i.e., high-side switches). During operation, the low-side and high-side devices can be turned on and off according to the switching cycle. Furthermore, as described herein, the switching cycle may include a dead time, during which both the low-side and high-side devices remain off. For example, a break-before-make cycle (i.e., dead time) may exist to mitigate the shoot-through current. According to the teachings herein, during the break-before-make cycle (i.e., dead time), the switching node voltage may decrease and / or increase (i.e., may "slew").

[0026] Applications can include any converter topology, such as LLC converters using common source cascode power devices.

[0027] Modern power converters, including resonant converters, typically use cascode power devices. Cascode power devices can include enhancement-mode devices (e.g., enhancement-mode n-channel MOSFETs) connected in a cascode manner to high-voltage depletion-mode devices (e.g., high-voltage gallium nitride (GaN) and / or silicon carbide (SiC) field-effect transistors). Enhancement-mode devices are often referred to as "normally off" devices, and depletion-mode devices are often referred to as "normally on" devices.

[0028] GaN devices can be used as fast switches and can operate at high frequencies. However, GaN devices typically use negative voltages to turn off (i.e., stop carrying current). In integrated circuits (ICs), providing both positive and negative voltages on a single chip or die is difficult.

[0029] GaN transistors are typically used in cascode configurations with low-voltage (LV) metal-oxide-semiconductor field-effect transistors (MOSFETs), where a switching signal or pulse is applied to the gate of the MOSFET. The gate of the GaN device is connected to ground to allow the GaN device to always be on, which allows the MOSFET to act as a controller to allow current to flow through the high-power GaN device. The use of a cascode configuration provides the advantage of using a unipolar voltage signal (e.g., always a positive voltage) to control the circuit. However, this approach also has disadvantages because the speed at which the cascode circuit is turned on and off (i.e., the slew rate) is not so controllable, which can lead to breakdown of the rest of the circuit.

[0030] Furthermore, as discussed above, some converter topologies may rely on hard switching—a technique different from ZVS, which allows switching devices (e.g., high-side and / or low-side devices) to change states with non-zero voltage and current. Unfortunately, hard switching can introduce higher levels of electromagnetic interference (EMI) and / or reduce converter efficiency. Therefore, controlling the slew rate in hard-switching topologies (such as the active three-phase AFE and totem-pole PFC topologies mentioned above) can advantageously mitigate (reduce) EMI while improving converter efficiency.

[0031] Therefore, it is necessary to control the slew rate in power converters using cascode power devices. This article describes programmable slew rate control for cascode power devices.

[0032] Figure 1A An example is shown of a (half-bridge LLC) power converter 100 including variable gate driver circuits 143-144 according to one embodiment.

[0033] The power converter 100 can be configured as a half-bridge LLC power converter 100; therefore, without departing from the scope of this disclosure, the power converter 100 can also be referred to as a half-bridge LLC power converter 100.

[0034] As illustrated, the power converter 100 includes a primary bridge circuit 103, a resonant transformer 107, and a resonant capacitor C. RES 1. Rectifiers 71 and 72, Output capacitor C O Feedback network 112 and controller 114. Primary bridge circuit 103 includes switch driver 102 and half-bridge 104. Furthermore, half-bridge 104 includes high-side (HS) cascode power device 126 and low-side (LS) cascode power device 128. Additionally, resonant transformer 107 includes transformer 106 and leakage inductor L. LK And excitation inductor L M .

[0035] As illustrated, a DC (dc) input voltage V, referenced to ground GND, can be applied at the primary input (i.e., the primary power supply node NV) of the power converter 100. IN The power converter 100 converts input power from the primary input into DC output power. This DC output power can be delivered to a load 113 having a regulated output voltage V referenced to secondary ground RTN. O And has an output current I O .

[0036] Leakage inductor L LK Magnetizing inductor L M Resonant capacitor C RES It is connected in series between the switching node NSW and ground GND. The controller 114 can provide a drive signal CLKD to the switch driver 102. In response, the switch driver 102 can provide a gate drive signal GH to the HS cascode power device 126 and a gate drive signal GL to the LS cascode power device 128.

[0037] Gate drive signals GH and GL can drive HS cascode power device 126 and LS cascode power device 128 respectively to generate a switching node voltage V at the switching node NSW. X Furthermore, the switching node voltage V X It can drive the resonant transformer 107.

[0038] During operation, transformer 106 can provide current isolation between the primary and secondary sides of power converter 100; in this way, signals on the primary side referenced to ground GND can be isolated from signals on the secondary side referenced to secondary ground RTN.

[0039] As illustrated, the primary winding 120 and the magnetizing inductor L M Parallel electrical coupling connects the terminals of the in-phase winding (as indicated by the dot, i.e., the dot terminals) to the leakage inductor L. LK The secondary winding 122 is connected in series with the rectifier 72 between the secondary ground RTN and the secondary output terminal (i.e., the secondary output node NVO), such that the non-in-phase winding terminal is connected to the secondary output node NVO. The secondary winding 124 is connected in series with the rectifier 71 between the secondary ground RTN and the secondary output node NVO, such that the non-in-phase winding terminal is connected to the cathode of the rectifier 71.

[0040] Furthermore, the anodes of rectifiers 71 and 72 are both connected to the secondary ground RTN; and the output capacitor C O Feedback network 112 is electrically coupled in parallel with load 113 between the secondary output (i.e., secondary output node NVO) and secondary ground RTN. As illustrated, controller 114 may provide drive signal CLKD based at least in part on feedback signal FB from feedback network 112.

[0041] The high-side (HS) cascode power device 126 includes a first (lower) n-channel field-effect transistor 155 electrically coupled to ground via a second (upper) NFET 156. Therefore, the source of the first (lower) NFET 155 can be electrically coupled to the switching node NSW. The drain of the first (lower) NFET 155 can be electrically coupled to the source of the second (upper) NFET 156; and the drain of the second (upper) NFET 156 can be electrically coupled to the primary power supply node NV.

[0042] The first (lower) NFET 155 may be an enhancement-mode NFET, and the second (upper) NFET 156 may be a depletion-mode NFET. For example, the first (lower) NFET 155 may be a lateral and / or vertical enhancement-mode NFET with a threshold voltage greater than zero; and the second (upper) NFET 156 may be a gallium nitride (GaN) depletion-mode power device capable of withstanding high drain-source voltages (e.g., 1 kilovolt or greater). Therefore, the gate of the first (lower) NFET 155 may be electrically coupled to the switch driver 102 to receive the gate drive signal GH; and the gate of the second (upper) NFET 156 may be electrically coupled to the source of the first (lower) NFET 155. Furthermore, as illustrated, the source of the second (upper) NFET 156 may be electrically coupled to the drain of the first (lower) NFET 155.

[0043] The low-side (LS) cascode power device 128 includes a first (lower) n-channel field-effect transistor (NFET) 165 electrically coupled to ground via a second (upper) NFET 166. Therefore, the source of the first (lower) NFET 165 can be electrically coupled to ground (GND). The drain of the first (lower) NFET 165 can be electrically coupled to the source of the second (upper) NFET 166; and the drain of the second (upper) NFET 166 can be electrically coupled to the switching node (NSW). Furthermore, as illustrated, the gate of the second (upper) NFET 166 can be connected via a charge storage element C. GDL Electrically coupled to the gate of the first (lower) NFET 165.

[0044] The first (lower) NFET 165 can be an enhancement-mode NFET, and the second (upper) NFET 166 can be a depletion-mode NFET. For example, the first (lower) NFET 165 can be a lateral and / or vertical enhancement-mode NFET with a threshold voltage greater than zero; and the second (upper) NFET 166 can be a gallium nitride (GaN) depletion-mode power device capable of withstanding high drain-source voltages (e.g., one kilovolt or greater). Therefore, the gate of the first (lower) NFET 165 can be electrically coupled to the switch driver 102 to receive the gate drive signal GL; and the gate of the second (upper) NFET 166 can be electrically coupled to the source of the first (lower) NFET 165.

[0045] During the transition, the switching node voltage Vx can change and cause a displacement current (i.e., the transition current). For example, the transition condition (i.e., the transition) at the switching node voltage Vx can be caused by the charge storage element C between the primary power supply node NV and the gate of the NFET 155. GDH The displacement current I caused by the middle XH (That is, the conversion current I) XH Similarly, the switching condition at the switching node voltage Vx can also be achieved between the switching node NSW and the gate of the first (lower) NFET 165, via the charge storage element C. GDL The displacement current I caused by the middle XL (That is, the conversion current I) XL The change of the switching node voltage Vx over time, i.e., the derivative of the switching node voltage Vx with respect to time dVx / dt, can be referred to in this paper as the "slew rate" of the (LS) cascode power device 128.

[0046] Based on the teachings herein, switch driver 102 can provide gate drive signals GH and GL to control the slew rate. Controlling the slew rate can advantageously protect HS cascode power device 126 and LS cascode power device 128; furthermore, controlling the slew rate can enhance device performance. For example, controlling the slew rate can enhance device performance by reducing ringing at power supply nodes and / or ground nodes.

[0047] The switch driver 102 may include one or more variable gate driver circuits 143, 144 and a charge storage element C. GDH C GDL .

[0048] The structure of the FET device creates a natural capacitance for the first (bottom) NFET 165 and the second (top) NFET 166, as follows: Figure 1B As shown, the capacitance of the first (bottom) NFET 165 and the capacitance of the second (top) NFET 166 can be Miller capacitors. Due to the cascode structure, there is no gain, and there is no Miller effect on the first (bottom) NFET 165. The gate of the second (top) NFET 166 is coupled to GND, so Cgan does not experience any switching effects during switching operation.

[0049] The change of current over time (the derivative of current with respect to time) can be controlled by a control voltage, but this may not provide control over the slew rate dVx / dt. To reduce slew, a resistor can be added to the gate of the second (upper) NFET 166 to generate a time constant for the slew rate dVx / dt; however, adding a resistor to the gate of the second (upper) NFET 166 may have only a limited effect on the slew rate dVx / dt.

[0050] Furthermore, adding a resistor to the gate of the second (upper) NFET 166 can introduce noise and oscillations into the overall circuitry, and the gate voltage will increase during the turn-off period of the second (upper) NFET 166. Consequently, the source voltage of the second (upper) NFET 166 will increase, which increases the risk of breakdown in the first (lower) NFET 165. The permissible resistance value for such a resistor is small, for example, 3 ohms, and the slew rate can be limited when the resistance is at such a maximum value (3 ohms). To make such a device programmable, large switches may be required when the device's resistance is less than the minimum resistance value (e.g., 0.5 ohms). These switches can be large, and the cost and size of such switches may make such a method prohibitively expensive.

[0051] Furthermore, based on the teachings of this paper, the slew rate of the HS cascode power device 126 and the LS cascode power device 128 can be increased by adding charge storage element C.GDH C GDL To improve the situation, use capacitors.

[0052] Based on the teachings of this article, the charge storage element C GDL It can be implemented at least partially by the field plate of a depletion-type NFET 166; and the charge storage element C GDH It can be implemented at least partially by a field plate of a depletion-type NFET 156.

[0053] As illustrated, the charge storage element C GDL It can be electrically coupled between the switching node NSW and the gate of the first (lower) NFET 165; and the charge storage element C GDH It can be coupled between the gate of node NV and the gate of the second (upper) NFET 166.

[0054] Figure 1B A power converter 100 including a variable gate driver circuit 143 according to another embodiment is illustrated. Figure 1B The implementation plan is similar to Figure 1A The implementation scheme differs in that it uses a flyback configuration and can therefore operate as a flyback converter. Therefore, without departing from the scope of this disclosure, Figure 1B The power converter 100 can also be referred to as a flyback power converter 100. Accordingly, the flyback power converter 100 may include an energy transfer element 176 and may exclude the HS cascode power device 126.

[0055] Figure 1C An example is illustrated of a three-phase AC input active front end (AFE) 150 according to another embodiment, including variable gate driver circuits 143a-143c, 144a-144c. The three-phase AC input AFE 150 includes half-bridges 104a-104c.

[0056] As discussed above, the three-phase AC input AFE 150 can be configured to undergo hard switching, and slew rate control can be used to advantageously reduce EMI and enhance performance.

[0057] The 104a-104c half-bridge can be similar to Figure 1A The half-bridge 104. For example, half-bridge 104a includes HS cascode power device 126a and LS cascode power device 128a. Half-bridge 104b includes HS cascode power device 126b and LS cascode power device 128b; and half-bridge 104c includes HS cascode power device 126c and LS cascode power device 128c.

[0058] HS common source cascode power devices 126a-126c can be similar to Figure 1A The HS cascode power device 126. For example, the HS cascode power device 126a includes an upper NFET 156a (similar to upper NFET 156) and a lower NFET 155a (similar to lower NFET 155). The HS cascode power device 126b includes an upper NFET 156b (similar to upper NFET 156) and a lower NFET 155b (similar to lower NFET 155); and the HS cascode power device 126c includes an upper NFET 156c (similar to upper NFET 156) and a lower NFET 155c (similar to lower NFET 155).

[0059] Similar to charge storage element C GDH Charge storage element C GDH1 -C GDH3 Electrically coupled to improve slew rate control. That is, the charge storage element C GDH1 Electrically coupled between the drain of the upper NFET 156a and the gate of the lower NFET 155a. Charge storage element C GDH2 Electrically coupled between the drain of the upper NFET 156b and the gate of the lower NFET 155b; and the charge storage element C GDH3 Electrically coupled between the drain of the upper NFET 156c and the gate of the lower NFET 155c.

[0060] Based on the teachings of this article, the charge storage element C GDH1 -C GDH3 (Similar to charge storage element C) GDH These can be implemented by the field plates (e.g., gate field plates) of their respective upper NFETs 156a-156c.

[0061] The LS cascode power devices 128a-128c can be similar to Figure 1A The LS cascode power device 128. For example, the LS cascode power device 128a includes an upper NFET 166a (similar to upper NFET 166) and a lower NFET 165a (similar to lower NFET 165). The LS cascode power device 128b includes an upper NFET 166b (similar to upper NFET 166) and a lower NFET 165b (similar to lower NFET 165); and the LS cascode power device 128c includes an upper NFET 166c (similar to upper NFET 166) and a lower NFET 165c (similar to lower NFET 165).

[0062] Similar to charge storage element C GDL Charge storage element C GDL1 -C GDL3Electrically coupled to improve slew rate control. That is, the charge storage element C GDL1 Electrically coupled between the drain of the upper NFET 166a and the gate of the lower NFET 165a. Charge storage element C GDL2 Electrically coupled between the drain of the upper NFET 166b and the gate of the lower NFET 165b; and the charge storage element C GDL3 Electrically coupled between the drain of the upper NFET 166c and the gate of the lower NFET 165c.

[0063] Based on the teachings of this article, the charge storage element C GDL1 -C GDL3 (Similar to charge storage element C) GDL These can be implemented by the field plates (e.g., gate field plates) of their respective upper NFETs 166a-166c.

[0064] The variable gate driver circuits 144a-144c are similar to the variable gate driver circuit 144. For example, the variable gate driver circuit 144a provides a gate drive signal GH1 to the HS cascode power device 126a (i.e., the gate of the down-facing NFET 155a). The variable gate driver circuit 144b provides a gate drive signal GH2 to the HS cascode power device 126b (i.e., the gate of the down-facing NFET 155b); and the variable gate driver circuit 144c provides a gate drive signal GH3 to the HS cascode power device 126c (i.e., the gate of the down-facing NFET 155c).

[0065] Based on the teachings of this paper, variable gate driver circuits 144a-144c (similar to variable gate driver circuit 144) can provide and / or change their respective gate drive signals (i.e., gate drive signals GH1-GH3) to control the slew rate. For example, the switching node voltage V at switching node NSW1 X1 The slew rate can be controlled by the variable gate driver circuit 144a; and as described herein, by using the charge storage element C GDH1 Coupled at the gate of the lower NFET 155a, the slew rate can be advantageously enhanced. Similarly, the switching node voltage V at the switching node NSW2... X2 The slew rate can be controlled by the variable gate driver circuit 144b and by the charge storage element C. GDH2 The coupling is enhanced; and the switching node voltage V at switching node NSW3 is also enhanced. X3 The slew rate can be controlled by the variable gate driver circuit 144c, and by the charge storage element C. GDH3 Enhanced by coupling.

[0066] The variable gate driver circuits 143a-143c are similar to the variable gate driver circuit 143. For example, the variable gate driver circuit 143a provides a gate drive signal GL1 to the LS cascode power device 128a (i.e., the gate of the down-facing NFET 165a). The variable gate driver circuit 143b provides a gate drive signal GL2 to the LS cascode power device 128b (i.e., the gate of the down-facing NFET 165b); and the variable gate driver circuit 143c provides a gate drive signal GL3 to the LS cascode power device 128c (i.e., the gate of the down-facing NFET 165c).

[0067] Furthermore, in accordance with the teachings of this paper, the variable gate driver circuits 143a-143c (similar to the variable gate driver circuit 143) can provide and / or change their respective gate drive signals (i.e., gate drive signals GL1-GL3) to control the slew rate. For example, the switching node voltage V at switching node NSW1 X1 The slew rate can be controlled by the variable gate driver circuit 143a; and as described herein, by using the charge storage element C GDHL1 Coupled at the gate of the lower NFET 165a, the slew rate can be advantageously enhanced. Similarly, the switching node voltage V at the switching node NSW2... X2 The slew rate can be controlled by the variable gate driver circuit 143b and by the charge storage element C. GDL2 The coupling is enhanced; and the switching node voltage V at switching node NSW3 is also enhanced. X3 The slew rate can be controlled by the variable gate driver circuit 143c, and by the charge storage element C. GDL3 Enhanced by coupling.

[0068] Figure 1D A bridgeless totem-pole PFC input stage 160 including variable gate driver circuits 143, 144 is illustrated according to another embodiment.

[0069] As discussed above, the bridgeless totem-pole PFC input stage 160 can also be configured to undergo hard switching, and slew rate control can be used to advantageously reduce EMI and enhance performance.

[0070] The variable gate driver circuits 143, 144 and the half-bridge 104 can be similar to Figure 1A Those; however, the half-bridge 104 operates as a high-frequency leg in the bridgeless totem pole PFC input stage 160.

[0071] The bridgeless totem-pole PFC input stage 160 also includes a low-frequency branch implemented by a half-bridge 151. The half-bridge 151 includes a high-side (HS) NFET MN1 and a low-side (LS) NFET MN2. The high-side NFET MN1 receives the gate signal GHX from the gate driver circuit 144x, and the low-side NFET MN2 receives the gate signal GLX from the gate driver circuit 143x. The HS NFET MN1 is electrically coupled to the LS NFET MN2 at node NSX; and the half-bridge 104 and half-bridge 151 are coupled at node NVT.

[0072] According to the bridgeless totem pole configuration, AC input 161 and inductor L1 are electrically coupled between switch node NSW and node NX.

[0073] Based on the teachings of this paper, the high-frequency branch implemented by the half-bridge 104 can be at least partially due to the gate drive signals GL, GH and / or the charge storage element C. GDH and C GDL Switching is achieved through enhanced slew rate control. As described in this paper, the charge storage element C... GDH and C GDL They can be implemented by their respective upper NFET 156, 166 field plates (e.g., gate field plates).

[0074] Figure 2 An example of a common-source cascode power device according to one embodiment is shown.

[0075] As discussed herein, the cascode power device 128 includes a first (lower) n-channel field-effect transistor (NFET) 165 electrically coupled to ground via a second (upper) NFET 166. The second (upper) NFET 166 may be referred to herein as a depletion-mode NFET 166. The source of the first (lower) NFET 165 may be electrically coupled to a potential V2, which may be a ground (GND) potential. In one aspect of this disclosure, potential V2 is a voltage potential lower than potential V1, which is electrically coupled to the drain of the second (upper) NFET 166. The drain of the first (lower) NFET 165 may be electrically coupled to the source of the second (upper) NFET 166; and the drain of the second (upper) NFET 166 may be electrically coupled to a voltage potential at node V1. The potential at node V1 may be higher than the potential at the source of the first (lower) NFET 165.

[0076] The first (bottom) NFET 165 can be an enhancement-mode NFET, and the second (top) NFET 166 can be a depletion-mode NFET. For example, the first (bottom) NFET 165 can be a lateral and / or vertical enhancement-mode NFET with a threshold voltage greater than zero; and the second (top) NFET 166 can be a gallium nitride (GaN) depletion-mode power device capable of withstanding high drain-source voltages (e.g., hundreds of volts to one thousand volts or greater). Therefore, the gate of the first (bottom) NFET 165 can be electrically coupled to a driver or other circuitry to receive a gate drive signal GL; and the gate of the second (top) NFET 166 can be electrically coupled to the source of the first (bottom) NFET 165. The capacitance between the switching node NSW and the source of the first (bottom) NFET 165 is shown as a charge storage element C. GD And the charge storage element C FPD It is shown between the switching node NSW and the gate of the first (lower) NFET 165.

[0077] During the voltage and / or current transition and / or other changes at the drain of the depletion-type NFET 166, the node voltage V1 can vary and cause a displacement current (i.e., transition current) I. DL That is, current I DL The change. For example, the switching conditions can be changed between the charge storage element C at the switching node NSW and the gate of the first (lower) NFET 165. FPD The displacement current I caused by the middle XL (That is, the conversion current I) XL ).

[0078] Based on the teachings of this article, the charge storage element C FPD It can be implemented at least partially by the field plate of a depletion-type NFET 166; and the charge storage element C GD It can be the remaining, inherent charge storage element (e.g., a capacitor) of a field-plate device of a depletion-type NFET 166.

[0079] As taught in this paper, the gate drive signal GL selectively allows current to flow in the first (lower) NFET 165, which effectively allows current to flow through the second (upper) NFET 166. Current I is monitored via the switching node NSW. DL Any change (i.e., current I) XL (Due to changes in voltage), the gate drive signal GL can be selectively turned on and off to provide switching of current through the cascode power device 128. Such switching can be determined at any point during a voltage change at node V1 or at current I... DLThe change occurs at any value. In some implementations, the cascode power device 128 can undergo zero-voltage switching (ZVS). To achieve ZVS, the gate drive signal GL can be transmitted via the charge storage element C. GD Or charge storage element C FPD Monitor current and / or voltage.

[0080] In one aspect of the invention, a device (i.e., a depletion-type NFET 166) is provided that allows the internal capacitance (i.e., internal charge storage) of the depletion-type NFET 166 to be divided into at least two portions. One portion is internally connected to the gate of the depletion-type NFET 166, and the other portion is coupled to a node referred to as a field plate (FP) node. Other portions may be coupled to other locations or other circuit devices as needed. Without departing from the scope of this disclosure, the ratio of the amount of capacitance dedicated to the FP node to the remaining capacitance may be varied as needed.

[0081] In such devices that can be used in a common-source, common-gate configuration, the FP node is connected to a control voltage (V). CTRL This control voltage, together with the first (lower) NFET 165 turn-on / off, controls the rate of turn-on / off of the depletion-type NFET 166.

[0082] The FP node is coupled to the gate of the first (lower) NFET 165, which is driven by one or more gate drivers. To control the slew rate, some of the gate drivers can be placed in a tri-state, such that the input pulse width modulation (PWM) does not change the on / off state of the device.

[0083] In one aspect of this disclosure, the slew rate can be digitally controlled over a wide range. Furthermore, the slew rate can be scaled by changing the capacitance ratio in the GaN instead of changing the gate driver.

[0084] Figure 3 An example of a common-source cascode power device 128 according to one embodiment is shown.

[0085] In one aspect of this disclosure, the variable gate driver circuit 143 (also referred to herein as a variable gate driver) can be implemented as a series of parallel branches 302, 304, 306, and 308. Although four branches 302, 304, 306, and 308 are shown, other configurations with more or fewer branches may be possible without departing from the scope of this disclosure.

[0086] In one aspect of this disclosure, one or more of branches 302, 304, 306, and 308 can be enabled by control block 310 and / or control block 312 to control the voltage and / or current at node Ng. This is because node Ng is coupled to the charge storage element C. FPD The variable gate driver circuit 143 can control the on and off of the cascode power device 314. The variable gate driver circuit 143 can be current-dependent, meaning the drive current to the cascode power device 314 can be determined by a fixed current source, or it can be voltage-dependent, meaning the drive current can be determined by the gate path resistance and voltage. Furthermore, monitoring nodes NSW and / or Ng allow for programmable variable gate driver circuit 143.

[0087] Therefore, a slew rate controller according to one aspect of this disclosure may include a cascode power device 314, which includes a low-voltage FET (LVFET) as a first device and a power device (power switch) coupled to the first device via a cascode ground as a second device. Figure 3 As illustrated, the first device is implemented using an NFET 165, and the second device is implemented using an NFET 166. Charge storage device C FPD It can be coupled between the first device and the second device. The controller may also include a variable gate driver circuit 143 coupled to the cascode power device 314. The charge storage device can shunt the gate of the first device to the drain of the second device.

[0088] The slew rate controller can be configured to provide a negative gain from the gate of the first device to the drain of the second device, and the charge storage device can be coupled between the gate of the first device and the drain of the second device, such as... Figure 3 As shown in the figure.

[0089] The charge storage device may include an external capacitor, or may be an integral part of a second device, such as a field plate. The drain of the second device may be coupled to a switching node NSW, such as... Figure 3 As shown. (As illustrated) Figure 2 As described herein, the first device may be an enhancement-mode n-channel field-effect transistor (NFET), and the second device may be a depletion-mode NFET. Furthermore, the depletion-mode NFET is a depletion-mode gallium nitride (GaN) NFET.

[0090] In one aspect of this disclosure, the common-source cascode power device 128 can be configured as follows: Figure 1A and Figure 1BThe power converter 100 shown is implemented therein. According to such an aspect, the power converter may include: a common-source cascode power device 128 electrically coupled to the input of the power converter 100; a driver circuit 143 electrically coupled to a control connection of the common-source cascode power device 128, wherein the driver circuit 143 is configured to selectively control the common-source cascode power device 128 using a drive signal; and a charge storage device C. GDL The charge storage device C GDL Electrically coupled to the control connection, wherein, when a drive signal is provided, the charge storage device 128 shunts the control connection to the drain of the cascode power device 128.

[0091] Such a power converter may optionally include a first transistor and a second transistor electrically connected in a common-source, common-gate configuration. The control connection may be the first gate of the first transistor, and the drain may be the drain of the second transistor.

[0092] The power converter may include: a first transistor, which is an enhancement-mode n-channel field-effect transistor (NFET); and a second transistor, which is a depletion-mode NFET; and the power circuit may further include a third transistor and a fourth transistor electrically connected in a common-source, common-gate configuration. The third transistor may be an enhancement-mode n-channel field-effect transistor (NFET), and the fourth transistor may be a depletion-mode NFET.

[0093] like Figure 1A and Figure 1B As shown, the power converter may have a power circuit electrically coupled to an energy transfer element of the power converter. The energy transfer element may be, for example, a resonant transformer 107 or an energy transfer element 176. The energy transfer element may be coupled to a load of the power converter, such as load 113, as... Figure 1A As shown in the figure.

[0094] The driver circuit of such a power converter can selectively control the power circuitry, at least in part, based on oscillations in the input signal. Oscillations in the input signal, for example, oscillations in Vin (shown in...) Figure 1A (In the middle), it can help control the driver circuit. This selective control of the power circuit can be at intervals determined at least in part by the frequency of the oscillation of the input signal.

[0095] In addition, such as Figure 3 The driver circuit shown can selectively control the cascode circuit by selecting the number of branches of the driver circuit to select the amount of current to be supplied to the cascode circuit.

[0096] Figure 4A A cross-section of a depletion-type NFET according to one embodiment is illustrated.

[0097] A depletion-type NFET, such as depletion-type NFET 166, can be fabricated using source metallization 402, drain metallization 403, gate field plate metallization 404, gate metallization 405, insulating layers 410, 411, 412, 413, 415, 416, and an epitaxial (EPI) layer 417. Additional layers may also be included without departing from the scope of this disclosure.

[0098] Source metallization 402, drain metallization 403, gate field plate metallization 404, and gate metallization 405 can be coupled to various voltages to turn the depletion-type NFET on and off, i.e., selectively allow or prevent current flow between source metallization 402 and drain metallization 403. Insulating layers 410, 412, 413, 415, and 416 isolate the metallization layers (i.e., source metallization 402, drain metallization 403, gate field plate metallization 404, and gate metallization 405) and the EPI layer 417, such that the current flow through the depletion-type NFET is selectively controlled by the voltages present on the respective metallization layers.

[0099] EPI layer 417 may include a compound semiconductor and generate a two-dimensional electron gas (2DEG). Without departing from the scope of this disclosure, for example, but not limited to, EPI layer 417 may include an aluminum gallium nitride (AlGaN) layer, a GaN layer, a SiC layer, or other semiconductor layers.

[0100] Figure 4B Examples are given corresponding to Figure 4A The embodiment of the charge storage element 450.

[0101] A charge storage element 450 (e.g., a capacitor) can be formed between the gate field plate metallization 404 and the drain metallization 403. Since the capacitance is given by C = εA / d, where ε is the absolute dielectric constant of the dielectric material, A is the area of ​​the charge storage plate, and d is the distance between the charge storage regions, a voltage applied to the gate field plate metallization 404 and the drain metallization 403 can store charge on those metallized volumes. Furthermore, the charge storage element 450 can be distributed, i.e., it can be located at multiple locations and / or in various regions of the depletion-type NFET.

[0102] like Figure 4BAs shown in the diagram and as illustrated in the equations above, the capacitance of the charge storage element 450 can be determined at least in part by the thickness d of the insulating layer 415. Furthermore, the type of material used for the insulating layer 415 (e.g., SiN, SiC, Al2O3) will also affect the capacitance of the charge storage element 450, since each or more materials used in the insulating layer 415 can have different dielectric constants. The thickness d of the insulating layer 415 can be determined at least in part based on the proximity of the 2DEG relative to the gate field plate metallization 404 and the drain metallization 403, since the 2DEG couples the drain metallization 402 below the gate field plate metallization 404.

[0103] The total capacitance of the charge storage element 450 can range from 1E-16 farads to 1E-15 farads per micrometer, but can be larger or smaller depending on the geometry, size, and voltage applied to the depletion-type NFET. Furthermore, the capacitance of the charge storage element 450 can be non-linear. Following the teachings herein, the gate field plate metallization 404 can be routed to improve the switching performance of the depletion-type NFET (e.g., depletion-type NFET 156 and / or depletion-type NFET 166). Additionally, if desired, the gate field plate metallization 404 can be routed differently for depletion-type NFET 156 and depletion-type NFET 166.

[0104] For example, but not limited to, such as Figure 2 As shown, the charge storage element 450 can be used to create and / or partially create the charge storage element C. FPD and / or charge storage element C GD The charge storage element C can be achieved by using a combination of charge storage element 450 and an external charge storage element. FPD and / or charge storage element C GD The desired capacitance can be achieved by using charge storage element 450 alone to achieve the charge storage element C. FP D and / or charge storage element C GD The desired capacitance can be achieved by using an external charge storage element, or by using an external charge storage element alone to achieve the charge storage element C. FPD and / or charge storage element C GD The expected capacitance.

[0105] Figure 5 Examples are given based on Figures 4A-4B A partial metallization layout of a depletion-type NFET in one embodiment.

[0106] As discussed herein, devices according to this disclosure may include multiple common-source cascode devices, such as... Figure 1AThe HS cascode power device 126 and LS cascode power device 128 shown are examples of, or a greater number of, cascode-connected devices. In one aspect, the layout of such devices can include multiple cells, such as... Figures 4A-4B As shown in the figure.

[0107] As seen from the top view, Figure 5 One or more stripes 504a, one or more stripes 504b, and one or more stripes 505 are shown. Stripe 504a is electrically coupled to drain metallization 403 of a depletion-type NFET (e.g., depletion-type NFET 166), stripe 504b is electrically coupled to drain metallization 403 of the depletion-type NFET, and stripe 505 may be electrically coupled to source metallization 402.

[0108] On the left side of line 525, the interconnect for the depletion-type NFET can be patterned such that gate field plate metallization 404 is electrically coupled to gate metallization 405. In such an aspect of this disclosure, this interconnect pattern provides... Figure 2 The charge storage element C shown GD .

[0109] To the right of line 526, the interconnects for the depletion-type NFETs can be patterned such that the gate field plate metallization 404 is electrically coupled to the field plate (FP) (floating) node 515. The location of the bonding pads for the FP node 515 is shown in... Figure 5 In the middle. The FP node 515 can be coupled to the gate of the first (lower) NFET 165, which provides, as Figure 2 The charge storage element C shown FPD By moving the positions of lines 525 and 526, charge storage element C can be charged. GD and / or charge storage element C FPD Add or remove charge storage element C GD and / or charge storage element C FPD Subtracting various amounts of capacitance allows for control of the overall device switching according to one aspect of this disclosure.

[0110] Figure 6 Examples are given based on Figure 5 The top-view metallization layout of the depletion-type NFET in the embodiment.

[0111] To electrically couple a depletion-type NFET (e.g., NFET 166) to other components in a circuit, external pads are typically provided on the die or chip. In one embodiment, the source of the depletion-type NFET may be coupled to pad 602, the drain of the depletion-type NFET may be coupled to pad 603, and the gate of the depletion-type NFET may be coupled to pad 605, and so on. Figure 5 The FP node 515 under discussion can be coupled to pad 615. Within the layout portion 625, gate field plate metallization 404 can be coupled to pad 615, while outside the layout portion 625, gate field plate metallization 404 is electrically coupled to gate metallization 405.

[0112] In such a respect, a certain percentage of the total capacitance associated with charge storage element 450 (e.g., approximately three to seven percent, which could be five percent, or some other percentage) can be used for charge storage element C within layout portion 625. FPD . refer to Figure 2 Charge storage element C FPD This can be achieved by connecting the FP node 515 to the gate of the first (lower) NFET 165 via pad 615. Without departing from the scope of this disclosure, the layout portion 625 can be made larger or smaller to increase or decrease the space available for the charge storage element C. FPD The percentage of the total capacitance associated with charge storage element 450.

[0113] It can be used in charge storage elements C GD The amount of total capacitance associated with charge storage element 450 corresponds to the interconnect portion outside layout portion 625, wherein gate field plate metallization 404 is coupled to gate metallization 405.

[0114] in conclusion The foregoing description of the illustrative embodiments of this disclosure, including those described in the abstract, is not intended to be exhaustive or to limit the precise forms disclosed. For example, other embodiments may exist, including motor driver topologies with alternative switching configurations. While specific embodiments and examples of programmable slew rates in cascode power devices have been described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of this disclosure. Indeed, it should be understood that specific example voltages, currents, frequencies, power range values, times, etc., are provided for illustrative purposes, and other values ​​may be employed in other embodiments and examples in accordance with the teachings herein.

[0115] The foregoing description may refer to elements or features as “connected” or “coupled” together. As used herein, unless otherwise expressly stated, “connected” means that one element / feature is directly or indirectly connected to another element / feature, and not necessarily mechanically. Similarly, unless otherwise expressly stated, “coupled” means that one element / feature is directly or indirectly coupled to another element / feature, and not necessarily mechanically. Therefore, although the various schematic diagrams shown in the accompanying drawings depict exemplary arrangements of elements and components, additional intermediate elements, devices, features, or components may be present in actual implementations (assuming that the function of the depicted circuit is not adversely affected).

[0116] Furthermore, the conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “eg,” “for example,” “such as,” etc., unless otherwise expressly stated or otherwise understood in the context in which they are used, is generally intended to convey that certain embodiments include certain features, elements, and / or states while other embodiments do not. Therefore, such conditional language is generally not intended to imply that features, elements, and / or states are required in any way for one or more embodiments, or that one or more embodiments necessarily include logic for determining whether such features, elements, and / or states are included or will be performed in any particular embodiment.

[0117] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel apparatuses, methods, and systems described herein can be embodied in a wide variety of other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the methods and systems described herein without departing from the spirit of this disclosure. For example, while the disclosed embodiments are presented with a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements can be implemented in a wide variety of different ways. Any suitable combination of elements and actions of the various embodiments described above can be combined to provide other embodiments. Therefore, the scope of the invention is defined only by the appended claims.

[0118] Although the claims set forth herein are submitted to the USPTO in a single dependent form, it should be understood that any claim may be dependent on any preceding claim of the same type, unless it is clearly not technically feasible.

Claims

1. A slew rate controller, comprising: First device; The second device is coupled to the first device via a common source and common gate ground. A charge storage device, wherein the charge storage device is coupled between the first device and the second device; as well as A driver configured to selectively provide a drive signal to the gate of the first device, wherein the charge storage device shunts the gate of the first device to the drain of the second device.

2. The slew rate controller according to claim 1, wherein, The first device and the second device are configured to provide a negative gain from the gate of the first device to the drain of the second device.

3. The slew rate controller according to claim 1, wherein, The charge storage device is coupled between the gate of the first device and the drain of the second device.

4. The slew rate controller according to claim 3, wherein, The charge storage device includes a capacitor.

5. The slew rate controller according to claim 3, wherein, The charge storage device is the field plate of the second device.

6. The slew rate controller according to claim 1, wherein, The drain of the second device is electrically coupled to the switching node.

7. The slew rate controller according to claim 1, wherein, The first device is an enhancement-mode n-channel field-effect transistor (NFET), and the second device is a depletion-mode NFET.

8. The slew rate controller according to claim 7, wherein, The depletion-type NFET is a depletion-type gallium nitride (GaN) NFET.

9. The slew rate controller according to claim 1, wherein, The charge storage device includes the internal charge storage of the second device.

10. The slew rate controller according to claim 9, wherein, The internal charge storage of the second device is divided into multiple parts.

11. The slew rate controller according to claim 10, wherein, The first portion of the plurality of portions is coupled between the drain of the second device and the source of the first device.

12. The slew rate controller according to claim 11, wherein, The second portion of the plurality of portions is coupled between the field plate of the second device and the gate of the first device.

13. The slew rate controller according to claim 12, wherein, The ratio between the first portion of the plurality of portions and the second portion of the plurality of portions is at least partially based on the slew rate of the slew rate controller.

14. A power converter, comprising: A common-source cascode circuit, which is electrically coupled to the input of the power converter; A driver circuit electrically coupled to a control connection terminal of the cascode circuit, wherein the driver circuit is configured to selectively control the cascode circuit with a drive signal; and A charge storage device electrically coupled to the control connection, wherein, when the drive signal is provided, the charge storage device shunts the control connection to the drain of the cascode circuit.

15. The power converter according to claim 14, wherein, The common-source, common-gate circuit includes a first transistor and a second transistor, which are electrically connected to each other via a common source, common gate.

16. The power converter according to claim 15, wherein, The control connection terminal is the first gate of the first transistor.

17. The power converter according to claim 15, wherein, The drain is the drain of the second transistor.

18. The power converter according to claim 15, wherein, The first transistor is an enhancement-mode n-channel field-effect transistor (NFET), and the second transistor is a depletion-mode NFET.

19. The power converter according to claim 15, wherein, The common-source, common-gate circuit further includes a third transistor and a fourth transistor, which are electrically connected to each other via a common-source, common-gate connection.

20. The power converter according to claim 19, wherein, The third transistor is an enhancement-mode n-channel field-effect transistor (NFET), and the fourth transistor is a depletion-mode NFET.

21. The power converter according to claim 20, wherein, The common source, common gate circuit is electrically coupled to the energy transfer element of the power converter.

22. The power converter according to claim 17, wherein, The energy transfer element is coupled to the load of the power converter.

23. The power converter according to claim 14, wherein, The driver circuit selectively controls the common-source cascode circuit based at least in part on oscillations in the input signal.

24. The power converter according to claim 23, wherein, The driver circuit selectively controls the common-source cascode circuit at intervals at least partially determined by the frequency of the oscillation.

25. The power converter according to claim 14, wherein, The driver circuit selectively controls the cascode circuit by selecting the number of branches of the driver circuit to select the amount of current to be supplied to the cascode circuit.

26. The power converter according to claim 14, wherein, The charge storage device includes the internal charge storage of the common-source, common-gate device.

27. The power converter according to claim 26, wherein, The internal charge storage of the common-source cascode device is divided into multiple parts.

28. The power converter according to claim 27, wherein, The first of the plurality of portions is coupled between the drain of the second device of the common-source cascode device and the source of the first device of the common-source cascode device.

29. The power converter according to claim 28, wherein, The second portion of the plurality of portions is coupled between the field plate of the second device of the cascode device and the gate of the first device of the cascode device.

30. The power converter according to claim 29, wherein, The ratio between the first portion of the plurality of portions and the second portion of the plurality of portions is at least partially based on the slew rate of the power converter.

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