A multi-frequency navigation signal simulation source signal generation method

Abstract

The application relates to a multi-frequency navigation signal simulation source signal generation method. The method comprises the following steps: arranging satellite and frequency point combinations in time sequence through a two-dimensional time slot rotation table, and distributing time slot lengths in proportion to the code rate of each frequency point. A single digital baseband channel generates the intermediate frequency signals of the corresponding combinations in each time slot in turn, and the signals are converted into analog intermediate frequency signals through a single DAC. Then, the signals are switched to the corresponding up-conversion branches according to the frequency point index through a radio frequency fast switching switch. The PLLs of the branches are locked to the local oscillator frequency before signal generation and remain locked, and the up-conversion output radio frequency signals are obtained. Meanwhile, the duty cycle loss is calculated according to the frequency point of the combination, and the output power is preset in combination with the target C / N0 and the engineering margin to ensure that the equivalent C / N0 of the receiver input end meets the standard. The output power is preset in combination with the target C / N0 and the engineering margin, so that the equivalent C / N0 of the receiver input end reaches the target C / N0, thereby being applicable to multi-frequency band wired test simulation sources.

Description

Technical Field

[0001] This application relates to the field of satellite navigation signal simulation and testing technology, and in particular to a method for generating multi-frequency navigation signal simulation source signals. Background Technology

[0002] Multi-frequency navigation signal simulation sources need to simultaneously generate satellite signals across multiple frequency bands (BDS B1C / B2a, GPS L1 / L5, etc.). In conventional architectures, each frequency point typically has a corresponding frequency conversion unit, filtering unit, and output matching unit, and multiple digital baseband channels and digital-to-analog conversion resources are configured in the front-end of each frequency point. The hardware scale is related to the product of the number of frequency points and the number of satellites. Therefore, the hardware cost of multi-frequency navigation signal simulation sources is relatively high. In receiver production line testing scenarios, simulation sources are essential testing equipment, and multi-band support will further increase the investment in production line construction.

[0003] Existing partial multiplexing schemes can reduce baseband processing resources to some extent. However, in multi-frequency navigation signal simulation sources, different frequencies usually still require corresponding frequency conversion units, filtering units, and output matching units. Existing schemes have not yet unified the processing of baseband channel multiplexing, digital-to-analog conversion multiplexing, and multi-frequency RF output.

[0004] In existing technologies, baseband channels, digital-to-analog converters, and output branches at various frequencies are typically configured separately according to frequency and channel. Although some time-division multiplexing schemes compress baseband channels, they have not yet solved the timing connection problem between a single baseband channel, a single digital-to-analog converter, and multiple frequency output branches. Summary of the Invention

[0005] To address the aforementioned issues, this application provides a method for generating analog source signals for multi-frequency navigation signals, which reduces the number of parallel baseband channels, digital-to-analog converters, and analog intermediate frequency preamplifiers in multi-frequency wired testing scenarios.

[0006] A method for generating multi-frequency navigation signal simulation source signals is disclosed. This method is used to generate multi-frequency navigation test signals under wired testing conditions, where the number of frequencies to be simulated is [number missing]. ,and The methods include: Obtain the number of satellites to be simulated, the number of frequency points, and the code rate of each frequency point; construct a two-dimensional time slot rotation table, and arrange the satellite-frequency combination of each satellite and each frequency point in time sequence according to the number of satellites and the number of frequency points; The effective time slot length corresponding to each frequency point is determined based on the code rate of each frequency point, so that the effective time slot length of different frequency points is inversely proportional to their respective code rates, and a guard interval is set between adjacent effective time slots. Following the order of the two-dimensional time slot rotation table, when the current satellite-frequency combination is selected, the intermediate frequency signal corresponding to the current satellite-frequency combination is generated by a single digital baseband channel within the current valid time slot; The intermediate frequency signal is converted into an analog intermediate frequency signal through a single-channel DAC; The analog intermediate frequency (IF) signal is input to the RF fast switching switch located on the analog IF path. Based on the frequency index corresponding to the current effective time slot, the analog IF signal is routed to the upconversion branch corresponding to the frequency point. Each frequency point corresponds to an upconversion branch, which includes a PLL, an upconversion unit, a filtering unit, and an output matching unit. The PLL locks to the local oscillator frequency required for the corresponding frequency point before signal generation and remains locked during signal generation, providing the local oscillator signal to the corresponding upconversion unit. The upconversion unit upconverts the received analog IF signal and outputs the RF signal of the corresponding frequency point. The duty cycle loss of a satellite-frequency combination is calculated based on the effective duty cycle of the individual satellite-frequency combination on its respective frequency. Based on the target C / N0 at the receiver input, the duty cycle loss, and the engineering margin, the C / N0 setting value of the frequency point in the satellite-frequency combination during the effective time slot output is determined in advance. The output power of the navigation signal analog source is then set according to the C / N0 setting value.

[0007] The aforementioned method for generating analog source signals for multi-frequency navigation signals arranges satellite and frequency points into the same two-dimensional time-slot rotation table. A single digital baseband channel generates intermediate frequency (IF) signals for each satellite-frequency point combination according to the time slots. By incorporating the frequency point dimension into the time-slot rotation table, a single digital baseband channel and a single DAC can generate IF signals for different satellite-frequency point combinations in a time-division manner, thereby reducing the need for independent configuration of baseband channels, DACs, and analog IF preamplifiers for each frequency point. The analog IF signal output from the single DAC is sent to the upconversion branch of the corresponding frequency point via an RF fast switching switch. The PLL in each upconversion branch is locked to the corresponding local oscillator frequency before signal generation and remains locked during signal generation, with the upconversion unit performing the upconversion. Thus, the hardware structure can be adjusted from K×N sets of parallel baseband channels and multiple digital-to-analog converters / IF preamplifiers to 1 set of baseband channels, 1 DAC, K upconversion branches, and 1 RF fast switching switch; different frequency points still retain corresponding upconversion units, filtering units, and output matching units. In wired testing, the duty cycle loss of a single satellite-frequency combination is calculated based on its respective frequency as the output power setting parameter, so that the equivalent C / N0 at the receiver input meets the target C / N0 condition. Attached Figure Description

[0008] Figure 1 This is a flowchart illustrating a method for generating analog source signals for multi-frequency navigation signals in one embodiment; Figure 2This is a schematic diagram of the hardware architecture of a multi-frequency navigation signal simulation source in one embodiment; Figure 3 This is a schematic diagram of the non-uniform length two-dimensional time slot rotation timing in one embodiment, which is allocated inversely proportional to the code rate; Figure 4 This is a comparison diagram of the rotation period and silence interval for equal-length and non-equal-length time slots in one embodiment. Figure 4 (a) is a comparison chart of rotation cycles. Figure 4 (b) is a comparison chart of silent intervals; Figure 5 This is a simulation diagram of receiver correlation tracking under the short time slot condition B2a in one embodiment, wherein, Figure 5 (a) is a comparison of normalized correlation peaks. Figure 5 (b) is a comparison chart of code phase tracking errors. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0010] In one embodiment, combined Figure 1 , Figures 2 to 3 A method for generating analog source signals for multi-frequency navigation signals is provided, comprising the following steps: Step 102: Obtain the number of satellites to be simulated, the number of frequency points, and the code rate of each frequency point; construct a two-dimensional time slot rotation table, and arrange the satellite-frequency combination of each satellite and each frequency point in sequence according to the number of satellites and the number of frequency points.

[0011] Let N be the number of satellites to be simulated, and K be the number of frequency points. The two dimensions of satellites and frequency points are unified into a two-dimensional time-slot rotation table, containing N×K combinations. Each combination corresponds to the signal generation task of one satellite on one frequency point. These combinations are arranged sequentially according to a preset order (including satellite first, then frequency point, or frequency point first, then satellite), forming a cyclical timing sequence. The construction of the two-dimensional time-slot rotation table is the foundation for including frequency points in the time-slot rotation framework, enabling subsequent single-channel processing of signals from all satellites and all frequency points uniformly, and allowing a single digital baseband channel to cover multiple frequency points without increasing the number of parallel channels.

[0012] Step 104: Determine the effective time slot length corresponding to each frequency point based on the code rate of each frequency point, so that the effective time slot length of different frequency points is inversely proportional to their respective code rates, and set a guard interval between adjacent effective time slots.

[0013] In multi-frequency scenarios, the code rates differ across frequencies. The code loop discriminator in the receiver's tracking loop needs to accumulate a sufficient number of chips within a single time slot to extract valid measurements. If the time slots for each frequency are of equal length, the number of chips accumulated by low-rate frequencies within the same time slot is far less than that of high-rate frequencies, potentially leading to ineffective tracking of low-rate frequencies. Based on this difference, this step allocates time slot lengths inversely proportional to the code rate: longer time slots for low-rate frequencies and shorter time slots for high-rate frequencies, ensuring that the equivalent chip accumulation amount for each frequency within each time slot is approximately equal.

[0014] Step 106: Following the order of the two-dimensional time slot rotation table, when the current satellite-frequency combination is selected, the single-channel digital baseband channel generates the intermediate frequency signal corresponding to the current satellite-frequency combination within the current effective time slot.

[0015] Each single-channel digital baseband system maintains an independent channel state for each satellite-frequency pair, including carrier NCO phase, code NCO phase, code generator state, message pointer, and last update time. When the channel rotates to a specific combination, it reads the state of that combination from the storage unit, calculates the carrier phase and code phase increments based on the time difference between the current time and the last update time of that combination, generates the intermediate frequency (IF) signal for the current time slot, and then writes back the updated state. A single-channel digital baseband system does not need to generate all N×K signals in parallel, and phase continuity is maintained when each combination is selected again. The IF frequencies for different frequencies can be the same (fixed IF) or set to different values ​​after digital up-conversion.

[0016] like Figure 3 The diagram shows a timing sequence for non-uniform two-dimensional time slot rotation. A guard interval is reserved after each time slot for rapid radio frequency switching. Satellites and frequencies are unified into a two-dimensional time slot rotation: .in, This indicates that for satellites, B1C and B2a, different code rate frequency points correspond to different effective time slot lengths, and the guard interval... Inserted between adjacent valid time slots.

[0017] Step 108: Convert the intermediate frequency signal into an analog intermediate frequency signal using a single-channel DAC.

[0018] A single-channel DAC converts the intermediate frequency (IF) digital signal output from the digital baseband channel into an analog IF signal for subsequent upconversion processing. Since the IF signals from all frequencies and satellites are multiplexed to the same digital stream via two-dimensional time slots in the time domain, a single DAC can complete the digital-to-analog conversion, reducing the need for independent DACs at each frequency.

[0019] Step 110: Input the analog intermediate frequency (IF) signal to the RF fast switching switch set on the analog IF path. Based on the frequency index corresponding to the current effective time slot, route the analog IF signal to the upconversion branch corresponding to the frequency point. Each frequency point corresponds to an upconversion branch, which includes a PLL, an upconversion unit, a filtering unit, and an output matching unit. The PLL locks to the local oscillator frequency required for the corresponding frequency point before signal generation and remains locked during signal generation. It provides the local oscillator signal to the corresponding upconversion unit. The upconversion unit upconverts the received analog IF signal and outputs the RF signal of the corresponding frequency point.

[0020] The system pre-configures K upconversion branches, each corresponding to a specific RF carrier frequency. The PLL in each upconversion branch locks to the required local oscillator frequency before signal generation and remains locked during signal generation, without being turned off or relocked during frequency switching. The RF fast switching switch receives the frequency index from the time slot selector and completes route switching within the guard interval of each time slot, sending the analog intermediate frequency signal to the corresponding upconversion branch. Because the PLL remains locked and the switching time is less than 100ns, frequency switching does not require waiting for PLL relocking. Finally, the PLL provides the local oscillator signal to the corresponding upconversion unit, which performs upconversion, filtering, and output matching before outputting the RF signal for each frequency.

[0021] Step 112: Calculate the duty cycle loss corresponding to the satellite-frequency combination based on the effective duty cycle of the individual satellite-frequency combination on its respective frequency point, and pre-determine the C / N0 setting value of the frequency point in the satellite-frequency combination during the effective time slot output period based on the target C / N0 at the receiver input, the duty cycle loss, and the engineering margin, and set the output power of the navigation signal analog source according to the C / N0 setting value.

[0022] Under non-uniform time slot conditions, the duty cycle loss is calculated based on a single satellite-frequency combination, and the value is taken separately according to the frequency points to which the combination belongs, rather than simply based on... Calculation. For a single satellite-frequency combination at frequency point The effective duty cycle can be expressed as: ; The corresponding single-combination duty cycle loss is: ; Therefore, different time slot lengths will result in different duty cycle losses for each satellite-frequency combination; correspondingly, this loss should be compared with the receiver tracking threshold and the wired test input power margin for each frequency.

[0023] When setting the output power for wired testing, the analog source first determines the C / N0 at the target receiver input, then adds the duty cycle loss and engineering margin to obtain the C / N0 setting value during the time slot output period. For frequency points... It can be set as follows: ; in, For frequency point The C / N0 setting value that should be set during time slot output; For the target receiver input terminal C / N0; For a single satellite-frequency combination in frequency point Duty cycle loss; This is for engineering margin.

[0024] The analog source can determine the output power of each frequency point before generating the signal; after deducting the duty cycle loss introduced by time division multiplexing, the receiver can still obtain the target C / N0.

[0025] In the above method, a two-dimensional time-slot rotation table uniformly arranges satellites and frequency points. A single digital baseband channel generates intermediate frequency (IF) signals for each pair of satellites and frequency points according to the time slot. K upconversion branches, equal in number to the frequency points, correspond to each frequency point. The PLL in each branch is locked to the corresponding local oscillator frequency before signal generation and remains locked during signal generation. The RF fast switching switch routes the analog IF signal output from the single DAC to the corresponding upconversion branch according to the frequency point index of the current time slot. The PLL provides the local oscillator, and the upconversion unit completes the upconversion. This structure allows each satellite-frequency point combination to reuse the same baseband and digital-to-analog conversion path according to the time slot, reducing the number of parallel baseband channels, DACs, and analog IF preamplifiers, and reducing the complexity of multi-channel synchronization and calibration. In wired testing, the analog source first calculates the duty cycle loss according to the frequency point to which the combination belongs, and then determines the output power of each frequency point by combining the C / N0 input of the target receiver and the reserved margin, so that the duty cycle loss is pre-included in the output power setting stage.

[0026] In one embodiment, the arrangement order of the combinations in the two-dimensional time-slot rotation table is as follows: first, traverse all satellites, and then traverse all frequency points for each satellite in turn; or first, traverse all frequency points, and then traverse all satellites for each frequency point in turn; the number of combinations of each satellite and each frequency point is determined based on the number of satellites and frequency points to be simulated. × One, of which The number of satellites to be simulated. This represents the number of frequency points.

[0027] The rotation order can be set according to the digital baseband processing flow. For example, a satellite-first, frequency-second order facilitates centralized frequency switching during signal generation from a single satellite, reducing the number of state loading operations; a frequency-first, satellite-second order facilitates maintaining the same frequency route across multiple consecutive satellite time slots, reducing the number of RF fast switching operations. Both orders are applicable to the two-dimensional time slot rotation table of this application.

[0028] In one embodiment, the time slot calculation process is as follows: ; in, For frequency point The corresponding time slot length, As the reference time slot length, For frequency point code rate, This represents the lowest code rate among all frequency points.

[0029] When calculating according to the above relationship, the chip accumulation of each frequency point in a single time slot is approximately equal, which can reduce the problems of insufficient accumulation of low-rate frequency points and redundant occupation of high-rate frequency points under equal-length time slots.

[0030] In one embodiment, the rotation period of the two-dimensional time-slot rotation table is... ; in, For sampling clock cycles, For frequency point The corresponding time slot length, The protection interval reserved after each time slot, The number of satellites to be simulated. This represents the number of frequency points.

[0031] The rotation period determines the time interval between two selections of each satellite-frequency pair. A shorter period results in a shorter silence time, which is more beneficial for the receiver PLL to maintain continuous tracking. Multi-rate time slot allocation is used to reduce redundant occupation of high-rate frequencies and shorten the rotation period.

[0032] In one embodiment, the length of each time slot must satisfy chip accumulation constraints, tracking continuity constraints, and switching constraints; The chip accumulation constraint is: ,in, For sampling clock cycles, For frequency point code rate, This is the minimum number of chips required by the receiver's code ring discriminator. The continuity constraint for tracking is: ,in, For frequency point The silence duration for the corresponding combination, For the rotation cycle, The time constant of the receiver PLL; The switch switching constraints are: ,and ,in, The protection interval reserved after each time slot, This refers to the RF switch switching time.

[0033] The three constraints mentioned above together determine the range of values ​​for the time slot length. By using multi-rate time slots allocated inversely proportional to the code rate, the chip accumulation at each frequency point can be nearly balanced, and the redundant increment of the rotation cycle can be reduced. When the number of satellites and frequencies is large, this allocation method can increase the margin to meet the tracking continuity constraint.

[0034] In one embodiment, during wired testing, the receiver operates in fixed gain mode, or automatic gain control is disabled, or automatic gain control is set to slow adjustment mode. Alternatively, the rotation period of the two-dimensional time slot rotation table can be made smaller than the equivalent time constant of the receiver's automatic gain control loop, so that the receiver's automatic gain control mainly responds to the average input power within the rotation period and does not adjust rapidly with changes in the time slot duty cycle of each satellite-frequency combination. If necessary, the analog source can output a preset noise floor in time slots not corresponding to the current satellite-frequency combination to reduce the variation in the total power at the receiver input within the rotation period.

[0035] If equal-length time slots are used (all frequency points are the same) Chip accumulation constraints Based on the lowest code rate frequency, that is For high-speed frequencies, this time slot length typically exceeds its necessary accumulation time, increasing the rotation cycle and making... Approaching the upper limit of the tracking continuity constraint. When and When the size is large, it may be difficult to simultaneously satisfy both the chip accumulation constraint and the tracking continuity constraint under equal-length time slots. Multi-rate allocation is then employed. back, It is mainly determined by the amount of chips required for each frequency point, which can reduce the redundant time caused by high-speed frequencies.

[0036] when and As the number of frequencies increases further, for example, to three frequencies or more than 40 satellites, the equal-length time slot scheme is more likely to approach or exceed the tracking continuity constraint due to excessively long rotation cycles. In this case, multi-rate allocation can reduce the redundant occupation of high-rate frequencies and reduce the risk of the rotation cycle increasing too rapidly with the number of frequencies and satellites.

[0037] In one embodiment, a protection interval is reserved after each time slot, and the RF fast switching switch completes the switching of frequency points within the protection interval; the protection interval is greater than the switching time of the RF fast switching switch and less than a preset proportion of the shortest effective time slot duration among all frequency points.

[0038] The protection interval can be set to several times the switching time and controlled to be a small fraction of the shortest effective time slot duration. For example, when the switching time of the RF fast switching switch is less than 100 ns, the protection interval can be 0.15 μs to 0.2 μs; when the shortest effective time slot is more than a few microseconds, the proportion of this protection interval is relatively small.

[0039] In one embodiment, each single-channel digital baseband channel maintains an independent channel state for each satellite-frequency pair. The channel state includes carrier NCO phase, code NCO phase, code generator state, message pointer, and last update time. When each combination is selected, the single-channel digital baseband channel reads the corresponding channel state, calculates the carrier phase and code phase increments based on the time difference between the current time and the last update time of that combination, generates the current timeslot signal, and then writes back the updated channel state.

[0040] This state recovery mechanism allows the carrier phase and code phase of each combination to continue to be calculated based on the elapsed time during the silent period. When a combination is selected again, the digital baseband channel reads and updates the corresponding state, thus eliminating the need to configure parallel real-time generation channels for each of the N×K combinations.

[0041] In one embodiment, the number of upconversion branches is equal to the number of frequency points. The PLL in each upconversion branch is locked to the local oscillator frequency required for the corresponding frequency point before signal generation, and remains locked during signal generation, without being turned off or relocked when the frequency point is switched.

[0042] In this structure, frequency switching does not rely on PLL relocking. Traditionally, PLL relocking typically takes tens to hundreds of microseconds when switching frequencies; in this application, the PLLs for each frequency remain locked during signal generation, and the frequency switching time is mainly determined by the RF fast switching switch.

[0043] In one embodiment, the intermediate frequency (IF) of different frequency points is the same, or the IF of different frequency points is set to different values ​​after being frequency-converted in the digital domain.

[0044] When the intermediate frequency (IF) is the same, each upconversion branch can obtain the corresponding radio frequency carrier through different PLL local oscillator frequencies; when the IF frequencies are different, preliminary spectrum shifting can be completed in the digital domain, and the local oscillator frequency of each upconversion branch is matched and set according to the corresponding IF frequency. The two methods can be selected according to the system requirements.

[0045] In one embodiment, the switching time of the radio frequency fast switching switch is less than 100 ns.

[0046] This switching time is shorter than the typical PLL lockout time (tens to hundreds of μs), reducing the waiting time introduced by frequency switching. In practical engineering, high-speed devices can be used to implement the aforementioned fast RF switching.

[0047] The following example, using a parameter calculation, further illustrates this method. The number of satellites to be simulated is set to N=30, with frequencies B1C (1575.42MHz, code rate 1.023Mcps) and B2a (1176.45MHz, code rate 10.23Mcps), and the number of frequency points K=2. The minimum code rate is 1.023Mcps (B1C), and the reference time slot sampling points are used. Therefore, the number of sampling points in time slot B1C is L(B1C) = 1000, and the number of sampling points in time slot B2a is L(B2a) = 1000 × (1.023 / 10.23) = 100. Assuming the sampling clock frequency is 20MHz, that is... Therefore, the effective time slot duration for B1C is 50μs, and the effective time slot duration for B2a is 5μs. The switching time of the RF fast switching switch is less than 100ns, and the protection interval can be 0.15μs, satisfying the requirements. .

[0048] Under the above parameters, the dual-frequency rotation cycle of the 30 satellites is: ; The silence duration for each satellite-frequency pair is as follows: B1C combination approximately The B2a combination is approximately If the receiver PLL time constant is 20ms, then the silence duration is less than approximately 8.3% of this time constant, which satisfies the tracking continuity constraint in this embodiment.

[0049] If equal-length time slots are used under the same parameters, and the chip accumulation requirement of the low code rate frequency point B1C is taken as the benchmark, then the B2a frequency point also needs to be allocated a 50μs effective time slot. A comparison between equal-length time slots and non-equal-length time slots in this embodiment is shown in Table 1: Table 1

[0050] Among them, the rotation period under equal-length time slots is approximately The rotation period under non-uniform time slots is approximately 1659 μs. Under this parameter, non-uniform time slots can shorten the rotation period by about 45%, and the silence time of each satellite-frequency combination is also reduced accordingly.

[0051] Figure 4 The number of satellites is shown to Within the range, compare the rotation period and silent interval of the equal-length time slot scheme and the non-equal-length time slot scheme that is inversely proportional to the code rate. Figure 4 (a) shows the trend of the complete rotation cycle as the number of satellites increases: In the equal-length time slot scheme, both B1C and B2a are allocated 50μs effective time slots, and the dual-frequency usage time of a single satellite is 100.3μs; in the non-equal-length time slot scheme, the effective time slot of B1C is 50μs, the effective time slot of B2a is 5μs, and the dual-frequency usage time of a single satellite is 55.3μs. Therefore, when At that time, the rotation period of the equal-length time slot scheme is about 5.015ms, while the rotation period of the non-equal-length time slot scheme is about 2.765ms. Figure 4 (b) The silence interval for the combination of B1C and B2a under the non-equal-length time slot scheme is given, with a difference of 0.045 ms, and in The average time interval is less than 3ms. This result shows that non-equal length time slot allocation can shorten the rotation cycle of multi-satellite dual-frequency circuits and keep the silence interval of each satellite-frequency combination within the time range that the receiver tracking loop can maintain.

[0052] In non-uniform time slots, the duty cycle loss is calculated separately for each frequency point of a single satellite-frequency combination. The parameter calculation results for this embodiment are shown in Table 2 below: Table 2

[0053] The C / N0 setting is calculated based on a target C / N0 of 45dB-Hz at the receiver input and an engineering margin of 3dB. These parameters can be used as the basis for calculating the output power setting for wired testing. The 0.15μs guard interval accounts for only 3% of the shortest effective time slot of 5μs, and has a minimal impact on the effective signal time.

[0054] Taking any satellite-frequency combination as an example, when this combination is selected again, the single digital baseband channel updates the carrier phase and code phase according to the time difference between the current time and the last update time, instead of restarting from the initial phase. Therefore, the state recovery process can work in conjunction with the two-dimensional time slot rotation table to maintain the phase continuity relationship of the same combination between adjacent output time slots. To verify the impact of this intermittent output mode on receiver tracking, correlation tracking simulation is performed below using the B2a frequency point with the shortest effective time slot.

[0055] Figure 5 The simulation results of receiver-dependent tracking under the short time slot condition of B2a are shown. The simulation uses a receiver-dependent tracking model, with the B2a frequency as the verification object, an effective time slot of 5μs for B2a, and a certain number of satellites. The target C / N0 at the receiver input is 45dB-Hz. The figure uses the continuously output B2a signal as the continuous output reference and compares the scheme with non-equal-length time-division output updated according to elapsed time with the scheme with equal-length time-division output updated according to elapsed time. Figure 5 (a) gives the normalized correlation peak. The correlation peak of the continuous output reference is normalized to 1. After the state is updated according to the elapsed time, the correlation peak of the non-equal length time division output scheme is close to that of the continuous output reference, and there is no periodic drop or jump. Figure 5 (b) The absolute value of the code phase tracking error is given, with 0.1 chip as the tracking threshold reference. The code phase error of the non-equal-length time-division output scheme remains within this threshold and is lower than that of the equal-length time-division scheme. This result shows that under the conditions of a short time slot of 5μs in B2a and a rotation period of about 1.659ms, a single digital baseband channel can maintain continuous correlation tracking of the receiver by saving the state of each satellite-frequency combination and updating the carrier phase and code phase according to the last update time.

[0056] The hardware configuration of this embodiment may include: a single baseband channel (with 30×2 sets of state storage), one DAC, two upconversion branches (each including a PLL, a local oscillator-driven upconversion unit, a filtering unit, and an output matching unit), and one RF fast switching switch. Compared with the scheme of configuring multiple baseband channels and multiple DACs and analog IF preamplifiers in parallel according to frequency points and satellites, this configuration reduces the number of baseband channels, DACs, and analog IF preamplifiers; the upconversion units, filtering units, and output matching units corresponding to different frequency points are still retained according to frequency points.

[0057] In the aforementioned multi-frequency navigation signal simulation source signal generation method, the two dimensions of satellite and frequency are uniformly arranged as a two-dimensional time-slot rotation. A single digital baseband channel generates the intermediate frequency (IF) signal for each pair of satellites and frequencies according to the time slots, and outputs the analog IF signal through a single DAC. The analog IF signal is routed to the corresponding up-conversion branch according to the frequency point via a fast RF switching switch; the PLL in each up-conversion branch provides the local oscillator signal, and the up-conversion unit completes the up-conversion. When setting the output power for wired testing, the duty cycle loss is first accounted for according to the frequency point of the combination, and then the C / N0 setting value of each frequency point is determined so that the equivalent C / N0 at the receiver input reaches the target C / N0. This structure can reduce the number of baseband channels, DACs, and analog IF preamplifiers, while retaining the necessary RF output branches for each frequency point, and is suitable for multi-band, miniaturized wired test simulation sources.

[0058] It should be understood that although the steps in the above embodiments are described in the order of description, these steps are not necessarily executed in that order. Unless otherwise expressly stated herein, there is no strict order restriction on the execution of these steps, and they may be executed in other orders. Moreover, at least some steps may include multiple sub-steps or multiple stages, which may not necessarily be completed at the same time, but may be executed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0059] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0060] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for generating analog source signals for multi-frequency navigation signals, characterized in that, The method described above is used to generate multi-frequency navigation test signals under wired testing conditions, where the number of frequencies to be simulated is [number missing]. ,and The method includes: Obtain the number of satellites to be simulated, the number of frequency points, and the code rate of each frequency point; construct a two-dimensional time slot rotation table, and arrange the satellite-frequency combination of each satellite and each frequency point in sequence according to the number of satellites and the number of frequency points; The effective time slot length corresponding to each frequency point is determined based on the code rate of each frequency point, so that the effective time slot length of different frequency points is inversely proportional to their respective code rates, and a guard interval is set between adjacent effective time slots. According to the order of the two-dimensional time slot rotation table, when the current satellite-frequency combination is selected, the intermediate frequency signal corresponding to the current satellite-frequency combination is generated by a single digital baseband channel within the current effective time slot; The intermediate frequency signal is converted into an analog intermediate frequency signal using a single-channel DAC; The analog intermediate frequency (IF) signal is input to a radio frequency fast switching switch located on the analog IF path. Based on the frequency index corresponding to the current effective time slot, the analog IF signal is routed to an upconversion branch corresponding to that frequency. Each frequency corresponds to an upconversion branch, which includes a PLL, an upconversion unit, a filtering unit, and an output matching unit. The PLL locks to the local oscillator frequency required for the corresponding frequency before signal generation and remains locked during signal generation, providing the local oscillator signal to the corresponding upconversion unit. The upconversion unit upconverts the received analog IF signal and outputs the radio frequency signal for the corresponding frequency. The duty cycle loss corresponding to the satellite-frequency combination is calculated based on the effective duty cycle of the individual satellite-frequency combination on its respective frequency. Based on the target C / N0 at the receiver input, the duty cycle loss, and the engineering margin, the C / N0 setting value of the frequency point in the satellite-frequency combination during the effective time slot output is determined in advance. The output power of the navigation signal analog source is set according to the C / N0 setting value.

2. The method according to claim 1, characterized in that, The arrangement order of the combinations in the two-dimensional time slot rotation table is as follows: first, traverse all satellites, and then traverse all frequency points for each satellite in turn; or first, traverse all frequency points, and then traverse all satellites for each frequency point in turn; the number of combinations of each satellite and each frequency point is determined according to the number of satellites and frequency points to be simulated. × One, of which The number of satellites to be simulated. This represents the number of frequency points.

3. The method according to claim 1, characterized in that, The calculation process for the length of each time slot includes: ； in, For frequency point The corresponding time slot length, As the reference time slot length, For frequency point code rate, This represents the lowest code rate among all frequency points.

4. The method according to claim 1, characterized in that, The rotation period of the two-dimensional time-slot rotation table is ； in, For sampling clock cycles, For frequency point The corresponding time slot length, The protection interval reserved after each time slot, The number of satellites to be simulated. This represents the number of frequency points.

5. The method according to claim 1, characterized in that, The method further includes: The length of each time slot must satisfy chip accumulation constraints, tracking continuity constraints, and switching constraints; The chip accumulation constraint is: ,in, For sampling clock cycles, For frequency point code rate, The minimum number of chips required by the receiver code ring discriminator. For frequency point The corresponding time slot length; The tracking continuity constraint is: ,in, For frequency point The silence duration for the corresponding combination, For the rotation cycle, The time constant of the receiver PLL; The switch switching constraint is: ,and ,in, The protection interval reserved after each time slot, This refers to the RF switch switching time.

6. The method according to claim 1, characterized in that, The method further includes: A protection interval is reserved after each time slot, and the radio frequency fast switching switch completes the switching of frequency points within the protection interval; the protection interval is greater than the switching time of the radio frequency fast switching switch and less than a preset proportion of the shortest effective time slot duration among all frequency points.

7. The method according to claim 1, characterized in that, The single-channel digital baseband channel maintains an independent channel state for each pair of satellite-frequency points. The channel state includes carrier NCO phase, code NCO phase, code generator state, message pointer, and last update time. When each combination is selected, the single-channel digital baseband channel reads the corresponding channel state, calculates the carrier phase and code phase increments based on the time difference between the current time and the last update time of the satellite-frequency point combination, generates the current time slot signal, and then writes back the updated channel state.

8. The method according to claim 1, characterized in that, The number of upconversion branches is equal to the number of frequency points. The PLL in each upconversion branch is locked to the local oscillator frequency required for the corresponding frequency point before signal generation, and remains locked during signal generation, without being turned off or relocked when the frequency point is switched.

9. The method according to claim 1, characterized in that, The intermediate frequency (IF) of different frequency points is the same, or the IF of different frequency points is set to different values ​​after upconversion in the digital domain; when different frequency points use the same IF, each upconversion branch obtains the corresponding RF carrier through different PLL local oscillator frequencies; when different frequency points use different IFs, the local oscillator frequency of each upconversion branch is matched and set according to the corresponding IF frequency.

10. The method according to claim 1, characterized in that, Under wired testing conditions, the receiver operates in fixed gain mode, or the receiver's automatic gain control is turned off or set to slow adjustment mode, or the rotation period of the two-dimensional time slot rotation table is less than the equivalent time constant of the receiver's automatic gain control loop, so that the receiver front-end gain does not adjust rapidly with the change of the time slot duty cycle of each satellite-frequency combination.

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