A wafer level bonding method for a sunken microlens array and a silicon base

Abstract

The application discloses a wafer-level bonding preparation method of a sunken microlens array and a silicon base, which comprises the following steps: step S1, base pretreatment; step S2, deposition of a SiN mask layer; step S3, photoetching and SiN windowing; step S4, KOH wet etching; step S5, back surface alignment and deep silicon etching; step S6, preparation of a sunken microlens array; step S7, deposition of a SiO2 mask and secondary photoetching; step S8, deep silicon etching to form a microstructure; step S9, super-clean cleaning; step S10, precise alignment and silicon-silicon pre-bonding; and step S11, high-temperature annealing and dicing: after high-temperature annealing and reinforcement of a bonding interface, an integrated sunken microlens array silicon base fiber coupling base finished device is obtained after dicing. The application realizes high-precision, high-reliability and wafer-level integrated preparation.

Description

Technical Field

[0001] This invention belongs to the fields of precision processing of silicon-based micro-opto-electro-mechanical devices, fabrication of integrated optical devices, and precision processing of semiconductor micro-nano devices. Specifically, it is a wafer-level bonding method for fabricating a sunken microlens array to a silicon-based substrate. Background Technology

[0002] Silicon-based fiber optic coupling bases are core components for high-speed optical communication, fiber optic sensing, and laser-coupled optoelectronic packaging. Their thin film deposition, photolithography, wet etching, deep silicon etching, and bonding integration processes directly determine the fiber insertion positioning accuracy, optical path coupling efficiency, and long-term reliability of the device.

[0003] Existing traditional fabrication processes suffer from inefficient process layouts, often employing elongated V-groove structures without features such as flared entry, flat-bottom transition, and through-hole positioning. This results in low fiber assembly tolerance and poor alignment. Conventional processes lack the protection of LPCVD-SiN and PECVD-SiO2 double-layer dielectric masks, making them prone to crystal morphology damage during processing. Microlenses and substrates are often fabricated separately and assembled using manual adhesive bonding, leading to issues such as adhesive aging, temperature drift, debonding failure, and poor batch consistency. Traditional planar microlenses cannot autonomously form optical path gaps, requiring additional etching to avoid cavities, increasing process complexity. Existing similar processes do not form a complete closed-loop fabrication route and cannot simultaneously meet the requirements for smooth fiber entry, flat-bottom transition, precise through-hole positioning, high-precision microlens integration, and glue-free mass production.

[0004] Therefore, to address the above issues, a wafer-level bonding fabrication method for a sunken microlens array and a silicon-based substrate is provided. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this invention provides a wafer-level bonding fabrication method for a sunken microlens array and a silicon-based substrate. This method overcomes the shortcomings of existing fabrication processes, such as poor process compatibility, inability to achieve centering using V-grooves, lack of dielectric layer mask protection, low back-side alignment accuracy, poor microlens forming consistency, and insufficient reliability due to reliance on adhesives for assembly. It achieves high-precision, high-reliability, and wafer-level integrated fabrication.

[0006] The technical solution to achieve the above objectives is: A wafer-level bonding fabrication method for a sunken microlens array to a silicon substrate includes: Step S1, Substrate pretreatment: Select a (100) crystal orientation single crystal silicon substrate, remove surface contaminants and oxide layer to obtain a clean silicon substrate body; Step S2, Deposit SiN (Silicon Nitride) mask layer: Prepare a SiN thin film on the surface of the silicon substrate as a wet etching mask; Step S3, Photolithography and SiN Windowing: Define the inverted pyramid import positioning groove pattern through photolithography and etch the SiN thin film; Step S4, KOH (potassium hydroxide) wet etching: Prepare a flat-bottomed, through-type inverted pyramid-shaped inlet positioning groove; Step S5, back side alignment and deep silicon etching: a back side alignment through hole is made on the back side of the silicon substrate body, and the inverted pyramid guide positioning groove is coaxially connected with the back side alignment through hole. Step S6, fabrication of a sunken microlens array: Select a microlens chip and form a microlens array with flat edges and a sunken center by photoresist thermal reflow and ICP (inductively coupled plasma) etching; Step S7, SiO2 (silicon dioxide) mask deposition and secondary photolithography: deposit a SiO2 thin film on the surface of the microlens chip substrate and photolithographically define the lens alignment reference step and limiting edge pattern; Step S8, Deep silicon etching to form microstructure: Etching to prepare lens alignment reference steps and limiting edges; Step S9, Ultra-clean cleaning: The silicon substrate wafer and the microlens chip wafer are cleaned by plasma ashing to remove residual photoresist, wet cleaning and dry plasma ultra-clean cleaning process, so that the bonding interface is atomically clean. Step S10, Precision alignment and silicon-silicon prebonding: Align the two wafers using machine vision and complete room temperature glue-free prebonding; Step S11, High-temperature annealing and dicing: After high-temperature annealing to strengthen the bonding interface, the integrated sunken microlens array silicon-based fiber coupling base finished device is obtained after dicing.

[0007] Preferably, in step S1, the single-crystal silicon substrate is a 4-inch (100) crystal orientation P-type double-polished single-crystal silicon wafer. The SC1 and SC2 standard wafer cleaning processes are used. After cleaning, the wafer is dried with high-purity nitrogen and placed in a constant temperature oven at 120°C for 15 minutes to remove organic residues, metal ion impurities, natural oxide layer and micro-nano particle contaminants from the surface, thereby obtaining a silicon-based substrate body with a surface cleanliness that meets the requirements of thin film deposition, photolithography and bonding processes.

[0008] Preferably, in step S2, SiN thin films are deposited using LPCVD (low-pressure chemical vapor deposition) process. The SiN thin film has a dense structure and serves as a special mask protective layer for subsequent KOH high-temperature wet etching, shielding the non-processed areas of single-crystal silicon from being etched by the etching solution.

[0009] Preferably, in step S3, the photolithography process includes spin-coating photoresist on the SiN thin film surface, pre-baking, exposure, development, and defining a square window array pattern corresponding to the inverted pyramid inlet positioning groove; A dry etching process is used to selectively remove the SiN film in the window area, exposing the underlying single-crystal silicon substrate, while the remaining areas retain the complete protection of the SiN mask.

[0010] Preferably, in step S4, the KOH etching solution has a mass concentration of 30%–40%, an etching temperature of 70–85°C, and an etching time of 15–40 min; Utilizing the anisotropic corrosion characteristics of (100) crystal-oriented single-crystal silicon, an inverted pyramid-shaped cavity with a wide top and narrow bottom is spontaneously formed, surrounded by four {111} smooth crystal planes. The bottom of the groove retains a flat bottom and does not form a sharp bottom convergent structure. A flat bottom through-type inverted pyramid inlet positioning groove is prepared, and the roughness of the groove sidewall is controlled at Ra≤5nm.

[0011] Preferably, in step S5, alignment marks and through-hole patterns are made using a wafer back-side alignment photolithography process, and back-side alignment through-holes are formed by vertical etching using Bosch deep silicon etching process. The small flat bottom of the inverted pyramid guide positioning groove is strictly coaxial with the back-side alignment through-hole and is vertically connected.

[0012] Preferably, in step S6, the microlens chip substrate is a double-polished silicon wafer with the same specification (100) crystal orientation. After photoresist spin coating, patterned exposure and development, a continuous and smooth microlens convex surface is formed by photoresist thermal reflow process. Then, the curved surface morphology is transferred to the microlens chip substrate by ICP inductively coupled plasma etching. At the same time, a ring bonding surface structure with a sunken center and flat edges is prepared to form a sunken microlens array. The array arrangement specifications correspond one-to-one with the inverted pyramid guide positioning groove.

[0013] Preferably, in step S7, a SiO2 dielectric film is deposited on the entire surface of the microlens chip wafer as a deep silicon etching hard mask using PECVD (plasma-enhanced chemical vapor deposition) process. Secondary photolithography defines the processing pattern of the lens alignment reference step and the limiting edges on both sides, and etching removes the SiO2 thin film in the pattern area to achieve windowing.

[0014] Preferably, in step S8, Bosch alternating etching and passivation cycle process is used for deep silicon etching, the verticality of the etched sidewall is controlled to be 89.5° to 90°, the flatness of the lens alignment reference step plane is 0.5 to 1 μm, and the mounting reference step and symmetrically arranged limiting edges are integrally processed to realize the bidirectional mechanical pre-limiting of the microlens chip in the lateral and longitudinal directions.

[0015] Preferably, in step S10, a high-precision machine vision double-sided alignment system is used to control the alignment deviation to ≤2μm; the vacuum degree of the bonding cavity is ≤5×10⁻³Pa; and a uniform pre-bonding pressure of 0.8~1.2MPa is applied to complete the glue-free silicon pre-bonding at room temperature. In step S11, the high-temperature annealing conditions are 350-450℃ and held at a constant temperature for 2-4 hours to allow silicon atoms at the bonding interface to fully diffuse and the lattice to fuse. After furnace cooling, the wafer is diced, shaped and cleaned to obtain the finished device of the integrated sunken microlens array silicon-based fiber coupling base. The microlens autonomously reserve a 1-10μm optical path gap by relying on its own sunken structure.

[0016] Compared with the prior art, the beneficial effects of the present invention are: This invention employs a flat-bottomed, through-type inverted pyramid-shaped guide and positioning groove to achieve smooth fiber optic port insertion, automatic centering, flat-bottom transition, and precise positioning of the lower circular hole, significantly improving assembly tolerance and coaxiality. This invention employs a dual-layer dielectric mask of LPCVD-SiN and PECVD-SiO2, which offers high process selectivity, good structural forming accuracy, and eliminates the need for additional cavity etching, thus simplifying the process flow. This invention relies on the microlens chip's own sunken structure to naturally form a 1-10 μm micron-level air optical path gap, eliminating the need for additional etching of optical path avoidance cavities on the silicon substrate surface; it uses direct silicon-silicon bonding to completely replace traditional organic adhesive bonding, avoiding problems such as adhesive layer aging, temperature drift, and debonding failure; the entire process is closed-loop controllable, with strong process repeatability, and is fully compatible with wafer-level whole-wafer processing, bonding, annealing, and dicing mass production modes. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart of steps S1-S5 in the preparation method described in this invention; Figure 2 This is a flowchart of steps S6-S8 in the preparation method described in this invention; Figure 3 This is a flowchart of steps S9-S11 in the preparation method described in this invention; Figure 4 This is a schematic diagram of the structural process flow of steps S1-S5 in the preparation method described in this invention; Figure 5 This is a schematic diagram of the structural process flow of steps S6-S8 in the preparation method described in this invention; Figure 6 This is a schematic diagram of the final integrated sunken microlens array silicon-based fiber coupling base device obtained by the preparation method described in this invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] like Figure 1-6 As shown, a wafer-level bonding fabrication method for a sunken microlens array to a silicon-based substrate includes: Step S1, Substrate pretreatment: Select a (100) crystal orientation single crystal silicon substrate, remove surface contaminants and oxide layer, and obtain a clean silicon substrate body 1.

[0020] In this embodiment, the monocrystalline silicon substrate is a 4-inch (100) crystal orientation P-type double-polished monocrystalline silicon wafer. The SC1 and SC2 standard wafer cleaning processes are used. After cleaning, the wafer is dried with high-purity nitrogen and placed in a constant temperature oven at 120°C for 15 minutes to remove organic residues, metal ion impurities, natural oxide layer and micro-nano particle contaminants on the surface. A silicon-based substrate body 1 with surface cleanliness that meets the requirements of thin film deposition, photolithography and bonding processes is obtained. In this embodiment, (100) crystal orientation monocrystalline silicon refers to monocrystalline silicon material with atomic arrangement direction along the cubic edge direction of the unit cell.

[0021] Step S2, depositing a SiN mask layer: a SiN thin film is prepared on the surface of the silicon substrate 1 as a wet etching mask.

[0022] In this embodiment, an LPCVD process is used to deposit a SiN thin film. The SiN thin film has a dense structure and serves as a dedicated mask protective layer for subsequent KOH high-temperature wet etching, shielding the non-processed areas of single-crystal silicon from being etched by the etching solution.

[0023] Step S3, Photolithography and SiN Windowing: Define the inverted pyramid import positioning groove 2 pattern through photolithography and etch the SiN thin film.

[0024] In this embodiment, the photolithography process includes spin coating of photoresist on the SiN thin film surface, pre-baking, exposure, and development, defining a square window array pattern corresponding to the inverted pyramid guide positioning groove 2; A dry etching process is used to selectively remove the SiN film in the window area, exposing the underlying single-crystal silicon substrate, while the remaining areas retain the complete protection of the SiN mask.

[0025] Step S4, KOH wet etching: Prepare a flat-bottomed through-type inverted pyramid-shaped inlet positioning groove 2.

[0026] In the examples, the KOH etching solution had a mass concentration of 30%–40%, an etching temperature of 70–85°C, and an etching time of 15–40 min. Utilizing the anisotropic etching characteristics of (100) oriented single-crystal silicon, an inverted pyramid-shaped cavity with a wider top and narrower bottom, surrounded by four {111} smooth crystal planes, is spontaneously formed. The bottom of the groove retains a flat bottom and does not form a sharp bottom convergent structure. This process prepares an inverted pyramid-shaped introductory positioning groove 2 with a flat bottom and a through-type structure. The roughness of the groove sidewall is controlled to Ra≤5nm. The {111} crystal plane is composed of all crystal planes that are equivalent to (111) symmetry (a total of 8), including (111), (1-11), (-111), (-1-11), (11-1), (1-1-1), (-11-1), (-1-1-1), (-1-1-1), a total of 8 equivalent crystal planes.

[0027] Step S5, back-side alignment and deep silicon etching: A back-side alignment through-hole 3 is made on the back side of the silicon substrate body 1, and the inverted pyramid guide positioning groove 2 is coaxially connected with the back-side alignment through-hole 3.

[0028] In this embodiment, alignment marks and through-hole patterns are made using a wafer back-side alignment photolithography process. The back-side alignment through-hole 3 is formed by vertical etching using a Bosch deep silicon etching process. The bottom flat bottom of the inverted pyramid guide positioning groove 2 is strictly coaxial with the back-side alignment through-hole 3 and is vertically connected.

[0029] Step S6, fabrication of a sunken microlens array: Select microlens chip 6, and form a microlens array with flat edges and a sunken center through photoresist thermal reflow and ICP etching.

[0030] In this embodiment, the substrate of the microlens chip 6 is a double-polished silicon wafer of the same specification (100). After photoresist spin coating, patterned exposure and development, a continuous and smooth microlens convex surface 7 is formed by photoresist thermal reflow process. Then, the curved surface morphology is transferred to the substrate of the microlens chip 6 by ICP inductively coupled plasma etching. At the same time, a ring bonding surface structure with a sunken center and flat edges is prepared to form a sunken microlens array. The array arrangement specifications correspond one-to-one with the inverted pyramid guide positioning groove 2.

[0031] Step S7, SiO2 mask deposition and secondary photolithography: SiO2 thin film is deposited on the substrate surface of microlens chip 6 and the lens alignment reference step 4 and limiting edge 5 are defined by photolithography.

[0032] In this embodiment, a SiO2 dielectric film is deposited on the entire surface of the microlens chip 6 wafer using PECVD process as a deep silicon etching hard mask. Secondary photolithography defines the processing pattern of the lens alignment reference step 4 and the two side limiting edges 5, and etching removes the SiO2 thin film in the pattern area to achieve windowing.

[0033] Step S8, Deep silicon etching to form microstructure: Etching to prepare lens alignment reference step 4 and limiting stop edge 5.

[0034] Step S9, Ultra-clean cleaning: The silicon substrate body 1 wafer and the microlens chip 6 wafer are cleaned using plasma ashing to remove residual photoresist, wet cleaning and dry plasma ultra-clean cleaning process to make the bonding interface atomically clean.

[0035] In this embodiment, a Bosch alternating etching and passivation cycle process is used for deep silicon etching. The verticality of the etched sidewall is controlled to be 89.5° to 90°, and the flatness of the lens alignment reference step 4 is 0.5 to 1 μm. The mounting reference step 4 and the symmetrically arranged limiting edge 5 are integrally processed to achieve bidirectional mechanical pre-limiting of the microlens chip 6 in the lateral and longitudinal directions.

[0036] Step S10, Precision alignment and silicon-silicon prebonding: Align the two wafers using machine vision and complete room temperature glue-free prebonding.

[0037] In this embodiment, a high-precision machine vision double-sided alignment system is used to control the alignment deviation to ≤2μm; the vacuum degree of the bonding cavity is ≤5×10⁻³Pa; and a uniform pre-bonding pressure of 0.8~1.2MPa is applied to complete the glue-free silicon pre-bonding at room temperature.

[0038] Step S11, High-temperature annealing and dicing: After high-temperature annealing to strengthen the bonding interface, the integrated sunken microlens array silicon-based fiber coupling base finished device is obtained after dicing.

[0039] In the embodiments, the high-temperature annealing conditions are constant temperature holding at 350-450℃ for 2-4 hours to allow silicon atoms at the bonding interface to fully diffuse and the lattice to fuse. After furnace cooling, the wafer is diced, shaped and cleaned to obtain the finished device of the integrated sunken microlens array silicon-based fiber coupling base. The microlens autonomously reserve a 1-10μm optical path gap by relying on its own sunken structure.

[0040] This invention employs a SiN / SiO2 dual-layer dielectric stepwise mask protection, strictly adhering to the process logic of wet etching followed by dry etching, effectively protecting the ultra-smooth crystal surface of the inverted pyramid groove {111}. It utilizes a self-contained flat-bottom through-hole inverted pyramid structure to achieve integrated fiber introduction, transition, and precise positioning. The recessed microlens relies on its own structure to reserve optical path gaps, eliminating the need for an additional etching cavity on the base. The entire process eliminates dispensing assembly, employing silicon-silicon bonding to improve the device's high and low temperature reliability and batch consistency. The process has strong repeatability, is suitable for wafer-level mass production, and can be applied to high-speed optical communication, fiber optic sensing, and laser-coupled precision optical packaging.

[0041] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A wafer-level bonding fabrication method for a sunken microlens array and a silicon-based substrate, characterized in that, include: Step S1, Substrate pretreatment: Select a (100) crystal orientation single crystal silicon substrate, remove surface contaminants and oxide layer, and obtain a clean silicon substrate body (1). Step S2, depositing SiN mask layer: prepare SiN thin film on the surface of silicon substrate body (1) as wet etching mask; Step S3, Photolithography and SiN Windowing: Define the inverted pyramid import positioning groove (2) pattern by photolithography and etch the SiN thin film; Step S4, KOH wet etching: Prepare a flat-bottomed through-type inverted pyramid inlet positioning groove (2); Step S5, back side alignment and deep silicon etching: a back side alignment through hole (3) is made on the back side of the silicon substrate body (1), and the inverted pyramid guide positioning groove (2) is coaxially connected with the back side alignment through hole (3). Step S6, prepare a sunken microlens array: select a microlens chip (6), and form a microlens array with flat edges and sunken center by photoresist thermal reflow and ICP etching; In step S6, the substrate of the microlens chip (6) is a double-polished silicon wafer with the same specification (100) crystal orientation. After photoresist spin coating, patterned exposure and development, a continuous and smooth microlens convex surface (7) is formed by photoresist hot reflow process. Then, the curved surface morphology is transferred to the substrate of the microlens chip (6) by ICP inductively coupled plasma etching. At the same time, a ring bonding surface structure with a sunken center and flat edges is prepared to form a sunken microlens array. The array arrangement specifications correspond one-to-one with the inverted pyramid guide positioning groove (2). Step S7, SiO2 mask deposition and secondary photolithography: SiO2 thin film is deposited on the substrate surface of the microlens chip (6) and the lens alignment reference step (4) and limiting edge (5) pattern are defined by photolithography; In step S7, a SiO2 dielectric film is deposited on the entire surface of the microlens chip (6) wafer as a deep silicon etching hard mask using the PECVD process; Secondary photolithography defines the processing pattern of the lens alignment reference step (4) and the two side limiting edges (5), and etching removes the SiO2 thin film in the pattern area to realize window opening; Step S8, Deep silicon etching to form microstructure: Etching to prepare lens alignment reference step (4) and limiting stop edge (5); Step S9, Ultra-clean cleaning: The silicon substrate body (1) wafer and the microlens chip (6) wafer are cleaned by plasma ashing to remove residual photoresist, wet cleaning and dry plasma ultra-clean cleaning process, so that the bonding interface is atomically clean. Step S10, Precision alignment and silicon-silicon prebonding: Align the two wafers using machine vision and complete room temperature glue-free prebonding; Step S11, High-temperature annealing and dicing: After high-temperature annealing to strengthen the bonding interface, the integrated sunken microlens array silicon-based fiber coupling base finished device is obtained after dicing.

2. The wafer-level bonding fabrication method for a sunken microlens array and a silicon substrate according to claim 1, characterized in that, In step S1, the single crystal silicon substrate is a 4-inch (100) crystal orientation P-type double polished single crystal silicon wafer. The SC1 and SC2 standard wafer cleaning processes are adopted. After cleaning, it is dried with high-purity nitrogen and placed in a constant temperature oven at 120°C for 15 minutes to remove organic residues, metal ion impurities, natural oxide layer and micro-nano particle contaminants on the surface, and obtain a silicon substrate body (1) with surface cleanliness that meets the requirements of thin film deposition, photolithography and bonding processes.

3. The wafer-level bonding fabrication method for a sunken microlens array and a silicon substrate according to claim 1, characterized in that, In step S2, SiN thin films are deposited using LPCVD technology. The SiN thin films have a dense structure and serve as a special mask protective layer for subsequent KOH high-temperature wet etching, shielding the non-processed areas of single-crystal silicon from being etched by the etching solution.

4. The wafer-level bonding fabrication method for a sunken microlens array and a silicon substrate according to claim 1, characterized in that, In step S3, the photolithography process includes spin coating of photoresist on the SiN thin film surface, pre-baking, exposure, development, and defining a square window array pattern corresponding to the inverted pyramid inlet positioning groove (2); A dry etching process is used to selectively remove the SiN film in the window area, exposing the underlying single-crystal silicon substrate, while the remaining areas retain the complete protection of the SiN mask.

5. The wafer-level bonding fabrication method for a sunken microlens array and a silicon substrate according to claim 1, characterized in that, In step S4, the KOH etching solution has a mass concentration of 30%–40%, an etching temperature of 70–85℃, and an etching time of 15–40 min. Utilizing the anisotropic corrosion characteristics of (100) crystal-oriented single-crystal silicon, an inverted pyramid-shaped cavity with a wide top and narrow bottom is spontaneously formed by four {111} smooth crystal planes. The bottom of the groove retains a flat bottom and does not form a sharp bottom convergent structure. A flat bottom through-type inverted pyramid inlet positioning groove (2) is prepared. The roughness of the sidewall of the groove is controlled at Ra≤5nm.

6. The wafer-level bonding fabrication method for a sunken microlens array and a silicon substrate according to claim 1, characterized in that, In step S5, alignment marks and through-hole patterns are made using wafer back-side alignment photolithography. The back-side alignment through-hole (3) is formed by vertical etching using Bosch deep silicon etching process. The bottom flat bottom of the inverted pyramid guide positioning groove (2) is strictly coaxial with the back-side alignment through-hole (3) and is vertically connected.

7. The wafer-level bonding fabrication method for a sunken microlens array and a silicon substrate according to claim 1, characterized in that, In step S8, Bosch alternating etching and passivation cycle process is used for deep silicon etching. The verticality of the etched sidewall is controlled to be 89.5° to 90°. The flatness of the lens alignment reference step (4) is 0.5 to 1 μm. The mounting reference step (4) and the symmetrically arranged limiting edge (5) are integrally processed to realize the horizontal and vertical bidirectional mechanical pre-limiting of the microlens chip (6).

8. The wafer-level bonding fabrication method for a sunken microlens array and a silicon substrate according to claim 1, characterized in that, In step S10, a high-precision machine vision double-sided alignment system is used to control the alignment deviation to ≤2μm; the vacuum degree of the bonding cavity is ≤5×10 -3 Pa, apply a uniform pre-bonding pressure of 0.8 to 1.2 MPa to complete the glue-free silicon pre-bonding at room temperature; In step S11, the high-temperature annealing conditions are 350-450℃ and held at a constant temperature for 2-4 hours to allow silicon atoms at the bonding interface to fully diffuse and the lattice to fuse. After furnace cooling, the wafer is diced, shaped and cleaned to obtain the finished device of the integrated sunken microlens array silicon-based fiber coupling base. The microlens autonomously reserve a 1-10μm optical path gap by relying on its own sunken structure.

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