Multi-channel acquisition time synchronization method for rail transit

Abstract

This disclosure provides a multi-channel acquisition time synchronization method for rail transit, comprising: responding to the validity of one of the external reference sources, performing phase and frequency training on the motherboard local clock according to the external reference source, calibrating the motherboard absolute time, and generating a time distribution signal and a synchronization enable signal for the daughterboard; responding to the failure of the external reference source, using a local clock compensation model to maintain the motherboard local clock and the motherboard absolute time, and generating a time distribution signal and a synchronization enable signal; responding to the motherboard being in place and the link between the motherboard and the daughterboard being in normal condition, synchronizing the daughterboard local clock and absolute time according to the time distribution signal sent by the motherboard; responding to the motherboard being out of place or the link between the motherboard and the daughterboard being in abnormal condition, independently operating the daughterboard local clock according to the previous time distribution signal received by the daughterboard; using a synchronization quality flag to mark data degradation; and using the motherboard local clock and the daughterboard local clock for multi-channel synchronous sampling.

Description

Technical Field

[0001] This disclosure relates to the field of multi-channel synchronous sampling technology, and more specifically to a multi-channel acquisition time synchronization method for rail transit. Background Technology

[0002] Multi-channel data acquisition systems for rail transit typically require the simultaneous acquisition of various signals, including train operating status, track environment, traction power supply equipment, and onboard or ground monitoring equipment. For data such as vibration, current, voltage, temperature, state variables, and event variables, the consistency of sampling time between different channels directly affects the accuracy of fault location, transient process reconstruction, event correlation analysis, and operational status assessment.

[0003] Existing time synchronization solutions typically use the motherboard as a single time distribution node, providing a time reference to the daughterboard via a single PPS, a single IRIG-B code, or network time synchronization. While this type of solution is simple in structure, it has the following shortcomings in field applications in rail transit: poor single-link interference immunity; lack of separate processing for absolute time and sampled phase; lack of a timekeeping model on the motherboard, leading to crystal oscillator drift accumulation after external interruptions; and excessive dependence of the daughterboard on the motherboard. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a multi-link, multi-source redundancy, and hierarchical synchronization method for multi-channel acquisition time synchronization in rail transit.

[0005] This disclosure provides a multi-channel acquisition time synchronization method for rail transit, comprising: responding to the validity of one of the external reference sources, performing phase and frequency discipline on the motherboard local clock according to the external reference source, calibrating the motherboard absolute time, and generating a time distribution signal and a synchronization enable signal for the sub-board, wherein the external reference sources include at least an external standard source and a network time synchronization source, the external standard source includes at least an external PPS standard source and an external IRIG-B standard source, and the time distribution signal includes at least a PPS second pulse and an IRIG-B time code; the synchronization enable signal is used to enable synchronization on the sub-board; responding to the failure of all external reference sources, using a local clock compensation model to maintain the motherboard local clock and motherboard absolute time, and generating a time distribution signal and a synchronization enable signal for the sub-board. The board's time distribution signal and synchronization enable signal are generated based on the disciplined data accumulated during the effective period of the external reference source. In response to the motherboard being in place and the link between the motherboard and the daughterboard being normal, the daughterboard's local clock and absolute time are synchronized according to the time distribution signal sent by the motherboard. In response to the motherboard being out of place or the link between the motherboard and the daughterboard being abnormal, the daughterboard's local clock operates independently according to the previous time distribution signal received by the daughterboard. Synchronization quality flags are used to mark data degradation. Multi-channel synchronous sampling is achieved using the motherboard's local clock and the daughterboard's local clock. The motherboard and daughterboard are connected via a three-wire hardware synchronization bus, which includes at least a PPS second pulse link, an IRIG-B time code link, and a synchronization enable link.

[0006] According to embodiments of this disclosure, phase and frequency discipline is performed on the local clock of the motherboard based on an external reference source to calibrate the absolute time of the motherboard. This includes: selecting a current reference source from valid external reference sources according to a preset priority, wherein the preset priority from high to low is an external standard source and a network time synchronization source; using the current reference source, obtaining discipline data to correct the phase and frequency of the local clock of the motherboard and the absolute time of the motherboard, wherein the discipline data includes at least one of an absolute time code, a phase difference, and a frequency deviation.

[0007] According to embodiments of this disclosure, when the current reference source is an external standard source, the current reference source is used to obtain compliant data, correct the phase and frequency of the motherboard local clock and the absolute time of the motherboard, including: capturing the second pulse edge of the external PPS standard source, calculating the phase difference between the second pulse edge and the local second pulse edge of the motherboard local clock; calculating the frequency deviation of the motherboard local clock based on multiple consecutive phase differences; and decoding the IRIG-B time code of the external IRIG-B standard source to correct the absolute time of the motherboard.

[0008] According to embodiments of this disclosure, when the current reference source is a network time source, the current reference source is used to obtain compliant data and correct the phase and frequency of the motherboard's local clock and the absolute time of the motherboard, including: obtaining network reference time through the network time source, calculating a first time deviation between the absolute time of the motherboard and the network reference time; and adjusting the absolute time of the motherboard using a smoothing correction method in response to the first time deviation exceeding a first preset threshold.

[0009] According to embodiments of this disclosure, a method for constructing a local clock compensation model includes: recording discipline data and temperature data at a preset period during the effective period of an external reference source to obtain a historical phase difference sequence, a historical frequency deviation sequence, and a historical temperature sequence; fitting a temperature drift formula for the frequency deviation with respect to temperature based on the historical temperature sequence and the historical frequency deviation sequence; and maintaining the motherboard's local clock using the local clock compensation model, including: obtaining the current frequency deviation based on the current temperature and the temperature drift formula; and integrating the last historical phase difference in the historical phase difference sequence with the current frequency deviation to obtain the current phase difference.

[0010] According to embodiments of this disclosure, the synchronization quality flag includes at least one of the following: current time source type, motherboard status, daughterboard status, PPS second pulse link status, IRIG-B time code link status, synchronization enable status, external standard source failure time, and resynchronization event flag. The motherboard status includes at least external reference source valid status and local compensation status, and the daughterboard status includes at least synchronous motherboard status and independent working status.

[0011] According to embodiments of this disclosure, synchronizing the daughterboard local clock and absolute time based on the time distribution signal sent by the motherboard includes: in response to the PPS second pulse and IRIG-B time code both being valid, calibrating the daughterboard local clock and the daughterboard absolute time using the PPS second pulse as the phase reference and the IRIG-B time code as the absolute time reference.

[0012] According to embodiments of this disclosure, the subboard local clock is operated independently based on the previous time distribution signal received by the subboard, including: in response to a short-term failure of either the PPS second pulse or the IRIG-B time code, calibrating the subboard local clock or absolute time using the PPS second pulse or the IRIG-B time code in the previous time distribution signal of the subboard; and in response to the motherboard being absent or at least one of the time distribution signals failing consecutively, generating a timestamp composed of the PPS second pulse and the IRIG-B time code based on the subboard local clock.

[0013] According to embodiments of this disclosure, a synchronization quality flag is used to mark data degradation. The process further includes: in response to detecting that the link between the motherboard and the daughterboard has returned to normal and a valid time distribution signal is received, resynchronizing the daughterboard's local clock and absolute time based on the time distribution signal sent by the motherboard. Specifically, this includes: comparing a second time deviation between the absolute time of the daughterboard's local clock and the absolute time of the IRIG-B time code; in response to the second time deviation being less than a second preset threshold, gradually synchronizing the daughterboard's local clock and the motherboard's local clock using a speed-limiting pull-off method; and in response to the second time deviation being greater than the second preset threshold, waiting for the next sampling frame boundary or a preset safety time based on the daughterboard's PPS second pulse, resynchronizing the daughterboard's local clock and the motherboard's local clock, and writing a resynchronization event flag.

[0014] According to embodiments of this disclosure, multi-channel synchronous sampling is achieved using the motherboard local clock and the daughterboard local clock, including: the daughterboard uses the same PPS second pulse edge as the zero point of the sampling counter or the starting point of the sampling frame to drive the analog-to-digital converter to synchronously sample and obtain the acquired data; wherein, the acquired data carries timestamp information, and the timestamp information includes at least the board number, channel number, absolute time second field, sub-second count field and sampling sequence number.

[0015] The second aspect of this disclosure provides a multi-channel acquisition time synchronization device for rail transit, capable of implementing the aforementioned multi-channel acquisition time synchronization method for rail transit, comprising: a master clock signal generation module, which, in response to the validity of one of the external reference sources, performs phase and frequency discipline on the motherboard local clock according to the external reference source, calibrates the motherboard absolute time, and generates a time distribution signal and a synchronization enable signal for the daughterboard; wherein the external reference source includes at least an external standard source and a network time synchronization source, the external standard source includes at least an external PPS standard source and an external IRIG-B standard source, and the time distribution signal includes at least a PPS second pulse and an IRIG-B time code; the synchronization enable signal is used to enable synchronization on the daughterboard; in response to the failure of all external reference sources, a local clock compensation model is used to maintain the motherboard local clock. The local clock and motherboard absolute time generate time distribution signals and synchronization enable signals for the daughter board. The local clock compensation model is generated based on the disciplined data accumulated during the effective time of the external reference source. The daughter board data acquisition module synchronizes the daughter board local clock and absolute time according to the time distribution signal sent by the motherboard when the motherboard is in place and the link between the motherboard and the daughter board is normal. When the motherboard is not in place or the link between the motherboard and the daughter board is abnormal, the daughter board local clock operates independently according to the previous time distribution signal received by the daughter board. Data degradation is marked using synchronization quality markers. Multi-channel synchronous sampling is achieved using the motherboard local clock and the daughter board local clock. The motherboard and daughter board are connected through a three-wire hardware synchronization bus, which includes at least a PPS second pulse link, an IRIG-B time code link, and a synchronization enable link.

[0016] A third aspect of this disclosure provides an electronic device comprising: one or more processors; and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors perform the aforementioned multi-channel acquisition time synchronization method for rail transit.

[0017] According to the multi-channel acquisition time synchronization method for rail transit provided in this disclosure, the sampling signal is generated automatically by the motherboard's local clock compensation model and the daughterboard using PPS second pulses. Since a clock synchronization method is provided for external reference source failure and motherboard failure, it at least partially solves the technical problems of weak timekeeping capability after external reference source interruption and strong daughterboard dependence on the motherboard. It achieves the technical effect of maintaining absolute time traceability, sampling phase consistency, and continuous system operation capability under conditions such as strong electromagnetic interference, external time source interruption, motherboard abnormality, or synchronization link failure. Attached Figure Description

[0018] Figure 1A flowchart illustrating a multi-channel acquisition time synchronization method for rail transit according to an embodiment of the present disclosure is shown schematically.

[0019] Figure 2 A system block diagram according to an embodiment of the present disclosure is illustrated schematically;

[0020] Figure 3 A schematic flowchart illustrating motherboard system time synchronization and timekeeping according to an embodiment of the present disclosure is shown.

[0021] Figure 4 A schematic diagram illustrating the time synchronization flowchart of a daughterboard system according to an embodiment of the present disclosure is shown.

[0022] Figure 5 A schematic diagram illustrating the sampling synchronization time flow of a motherboard according to an embodiment of the present disclosure is shown.

[0023] Figure 6 A schematic diagram of a board ADC synchronous sampling process according to an embodiment of the present disclosure is shown. Detailed Implementation

[0024] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0026] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0027] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0028] It should be noted that this disclosure also relates to the field of rail transit data acquisition and distributed clock synchronization technology, and is applicable to synchronous acquisition systems that include a motherboard, at least one daughterboard, and multiple ADCs or event acquisition channels.

[0029] Existing time synchronization solutions typically treat the motherboard as a single time distribution node, providing a time reference to the daughterboard via a single PPS, a single IRIG-B code, or network time synchronization. Specifically, they have the following shortcomings:

[0030] (1) A single time synchronization link is often used between the motherboard and the daughterboard, or only PPS is used as the second boundary and only IRIG-B is used as the absolute time. When the link is affected by electromagnetic interference, poor connector contact or decoding abnormality, the daughterboard has difficulty in timely judging the fault type, and timestamp errors or sampling phase drift are likely to occur.

[0031] (2) Existing solutions often only focus on whether the system time is correct, without separating the absolute time reference from the sampling phase reference. When a time step occurs during network time synchronization or manual time calibration, it may cause invisible disturbances in the ADC sampling counter, data frame boundary, or multi-subboard synchronous triggering.

[0032] (3) The motherboard is highly dependent on external reference sources. When the BeiDou / GPS, external PPS or external IRIG-B standard sources are interrupted, if there is no timekeeping model based on historical discipline parameters, the drift of the local crystal oscillator on the motherboard will continue to accumulate, which will lead to a gradual increase in the sampling synchronization error and absolute time error of the daughterboard.

[0033] (4) The daughterboard usually relies entirely on the motherboard to provide the time reference. When the motherboard loses power, is not in place, has abnormal synchronization enable, or the PPS / IRIG-B link is interrupted, the daughterboard cannot distinguish between short-term link disturbances and long-term faults, and also lacks independent working and recovery switching mechanisms, resulting in insufficient data acquisition continuity and single-board testing capabilities.

[0034] (5) There is a lack of a unified sampling phase discipline and synchronization quality marking mechanism among multiple sub-boards. Even if each sub-board obtains the same absolute time, there may still be differences in the ADC start-up boundary, sampling sequence zero point and sub-second count of different sub-boards, making it difficult for subsequent software to determine the time reliability of each data segment.

[0035] Therefore, a multi-link, multi-source redundancy, hierarchical synchronization, and diagnostic time synchronization method is needed for rail transit sites. This method should enable the system to not only obtain a unified absolute time, but also maintain the sampling phase consistency of multi-subboard and multi-channel acquisition, and avoid timestamp mutations during anomaly occurrence and recovery.

[0036] Figure 1A flowchart illustrating a multi-channel data acquisition time synchronization method for rail transit according to an embodiment of the present disclosure is shown, such as... Figure 1 As shown, embodiments of this disclosure provide a multi-channel acquisition time synchronization method for rail transit, comprising: responding to the validity of one of the external reference sources, performing phase and frequency discipline on the motherboard local clock according to the external reference source, calibrating the motherboard absolute time, and generating a time distribution signal and a synchronization enable signal for the daughterboard, wherein the external reference source includes at least an external standard source and a network time synchronization source, the external standard source includes at least an external PPS standard source and an external IRIG-B standard source, and the time distribution signal includes at least a PPS second pulse and an IRIG-B time code; the synchronization enable signal is used to enable synchronization on the daughterboard; responding to the failure of all external reference sources, using a local clock compensation model to maintain the motherboard local clock and the motherboard absolute time, and generating a time distribution signal for the daughterboard. The local clock compensation model is generated based on the disciplined data accumulated when the external reference source is valid, along with the synchronization enable signal. In response to the motherboard being in place and the link between the motherboard and the daughterboard being normal, the daughterboard's local clock and absolute time are synchronized according to the time distribution signal sent by the motherboard. In response to the motherboard being out of place or the link between the motherboard and the daughterboard being abnormal, the daughterboard's local clock operates independently according to the previous time distribution signal received by the daughterboard. Data degradation is marked using a synchronization quality flag. Multi-channel synchronous sampling is achieved using the motherboard's local clock and the daughterboard's local clock. The motherboard and daughterboard are connected via a three-wire hardware synchronization bus to achieve absolute time transmission, sampling phase anchoring, and synchronization status control. The three-wire hardware synchronization bus includes at least a PPS second pulse link, an IRIG-B time code link, and a synchronization enable link.

[0037] Figure 2 A system block diagram according to an embodiment of the present disclosure is illustrated schematically, such as Figure 2As shown, the motherboard acts as the system time master node, supporting redundant inputs from external PPS (Pulse Per Second) standard sources, external IRIG-B (Inter-Range Instrumentation Group B-code) standard sources, and network time synchronization sources. The PPS second pulse link is simultaneously sent from the motherboard to all daughterboards to define a unified second boundary and serve as a phase anchor point for aligning the daughterboard's local counter, sampling counter, and ADC frame start point. Preferably, the effective edge of the PPS is a rising edge. When the daughterboard captures this edge, it latches the local high-frequency counter value and calculates the local second boundary phase error accordingly. The IRIG-B code link continuously sends a time code containing complete absolute time fields such as year, month, day, hour, minute, and second from the motherboard to all daughterboards. Preferably, the IRIG-B code uses DC-biased Manchester encoded IRIG-B (DC) code. The daughterboard binds the second field obtained from the IRIG-B decoding with the PPS boundary to form a timestamp of "absolute second field and sub-second count". The synchronization enable link is output uniformly by the motherboard and is used to control the synchronization status, sampling start status, or resynchronization status of the daughterboard. Synchronization enable can be a level-active signal or a sampling start signal that takes effect after a specified PPS second boundary or a specified delay. The daughterboard only enters the motherboard synchronization state and locks the motherboard for synchronization when the synchronization enable, PPS, and IRIG-B states meet preset consistency conditions.

[0038] The hardware synchronization link preferably adopts RS-485, LVDS, CML, or other differential transmission methods, and can be combined with star distribution, equal-length cabling, termination matching, isolation protection, and link delay compensation to improve synchronization reliability in the strong electromagnetic interference environment of rail transit sites. PPS, IRIG-B, and synchronization enable constitute a hardware three-wire synchronization bus, which can provide absolute time, sampling phase, and unified control, avoiding system-wide synchronization loss due to the failure of a single link.

[0039] Through the embodiments of this disclosure, both the motherboard and the daughterboard have independent clock maintenance capabilities. Under any link state, ADC sampling is not interrupted, only the time reliability is degraded. Under conditions such as strong electromagnetic interference, external time source interruption, motherboard abnormality or synchronization link failure, the absolute time traceability of the collected data, sampling phase consistency and system continuous working capability can be maintained.

[0040] It should be noted that the system time is divided into two levels: "absolute time reference" and "sampling phase reference". The absolute time reference is used to express the year, month, day, hour, minute, second, and event occurrence time, while the sampling phase reference is used to express the PPS second boundary, the sampling frame start point, the ADC sampling sequence number, and the multi-daughterboard synchronization boundary. Through this two-layer time model, even if the absolute time needs to be smoothed by NTP or other network sources, it will not cause a step disturbance to the running multi-daughterboard synchronization sampling.

[0041] Based on the above embodiments, the motherboard local clock is phase and frequency tamped according to an external reference source to calibrate the motherboard absolute time. This includes: selecting the current reference source from the valid external reference sources according to a preset priority, wherein the preset priority from high to low is the external standard source and the network time synchronization source; using the current reference source, obtaining tamped data to correct the phase and frequency of the motherboard local clock and the absolute time of the motherboard, wherein the tamped data includes at least one of the absolute time code, phase difference, and frequency deviation.

[0042] In this embodiment, the external standard source can come from a BeiDou / GPS dual-mode time synchronization module, a rail transit-specific time server, or other devices capable of outputting standard PPS, IRIG-B, or equivalent time codes; the network time synchronization source can be an NTP server, and can be expanded to PTP or a dedicated network time protocol as needed for the project.

[0043] Furthermore, the motherboard does not use "whether a signal is received" as the sole basis for time synchronization, but instead evaluates the reliability of each time source. Priority is determined based on the reliability evaluation, and the evaluation parameters include, but are not limited to: the existence of PPS, PPS period error, PPS edge jitter, whether IRIG-B decoding is successful, whether the IRIG-B time field is continuous, network time synchronization round-trip latency, network time synchronization deviation, local timekeeping duration, mutual deviation between time sources, and whether abnormal jumps occur in the time field. Based on the evaluation of the PPS standard source, IRIG-B standard source, and network time source, the motherboard establishes a time source reliability status and selects the current time base according to priority. Optionally, if the reliability of the PPS standard source and the IRIG-B standard source meets a preset threshold, the time base is updated with reference to the PPS standard source and the IRIG-B standard source; if the reliability of the PPS standard source and the network time source both meet a preset threshold, but the reliability of the IRIG-B standard source does not meet a preset threshold, the time base is updated with reference to the PPS standard source and the network time source; if the reliability of the PPS standard source does not meet a preset threshold, but the reliability of the IRIG-B standard source meets a preset threshold, the time base is updated with reference to the IRIG-B standard source; if the reliability of both the PPS standard source and the IRIG-B standard source does not meet a preset threshold, but the reliability of the network time source meets a preset threshold, the time base is updated with reference to the network time source; if the reliability of all three time bases does not meet a preset threshold, the master clock is maintained as the local clock.

[0044] Preferably, when both the external PPS and external IRIG-B are active, the motherboard enters an external lockout state; when the external standard source fails but the network time synchronization source is active, the motherboard enters a network calibration state; when both the external standard source and the network time synchronization source are unavailable, the motherboard enters a local compensation state; when the local compensation timekeeping duration exceeds a preset threshold or the time deviation cannot be assessed, the motherboard marks the data as degraded output. The external lockout state and network calibration state can be summarized by the active status of the external reference source.

[0045] In the embodiments of this disclosure, the motherboard uses an OCXO, TCXO, or other stable crystal oscillator as its local clock source. A high-precision external standard source is preferred. When the external reference source is valid, the motherboard uses the PPS edge to capture the phase error of the local second count boundary and combines it with the absolute time field obtained from IRIG-B decoding to perform phase and frequency training on the motherboard's local clock, calibrating the motherboard's absolute time. When the standard source fails, it seamlessly switches to a network time source, improving system stability.

[0046] Figure 3 This schematically illustrates a flowchart of motherboard system time synchronization and timekeeping according to an embodiment of the present disclosure. Figure 5 A schematic diagram illustrating the sampling synchronization time flow of a motherboard according to an embodiment of the present disclosure is shown, such as... Figure 3 and Figure 5 As shown, the motherboard's local clock corrects the local absolute time using an external reference IRIG-B or NTP time, and calibrates the phase reference using an external PPS, thereby providing PPS synchronization signals and IRIG-B signals to the daughterboard.

[0047] Based on the above embodiments, when the current reference source is an external standard source, the compliant data is obtained using the current reference source to correct the phase and frequency of the motherboard's local clock and the absolute time of the motherboard, including: capturing the second pulse edge of the external PPS standard source and calculating the phase difference between the second pulse edge and the local second pulse edge of the motherboard's local clock; calculating the frequency deviation of the motherboard's local clock based on multiple consecutive phase differences; and decoding the IRIG-B time code of the external IRIG-B standard source to correct the absolute time of the motherboard.

[0048] In a preferred embodiment, the motherboard measures the phase error e(k) between the reference second boundary and the local second boundary at the k-th PPS edge, estimates the local clock frequency deviation and drift trend based on multiple consecutive phase errors, and corrects the local clock by at least one of loop filtering, frequency control word correction, counter compensation, temperature compensation, or lookup table compensation.

[0049] Through the embodiments of this disclosure, the phase comparison is performed using the second pulse characteristics of PPS, eliminating slow clock drift; and the absolute time is assigned using the complete time information of IRIG-B. The system can not only obtain a unified absolute time, but also maintain the sampling phase consistency of multi-subboard and multi-channel acquisition.

[0050] Based on the above embodiments, when the current reference source is a network time source, the current reference source is used to obtain compliant data and correct the phase and frequency of the motherboard's local clock and the absolute time of the motherboard, including: obtaining the network reference time through the network time source and calculating the first time deviation between the absolute time of the motherboard and the network reference time; in response to the first time deviation exceeding a first preset threshold, the absolute time of the motherboard is adjusted using a smoothing correction method.

[0051] In this embodiment, when the NTP network time synchronization detects an absolute time deviation, the system only performs a rate-limited smoothing correction on the absolute time reference, while maintaining the continuity and stability of the sampling phase reference. This effectively blocks clock steps that may be caused by network time synchronization, ensuring that even during absolute time correction, the ADC sampling triggering, data frame boundaries, and sampling counters of multiple daughterboards will not jump or be disturbed. Thus, under complex operating conditions such as strong interference and external interruptions, the phase consistency of multi-channel acquired data and the accuracy of coherence analysis are always guaranteed.

[0052] In the embodiments of this disclosure, when an external standard source fails and an NTP (Network Time Protocol) time source is available, the motherboard continuously compares the deviation between the local absolute time and the network time source time. When the deviation exceeds a preset threshold, the motherboard obtains a correction amount through NTP and uses a rate-limited smoothing correction method to correct the absolute time mapping relationship without making a step modification to the sampling phase reference. Thus, the motherboard can both gradually converge the absolute time to the network time and maintain the continuity of PPS output, sampling counter, and daughterboard ADC synchronous triggering.

[0053] Based on the above embodiments, the method for constructing a local clock compensation model includes: recording discipline data and temperature data at a preset period during the effective period of the external reference source to obtain a historical phase difference sequence, a historical frequency deviation sequence, and a historical temperature sequence; fitting a temperature drift formula for the frequency deviation with respect to temperature based on the historical temperature sequence and the historical frequency deviation sequence; and maintaining the motherboard local clock using the local clock compensation model, including: obtaining the current frequency deviation based on the current temperature and the temperature drift formula; and integrating the last historical phase difference in the historical phase difference sequence with the current frequency deviation to obtain the current phase difference.

[0054] Through the embodiments of this disclosure, when an external standard source is lost, the motherboard does not immediately stop synchronous output, but instead enters a local compensation timekeeping mode. The timekeeping mode uses frequency deviation, drift rate, temperature-related parameters, and historical phase errors accumulated during the external locking phase to establish a compensation model, which corrects the local crystal oscillator in real time, enabling the motherboard to continue generating continuous PPS second pulses and IRIG-B time codes, thus solving the technical problem of weak timekeeping capability after an external reference source interruption.

[0055] Based on the above embodiments, the synchronization quality flag includes at least one of the following: current time source type, motherboard status, daughterboard status, PPS second pulse link status, IRIG-B time code link status, synchronization enable status, external standard source failure time and resynchronization event flag. The motherboard status includes at least the external reference source valid status and local compensation status, and the daughterboard status includes at least the synchronous motherboard status and independent working status.

[0056] Furthermore, the independent working state also includes the short-term link failure state and the completely independent working state. In the case of a short-term link failure, the sampling pulse is still triggered by the synchronization enable signal sent by the motherboard. In the completely independent working state, the sampling pulse is triggered by the PPS second pulse of the daughterboard itself.

[0057] Through the embodiments of this disclosure, by embedding multi-dimensional quality markers in data frames, the background analysis software can not rely on external logs, but not only know the time when the data occurred, but also judge the reliability of each frame of data. When measurement anomalies occur, the markers can be used to quickly locate whether it is a sensor failure, a synchronization link failure, or a clock source failure, thus reducing the difficulty of operation and maintenance.

[0058] Figure 4 A schematic diagram illustrating the time synchronization flowchart of a daughterboard system according to an embodiment of the present disclosure is shown. Figure 6 A schematic diagram illustrating the board ADC synchronous sampling flowchart according to an embodiment of the present disclosure is shown, such as... Figure 4 and Figure 6 As shown, when the motherboard's time distribution signal is received, the daughterboard updates its own absolute time and phase according to the motherboard. When the link is abnormal or the motherboard is not in place, it relies on itself to maintain a local clock and generate sampling pulses.

[0059] Based on the above embodiments, according to the time distribution signal sent by the motherboard, the local clock and absolute time of the sub-board are synchronized, including: in response to the PPS second pulse and the IRIG-B time code being valid, the local clock and absolute time of the sub-board are calibrated with the PPS second pulse as the phase reference and the IRIG-B time code as the absolute time reference.

[0060] In the embodiments of this disclosure, the daughterboard uses the motherboard's PPS as the second boundary and sampling phase anchor point, and the IRIG-B code as the absolute time source. The daughterboard adjusts its own sampling clock through local PLL, NCO, frequency divider, high-frequency counter, or sampling clock compensation logic to ensure that the local second boundary, sampling frame start point, and sampling sequence number are consistent with the motherboard reference.

[0061] Based on the above embodiments, the sub-board local clock is operated independently according to the previous time distribution signal received by the sub-board, including: in response to a short-term failure of either the PPS second pulse or the IRIG-B time code, the sub-board local clock or absolute time is calibrated using the PPS second pulse or the IRIG-B time code in the previous time distribution signal of the sub-board; in response to the motherboard being absent or at least one of the time distribution signals failing consecutively, a timestamp composed of the PPS second pulse and the IRIG-B time code is generated based on the sub-board local clock.

[0062] Through the embodiments of this disclosure, in the short-term link hold state, if either PPS or IRIG-B is briefly lost, but the other link remains valid and the abnormal duration does not exceed a preset threshold, the daughterboard uses the local frequency compensation parameters obtained in the most recent motherboard lock state to maintain sampling phase and time continuity, and marks the link abnormality or time quality degradation in the acquired data. In the fully independent working state, when the daughterboard detects that the motherboard is unresponsive, the motherboard is powered off, the synchronization enable is abnormal, or PPS and IRIG-B fail consecutively, the daughterboard uses its own previously calibrated local clock as a time reference to independently generate local system time, local PPS, and sampling trigger signals to continue multi-channel acquisition. This state is applicable to fault hold when the motherboard is abnormal, as well as single-board testing and maintenance scenarios, solving the problem of the daughterboard's strong dependence on the motherboard.

[0063] Based on the above embodiments, a synchronization quality flag is used to mark data degradation. The process then includes: in response to the detection that the link between the motherboard and the daughterboard has returned to normal and a valid time distribution signal has been received, the daughterboard local clock and absolute time are resynchronized according to the time distribution signal sent by the motherboard. Specifically, this includes: comparing the absolute time of the daughterboard local clock with the absolute time of the IRIG-B time code to determine a second time deviation; in response to the second time deviation being less than a second preset threshold, gradually synchronizing the daughterboard local clock and the motherboard local clock using a speed-limiting pull-off method; and in response to the second time deviation being greater than the second preset threshold, waiting for the next sampling frame boundary or a preset safety time based on the daughterboard's PPS second pulse, resynchronizing the daughterboard local clock and the motherboard local clock, and writing a resynchronization event flag.

[0064] In the embodiments of this disclosure, when the daughterboard detects that the motherboard link has been restored during the resynchronization process, it does not directly overwrite the local time with a step jump. Instead, it compares the time difference, phase difference, and sampling frame boundary between the local time and the motherboard time. When the difference is less than a threshold, the daughterboard gradually reverts to the motherboard time using a speed-limiting biasing method. When the difference is greater than the threshold, the daughterboard waits for the sampling frame boundary or a preset safety time to reload the motherboard time and writes a resynchronization event flag. This prevents step jumps when the difference is small and prevents sampling data breakage when the difference is large.

[0065] Based on the above embodiments, multi-channel synchronous sampling is achieved using the motherboard local clock and the daughterboard local clock. This includes: the daughterboard uses the same PPS second pulse edge as the zero point of the sampling counter or the starting point of the sampling frame to drive the analog-to-digital converter to synchronously sample and obtain the acquired data; wherein the acquired data carries timestamp information, which includes at least the board number, channel number, absolute time (seconds) field, sub-second count field, and sampling sequence number. The absolute time (seconds) field is derived from IRIG-B or the motherboard's timekeeping, the sub-second count field is provided by the daughterboard's local high-frequency counter, and the sampling sequence number field indicates the sample number starting from the synchronous sampling start point.

[0066] In this embodiment, when the motherboard is in place, synchronous sampling of multiple daughter boards is triggered jointly by the motherboard's PPS and synchronization enable signals. The motherboard can choose to output synchronization enable at a specified PPS second boundary, or at a fixed delay after the PPS second boundary. When the motherboard is not in place, the daughter boards generate sampling pulses based on their own clocks. Each daughter board uses the same PPS second boundary as the zero point of its sampling counter or the start point of its sampling frame to drive its respective ADC into synchronous sampling, thereby ensuring that the sampling data from different daughter boards have a consistent sampling time reference.

[0067] Through the embodiments of this disclosure, even when the motherboard is not in place, the daughterboard can still generate sampling pulses based on its own PPS second pulse edge drive, ensuring the continuity of sampling data.

[0068] It should be noted that, without departing from the core idea of ​​this invention, the external standard time source can be replaced with other time synchronization devices capable of outputting standard PPS or absolute time codes; the network time synchronization source can be NTP, PTP, or a dedicated rail transit time server; the differential interface form of the hardware synchronization bus can be selected from RS-485, LVDS, CML, or other electrical standards according to the board distance, backplane structure, and anti-interference requirements; the local clock can be OCXO, TCXO, crystal oscillator with temperature compensation model, or other equivalent timekeeping clock sources.

[0069] The number of daughter boards can be one or more, and the data acquisition target can be ADC analog signal acquisition, or it can be expanded to digital event acquisition, status signal acquisition, or other acquisition modules that require a unified timestamp. All the above substitutions are equivalent implementations of this disclosure.

[0070] Example 1, Hardware Link Configuration:

[0071] The motherboard adopts an FPGA and CPU architecture. The FPGA is responsible for external PPS capture, IRIG-B decoding, PPS generation, IRIG-B encoding, synchronization enable control, motherboard local counter calibration, and state machine execution; the CPU is responsible for network time synchronization client, running parameter configuration, status log recording, and communication with the host computer.

[0072] The daughterboard employs an FPGA and multi-channel ADC synchronous acquisition architecture. The daughterboard FPGA is responsible for PPS capture, IRIG-B decoding, daughterboard local clock discipline, sampling counter maintenance, ADC synchronous sampling control, and timestamp generation. The multi-channel ADC operates under the same sampling trigger reference and combines the sampled data with the board number, channel number, timestamp, and synchronization quality flag to form a data frame.

[0073] Differential transmission interfaces are preferred for PPS, IRIG-B, and synchronization enable between the motherboard and daughterboards. IRIG-B can use an RS-485 differential interface, while PPS and synchronization enable can use LVDS or RS-485 differential interfaces. Multiple daughterboards can be connected in a star or bus configuration; when using a bus configuration, impedance matching at the end is preferred.

[0074] Example 2, Clock Discipline and Timekeeping Parameters:

[0075] The external standard source can be a BeiDou / GPS dual-mode timing module, outputting 1PPS pulses and IRIG-B (DC) code. The motherboard's local timekeeping clock can be an OCXO or TCXO. When the external reference source is normal, the motherboard performs phase measurement and frequency compensation with a 1-second base period; when the external reference source is lost, the motherboard enters timekeeping mode and continues to generate a time reference based on the compensation parameters saved during the external locking phase.

[0076] In a preferred embodiment, the motherboard sets four time quality levels: external lock, timekeeping, network correction, and degradation. When the motherboard enters timekeeping mode, the longer the timekeeping duration, the lower the time quality level. When a network time source is available and the deviation exceeds a preset threshold, the motherboard corrects the absolute time in a smooth manner and records the correction process in the time quality field.

[0077] In timed mode, the motherboard continues to generate PPS and IRIG-B. PPS is used to maintain phase consistency of the daughterboard sampling, and IRIG-B is used to maintain consistency of the absolute time field of the daughterboards. Even if the external reference source is temporarily unavailable, multiple daughterboards can still maintain sampling synchronization based on the same output of the motherboard.

[0078] Example 3: Switching logic between synchronous and independent operation of the daughterboard:

[0079] The sub-board checks the validity of PPS and IRIG-B every 1 second or at a configurable period. If no valid PPS is detected or several consecutive frames of IRIG-B decoding fail, the sub-board enters the link anomaly judgment process. If the anomaly duration is short, the sub-board uses the local frequency compensation parameters obtained in the most recent motherboard locked state to maintain the sampling phase; if the anomaly duration exceeds the threshold, the sub-board enters independent working state.

[0080] In independent operating mode, the daughterboard's local clock generates local system time and local PPS, and continues to drive ADC sampling. This mode is particularly suitable for scenarios such as single-board testing, motherboard maintenance, link fault troubleshooting, or motherboard power failure. Data generated by the daughterboard in independent operating mode is marked as a local time source to avoid confusion with data in the motherboard locked state during subsequent analysis.

[0081] After the motherboard recovers, the daughterboard first receives multiple consecutive valid PPS and IRIG-B frames and calculates the difference between its local time and the motherboard time. If the difference is within the allowable range, the daughterboard gradually adjusts its local clock back to the motherboard time; if the difference is too large, the daughterboard waits for the sampling frame boundary to reload the motherboard time and generates a resynchronization event record.

[0082] Example 4, Sampling data format:

[0083] The sampled data frame may include a frame header, board number, channel number, sampling rate, absolute time in seconds field, sub-second count field, sampling sequence number, data length, data payload, time source status, synchronization link status, and checksum field. The time source status can indicate external lockout, timekeeping, network correction, independent operation, or degradation; the synchronization link status can indicate whether PPS, IRIG-B, and synchronization enable are effective.

[0084] Using the above data format, the host computer or post-processing software can determine the time reliability of each data segment without relying on additional logs, and can automatically filter or mark data segments with low time quality in rail transit fault location, event replay and multi-channel correlation analysis.

[0085] Example 5, Synchronous Workflow:

[0086] System startup phase: After the motherboard powers on, it initializes the local clock, time source interface, and synchronization output module. If the external PPS or IRIG-B standard source is valid, the motherboard enters an external lock state and calibrates the local clock using a discipline algorithm. The motherboard then outputs PPS, IRIG-B, and synchronization enable signals. After the daughterboard powers on, it enters a synchronization waiting state, captures the PPS and decodes the IRIG-B, and enters the motherboard lock state after completing the local clock discipline.

[0087] During normal operation: The motherboard continuously tracks an external standard source, generating stable PPS and IRIG-B; the daughterboard continuously calibrates the local sampling phase based on the PPS, calibrates the absolute time based on IRIG-B, and writes timestamps and synchronization quality markers into the sampling data. Multiple daughterboards start sampling under the same PPS second boundary or the same synchronization enable event.

[0088] External reference source interruption phase: After the motherboard detects the failure of the external standard source, it enters the timekeeping mode and uses the compensation model to maintain the local time; if the network time source is available and the absolute time deviation is detected to exceed the preset threshold, the motherboard performs smoothing correction; the daughterboard still works based on the PPS and IRIG-B output by the motherboard, so the external reference source interruption will not directly cause the daughterboard sampling interruption.

[0089] During motherboard or synchronization link failure phases: If the daughterboard continuously fails to detect valid PPS or IRIG-B, or if the motherboard is not present, it enters a short-term link hold or independent operation state based on the state machine. The daughterboard continues to use the local clock to drive ADC sampling, while simultaneously marking the synchronization quality degradation in the data.

[0090] Motherboard recovery phase: After the daughterboard detects that the motherboard synchronization link has been restored, it enters the recovery resynchronization state. The daughterboard switches back to the motherboard reference based on the time difference and phase difference, choosing either a speed-limited pull or a frame boundary reload method, and writes a resynchronization event flag to ensure data continuity and traceability.

[0091] Based on the above-described multi-channel acquisition time synchronization method for rail transit, this disclosure also provides a multi-channel acquisition time synchronization device for rail transit, which can be used to implement the above-described multi-channel acquisition time synchronization method for rail transit. The device includes: a master clock signal generation module, which, in response to the validity of one of the external reference sources, performs phase and frequency training on the motherboard's local clock according to the external reference source, calibrates the motherboard's absolute time, and generates a time distribution signal and a synchronization enable signal for the daughter board. The external reference sources include at least an external standard source and a network time synchronization source; the external standard sources include at least an external PPS standard source and an external IRIG-B standard source; the time distribution signal includes at least a PPS second pulse and an IRIG-B time code; the synchronization enable signal is used to enable synchronization on the daughter board; in response to the failure of all external reference sources, the local clock is used to compensate. The compensation model maintains the motherboard's local clock and absolute time, generating time distribution signals and synchronization enable signals for the daughter board. The local clock compensation model is generated based on the disciplined data accumulated during the effective time of the external reference source. The daughter clock data acquisition module, in response to the motherboard being in place and the link between the motherboard and the daughter board being normal, synchronizes the daughter board's local clock and absolute time according to the time distribution signal sent by the motherboard. In response to the motherboard being out of place or the link between the motherboard and the daughter board being abnormal, it independently operates the daughter board's local clock according to the previous time distribution signal received by the daughter board. Synchronization quality flags are used to mark data degradation. Multi-channel synchronous sampling is achieved using the motherboard's local clock and the daughter board's local clock. The motherboard and daughter board are connected through a three-wire hardware synchronization bus, which includes at least a PPS second pulse link, an IRIG-B time code link, and a synchronization enable link.

[0092] Based on the above-described multi-channel acquisition time synchronization method for rail transit, this disclosure also provides an electronic device, including: one or more processors; and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors execute the above-described multi-channel acquisition time synchronization method for rail transit.

[0093] An electronic device according to embodiments of the present disclosure includes a processor that can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) or a program loaded from a storage portion into random access memory (RAM). The processor may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor may also include onboard memory for caching purposes. The processor may include a single processing unit or multiple processing units for performing different actions of the method flow according to embodiments of the present disclosure.

[0094] The RAM stores various programs and data required for the operation of the electronic device. The processor, ROM, and RAM are interconnected via a bus. The processor performs various operations of the method flow according to embodiments of this disclosure by executing programs in the ROM and / or RAM. It should be noted that the programs may also be stored in one or more memories other than ROM and RAM. The processor may also perform various operations of the method flow according to embodiments of this disclosure by executing programs stored in said one or more memories.

[0095] According to embodiments of this disclosure, the electronic device may further include an input / output (I / O) interface, which is also connected to a bus. The electronic device may also include one or more of the following components connected to the I / O interface: an input section including a keyboard, mouse, etc.; an output section including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section including a hard disk, etc.; and a communication section including a network interface card such as a LAN card, modem, etc. The communication section performs communication processing via a network such as the Internet. A drive is also connected to the I / O interface as needed. Removable media, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on the drive as needed so that computer programs read from them can be installed into the storage section as needed.

[0096] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0097] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A multi-channel time synchronization method for rail transit, characterized in that, include: In response to the validity of one of the external reference sources, the motherboard local clock is phase and frequency disciplined according to the external reference source, the motherboard absolute time is calibrated, and a time distribution signal and a synchronization enable signal for the daughterboard are generated. The external reference source includes at least an external standard source and a network time source. The external standard source includes at least an external PPS standard source and an external IRIG-B standard source. The time distribution signal includes at least a PPS second pulse and an IRIG-B time code. The synchronization enable signal is used to enable synchronization on the daughterboard. In response to the failure of all external reference sources, the local clock compensation model is used to maintain the motherboard local clock and the motherboard absolute time, and to generate time distribution signals and synchronization enable signals for the daughterboard. The local clock compensation model is generated based on the disciplined data accumulated when the external reference sources are valid. If the motherboard is in place and the link between the motherboard and the daughterboard is normal, then the local clock and absolute time of the daughterboard are synchronized according to the time distribution signal sent by the motherboard. In response to the motherboard being absent or the link between the motherboard and the daughterboard being abnormal, the daughterboard's local clock operates independently based on the previous time distribution signal received by the daughterboard; and data degradation is marked using a synchronization quality flag. In response to the synchronization enable being turned on on the daughterboard or the daughterboard local clock operating independently, multi-channel synchronous sampling is achieved using the motherboard local clock and the daughterboard local clock. The motherboard and the daughterboard are connected via a three-wire hardware synchronization bus, which includes at least a PPS second pulse link, an IRIG-B time code link, and a synchronization enable link.

2. The method according to claim 1, wherein, The step of calibrating the motherboard absolute time by performing phase and frequency training on the motherboard local clock based on the external reference source includes: According to a preset priority, the current reference source is selected from the valid external reference sources, wherein the preset priority from high to low is the external standard source and the network time synchronization source; Using the current reference source, discipline data is obtained to correct the phase and frequency of the motherboard's local clock and the absolute time of the motherboard. The discipline data includes at least one of the following: absolute time code, phase difference, and frequency deviation.

3. The method according to claim 2, wherein, When the current reference source is the external standard source, the step of using the current reference source to obtain compliant data and correct the phase and frequency of the motherboard's local clock and the motherboard's absolute time includes: Capture the second pulse edge of the external PPS standard source and calculate the phase difference between the second pulse edge and the local second pulse edge of the motherboard local clock; The frequency deviation of the motherboard local clock is calculated based on multiple consecutive phase differences. Decode the IRIG-B time code of the external IRIG-B standard source and correct the absolute time.

4. The method according to claim 2, wherein, When the current reference source is the network time source, the step of using the current reference source to obtain compliant data and correct the phase and frequency of the motherboard's local clock and the motherboard's absolute time includes: The network reference time is obtained through the network time source, and the first time deviation between the absolute time of the motherboard and the network reference time is calculated. In response to the first time deviation exceeding a first preset threshold, the absolute time of the motherboard is adjusted using a smooth correction method.

5. The method according to claim 2, wherein, The method for constructing the local clock compensation model includes: During the effective period of the external reference source, the docility data and temperature data are recorded at a preset period to obtain historical phase difference sequence, historical frequency deviation sequence and historical temperature sequence; Based on the historical temperature sequence and the historical frequency deviation sequence, a temperature drift formula for the frequency deviation with respect to temperature is obtained by fitting. The method of using a local clock compensation model to maintain the motherboard's local clock includes: The current frequency deviation is obtained based on the current temperature and the temperature drift formula. The current phase difference is obtained by integrating the last historical phase difference in the historical phase difference sequence and the current frequency deviation.

6. The method according to claim 1, wherein, The synchronization quality flags include at least one of the following: current time source type, motherboard status, daughterboard status, PPS second pulse link status, IRIG-B time code link status, synchronization enable status, external standard source failure time, and resynchronization event flags. The motherboard status includes at least the external reference source valid status and local compensation status, and the daughterboard status includes at least the synchronous motherboard status and independent working status.

7. The method according to claim 1, wherein, The step of synchronizing the daughterboard's local clock and absolute time based on the time distribution signal sent by the motherboard includes: In response to the PPS second pulse, the IRIG-B time code, and the synchronization enable signal all being valid, the local clock of the sub-board and the absolute time of the sub-board are calibrated using the PPS second pulse as the phase reference and the IRIG-B time code as the absolute time reference.

8. The method according to claim 1, wherein, The step of independently operating the local clock of the sub-board based on the previously received time distribution signal includes: In response to a short-term failure of either the PPS second pulse or the IRIG-B time code, the local clock or absolute time of the sub-board is calibrated using the PPS second pulse or IRIG-B time code in the previous time distribution signal of the sub-board. In response to the motherboard being absent or at least one of the time distribution signals failing consecutively, a timestamp consisting of a PPS second pulse and an IRIG-B time code is generated based on the daughterboard's local clock.

9. The method according to claim 1, wherein, The process of using synchronization quality markers to mark data degradation then includes: In response to the detection that the link between the motherboard and the daughterboard has been restored and a valid time distribution signal has been received, the daughterboard's local clock and absolute time are resynchronized according to the time distribution signal sent by the motherboard. Specifically, this includes: Compare the second time deviation between the absolute time of the local clock on the subboard and the absolute time of the IRIG-B time code; If the second time deviation is less than the second preset threshold, the local clock of the sub-board and the local clock of the motherboard are gradually synchronized by a speed-limiting pull method. In response to the second time deviation being greater than the second preset threshold, the local clock of the sub-board and the local clock of the motherboard are resynchronized according to the PPS second pulse of the sub-board, waiting for the next sampling frame boundary or a preset safety time, and a resynchronization event flag is written.

10. The method according to claim 1, wherein, In response to the synchronization enable of the daughterboard or the independent operation of the daughterboard local clock, multi-channel synchronous sampling is achieved using the motherboard local clock and the daughterboard local clock, including: The sub-board uses the same PPS second pulse edge as the zero point of the sampling counter or the starting point of the sampling frame to drive the analog-to-digital converter to synchronously sample and obtain the acquired data. The collected data carries timestamp information, which includes at least the board number, channel number, absolute time in seconds, sub-second count field, and sampling sequence number.

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