Data search method and FPGA chip

Abstract

This application provides a data search method and an FPGA chip, relating to the field of communication technology. The method includes: reading a data block of data to be searched from an external memory and writing the data block into a first buffer; when the number of data units in the first buffer reaches a first preset threshold, reading multiple data units of the same length as a reference sequence from the first buffer and writing the multiple data units into a second buffer to form initial sliding window data, and performing sliding correlation operations based on the initial sliding window data; a cyclic sliding update step: after the current sliding correlation operation is completed, reading a single data unit from the first buffer, writing the single data unit into the second buffer, and performing the next sliding correlation operation; repeating the cyclic sliding update step until a preset single search length is reached, and outputting the data search result. This application can effectively reduce the consumption of on-chip storage resources and computing resources.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a data search method and an FPGA chip. Background Technology

[0002] In fields such as communications, radar, navigation, and digital signal processing, it is often necessary to accurately search for and locate a known reference signal (such as a synchronization code, preamble sequence, or spreading code) within long-term sampled or large-scale stored data. The core operation for achieving this data search is sliding correlation, which involves performing complex multiplication point by point between the data to be searched and the reference sequence and accumulating the results. When the correlation result exceeds a preset threshold, the target data is considered to have been located.

[0003] Existing data search methods typically involve mounting large-capacity SRAM (Static Random-Access Memory) / QDR (Quad Data Rate Static Random-Access Memory) memory inside or outside the FPGA (Field-Programmable Gate Array). The entire block of data to be searched is read from DDR (Double Data Rate Synchronous Dynamic Random-Access Memory) into the FPGA's on-chip cache at once, and then pipelined sliding correlation operations are performed within this cache. When the length of the data to be searched is large, it requires a large amount of storage space, resulting in a surge in the consumption of on-chip storage and computing resources. Summary of the Invention

[0004] This application provides a data search method and an FPGA chip to solve the technical problem in the prior art that the entire data to be searched is read from DDR into the on-chip cache of the FPGA at once, and then pipelined sliding correlation operations are performed in the cache. When the length of the data to be searched is large, a large amount of storage space is required, which leads to a sharp increase in the consumption of on-chip storage resources and computing resources.

[0005] This application provides a data search method, including: A data block of data to be searched is read from an external memory and written into a first buffer; wherein the depth of the first buffer is greater than the length of the reference sequence; the data block includes at least one data unit. When the number of data units in the first buffer reaches a first preset threshold, multiple data units with the same length as the reference sequence are read from the first buffer, and the multiple data units are written into the second buffer to form initial sliding window data, and sliding related operations are performed based on the initial sliding window data; The cyclic sliding update step is as follows: After the current sliding-related operation is completed, a single data unit is read from the first buffer and written into the second buffer to cover the data unit with the smallest write address in the second buffer, forming the updated sliding window data. The next sliding-related operation is then performed based on the updated sliding window data. The depth of the second buffer is the same as the length of the reference sequence. Repeat the cyclic sliding update step until the preset single search length is reached, and output the data search result based on the comparison result of the relevant calculation result of each sliding with the preset threshold value.

[0006] According to the data search method provided in this application, the step of "when the number of data units in the first cache reaches a first preset threshold" includes: When the number of data units in the first buffer is greater than or equal to the length of the reference sequence.

[0007] According to the data search method provided in this application, the step of reading a single data unit from the first buffer after the current sliding related calculation is completed includes: After the current sliding related operation is completed, the first buffer is determined to be non-empty based on the state of the empty marker in the first buffer, and a single data unit is read from the first buffer.

[0008] According to the data search method provided in this application, the step of writing the single data unit into the second buffer to cover the data unit with the smallest write address in the second buffer, forming updated sliding window data, includes: The data unit with the smallest write address in the second buffer is determined, and the data unit with the smallest write address is replaced with the single data unit. The write address of the updated sliding window data is then updated.

[0009] According to the data search method provided in this application, the sliding correlation operation includes: Multiply the current sliding window data with the reference sequence to output L complex product results; where L is the length of the reference sequence. The results of the L complex number products are summed to obtain the complex number summation result; Calculate the relevant characteristic values ​​of the complex number accumulation result; wherein, the relevant characteristic values ​​include the amplitude.

[0010] According to the data search method provided in this application, the step of outputting data search results based on the comparison result of each sliding-related calculation with a preset threshold value includes: If the relevant feature value is greater than or equal to the preset threshold value, the sliding window data corresponding to the relevant feature value is determined as valid data; wherein, the preset threshold value is determined based on the relevant feature value of the reference sequence.

[0011] According to the data search method provided in this application, the cyclic sliding update step further includes: Based on the state of the programmable full mark in the first buffer, if the number of data units in the first buffer is greater than or equal to a second preset threshold, then stop reading data blocks of data to be searched from external memory.

[0012] According to the data search method provided in this application, the length of the data block is less than or equal to the length of the reference sequence.

[0013] According to the data search method provided in this application, before reading the data block of data to be searched from external memory and writing the data block into the first cache, the method further includes: Reset the control flags of the first buffer, wherein the control flags include the first L data ready flag, the empty flag, and the programmable full flag; wherein L is the reference sequence length.

[0014] This application also provides an FPGA chip, including: A data block writing module is used to read a data block of data to be searched from an external memory and write the data block into a first buffer; wherein the depth of the first buffer is greater than the length of the reference sequence; the data block includes at least one data unit. The initial sliding operation module is used to read multiple data units with the same length as the reference sequence from the first buffer when the number of data units in the first buffer reaches a first preset threshold, write the multiple data units into the second buffer to form initial sliding window data, and perform sliding related operations based on the initial sliding window data; The cyclic sliding update module is used to read a single data unit from the first buffer after the current sliding related operation is completed, write the single data unit into the second buffer to cover the data unit with the smallest write address in the second buffer, form updated sliding window data, and perform the next sliding related operation based on the updated sliding window data; wherein, the depth of the second buffer is consistent with the length of the reference sequence; The search result output module is used to repeatedly run the loop sliding update module until the preset single search length is reached, and output the data search results based on the comparison results of the relevant calculation results of each sliding with the preset threshold value.

[0015] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement any of the data search methods described above.

[0016] This application also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data search method as described above.

[0017] This application also provides a computer program product, including a computer program that, when executed by a processor, implements any of the data search methods described above.

[0018] After the initial sliding correlation operation is completed, this application reads and writes only a single data unit each time under the circular addressing mechanism to form the updated sliding window data. There is no need to reload the entire window or physically shift all the data, which can effectively avoid the problem of reading the entire data to be searched into the cache at once, resulting in a large amount of storage space being occupied. This can effectively reduce the consumption of on-chip storage and computing resources, making it suitable for data search scenarios in low-to-mid-range FPGAs and effectively ensuring access efficiency. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is one of the flowcharts illustrating the data search method provided in this application.

[0021] Figure 2 This is a schematic diagram of the overall control state transition provided in the embodiments of this application.

[0022] Figure 3 This is a schematic diagram of the status markers provided in this application.

[0023] Figure 4 This is a schematic diagram of the second cache area provided in this application.

[0024] Figure 5 This is a schematic diagram of the sliding dot product provided in this application.

[0025] Figure 6 This is the second flowchart illustrating the data search method provided in this application.

[0026] Figure 7 This is a schematic diagram of the structure of the data search system provided in this application.

[0027] Figure 8 This is a schematic diagram of the FPGA chip provided in this application.

[0028] Figure 9 This is a schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] In this embodiment, an FPGA chip can be used as the execution entity to execute a data search method provided in this embodiment. Before step S1, the FPGA can be powered on and initialized to perform a hardware reset and configure relevant search parameters. These relevant search parameters include the reference sequence length, single search length, depth of the first buffer, depth of the second buffer, and a preset threshold value.

[0031] Figure 1 This is one of the flowcharts illustrating the data search method provided in this application, such as... Figure 1 As shown, the method includes the following: S1. Read a data block of data to be searched from an external memory and write the data block into a first buffer; wherein the depth of the first buffer is greater than the length of the reference sequence; the data block includes at least one data unit. In this embodiment of the application, before reading the data block of data to be searched from the external memory, the control flags of the first buffer are reset, wherein the control flags include the first L data ready flag First_L_corr_ready, the empty flag fifo_empty, and the programmable full flag fifo_prog_full.

[0032] In one embodiment, the relevant search parameters configured in this application embodiment may be: reference sequence length L, single search length find_len (find_len is usually much larger than L), and the depth of the first buffer is 2. L+8, the depth of the second buffer is L, and the preset threshold is set to 0.5. 2^16 = 32767, and monitor whether there is a single search command. If so, enter the single search process.

[0033] It should be noted that the preset threshold value is determined based on the relevant feature value of the sequence length L. For example, it can be obtained by multiplying the correction coefficient by the relevant feature value of the sequence length L.

[0034] In this embodiment, the first buffer can be a FIFO (First In, First Out) buffer queue. The data to be searched is stored in external memory, which can be Double Data Rate Synchronous Dynamic Random-Access Memory (DDR). The FPGA chip reads the data block of the data to be searched from the DDR and writes the read data block into the first buffer.

[0035] S2. When the number of data units in the first buffer reaches a first preset threshold, read multiple data units with the same length as the reference sequence from the first buffer, write the multiple data units into the second buffer to form initial sliding window data, and perform sliding related operations based on the initial sliding window data. In this embodiment, the first preset threshold can be the length of the reference sequence. While writing data blocks into the first buffer, the number of data units written to the first buffer, wr_real_time_cnt, is counted in real time. When wr_real_time_cnt >= L, First_L_corr_ready is set to 1, initiating the first continuous reading of L data units from the first buffer and writing them to the second buffer to initiate the first L dot-multiplication operations, triggering the first sliding-related core calculation. After the second buffer is full, it immediately performs pointwise complex multiplication with the reference sequence and accumulates the results. The second buffer can be a circular buffer (LOOPBUF).

[0036] S3. Cyclic sliding update step: After the current sliding related operation is completed, a single data unit is read from the first buffer and written into the second buffer to cover the data unit with the smallest write address in the second buffer, forming the updated sliding window data, and the next sliding related operation is performed based on the updated sliding window data; wherein, the depth of the second buffer is consistent with the length of the reference sequence; In the embodiment of the present application, after the first sliding correlation operation is completed, the master control state machine detects the state of the empty flag. If the empty flag is 0, it indicates that the first buffer area is currently non-empty, and the master control state machine initiates a single-point data read operation, that is, only a single data unit is read from the first buffer area, and the read single data unit is written into the second buffer area. Since there are already L data units in the second buffer area, after the single data unit is written into the second buffer area, the data unit with the smallest write address in the second buffer area is overwritten to form updated sliding window data, and the next sliding correlation operation is performed based on the updated sliding window data.

[0037] S4. Repeatedly performing the cyclic sliding update step until a preset single search length is reached, and outputting a data search result according to the comparison result between each sliding correlation operation result and a preset threshold value.

[0038] In the embodiment of the present application, each time the cyclic sliding update step is performed, the sliding position is advanced by one data unit, and the count value of the sliding counter is increased by 1 at the same time. The preset single search length refers to the total number of sliding advances required by the current search task, that is, the maximum number of sliding correlation operations that need to be performed starting from the starting position. During the execution of the cyclic sliding update step, after each sliding correlation operation is completed, the master control state machine compares the current count value of the sliding counter slide_cnt with the find_len value stored in the configuration register. If slide_cnt < find_len, the next cyclic sliding update step is continued; if slide_cnt >= find_len, it is determined that the current search task is completed, and the master control state machine jumps to the completion state to end the current search process.

[0039] After the first sliding correlation operation is completed, the embodiment of the present application only reads and writes a single data unit each time under the cyclic addressing mechanism to form the updated sliding window data, without reloading the entire window or physically shifting all data, which can effectively avoid the problem of occupying a large amount of storage space caused by reading all the to-be-searched data into the buffer at one time, thereby effectively reducing the consumption of on-chip storage resources and computing resources, being applicable to data search scenarios of mid-to-low end FPGAs, and effectively ensuring access efficiency.

[0040] In one embodiment, step S2, when the number of data units in the first buffer area reaches a first preset threshold, includes: When the number of data units in the first buffer area is greater than or equal to the length of the reference sequence.

[0041] In this embodiment, during the process of reading data from the external memory and writing it to the first buffer, the real-time write counter built into the FPGA chip increments with each data unit written. When the count value of the real-time write counter reaches or exceeds the reference sequence length L, it is determined that the number of data units in the first buffer has reached the first preset threshold. At least L data units have accumulated in the first buffer, sufficient to form a complete sliding window data length for sliding correlation operations.

[0042] It should be noted that since the external memory uses burst transmission for data reading, data does not arrive one by one, but in batches in burst blocks. In this case, the count value of the real-time write counter may jump directly from a value less than L to a value greater than L, thus skipping the value point L. If an equal-L condition is used, the triggering condition will be skipped, preventing the initiation of the first sliding related operation and causing a deadlock in the search process. This embodiment uses a condition of greater than or equal to L. Regardless of the burst block size, subsequent operations can be reliably triggered when the count value reaches or exceeds L, ensuring normal operation under different burst transmission length configurations.

[0043] In this embodiment, the triggering condition can be executed in real time by a hardware comparator. One input of the comparator receives the count value of a real-time write counter, and the other input receives the configuration register value storing the reference sequence length L. When the comparison result is true, the comparator outputs a valid signal, which is used to set the first L data ready flag (First_L_corr_ready) to valid, thereby triggering the operation in step S2 of reading multiple data units with the same length as the reference sequence from the first buffer.

[0044] It should be noted that when the trigger condition is met, after the second cache reads L data units from the first cache, there may still be additional data units remaining in the first cache. For example, if the count value at the trigger time is L+8, then after reading L, there are 8 remaining. The remaining data units can be supplied to the second cache in the subsequent cyclic sliding update steps without waiting for the next round of DDR reading, thus effectively ensuring the continuity and high throughput of the sliding search process.

[0045] In one embodiment, step S3, after the current sliding-related calculation is completed, reads a single data unit from the first buffer, including: After the current sliding related operation is completed, the first buffer is determined to be non-empty based on the state of the empty marker in the first buffer, and a single data unit is read from the first buffer.

[0046] In this embodiment, the state of the empty marker in the first buffer is monitored in real time. The empty marker is used to indicate whether the first buffer is empty. When the number of data units stored in the first buffer is zero, the empty marker is set to a valid state, such as logical "1", indicating that there are currently no data units to be read; when at least one data unit is stored in the first buffer, the empty marker is set to an invalid state, such as logical "0", indicating that there are currently readable data units.

[0047] After each sliding window operation is completed, the central control state machine first samples the state of the empty flag. If the empty flag indicates that the first buffer is not empty (i.e., fifo_empty == 0), the central control state machine sends a single-cycle read enable signal to the first buffer and reads one data unit from the first buffer for subsequent sliding window data updates. If the empty flag indicates that the first buffer is empty (i.e., fifo_empty == 1), the central control state machine pauses the read operation, enters a waiting state, and continuously monitors the empty flag. When the empty flag changes to a non-empty state, the central control state machine exits the waiting state and then executes the operation of reading a single data unit.

[0048] Furthermore, the timing constraints after the completion of the current sliding correlation operation can be implemented as follows: The central control state machine maintains an operation completion flag. When the accumulator outputs a valid result and the current sliding count has not reached the preset search count, the operation completion flag is set to valid. The central control state machine only starts sampling the empty flag in the next clock cycle after the operation completion flag is valid, thereby ensuring that the read operation will not cause data conflicts with the ongoing sliding correlation operation.

[0049] In this embodiment of the application, when the first cache is determined to be non-empty, a single data unit is read from the first cache. No invalid read operations are performed during the waiting process, which can effectively avoid data errors caused by reading an empty cache, thereby effectively improving the reliability of data search.

[0050] Please see Figure 2 This is a schematic diagram of a master control state transition provided in an embodiment of this application. Figure 2 As shown, after the system powers on and initializes, data from the external memory enters the first buffer via read operations. When the data meets the conditions, the first L data ready flag is triggered. Data flows from the first buffer into the second buffer via write operations, and the empty and full flags are monitored to control read and write operations. During the search process, complex dot multiplication and accumulation operations are performed at each sliding position, while continuously checking whether the current number of search points has reached the length of a single search, and finally outputting the search result.

[0051] Please see Figure 3This is a schematic diagram of a state marker provided in an embodiment of this application. Figure 3 As shown, external data is continuously written to the first buffer. The number of current data units is monitored in real time. When the number reaches the reference sequence length L, the first L data is ready flag is triggered, allowing the subsequent module to initiate the first continuous block read operation, read out L data at once, and start the first L dot multiplication operation.

[0052] After completing the initial batch read, the system switches to point-to-point read mode. An empty flag indicates whether the first buffer is empty. When the buffer is not empty, subsequent modules are allowed to perform single-data-unit read operations, reading only one data unit at a time for the sliding window to update. A programmable full flag is used for write-side control. When the amount of data in the buffer reaches a preset threshold, this flag takes effect, allowing the preceding write buffer operations to be paused or limited to prevent data overflow.

[0053] In one embodiment, step S3, writing the single data unit into the second buffer to overwrite the data unit with the smallest write address in the second buffer, forming updated sliding window data, includes: The data unit with the smallest write address in the second buffer is determined, and the data unit with the smallest write address is replaced with the single data unit. The write address of the updated sliding window data is then updated.

[0054] In this embodiment, the data unit with the smallest write address refers to the data unit in the second buffer that was written to earliest at the current time. For example, the write addresses of L data units are determined according to their write times, including C0, C1, C2, ..., CL-1, where C0 has the smallest write address. The second buffer is a circular buffer, and under the circular addressing mechanism, this data unit is located at the address currently pointed to by the write address pointer. Therefore, determining the data unit with the smallest write address is equivalent to determining the memory address currently pointed to by the write address pointer.

[0055] It is worth noting that, compared with the existing technology that uses physical shift registers to implement sliding window updates, this embodiment only requires a single-point write operation to complete the window update, without shifting all L data units, significantly reducing power consumption and logic resource consumption. At the same time, this single-point write operation consumes only a single clock cycle, resulting in minimal latency in the sliding update step, which is beneficial for the high-speed operation of the search pipeline.

[0056] In this embodiment of the application, updating the write address of the updated sliding window data includes: After completing the above write operation, the write address pointer is incremented by 1. When the write address pointer is incremented to L, it is reset to zero, thereby realizing the cyclic increment of the write address in the range of 0 to L-1, thus ensuring that each memory address is overwritten in turn, so that the second cache always keeps the latest L consecutive data units.

[0057] In this embodiment, the second buffer also includes a read address pointer, which is independent of the write address pointer. The starting address of the read address pointer changes with the number of slides to ensure that the data units read from the second buffer maintain consistency with the reference sequence in time order.

[0058] This application embodiment determines the data unit with the smallest write address in the second cache area and replaces the data unit with the smallest write address with the single data unit. This enables sliding window updates to be achieved with a single write operation, without having to move the entire window data, thereby effectively reducing the time overhead and power consumption of each sliding update.

[0059] In one embodiment, the sliding correlation operation includes: Multiply the current sliding window data with the reference sequence to output L complex product results; where L is the length of the reference sequence. In this embodiment, a complex multiplier can be used to multiply the current sliding window data and the reference sequence point by point, thereby obtaining L complex product results: mult_i0 + mult_q0. j,mult_i1+mult_q1 j,…,mult_iL-1+mult_qL-1 j, where mult_i is the real part of the complex product and mult_q is the imaginary part of the complex product; 0, 1, ..., L-1 represent the nth product result in the sequence; j is the imaginary unit.

[0060] The results of the L complex number products are summed to obtain the complex number summation result; In this embodiment, the complex sum result sum_I+sum_Q can be obtained by summing the L complex product results using an accumulator. j, i.e., sum(mult_i0+mult_q0) j,mult_i1+mult_q1 j,…,mult_iL-1+mult_qL-1 j); where sum_I is the real part of the complex summation result and sum_Q is the imaginary part of the complex summation result.

[0061] Calculate the relevant characteristic values ​​of the complex number accumulation result; wherein, the relevant characteristic values ​​include the amplitude.

[0062] In this embodiment of the application, taking amplitude as a relevant feature value as an example, the formula for calculating amplitude is as follows: power = sum_I^2 + sum_Q^2 SQRT (power) Where power is the energy value and SQRT(power) is the amplitude.

[0063] This application embodiment uses time-division multiplexing of a single complex multiplier to enable L complex multiplications to be completed sequentially within L clock cycles. The consumption of the complex multiplier is constant at 1, regardless of the length L of the reference sequence, thereby effectively reducing the multiplier resource occupation of the FPGA chip and effectively improving the efficiency of data search.

[0064] Please see Figure 4 This is a schematic diagram of a second cache storage provided in an embodiment of this application. Figure 4 As shown, data units from the previous level second cache are written into the second cache sequentially, with the write address ranging from 0 to L-1. The data is written in address order. In the first round, data0, data1, ..., dataL-1 are written to the second cache addresses 0, 1, 2, 3...L-1, and then the loop returns to address 0. The address where datan is written is 0, the address where datan+1 is written is 1, and so on.

[0065] The read addresses of the second cache are also sequentially from 0 to L-1: The initial address of the first L-point read from the reference sequence is 0, and L local correlation coefficients are read out sequentially by incrementing the address. The initial address of the second L point read from the reference sequence is L-1, and it is incremented sequentially by 0 (LOOP cyclic regression), 1, 2...L-2; The initial address of the third L-point read from the reference sequence is L-2, and it increments sequentially by L-1, 0 (LOOP cyclic regression), 1, 2...L-3; Finally, it returns to the reference sequence, where the initial address of the nth L-th point is 0, and increments by 1 (LOOP loop return), 1, 2...L-1... until the search of the configured length find_len is completed.

[0066] Please see Figure 5 This is a schematic diagram of a sliding dot product provided in an embodiment of this application. Figure 5As shown, the data `Data` is a continuously input data stream, such as `Data0` to `Data2n-1`; the coefficients `C0` to `CL-1` are a fixed reference sequence of length `L`; the first to nth iterations represent the repeated execution of the "one coefficient multiplication" operation n times. Each multiplication uses the same set of coefficients, but operates on a sliding window at different starting positions in the data stream, forming a sliding scan of the continuous data. In the diagram, the horizontal direction represents the progression of time or data index, and the vertical direction represents the pipelined overlapping execution of different batches of multiplication.

[0067] In one embodiment, step S4, based on the comparison between the result of each sliding-related calculation and a preset threshold value, outputs the data search result, including: If the relevant feature value is greater than or equal to the preset threshold value, the sliding window data corresponding to the relevant feature value is determined as valid data; wherein, the preset threshold value is determined based on the relevant feature value of the reference sequence.

[0068] In this embodiment, the preset threshold is a pre-defined decision benchmark value used to distinguish between two states: the presence of target data and the presence of only noise signals. After each sliding correlation operation, a correlation feature value, such as energy value or amplitude, is obtained. This correlation feature value reflects the degree of matching between the data to be searched and the reference sequence at the current sliding position. The larger the correlation feature value, the higher the probability that target data exists at that position; the smaller the correlation feature value, the more likely that the position is noise or non-matching data.

[0069] In this embodiment of the application, if the relevant feature value SQRT(power) is greater than or equal to the preset threshold value, the sliding window data corresponding to the relevant feature value is determined to be valid data.

[0070] In this embodiment, the preset threshold value can be determined based on the correlation characteristics of the reference sequence itself. Under ideal noise-free conditions, when the data to be searched perfectly matches the reference sequence, the correlation characteristic value obtained by the sliding correlation operation will reach the theoretical maximum value; when the data to be searched does not match the reference sequence at all, the correlation characteristic value will approach zero or remain at a low level. The preset threshold value is set at a suitable position between the autocorrelation peak and the noise floor, such as the median value.

[0071] In one embodiment, step S3, the cyclic sliding update step, further includes: Based on the state of the programmable full mark in the first buffer, if the number of data units in the first buffer is greater than or equal to a second preset threshold, then stop reading data blocks of data to be searched from external memory.

[0072] In this embodiment, the trigger threshold of the programmable full marker is user-configurable, rather than fixed to the physical depth of the second buffer. The programmable full marker is used to issue an early warning signal before the second buffer is filled, informing the upstream data source that the cache space is about to run out and requesting a slowdown or pause in writing.

[0073] In this embodiment, the second preset threshold is configured as L+8, where L is the length of the reference sequence. That is, when the number of data units in the first buffer reaches or exceeds L+8, the programmable full flag is set to a valid state (e.g., logic 1); when the number of data units in the first buffer drops below L+8, the programmable full flag is set to an invalid state (e.g., logic 0).

[0074] In this embodiment, the trigger threshold L+8 for the programmable full mark is determined as follows: the total depth of the first buffer is 2L+8. When the number of data units reaches L+8, the remaining free storage space in the first buffer is (2L+8)-(L+8)=L data units. These L free units are reserved to accommodate data that has been sent by the external memory controller but is still in transit. Since the data length of a single DDR burst read is configured to be less than or equal to L, even if a burst read operation of the maximum length L has been initiated and all L data units are in transit, the free space of the L data units reserved in the first buffer is sufficient to accommodate these data in transit, ensuring that no overflow occurs.

[0075] In this embodiment of the application, when the programmable full flag is set to valid, stopping the reading of the data block to be searched from the external memory includes: Once the master control state machine or DDR read control logic detects that the programmable full flag is valid, it immediately pulls the read enable signal of the DDR controller low, pausing the initiation of new DDR burst read requests. It is important to emphasize that this pause operation does not interrupt DDR read operations that are already initiated and in progress; data in transit will still arrive and be written to the first buffer normally. When the number of data units in the first buffer drops below L+8 due to the continuous consumption of backend sliding correlation operations, the programmable full flag is invalidated. Upon detecting that the flag has become invalid, the master control state machine or DDR read control logic pulls the read enable signal of the DDR controller high again, resuming burst read operations from external memory.

[0076] This application embodiment monitors the programmable full mark status, which can provide early warning when there is free space in the first buffer, reserving sufficient storage space for data blocks in transmission. This effectively prevents data loss due to overflow of the second buffer, thereby effectively improving the reliability and accuracy of data search.

[0077] In one embodiment, the length of the data block is less than or equal to the length of the reference sequence.

[0078] In this embodiment, data blocks are transferred from external memory to the first buffer in burst transmission. The reference sequence length is the number of data units contained in the reference sequence pre-configured and stored inside the FPGA. The length of the data block is configured to be an integer power of 2, such as 2^32. 3 And 2 3 Less than or equal to the reference sequence length L.

[0079] It should be noted that setting the data block length to a power of 2 effectively improves the bandwidth utilization efficiency of external memory and avoids additional bus latency caused by unaligned access or lengths other than powers of 2. Furthermore, using a power of 2 length allows the FPGA's internal address accumulation logic to be implemented through simple shift operations, eliminating the need for complex adders.

[0080] In addition, by setting the length of the data block to be less than or equal to the length of the reference sequence, this embodiment of the application can ensure that the amount of data read in a single burst does not exceed the number of free units reserved in the first buffer for data in transmission.

[0081] Please see Figure 6 This is a second schematic flowchart illustrating a data search method provided in one embodiment of this application. Figure 6 As shown, the FPGA chip is powered on and initialized, and search parameters are configured, including single search length, reference sequence and threshold value. It is also determined whether there is a single search command. A data block in DDR is read through a read operation. The data block is transferred to the first buffer in burst mode, and the data in the first buffer is written into the second buffer. If it is determined that the number of data units in the first buffer is greater than L+8, the reading of data blocks in DDR through read operation is stopped.

[0082] In this embodiment, data units from the first buffer are written into the second buffer to form sliding window data. When the number of data units in the first buffer is L, the first L data is detected as ready and marked as valid. At this time, L data units are continuously read from the second buffer and used as the initial sliding window data. Sliding related operations are performed, including complex dot multiplication, accumulation, and complex energy squarer operations, to obtain related feature values. Then, by comparing the related feature values ​​with threshold values, the sliding window data corresponding to the related feature values ​​is determined to be valid data.

[0083] If the current number of search points has not reached the length of a single search, repeat the step of reading data blocks in DDR, and write a single data unit into the second buffer during the next sliding-related operation to obtain the updated sliding window data.

[0084] Please see Figure 7 This is a schematic diagram of the structure of a data search system provided in an embodiment of this application. Please refer to... Figure 7 The FPGA chip includes a first buffer, a second buffer, a complex dot product module, an accumulator, a complex energy squarer, and a comparator. During the preparation phase, the search parameters, including the single search length, reference sequence, and threshold value, can be configured through the processor.

[0085] The first buffer reads data blocks from DDR via read operations. The read method is burst transfer, and the read data blocks are the smallest burst blocks, with a length less than or equal to L. The overall control state machine monitors the data changes in the FPGA chip in real time. When the number of data units in the first buffer is greater than or equal to the single search length, the current read operation is terminated; when the number of data units in the first buffer is greater than or equal to L+8, the read operation is paused.

[0086] When the first L data is marked as ready, a sliding correlation operation is initiated, including complex dot product, accumulation, and complex energy square operation, to obtain relevant feature values. These feature values ​​are then compared with threshold values ​​using a comparator to determine that the sliding window data corresponding to the relevant feature values ​​is valid data. The sliding correlation operation can be performed through the complex dot product module, the accumulator, and the complex energy squarer.

[0087] When an empty tag in the first buffer is invalid, the second buffer reads a single data unit from the first buffer. During the next sliding-related operation, the single data unit is written to the second buffer to obtain the updated sliding window data.

[0088] Please refer to Table 1. In one embodiment, taking a search length N=1M and a correlation coefficient L=256 as an example, the resource consumption for data location search based on bursty data blocks is shown in Table 1 below: Table 1: Resource Consumption

[0089] Among them, SLICE stands for logical slice; BlockRAM stands for Block Random Access Memory, which is a dedicated storage unit that exists independently in blocks.

[0090] Implementing the embodiments of this application has the following beneficial effects: In this embodiment, after the initial sliding correlation operation is completed, under the circular addressing mechanism, only a single data unit is read and written each time to form the updated sliding window data. There is no need to reload the entire window or physically shift all the data, which can effectively avoid the problem of reading the entire data block of the data to be searched into the cache at once, resulting in a large amount of storage space being occupied. This can effectively reduce the consumption of on-chip storage resources and computing resources, making it suitable for data search scenarios of low-to-mid-range FPGAs, and effectively ensuring access efficiency.

[0091] Furthermore, by monitoring the programmable full mark status, this embodiment of the application can provide early warning when there is free space in the first buffer, reserving sufficient storage space for data blocks in transmission. This effectively prevents data loss due to overflow of the second buffer, thereby effectively improving the reliability and accuracy of data search.

[0092] The FPGA chip provided in this application is described below. The FPGA chip described below and the data search method described above can be referred to in correspondence.

[0093] Please see Figure 8 An FPGA chip provided in this application embodiment includes: The data block writing module 810 is used to read a data block of data to be searched from an external memory and write the data block into a first buffer; wherein the depth of the first buffer is greater than the length of the reference sequence; the data block includes at least one data unit. The initial sliding operation module 820 is used to read multiple data units with the same length as the reference sequence from the first buffer when the number of data units in the first buffer reaches a first preset threshold, write the multiple data units into the second buffer to form initial sliding window data, and perform sliding related operations based on the initial sliding window data. The cyclic sliding update module 830 is used to read a single data unit from the first buffer after the current sliding related operation is completed, write the single data unit into the second buffer to cover the data unit with the smallest write address in the second buffer, form updated sliding window data, and perform the next sliding related operation based on the updated sliding window data; wherein, the depth of the second buffer is consistent with the length of the reference sequence; The search result output module 840 is used to repeatedly run the cyclic sliding update module until the preset single search length is reached, and output the data search results based on the comparison results of the relevant calculation results of each sliding with the preset threshold value.

[0094] In one embodiment, the step of the number of data units in the first buffer reaching a first preset threshold includes: When the number of data units in the first buffer is greater than or equal to the length of the reference sequence.

[0095] In one embodiment, reading a single data unit from the first buffer after the current sliding-related calculation is completed includes: After the current sliding related operation is completed, the first buffer is determined to be non-empty based on the state of the empty marker in the first buffer, and a single data unit is read from the first buffer.

[0096] In one embodiment, writing the single data unit into the second buffer to overwrite the data unit with the smallest write address in the second buffer, forming updated sliding window data, includes: The data unit with the smallest write address in the second buffer is determined, and the data unit with the smallest write address is replaced with the single data unit. The write address of the updated sliding window data is then updated.

[0097] In one embodiment, the sliding correlation operation includes: Multiply the current sliding window data with the reference sequence to output L complex product results; where L is the length of the reference sequence. The results of the L complex number products are summed to obtain the complex number summation result; Calculate the relevant characteristic values ​​of the complex number accumulation result; wherein, the relevant characteristic values ​​include the amplitude.

[0098] In one embodiment, the step of outputting the data search result based on the comparison result of each sliding-related calculation with a preset threshold value includes: If the relevant feature value is greater than or equal to the preset threshold value, the sliding window data corresponding to the relevant feature value is determined as valid data; wherein, the preset threshold value is determined based on the relevant feature value of the reference sequence.

[0099] In one embodiment, the cyclic sliding update module is further configured to: Based on the state of the programmable full mark in the first buffer, if the number of data units in the first buffer is greater than or equal to a second preset threshold, then stop reading data blocks of data to be searched from external memory.

[0100] In one embodiment, the length of the data block is less than or equal to the length of the reference sequence.

[0101] In one embodiment, before reading a data block of data to be searched from external memory and writing the data block into a first cache, the method further includes: Reset the control flags of the first buffer, wherein the control flags include the first L data ready flag, the empty flag, and the programmable full flag; wherein L is the reference sequence length.

[0102] Implementing the embodiments of this application has the following beneficial effects: In this embodiment, after the initial sliding correlation operation is completed, under the circular addressing mechanism, only a single data unit is read and written each time to form the updated sliding window data. There is no need to reload the entire window or physically shift all the data, which can effectively avoid the problem of reading the entire data block of the data to be searched into the cache at once, resulting in a large amount of storage space being occupied. This can effectively reduce the consumption of on-chip storage resources and computing resources, making it suitable for data search scenarios of low-to-mid-range FPGAs, and effectively ensuring access efficiency.

[0103] Furthermore, by monitoring the programmable full mark status, this embodiment of the application can provide early warning when there is free space in the first buffer, reserving sufficient storage space for data blocks in transmission. This effectively prevents data loss due to overflow of the second buffer, thereby effectively improving the reliability and accuracy of data search.

[0104] Figure 9 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 9 As shown, the electronic device may include: a processor 910, a communications interface 920, a memory 930, and a communication bus 940, wherein the processor 910, the communications interface 920, and the memory 930 communicate with each other via the communication bus 940. The processor 910 can call logical instructions in the memory 930 to execute a data search method, which includes: A data block of data to be searched is read from an external memory and written into a first buffer; wherein the depth of the first buffer is greater than the length of the reference sequence; the data block includes at least one data unit. When the number of data units in the first buffer reaches a first preset threshold, multiple data units with the same length as the reference sequence are read from the first buffer, and the multiple data units are written into the second buffer to form initial sliding window data, and sliding related operations are performed based on the initial sliding window data; The cyclic sliding update step is as follows: After the current sliding-related operation is completed, a single data unit is read from the first buffer and written into the second buffer to cover the data unit with the smallest write address in the second buffer, forming the updated sliding window data. The next sliding-related operation is then performed based on the updated sliding window data. The depth of the second buffer is the same as the length of the reference sequence. Repeat the cyclic sliding update step until the preset single search length is reached, and output the data search result based on the comparison result of the relevant calculation result of each sliding with the preset threshold value.

[0105] Furthermore, the logical instructions in the aforementioned memory 930 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0106] On the other hand, this application also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer is able to perform the data search methods provided by the above methods, the method including: A data block of data to be searched is read from an external memory and written into a first buffer; wherein the depth of the first buffer is greater than the length of the reference sequence; the data block includes at least one data unit. When the number of data units in the first buffer reaches a first preset threshold, multiple data units with the same length as the reference sequence are read from the first buffer, and the multiple data units are written into the second buffer to form initial sliding window data, and sliding related operations are performed based on the initial sliding window data; The cyclic sliding update step is as follows: After the current sliding-related operation is completed, a single data unit is read from the first buffer and written into the second buffer to cover the data unit with the smallest write address in the second buffer, forming the updated sliding window data. The next sliding-related operation is then performed based on the updated sliding window data. The depth of the second buffer is the same as the length of the reference sequence. Repeat the cyclic sliding update step until the preset single search length is reached, and output the data search result based on the comparison result of the relevant calculation result of each sliding with the preset threshold value.

[0107] Furthermore, this application also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is implemented to perform the data search methods provided by the methods described above, the method comprising: A data block of data to be searched is read from an external memory and written into a first buffer; wherein the depth of the first buffer is greater than the length of the reference sequence; the data block includes at least one data unit. When the number of data units in the first buffer reaches a first preset threshold, multiple data units with the same length as the reference sequence are read from the first buffer, and the multiple data units are written into the second buffer to form initial sliding window data, and sliding related operations are performed based on the initial sliding window data; The cyclic sliding update step is as follows: After the current sliding-related operation is completed, a single data unit is read from the first buffer and written into the second buffer to cover the data unit with the smallest write address in the second buffer, forming the updated sliding window data. The next sliding-related operation is then performed based on the updated sliding window data. The depth of the second buffer is the same as the length of the reference sequence. Repeat the cyclic sliding update step until the preset single search length is reached, and output the data search result based on the comparison result of the relevant calculation result of each sliding with the preset threshold value.

[0108] The FPGA chip embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0109] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A data search method, characterized in that, include: A data block of data to be searched is read from an external memory and written into a first buffer; wherein the depth of the first buffer is greater than the length of the reference sequence; the data block includes at least one data unit. When the number of data units in the first buffer reaches a first preset threshold, multiple data units with the same length as the reference sequence are read from the first buffer, and the multiple data units are written into the second buffer to form initial sliding window data, and sliding related operations are performed based on the initial sliding window data; The cyclic sliding update step is as follows: After the current sliding-related operation is completed, a single data unit is read from the first buffer and written into the second buffer to cover the data unit with the smallest write address in the second buffer, forming the updated sliding window data. The next sliding-related operation is then performed based on the updated sliding window data. The depth of the second buffer is the same as the length of the reference sequence. Repeat the cyclic sliding update step until the preset single search length is reached, and output the data search result based on the comparison result of the relevant calculation result of each sliding with the preset threshold value.

2. The data search method as described in claim 1, characterized in that, The condition where the number of data units in the first buffer reaches a first preset threshold includes: When the number of data units in the first buffer is greater than or equal to the length of the reference sequence.

3. The data search method as described in claim 1, characterized in that, The step of reading a single data unit from the first buffer after the current sliding-related calculation is completed includes: After the current sliding related operation is completed, the first buffer is determined to be non-empty based on the state of the empty marker in the first buffer, and a single data unit is read from the first buffer.

4. The data search method as described in claim 1, characterized in that, The step of writing the single data unit into the second buffer to overwrite the data unit with the smallest write address in the second buffer, forming the updated sliding window data, includes: The data unit with the smallest write address in the second buffer is determined, and the data unit with the smallest write address is replaced with the single data unit. The write address of the updated sliding window data is then updated.

5. The data search method as described in claim 1, characterized in that, The sliding correlation operation includes: Multiply the current sliding window data with the reference sequence to output L complex product results; where L is the length of the reference sequence. The results of the L complex number products are summed to obtain the complex number summation result; Calculate the relevant characteristic values ​​of the complex number accumulation result; wherein, the relevant characteristic values ​​include the amplitude.

6. The data search method as described in claim 5, characterized in that, The step of comparing the result of each sliding operation with a preset threshold value and outputting the data search result includes: If the relevant feature value is greater than or equal to the preset threshold value, the sliding window data corresponding to the relevant feature value is determined as valid data; wherein, the preset threshold value is determined based on the relevant feature value of the reference sequence.

7. The data search method as described in claim 1, characterized in that, The cyclic sliding update step further includes: Based on the state of the programmable full mark in the first buffer, if the number of data units in the first buffer is greater than or equal to a second preset threshold, then stop reading data blocks of data to be searched from external memory.

8. The data search method as described in claim 1, characterized in that, The length of the data block is less than or equal to the length of the reference sequence.

9. The data search method as described in claim 1, characterized in that, Before reading the data block of the data to be searched from external memory and writing the data block into the first buffer, the process also includes: Reset the control flags of the first buffer, wherein the control flags include the first L data ready flag, the empty flag, and the programmable full flag; wherein L is the reference sequence length.

10. An FPGA chip, characterized in that, include: A data block writing module is used to read a data block of data to be searched from an external memory and write the data block into a first buffer; wherein the depth of the first buffer is greater than the length of the reference sequence; the data block includes at least one data unit. The initial sliding operation module is used to read multiple data units with the same length as the reference sequence from the first buffer when the number of data units in the first buffer reaches a first preset threshold, write the multiple data units into the second buffer to form initial sliding window data, and perform sliding related operations based on the initial sliding window data; The cyclic sliding update module is used to read a single data unit from the first buffer after the current sliding related operation is completed, write the single data unit into the second buffer to cover the data unit with the smallest write address in the second buffer, form updated sliding window data, and perform the next sliding related operation based on the updated sliding window data; wherein, the depth of the second buffer is consistent with the length of the reference sequence; The search result output module is used to repeatedly run the loop sliding update module until the preset single search length is reached, and output the data search results based on the comparison results of the relevant calculation results of each sliding with the preset threshold value.

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