An hmb mapping cache layout method and device for a DRAM-less solid state disk

CN122711368APending Publication Date: 2026-09-08HUIJU ELECTRONICS (DONGGUAN) IND CO LTD
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Patent Information

Application Number
CN202610863120.7
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-06-15
Publication Date
2026-09-08

AI Technical Summary

Technical Problem

上述方案未将HMB主机内存区域边界、连续空闲空间长度、映射段占用长度、映射段更新后的长度变化和DMA访问片段数量共同用于映射段存放位置确定

Benefits of technology

本实施例中,通过在HMB区域描述信息形成HMB空间描述表,L2P映射表形成映射段描述项,映射段描述项形成待布局映射段,待布局映射段形成占用长度和扩展预留长度,占用长度、扩展预留长度和HMB空间描述表共同形成候选HMB空间单元,候选HMB空间单元形成布局评价值,布局评价值形成目标HMB空间单元。通过在写入映射段前,通过HMB空间描述表和映射段描述项确定写入位置,使映射段写入过程具有连续的数据输入和状态更新路径。

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Abstract

The application discloses a HMB mapping cache layout method and device for a DRAM-less solid state disk, and the method is applied to a solid state disk controller without setting an independent DRAM cache, and the solid state disk controller caches L2P mapping information through a host memory buffer HMB. The method comprises the following steps: acquiring HMB region description information and establishing an HMB space description table; dividing an L2P mapping table into multiple mapping segments and establishing mapping segment description items; determining a target storage format, an occupied length and an extended reserved length of a mapping segment to be laid out; determining a candidate HMB space unit according to the HMB space description table, the occupied length and the extended reserved length, and calculating a layout evaluation value according to a space matching value, a cross-region storage quantity and a DMA access frequency; determining a target HMB space unit according to the layout evaluation value, and writing the mapping segment to be laid out into the target HMB space unit and updating the HMB space description table and the mapping segment description items.
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Description

Technical Field

[0001] This invention relates to the field of solid-state drive data management technology, and in particular to an HMB mapping cache layout method and apparatus for DRAM-less solid-state drives. Background Technology

[0002] A solid-state drive (SSD) consists of NAND Flash, an SSD controller, and a host interface. When the host sends a read / write request to the SSD, the request carries a logical address. The SSD controller determines the physical storage location in the NAND Flash based on the mapping between logical and physical addresses. This mapping is typically recorded in an L2P mapping table.

[0003] Solid-state drives (SSDs) with dedicated DRAM caches typically store at least a portion of their L2P mapping table in a dedicated DRAM cache. DRAM-less SSDs do not have dedicated DRAM caches, and their controllers have limited internal SRAM capacity. To cache L2P mapping information, DRAM-less SSDs cache L2P mapping information through the Host Memory Buffer (HMB). The HMB is allocated by the host, and the SSD controller accesses the HMB through the host interface.

[0004] The host-allocated HMB consists of one or more host memory regions. Each host memory region has a starting address and a region length. Multiple host memory regions are not necessarily contiguous. When the solid-state drive controller accesses mapped data stored across multiple host memory regions, it needs to form corresponding access segments according to the different host memory regions.

[0005] Existing HMB mapping caching schemes typically focus on which L2P mapping information to cache in the HMB, or on replacing mapping data in the HMB based on access statistics. These schemes do not consider the HMB host memory region boundaries, the length of contiguous free space, the length occupied by the mapping segment, the length change of the updated mapping segment, and the number of DMA access segments in determining the location of the mapping segment.

[0006] Therefore, an HMB mapping segment layout method is needed so that the solid-state drive controller can determine the storage location of the mapping segment in the HMB based on the HMB space description information and the length information of the mapping segment to be written before writing L2P mapping information. Summary of the Invention

[0007] To overcome the shortcomings mentioned above, the present invention aims to provide a technical solution that can solve the above problems.

[0008] This invention provides an HMB mapping cache layout method for DRAM-less solid-state drives (SSDs). This method is applied to SSD controllers that do not have a separate DRAM cache. The SSD controller caches L2P mapping information through the HMB.

[0009] The method includes: acquiring HMB region description information allocated by the host to the solid-state drive controller; establishing an HMB space description table based on the HMB region description information, wherein the HMB space description table records the region boundary information and continuous free space length of HMB space units; dividing an L2P mapping table into multiple mapping segments according to logical address ranges; establishing a mapping segment description entry for each mapping segment, wherein the mapping segment description entry records the mapping segment identifier, logical address range, update statistics, and HMB storage status; determining the mapping segment to be laid out based on the mapping segment description entry; and determining the target storage format based on the correspondence between logical addresses and physical addresses within the mapping segment to be laid out. The occupied length of the mapping segment to be laid out is determined according to the target storage format, and the extended reserved length of the mapping segment to be laid out is determined according to the update statistics. Candidate HMB space units are determined according to the HMB space description table, the occupied length, and the extended reserved length. For each candidate HMB space unit, a layout evaluation value is calculated based on the space matching value, the number of cross-region storage units, and the number of DMA accesses. The target HMB space unit is determined according to the layout evaluation value. The mapping segment to be laid out is written into the target HMB space unit according to the target storage format, and the HMB space description table and the mapping segment description item of the mapping segment to be laid out are updated.

[0010] The present invention also provides an HMB mapping cache layout device for DRAM-less solid-state drives.

[0011] The device includes: an HMB space description module, used to acquire HMB region description information allocated by the host to the solid-state drive controller, and establish an HMB space description table based on the HMB region description information, wherein the HMB space description table records the region boundary information and continuous free space length of HMB space units; a mapping segment management module, used to divide the L2P mapping table into multiple mapping segments according to the logical address range, and establish a mapping segment description entry for each mapping segment, wherein the mapping segment description entry records the mapping segment identifier, logical address range, update statistics, and HMB storage status; and a length determination module, used to determine the mapping segment to be laid out based on the mapping segment description entry, and determine the target length based on the correspondence between logical addresses and physical addresses within the mapping segment to be laid out. The system comprises a target storage format, which determines the occupied length of the mapping segment to be laid out based on the target storage format, and determines the extended reserved length of the mapping segment to be laid out based on the updated statistics; a layout evaluation module, which determines candidate HMB space units based on the HMB space description table, the occupied length, and the extended reserved length, and calculates a layout evaluation value for each candidate HMB space unit based on the space matching value, the number of cross-region storage, and the number of DMA accesses; and a write update module, which determines the target HMB space unit based on the layout evaluation value, writes the mapping segment to be laid out into the target HMB space unit according to the target storage format, and updates the HMB space description table and the mapping segment description item of the mapping segment to be laid out.

[0012] Compared with the prior art, the beneficial effects of the present invention are: In this embodiment, an HMB spatial description table is formed from HMB region description information, a mapping segment description item is formed from an L2P mapping table, a mapping segment description item forms a mapping segment to be laid out, the mapping segment to be laid out forms an occupied length and an extended reserved length, the occupied length, the extended reserved length, and the HMB spatial description table together form a candidate HMB spatial cell, the candidate HMB spatial cell forms a layout evaluation value, and the layout evaluation value forms a target HMB spatial cell. By determining the write position through the HMB spatial description table and the mapping segment description item before writing the mapping segment, the mapping segment writing process has a continuous data input and state update path. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a flowchart of the method steps of the present invention; Figure 2 This is a block diagram of the device structure of the present invention. Detailed Implementation

[0015] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] like Figure 1 As shown, this embodiment provides an HMB mapping cache layout method for DRAM-less solid-state drives (SSDs). This method is applied to SSD controllers that do not have a dedicated DRAM cache. The SSD controller caches L2P mapping information through the host memory buffer (HMB).

[0017] The above methods include: S100, the solid-state drive controller obtains the HMB region description information allocated by the host to the solid-state drive controller, and establishes an HMB space description table based on the HMB region description information. The HMB region description information includes the starting address and region length of at least one host memory region. The HMB space description table records the region boundary information and the length of continuous free space of HMB space units.

[0018] In the S200, the solid-state drive controller divides the L2P mapping table into multiple mapping segments according to the logical address range, and establishes a mapping segment description entry for each mapping segment. The mapping segment description entry records the mapping segment identifier, logical address range, update statistics, and HMB storage status.

[0019] S300: The solid-state drive controller determines the mapping segment to be laid out based on the mapping segment description, determines the target storage format based on the correspondence between logical addresses and physical addresses within the mapping segment to be laid out, determines the occupied length of the mapping segment to be laid out based on the target storage format, and determines the extended reserved length of the mapping segment to be laid out based on the updated statistics.

[0020] The S400 solid-state drive controller determines candidate HMB space units based on the HMB space description table, occupied length, and extended reserved length, and calculates a layout evaluation value for each candidate HMB space unit based on the space matching value, cross-region storage quantity, and DMA access count.

[0021] S500: The solid-state drive controller determines the target HMB space unit based on the layout evaluation value, writes the mapping segment to be laid out into the target HMB space unit according to the target storage format, and updates the HMB space description table and the mapping segment description item of the mapping segment to be laid out.

[0022] In this embodiment, an HMB spatial description table is formed from HMB region description information, a mapping segment description item is formed from an L2P mapping table, a mapping segment description item forms a mapping segment to be laid out, the mapping segment to be laid out forms an occupied length and an extended reserved length, the occupied length, the extended reserved length, and the HMB spatial description table together form a candidate HMB spatial cell, the candidate HMB spatial cell forms a layout evaluation value, and the layout evaluation value forms a target HMB spatial cell. By determining the write position through the HMB spatial description table and the mapping segment description item before writing the mapping segment, the mapping segment writing process has a continuous data input and state update path.

[0023] The following examples will further illustrate the HMB mapping cache layout method for DRAM-less solid-state drives described above.

[0024] In step S100, the solid-state drive controller divides the HMB into multiple primary space units based on the host memory region start address and region length in the HMB region description information. Each primary space unit corresponds to a continuous address range within a host memory region. Then, within each primary space unit, it is further divided into multiple secondary space units according to a preset management granularity. The preset management granularity is 4KB, 8KB, 16KB, 32KB, or 64KB. Furthermore, the controller records the idle status, occupied status, and associated mapping segment identifier for each secondary space unit. An idle status indicates that the secondary space unit has not been allocated to a mapping segment. An occupied status indicates that the secondary space unit has been allocated to a mapping segment. The associated mapping segment identifier is used to record the mapping segment occupying the secondary space unit.

[0025] Next, based on the number of consecutively idle secondary space units within the same primary space unit, the length of the consecutively idle space within that primary space unit is determined. The length of the consecutively idle space is equal to the product of the number of consecutively idle secondary space units and the preset management granularity. Thus, the starting address, region length, region boundary information, and length of the consecutively idle space of the primary space unit are written into the HMB space description table.

[0026] In this embodiment, the output of HMB region description information is a first-level spatial unit, the output of the first-level spatial unit is a second-level spatial unit, and the status output of the second-level spatial unit is the length of continuous free space. The length of continuous free space is written into the HMB space description table. The HMB space description table records the boundaries of the host memory region and the continuous free space within the region, so that the subsequent candidate HMB space unit determination step can read the length of continuous free space and the region boundary information.

[0027] In step S200, the solid-state drive controller divides the L2P mapping table according to a preset logical address span, resulting in multiple mapping segments. The preset logical address span is a fixed number of logical block addresses.

[0028] In another implementation, the solid-state drive controller divides the L2P mapping table according to the logical address span corresponding to the block, superblock, stripe or channel interleaving range of the NAND Flash, and obtains multiple mapping segments.

[0029] Next, the start logical address, end logical address, and mapping segment identifier of each mapping segment are written into the mapping segment description item of that mapping segment.

[0030] When the mapping segment corresponding to the logical address range hit by the host read / write request is not stored in the HMB, the corresponding mapping segment is determined as the mapping segment to be laid out.

[0031] When a mapping segment already stored in the HMB is updated and the re-layout conditions are met, the corresponding mapping segment is identified as the mapping segment to be laid out. The re-layout conditions include that the updated occupied length is greater than the sum of the original occupied length and the original extended reserved length.

[0032] In this embodiment, the logical address range of the host read / write request is input as a mapping segment description item, the mapping segment description item outputs the HMB storage status, and the HMB storage status outputs the mapping segment to be laid out. The conditions for generating the mapping segment to be laid out are limited to cache misses or the need for re-layout after updates, ensuring that the input objects in subsequent S300 have a definite source.

[0033] In step S300, the solid-state drive controller obtains the physical address difference between adjacent logical addresses within the mapping segment to be laid out.

[0034] Suppose that the segment to be mapped includes n mapping entries, which are arranged in ascending order of logical address. The i-th mapping entry includes logical address LBAi and physical address PPAi, and the (i+1)-th mapping entry includes logical address LBA(i+1) and physical address PPA(i+1), and the difference between LBA(i+1) and LBAi is equal to the preset logical address step size U. Then the difference Δi of the i-th physical address satisfies: Δi = PPA(i+1) - PPAi.

[0035] The solid-state drive controller determines whether the i-th mapping item and the (i+1)-th mapping item conform to a continuous mapping relationship based on whether the physical address difference Δi falls within a preset physical address difference range. Specifically, when Δi falls within the preset physical address difference range [Δmin, Δmax], the i-th mapping item and the (i+1)-th mapping item are determined to conform to a continuous mapping relationship; when Δi does not fall within the preset physical address difference range, the i-th mapping item and the (i+1)-th mapping item are determined not to conform to a continuous mapping relationship. The preset difference range is determined by the NAND Flash page address increment rule, channel interleaving rule, or stripe address increment rule.

[0036] Then, the mapping continuity parameter is determined based on the ratio of the number of mapping items that conform to the continuous mapping relationship to the total number of mapping items in the mapping segment to be laid out.

[0037] When the mapping continuity parameter is greater than or equal to the first threshold, the base address plus offset format is determined as the target storage format. The base address plus offset format includes the physical base address and multiple offset values.

[0038] When the mapping continuity parameter is less than the first threshold, and the number of mapping items that do not conform to the continuous mapping relationship is less than or equal to the second threshold, the bitmap with exceptions format is determined as the target storage format. The bitmap with exceptions format includes a continuous mapping bitmap and an exception table.

[0039] When the mapping continuity parameter is less than the first threshold and the number of mapping items that do not conform to the continuous mapping relationship is greater than the second threshold, the uncompressed format is determined as the target storage format.

[0040] In this embodiment, the adjacent physical address difference of the mapping segment to be laid out is output, the adjacent physical address difference is output as a mapping continuity parameter, and the mapping continuity parameter and the number of mapping items that do not conform to the continuous mapping relationship are output as the target storage format.

[0041] Furthermore, the solid-state drive controller reads the lengths of multiple compressed mapping data of the mapping segments to be laid out within the statistics window from the updated statistics.

[0042] Let the lengths of the compressed mapped data segment within the statistical window be C1, C2, ..., Cm, respectively. Determine the size variation parameter D based on the maximum value among the multiple compressed mapped data lengths and the current compressed mapped data length. D=max(C1,C2,…,Cm)-Cm.

[0043] Then, the extended reserve length R is determined based on the size change parameter D, the preset reserve coefficient K, and the preset management granularity G of the HMB space description table: R = ceil(D × K / G) × G.

[0044] Here, ceil means rounding up.

[0045] Write the extended reserved length R into the mapping segment description item of the mapping segment to be laid out.

[0046] In this embodiment, the updated statistical value outputs the lengths of multiple compressed mapped data within the statistical window. These multiple compressed mapped data lengths output a size change parameter, which in turn outputs an extended reserved length. This extended reserved length is then written into the mapping segment description item. The extended reserved length is calculated from the historical compressed length and the current compressed length of the mapping segment, enabling the candidate HMB space cell determination step to simultaneously read both the occupied length and the extended reserved length.

[0047] In step S400, the solid-state drive controller reads the length of the continuous free space of each HMB space unit from the HMB space description table. Specifically, HMB space units with a continuous free space length greater than or equal to the sum of the occupied length and the extended reserved length are identified as candidate HMB space units. Then, based on the starting address, region boundary information, occupied length, and extended reserved length of the candidate HMB space unit, the number of host memory regions traversed and the number of storage segments formed when the layout mapping segment is written to the candidate HMB space unit are determined. The number of host memory regions traversed is taken as the cross-region storage quantity, and the number of storage segments formed is taken as the DMA access count.

[0048] In this embodiment, the HMB space description table outputs the length of continuous free space and region boundary information. The occupied length and extended reserved length output the space requirement length. The length of continuous free space and the space requirement length output candidate HMB space cells. The candidate HMB space cells and region boundary information output the number of cross-region storage units and the number of DMA accesses. By determining the candidate HMB space cells, which are constrained by both the space requirement length and the HMB region boundary, the layout evaluation value calculation can read the space matching value, the number of cross-region storage units, and the number of DMA accesses.

[0049] Furthermore, the solid-state drive controller determines the continuous free space length F of the candidate HMB space unit, the occupied length L of the segment to be laid out and mapped, and the extended reserved length R.

[0050] Then calculate the spatial difference A: A=FLR.

[0051] When A is greater than or equal to 0, the solid-state drive controller calculates the space matching value M based on A and the preset management granularity G: M = 1 / (1 + A / G).

[0052] The solid-state drive controller determines the cross-region storage quantity B and the number of DMA accesses Q when the layout mapping segment is written to the candidate HMB space unit.

[0053] The solid-state drive controller calculates the layout evaluation value S based on the space matching value M, the number of cross-region storage units B, and the number of DMA accesses Q. S = W1 × M - W2 × B - W3 × Q.

[0054] Among them, W1, W2 and W3 are preset weights, and W1, W2 and W3 are all positive numbers.

[0055] The solid-state drive controller selects the candidate HMB space unit with the largest layout evaluation value S as the target HMB space unit.

[0056] In this embodiment, the length of continuous free space, the length of occupied space and the length of extended reserved space are output as space difference. The space difference is output as space matching value. The space matching value, the number of cross-region storage and the number of DMA accesses are output as layout evaluation value. The layout evaluation value is output as target HMB space unit.

[0057] In another implementation, when there are no HMB space units in the HMB space descriptor table with a contiguous free space length greater than or equal to the sum of the occupied length and the extended reserved length, the solid-state drive controller splits the mapping segment to be laid out into multiple mapping sub-segments according to the logical address order of the mapping segment to be laid out. Each mapping sub-segment then corresponds to a contiguous logical address sub-range within the mapping segment to be laid out. Next, the sub-segment occupied length and sub-segment storage address of each mapping sub-segment are determined. The multiple mapping sub-segments are then written into different HMB space units. Then, the sub-segment number, logical address sub-range, sub-segment storage address, and sub-segment occupied length of each mapping sub-segment are recorded in the mapping segment descriptor entry of the mapping segment to be laid out. Subsequently, when reading the mapping segment to be laid out, the solid-state drive controller reads multiple mapping sub-segments according to the sub-segment number in the mapping segment descriptor entry and reassembles the mapping segment to be laid out according to the sub-segment number.

[0058] In this embodiment, the mapping segment to be laid out outputs multiple mapping sub-segments. Each mapping sub-segment outputs its length and storage address, which are then written into the mapping segment description item. When there is no contiguous space that satisfies the writing requirements of the complete mapping segment, the mapping segment description item records the order and address of the multiple mapping sub-segments, enabling the mapping segment to be reassembled in sequence during the reading phase.

[0059] In another implementation, when a mapped segment already written to the HMB is updated, the solid-state drive controller re-determines the updated target storage format and the updated occupied length of the mapped segment. Then, it reads the original occupied length and the original extended reserved length from the mapped segment descriptor. When the updated occupied length is less than or equal to the sum of the original occupied length and the original extended reserved length, the updated mapped segment is written into the original target HMB space unit of the mapped segment, and the mapped segment descriptor is updated. When the updated occupied length is greater than the sum of the original occupied length and the original extended reserved length, the mapped segment is identified as a new mapped segment to be laid out, and steps S300 to S500 are executed.

[0060] In this embodiment, the updated mapping segment outputs the updated target storage format and the updated occupied length. The updated occupied length is compared with the original occupied length and the original extended reserved length. The comparison result outputs the in-situ write path or the rearrangement path. After the mapping segment is updated, the processing path is determined according to whether the occupied length exceeds the sum of the original occupied length and the original extended reserved length, so that the mapping segment descriptor remains updated after in-situ writing or rearrangement.

[0061] In another implementation, before writing the mapping segment to be laid out into the HMB, the SSD controller generates a version number and a checksum for the mapping segment. The version number is a value that increments with each update of the mapping segment. The checksum is verification data calculated based on the content of the mapping segment under the target storage format. Then, after writing the mapping segment to be laid out into the HMB, the version number, checksum, storage address, and occupied length are written to the mapping segment description field of the mapping segment. When the mapping content of the mapping segment to be laid out has been updated but has not yet been written to the NAND Flash metadata area, a dirty flag is set in the mapping segment description field. When a mapping segment with a dirty flag is migrated, obsolete, or re-laid out, the version number and mapping content of the mapping segment are written to the NAND Flash metadata log area, and the dirty flag is cleared after the write is complete. Then, when reading a mapping segment from the HMB, the read mapping segment is verified against the version number and checksum in the mapping segment description field. If the checksum is inconsistent, the SSD controller reads the mapping content of the mapping segment from the NAND Flash metadata log area.

[0062] In this embodiment, the version number and checksum of the mapping segment to be laid out are output. The version number and checksum are written into the mapping segment description item, and the dirty flag in the mapping segment description item is output as a write action to the NAND Flash metadata log area. By recording the version number, checksum, storage address, occupied length, and dirty flag through the mapping segment description item, a state correspondence is established between the mapping segment in the HMB and the NAND Flash metadata log area.

[0063] Please see Figure 2 This embodiment provides an HMB mapping cache layout device for DRAM-less solid-state drives. The device includes: HMB space description module 100 is used to obtain HMB region description information allocated by the host to the solid-state drive controller, and to establish an HMB space description table based on the HMB region description information. The HMB space description table records the region boundary information and continuous free space length of the HMB space unit. The mapping segment management module 200 is used to divide the L2P mapping table into multiple mapping segments according to the logical address range, and to establish a mapping segment description item for each mapping segment. The mapping segment description item records the mapping segment identifier, logical address range, update statistics and HMB storage status. The length determination module 300 is used to determine the mapping segment to be laid out based on the mapping segment description item, determine the target storage format based on the correspondence between logical addresses and physical addresses in the mapping segment to be laid out, determine the occupied length of the mapping segment to be laid out based on the target storage format, and determine the extended reserved length of the mapping segment to be laid out based on the update statistics. The layout evaluation module 400 is used to determine candidate HMB space units based on the HMB space description table, the occupied length and the extended reserved length, and to calculate a layout evaluation value for each candidate HMB space unit based on the space matching value, the cross-region storage quantity and the number of DMA accesses. The write update module 500 is used to determine the target HMB space unit based on the layout evaluation value, write the mapping segment to be laid out into the target HMB space unit according to the target storage format, and update the HMB space description table and the mapping segment description item of the mapping segment to be laid out.

[0064] This embodiment also provides a DRAM-less solid-state drive. The DRAM-less solid-state drive includes NAND Flash, a solid-state drive controller, and an interface for accessing the host memory buffer (HMB).

[0065] NAND Flash is used to store user data and metadata. The solid-state drive (SSD) controller is used to perform host command processing, L2P mapping management, HMB access, and mapping cache layout. The interface allows the SSD controller to access the host-allocated HMB. The SSD controller is configured to perform the aforementioned HMB mapping cache layout method for DRAM-less SSDs.

[0066] This embodiment also provides a computer-readable storage medium. The computer-readable storage medium stores program instructions executable by a solid-state drive controller. When the program instructions are executed, the solid-state drive controller performs the aforementioned HMB mapping cache layout method for DRAM-less solid-state drives.

[0067] The computer-readable storage medium is the firmware storage area inside the solid-state drive controller, the NAND Flash firmware area, or other non-volatile storage media that can be read by the solid-state drive controller.

[0068] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.

Claims

1. A method for HMB mapping cache layout for DRAM-less solid-state drives, characterized in that, A method for a solid-state drive (SSD) controller that does not have a dedicated DRAM cache, wherein the SSD controller caches L2P mapping information through a host memory buffer (HMB), the method comprising: S100: Obtain HMB region description information allocated by the host to the solid-state drive controller; establish an HMB space description table based on the HMB region description information; the HMB space description table records the region boundary information and continuous free space length of the HMB space unit. S200, the L2P mapping table is divided into multiple mapping segments according to the logical address range, and a mapping segment description item is established for each mapping segment. The mapping segment description item records the mapping segment identifier, logical address range, update statistics and HMB storage status. S300, determine the mapping segment to be laid out according to the mapping segment description item, determine the target storage format according to the correspondence between logical address and physical address in the mapping segment to be laid out, determine the occupied length of the mapping segment to be laid out according to the target storage format, and determine the extended reserved length of the mapping segment to be laid out according to the update statistics. S400, determine candidate HMB space units according to the HMB space description table, the occupied length and the extended reserved length, and calculate the layout evaluation value for each candidate HMB space unit based on the space matching value, the cross-region storage quantity and the DMA access count; S500, determine the target HMB space unit based on the layout evaluation value, write the mapping segment to be laid out into the target HMB space unit according to the target storage format, and update the HMB space description table and the mapping segment description item of the mapping segment to be laid out.

2. The method according to claim 1, characterized in that, S100 includes: Based on the host memory region start address and region length in the HMB region description information, the HMB is divided into multiple first-level spatial units, each of which corresponds to a continuous address range within a host memory region. Each primary spatial unit is divided into multiple secondary spatial units according to a preset management granularity; Record the idle status, occupied status, and the identifier of the mapping segment to which each secondary spatial unit belongs; The length of consecutive idle space within a first-level spatial unit is determined based on the number of consecutive idle second-level spatial units within the same first-level spatial unit. The starting address, region length, region boundary information, and continuous free space length of the first-level spatial unit are written into the HMB spatial description table.

3. The method according to claim 1, characterized in that, S200 includes: The L2P mapping table is divided according to a preset logical address span to obtain multiple mapping segments; or, the L2P mapping table is divided according to the logical address span corresponding to the block, superblock, stripe or channel interleaving range of the NAND Flash to obtain multiple mapping segments. Write the start logical address, end logical address, and mapping segment identifier of each mapping segment into the mapping segment description field of that mapping segment; When the mapping segment corresponding to the logical address range hit by the host read / write request is not stored in the HMB, or when the mapping segment already stored in the HMB is updated and meets the re-layout conditions, the corresponding mapping segment is determined as the mapping segment to be laid out.

4. The method according to claim 1, characterized in that, In step S300, determining the target storage format based on the correspondence between logical addresses and physical addresses within the mapping segment to be laid out includes: Obtain the physical address difference between adjacent logical addresses within the mapping segment to be laid out; The number of mapping entries that conform to a continuous mapping relationship is counted based on the physical address difference. The mapping continuity parameter is determined based on the ratio of the number of mapping items that conform to the continuous mapping relationship to the total number of mapping items in the mapping segment to be laid out. When the mapping continuity parameter is greater than or equal to the first threshold, the base address plus offset format is determined as the target storage format; When the mapping continuity parameter is less than the first threshold and the number of mapping items that do not conform to the continuous mapping relationship is less than or equal to the second threshold, the bitmap with exception format is determined as the target storage format. When the mapping continuity parameter is less than the first threshold and the number of mapping items that do not conform to the continuous mapping relationship is greater than the second threshold, the uncompressed format is determined as the target storage format.

5. The method according to claim 1, characterized in that, In step S300, determining the extended reserved length of the mapping segment to be laid out based on the updated statistical value includes: Read the lengths of multiple compressed mapping data of the mapping segment to be laid out within the statistics window from the updated statistics value; The size change parameter is determined based on the maximum value among the multiple compressed mapped data lengths and the current compressed mapped data length; The extended reserved length is determined based on the size change parameters, the preset reservation coefficient, and the preset management granularity of the HMB space description table; Write the extended reserved length into the mapping segment description item of the mapping segment to be laid out.

6. The method according to claim 1, characterized in that, In S400, Determining candidate HMB space units based on the HMB space description table, the occupied length, and the extended reserved length includes: Read the length of consecutive free space for each HMB space unit from the HMB space description table; HMB space units with a continuous free space length greater than or equal to the sum of the occupied length and the extended reserved length are identified as candidate HMB space units; Based on the starting address of the candidate HMB space unit, the region boundary information, the occupied length, and the extended reserved length, determine the number of host memory regions traversed and the number of storage segments formed when the mapping segment to be laid out is written into the candidate HMB space unit. The number of host memory regions traversed is taken as the cross-region storage quantity, and the number of storage fragments formed is taken as the DMA access count.

7. The method according to claim 1, characterized in that, In step S400, the layout evaluation value is calculated as follows: Determine the continuous free space length F of the candidate HMB space unit, the occupied length L, and the extended reserved length R; Calculate the spatial difference A, where A = FLR; When A is greater than or equal to 0, calculate the spatial matching value M based on A and the preset management granularity G, M=1 / (1+A / G); Determine the cross-region storage quantity B and the DMA access count Q when the mapping segment to be laid out is written to the candidate HMB space unit; The layout evaluation value S is calculated based on the spatial matching value M, the cross-region storage quantity B, and the DMA access count Q. S = W1×M - W2×B - W3×Q, where W1, W2, and W3 are preset weights, and W1, W2, and W3 are all positive numbers.

8. The method according to claim 1, characterized in that, The method further includes: When there is no HMB space unit in the HMB space description table with a continuous free space length greater than or equal to the sum of the occupied length and the extended reserved length, the mapping segment to be laid out is split into multiple mapping sub-segments according to the logical address order of the mapping segment to be laid out; Determine the segment length and segment storage address for each mapped segment; Write the multiple mapping segments into different HMB space units respectively; The mapping segment description item of the mapping segment to be laid out records the sub-segment number, logical address sub-range, sub-segment storage address and sub-segment occupied length of each mapping sub-segment.

9. The method according to claim 1, characterized in that, The method further includes: When a mapped segment already written to the HMB is updated, the target storage format and the length occupied after the update of the mapped segment are re-determined; Read the original occupied length and original extended reserved length from the mapping segment description item of the mapping segment; When the updated occupied length is less than or equal to the sum of the original occupied length and the original extended reserved length, the updated mapping segment is written into the original target HMB space unit of the mapping segment, and the mapping segment description item of the mapping segment is updated. When the updated occupied length is greater than the sum of the original occupied length and the original extended reserved length, the mapping segment is determined as a new mapping segment to be laid out, and S300 to S500 are executed.

10. An HMB mapping cache layout device for DRAM-less solid-state drives, characterized in that, include: The HMB space description module is used to obtain HMB region description information allocated by the host to the solid-state drive controller, and to establish an HMB space description table based on the HMB region description information. The HMB space description table records the region boundary information and continuous free space length of the HMB space unit. The mapping segment management module is used to divide the L2P mapping table into multiple mapping segments according to the logical address range, and to establish a mapping segment description item for each mapping segment. The mapping segment description item records the mapping segment identifier, logical address range, update statistics and HMB storage status. The length determination module is used to determine the mapping segment to be laid out based on the mapping segment description item, determine the target storage format based on the correspondence between logical addresses and physical addresses in the mapping segment to be laid out, determine the occupied length of the mapping segment to be laid out based on the target storage format, and determine the extended reserved length of the mapping segment to be laid out based on the update statistics. The layout evaluation module is used to determine candidate HMB space units based on the HMB space description table, the occupied length and the extended reserved length, and to calculate the layout evaluation value for each candidate HMB space unit based on the space matching value, the cross-region storage quantity and the number of DMA accesses. The write update module is used to determine the target HMB space unit based on the layout evaluation value, write the mapping segment to be laid out into the target HMB space unit according to the target storage format, and update the HMB space description table and the mapping segment description item of the mapping segment to be laid out.