A cpu performance analysis apparatus and method

Abstract

The application discloses a CPU performance analysis device and method, wherein the CPU performance analysis method comprises the following steps: inserting transaction monitoring logic on each key passage of the CPU to capture transaction messages on an interface protocol in real time; extracting key information in the transaction messages; temporarily storing the extracted key information into a cache array, each cache item recording all transactions on each data passage in the whole life cycle of a read-write operation; when the whole life cycle of a read-write operation ends, exporting the data recorded in the item in the cache array, and monitoring the cycle number of the whole life cycle of each read-write operation; classifying the exported data in the cache array; processing the classified data, extracting delay and bandwidth performance indexes; decomposing the delay and bandwidth performance indexes in time and space dimensions; and outputting the performance index change curves after decomposition, obtaining the influence of each decomposed performance index on the overall performance, and detecting the CPU performance.

Description

Technical Field

[0001] This invention relates to the field of computer architecture technology, and in particular to a CPU performance analysis device and method. Background Technology

[0002] PPA (Performance Power Area) is three important metrics for evaluating chip design. Correspondingly, functional verification, performance analysis, and power consumption assessment are crucial stages in the chip development process. Performance data monitoring and analysis can be categorized from various perspectives, including the object of monitoring and analysis, data sensitization methods, data collection mechanisms, and operating environments, resulting in multiple methods. Monitoring objects can be at the component level, subsystem level, or system-wide level. Regarding data sensitization methods, they can be applied to real-world application scenarios, standard test stimuli, or specific methods within a pre-silicon simulation environment. In terms of data collection mechanisms, standard performance test stimuli can be used to obtain system-wide performance results. For example, standard test stimuli linpack scores can be used to assess integer / floating-point computing capabilities, latency test results can be used to determine memory access latency, and standard test stream test results can be used to determine memory access bandwidth. Alternatively, performance parameters can be monitored, and then performance analysis-assisted design or specialized analysis tools or scripts can be used to analyze and process the monitored data to obtain performance results. In terms of runtime environment, tests can be performed on an architecture simulator, run on the pre-silicon Verilog implementation logic, or even run on silicon.

[0003] Architecture simulators model the chip's architecture and microarchitecture, obtaining performance data by running standard test stimuli, and then using this data to optimize the chip design. While performance monitoring based on architecture simulators is convenient and has low development costs, this type of performance analysis method suffers from discrepancies between simulator modeling and real chip design details. For performance metrics that are highly sensitive to latency or the number of resources such as buffer units, there are discrepancies between simulated and real performance results. Performance analysis methods based on real Verilog implementations are gradually becoming a more reliable approach.

[0004] Currently, performance analysis based on real chip designs mainly monitors some scattered performance data, which is not systematic. Moreover, the performance indicators are either limited to the overall performance results without decomposing the performance results, or limited to independent local performance indicators, which cannot intuitively reflect their impact on the overall performance indicators, or are based on architecture simulators and lack performance test scenarios of real designs. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a CPU performance analysis device and method capable of detecting CPU performance.

[0006] The first aspect of this invention provides a CPU performance analysis method, comprising the following steps: Insert transaction monitoring logic into each critical path of the CPU to capture transaction messages on the interface protocol in real time; The protocol analyzer extracts key information from transaction messages, including operation type, address, data size, unique transaction identifier, and timestamp. The extracted key information is temporarily stored in a cache array, and each cache item records all transactions on each data path throughout the entire lifecycle of a read and write operation; When a read / write operation reaches the end of its entire lifecycle, the data recorded in that entry in the cache array is exported, and the number of cycles in the entire lifecycle of each read / write operation is monitored. The data exported from the cache array is categorized according to the transaction type and the target device; The categorized data is processed online or offline to extract latency and bandwidth performance metrics. Decompose latency and bandwidth performance metrics into temporal and spatial dimensions to generate performance analysis results; Output the performance index change curves after decomposition to obtain the impact of each decomposed performance index on the overall performance.

[0007] Optionally, the key pathways include: transaction transmission channels between RN nodes and on-chip network, between on-chip network and HN nodes, and between on-chip network and SN nodes; high-speed interconnect protocol interfaces; and UCIE or CXL protocol interfaces.

[0008] Optionally, each item in the cache array is set with v and e fields. The v field indicates that the item is valid, and the e field indicates that the item has ended. The monitoring logic is responsible for making the item valid, and the export control unit is responsible for clearing it.

[0009] Optionally, when a read / write operation reaches the end of its entire lifecycle, the data recorded in that entry in the cache array is exported. Simultaneously, the number of cycles in the entire lifecycle of each read / write operation is monitored. Furthermore, if a read / write operation fails to complete for an extended period, an error is reported. The error reporting includes the following steps: The exception handling module detects in real time whether a read / write request has not been completed for a long time, or whether some transactions cannot be matched with cached items, or whether the number of cache array items is insufficient to cache new read / write operations. If so, the exception information is stored in the relevant register and an exception is reported.

[0010] Optionally, an address filter can be set before exporting the data recorded in this item in the cache array to filter read and write transactions within a preset address range.

[0011] Optionally, the categorized data can be processed online or offline to extract latency and bandwidth performance metrics, including: Extract time and read / write data volume information from the cache array data to obtain the transaction processing latency of hn and SN nodes, the transmission latency between rn, hn, and sn, and the data bandwidth of rn, hn, sn, or EXT nodes.

[0012] Optionally, the latency performance metrics are decomposed after processing by the latency / bandwidth extraction unit, including the following steps: Calculate the total latency of read and write operations; Decompose the transmission delay of the request from the RN node to the HN node; Decompose data or complete message transmission delay from HN node to RN node; Decompose the queuing time of HN nodes; Decomposition of SN nodes processing delay.

[0013] Optionally, the generated performance analysis results include: Obtain the maximum and minimum values ​​of the delay values ​​extracted by the delay / bandwidth extraction unit for each stage; After processing by the time slice performance analysis unit, the maximum delay, minimum delay, and average delay within a fixed time slice are calculated; Threshold filtering is applied to the calculated maximum, minimum, and average delay values ​​within a fixed time slice to filter out read and write operations that exceed the delay threshold or fall below the bandwidth threshold.

[0014] Optionally, the bandwidth performance metrics are decomposed after processing by the latency / bandwidth extraction unit, including the following steps: Calculate the total amount of data completed on each transmission path per unit time; Generate bandwidth curves for different data transmission paths.

[0015] A second aspect of the present invention provides a CPU performance analysis apparatus, including a processor, wherein the processor executes the steps of the CPU performance analysis method described above.

[0016] The technical solution provided by the embodiments of the present invention has the following advantages compared with the prior art: The CPU performance analysis device and method provided in this invention monitor the entire transaction lifecycle of each critical path in real chip design code, stores and analyzes the monitored transaction data in a capsule format, and decomposes the two important system-level performance indicators, latency and bandwidth, into temporal and spatial dimensions to accurately pinpoint system performance design bottlenecks in a timely manner. Simultaneously, it provides curves showing the changes of each performance indicator over time and space after the spatiotemporal decomposition, allowing for a direct understanding of the impact of each decomposed performance indicator on overall performance. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a typical CPU structure and capsule-type transaction monitoring provided in an embodiment of the present invention; Figure 2 This invention provides a top-down performance decomposition and analysis of the transaction capsule in an embodiment of the invention. Figure 3 This is a schematic diagram of the online data analysis unit structure provided in an embodiment of the present invention; Figure 4 This is a flowchart illustrating the CPU performance analysis method provided in an embodiment of the present invention. Detailed Implementation

[0018] The following detailed description of a specific embodiment of the present invention is provided in conjunction with the accompanying drawings. However, it should be understood that the scope of protection of the present invention is not limited to the specific embodiment.

[0019] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the technical solution of this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0020] The present invention will be described below through several specific embodiments. To keep the following description of the embodiments clear and concise, detailed descriptions of known functions and components may be omitted. When any component of an embodiment of the present invention appears in more than one drawing, the component may be represented by the same reference numerals in each drawing.

[0021] The first aspect of this invention provides a CPU performance analysis method, comprising the following steps: Insert transaction monitoring logic into each critical path of the CPU to capture transaction messages on the interface protocol in real time; The protocol analyzer extracts key information from transaction messages, including operation type, address, data size, unique transaction identifier, and timestamp. The extracted key information is temporarily stored in a cache array, and each cache item records all transactions on each data path throughout the entire lifecycle of a read and write operation; When a read / write operation reaches the end of its entire lifecycle, the data recorded in that entry in the cache array is exported, and the number of cycles in the entire lifecycle of each read / write operation is monitored. The data exported from the cache array is categorized according to the transaction type and the target device; The categorized data is processed online or offline to extract latency and bandwidth performance metrics. Decompose latency and bandwidth performance metrics into temporal and spatial dimensions to generate performance analysis results; Output the performance index change curves after decomposition to obtain the impact of each decomposed performance index on the overall performance.

[0022] The CPU performance analysis method provided in this invention monitors the entire transaction lifecycle of each critical path in real chip design code, stores and analyzes the monitored transaction data in a capsule format, and decomposes the two important system-level performance indicators, latency and bandwidth, into temporal and spatial dimensions to accurately pinpoint system performance design bottlenecks in a timely manner. Simultaneously, it provides curves showing the changes of each performance indicator over time and space after the spatiotemporal decomposition, allowing for a direct understanding of the impact of each decomposed performance indicator on overall performance.

[0023] To further decompose the latency and bandwidth of IO access or cross-DIE access in terms of time and space, the key paths include: transaction transmission channels between RN nodes and on-chip network, between on-chip network and HN nodes, and between on-chip network and SN nodes, high-speed interconnect protocol interfaces, and UCIE or CXL protocol interfaces.

[0024] Optionally, each item in the cache array is set with v and e fields. The v field indicates that the item is valid, and the e field indicates that the item has ended. The monitoring logic is responsible for making the item valid, and the export control unit is responsible for clearing it.

[0025] Optionally, when a read / write operation reaches the end of its lifecycle, the data recorded in that entry in the cache array is exported. Simultaneously, the number of lifecycle cycles for each read / write operation is monitored. Furthermore, if a read / write operation fails to complete for an extended period, an error is reported. The error reporting includes the following steps: The exception handling module detects in real time whether a read / write request has not been completed for a long time, or whether some transactions cannot be matched with cached items, or whether the number of cache array items is insufficient to cache new read / write operations. If so, the exception information is stored in the relevant register and an exception is reported.

[0026] To prevent identified performance defects or shortcomings from interfering with the screening of other performance defects or shortcomings, it may be necessary to exclude the identified performance defects or shortcomings. Therefore, before performing performance analysis on the data in the cached item, an address filter should be set before exporting the data recorded in that item from the cache array to filter read and write transactions within a preset address range.

[0027] Optionally, the categorized data can be processed online or offline to extract latency and bandwidth performance metrics, including: Extract time and read / write data volume information from the cache array data to obtain the transaction processing latency of hn and SN nodes, the transmission latency between rn, hn, and sn, and the data bandwidth of rn, hn, sn, or EXT nodes.

[0028] Optionally, the latency performance metrics are decomposed after processing by the latency / bandwidth extraction unit, including the following steps: Calculate the total latency of read and write operations; Decompose the transmission delay of the request from the RN node to the HN node; Decompose data or complete message transmission delay from HN node to RN node; Decompose the queuing time of HN nodes; Decomposition of SN nodes processing delay.

[0029] Optionally, the generated performance analysis results include: Obtain the maximum and minimum values ​​of the delay values ​​extracted by the delay / bandwidth extraction unit for each stage; After processing by the time slice performance analysis unit, the maximum delay, minimum delay, and average delay within a fixed time slice are calculated; Threshold filtering is applied to the calculated maximum, minimum, and average delay values ​​within a fixed time slice to filter out read and write operations that exceed the delay threshold or fall below the bandwidth threshold.

[0030] Optionally, the bandwidth performance metrics are decomposed after processing by the latency / bandwidth extraction unit, including the following steps: Calculate the total amount of data completed on each transmission path per unit time; Generate bandwidth curves for different data transmission paths.

[0031] A second aspect of the present invention provides a CPU performance analysis apparatus, including a processor, which executes the steps of the CPU performance analysis method described above.

[0032] The CPU performance analysis device and method of the present invention includes, on the one hand, monitoring and storing the entire lifecycle of transactions on each critical path in chip design; on the other hand, employing a top-down performance analysis method, decomposing indicators such as latency and bandwidth that affect overall performance results in both time and space dimensions, processing the collected transaction capsules online or offline, accurately calculating the maximum and minimum latency of each read and write transaction, as well as the data transmission bandwidth within different time slices, to locate scenarios with significant anomalies in read and write transaction latency and data transmission bandwidth on critical paths, so as to identify design defects affecting system performance through waveform analysis and other methods. Simultaneously, it provides curves showing the changes in read and write transaction latency, minimum latency, and average latency after spatiotemporal decomposition, as well as the maximum, minimum, and average bandwidth of critical data paths as a function of the program, intuitively obtaining the impact of each decomposed performance indicator on overall performance. Specific Implementation Example 1: To monitor the entire lifecycle of transactions on critical pathways, it is necessary to... Figure 1 The typical CPU design shown includes transaction monitoring logic. A typical CPU architecture contains processor cores or processor core clusters, a distributed or centralized directory management unit (DCM) including a directory management unit (DCU) and a request cache queue (ROPQ), and may also include an on-chip network cache layer, such as... Figure 1 The circles in the diagram indicate on-chip networks (BTCs) using interconnect protocols such as CHI (Conformity Hub Interface), crossbar switches, ring networks, or tile-type interconnects. These networks may contain DDR (Double Data Rate) synchronous dynamic random access memory, HBM (High Bandwidth Memory), or other types of storage. They may also include uCIE (Universal Encryption Interface), CXL (Compute Fast Link), or other types of DIE (Digital Interconnect) interfaces. Additionally, there are UART (Universal ART) ports for printing, flash memory for loading the bootloader, and PCIe (Peripheral Component Interconnect) interfaces for connecting various high-speed I / O devices. The uCIE ports, flash memory, and PCIe interfaces may be integrated into pluggable multi-purpose modules (PMMs) via high-speed interconnect protocols such as AXI (Advanced Extensible Interface) and then uniformly connected to the BTC network. Processor cores or core clusters, uCIE, CXL, or other types of DIE fast interconnect interfaces, and PCIe interfaces for connecting RC devices such as network cards, can all potentially initiate read / write requests to the CPU; therefore, they are collectively referred to as request nodes. Figure 1The diagram marked "1" is represented by RN0 to RNn. These include DDR, HBM, or other types of storage; uCIE, cXL, or other types of DIE inter-connection interfaces; a UART serial port for printing; flash memory for storing the bootloader; a PCIe interface for connecting SATA (Serial Advanced Technology Attachment) disks and other EP devices; and slave nodes (SNs). These slave nodes passively accept read / write requests from RN nodes. Figure 1 The figure marked "3" shows the directory management unit, responsible for directory and data consistency management, collectively referred to as the master node (HN), such as... Figure 1 As shown in the figure marked "2", the serial port UART for printing, the flash memory for storing the boot program, and the high-speed interconnect interface PCIe for connecting various high-speed I / O devices are integrated on the PMM unit through high-speed interconnect protocols such as AXI, and then connected to the on-chip network through protocol interfaces such as CHI. Therefore, they are collectively referred to as Extended Nodes (EXTs). Figure 1 As shown in the figure marked "4", Figure 1 The graphical representation of a monitor without added numbers, such as rn_mon, hn_mon, sn_mon, ext_mon.

[0034] To facilitate the decomposition of metrics affecting overall performance, such as latency and bandwidth, into temporal and spatial dimensions, transaction capsule monitoring units should be inserted into the transaction transmission channels between the RN node and the on-chip network, between the on-chip network and the HN node, and between the on-chip network and the SN node. These units should be named rn_mon, hn_mon, and sn_mon, respectively. To further decompose the latency and bandwidth of IO access or cross-DIE access into temporal and spatial dimensions, transaction monitoring units named ext_mon can be inserted into high-speed interconnect protocol interfaces such as AXI and protocol interfaces such as UCIE or CXL.

[0035] refer to Figure 2The `rn_mon`, `hn_mon`, `sn_mon`, and `ext_mon` functions capture transaction messages on the corresponding interface protocols in real time. These messages are then analyzed by the protocol analyzers `rn_ana`, `hn_ana`, `sn_ana`, and `ext_ana` to extract the necessary key information. The specific type and quantity of this key information depend on the type of the interface protocol. For example, for the CHI protocol, it is necessary to capture the opcode, address information (addr), data size, and ExpComAck (whether an ACK message needs to be sent back after receiving data) on the REQ (request) channel. This includes tgtid, srcid, txnid, ReturnNID, ReturnTxnID, etc., used to indicate transaction uniqueness, as well as the current value of the global clock calculator. The listening channel also includes srcid, txnid, FwdNID, FwdTxnID, etc., used for transaction uniqueness, as well as the current value of the global clock calculator. The data channel includes srcid, tgtid, txnid, DBID, HomeNID, etc., used for transaction uniqueness, as well as the current value of the global clock calculator. The response channel includes the opcode indicating the operation type, srcid, tgtid, txnid, DBID, etc., used for transaction uniqueness, as well as the current value of the global clock calculator. For the AXI protocol, it is necessary to capture the write address AWADDR of the write command channel, the AWID of the transaction, the AWLEN of the write data packet length, the AWSIZE of each data packet size, and the AWVALID and AWREADY indicating the validity of the packet, as well as the current value of the global clock calculator; the WID of the write data channel, the WVALID and WREADY indicating the validity of the packet, as well as the current value of the global clock calculator; the BID of the write response channel, the BVALID and BREADY indicating the validity of the packet, as well as the current value of the global clock calculator; the ARADDR of the read command channel, the ARID of the transaction, the ARLEN of the write data packet length, the ARSIZE of each data packet size, and the ARVALID and ARREADY indicating the validity of the packet, as well as the current value of the global clock calculator; and the RID of the read data channel, the RVALID and RREADY indicating the validity of the packet, as well as the current value of the global clock calculator.

[0036] After the above information is extracted, it is temporarily stored in the cache array. Each item in the cache array is used to temporarily store all transactions on each data path throughout the entire lifecycle of a read / write operation. The number of items is determined by the theoretical extreme value of the number of read / write transactions in the CPU during operation. The information of the fields contained in each item is as follows: Figure 2 As shown in the image.

[0037] rn_mon writes the opcode from the CHI protocol request channel, or the ARVALID and ARREADY from the AXI protocol read command channel, or the AWVALID and AWREADY from the AXI protocol write command channel, into the type field. The CHI protocol request message, or the AXI protocol read command channel message, or the AXI protocol write command channel message sent by the RN node marks the beginning of a read / write transaction. Therefore, rn_mon extracts the aforementioned key information and writes it into the rsi field of the empty buffer entry. Simultaneously, it writes the current value of the global clock calculator into the rst field.

[0038] If the read / write request eventually reaches the EXTN node, then the key information of each transaction message on each channel of the EXTN node interface protocol is written into the rexti field of the cache item. At the same time, the value of the global clock calculator at the corresponding time is written into the rextt field. The key information of each transaction message on each channel of the SN node interface protocol is written into the rtni field of the cache item. At the same time, the value of the global clock calculator at the corresponding time is written into the rtnt field. The key information of each transaction message on each channel of the HN node interface protocol is written into the rtn1i, rtn2i, etc. fields of the cache item. At the same time, the value of the global clock calculator at the corresponding time is written into the rt1t, rt2t fields. If the read / write request ultimately reaches only the SN node, then the key information from the transaction messages on each channel of the SN node interface protocol is written to the rtni field of the cache entry. Simultaneously, the value of the global clock calculator at the corresponding time is written to the rtnt field. Similarly, the key information from the transaction messages on each channel of the HN node interface protocol is written to the rtn1i, rtn2i, etc., fields of the cache entry shown in Figure 9. The value of the global clock calculator at the corresponding time is also written to the rt1t, rt2t fields. If the read / write request ultimately reaches only the HN node, then the key information from the transaction messages on each channel of the HN node interface protocol is written to the rtn1i, rtn2i, etc., fields of the cache entry. Simultaneously, the value of the global clock calculator at the corresponding time is written to the rt1t, rt2t fields. RN nodes may send read / write requests to multiple RN nodes and EXTN nodes; the rtni, rtnt fields and the rexti, rext fields can be flexibly reused.

[0039] On the one hand, even if a read / write operation requests to a specific target address, due to differences in data storage locations, the data may ultimately reach the SN node or EXT node, or it may only reach the HN node before the hit ends, resulting in significant latency differences. On the other hand, different SN or EXT nodes may have different logical distances from the RN node, and the operating frequencies of various modules in the chip also vary considerably, leading to large latency differences and making them incomparable. Therefore, hn_ana needs to fill in the prop field based on the SN node type and the actual data hit situation to differentiate between the above situations.

[0040] When an RN node initiates a new read / write operation, `rn_ana` occupies a free entry in the cache array. When the entire lifecycle of this read / write operation ends, all transaction data in the corresponding entry must be invalidated. To achieve this, a valid field `v` indicating whether the entry is free is set in the cache entry. This field is set by `rn_ana` and cleared by the export control unit `exporter`. Simultaneously, an end field `e` indicating whether the entire lifecycle of the read / write operation has ended is set. Depending on the actual situation, this field may be set by `rn_ana`, `hn_ana`, `sn_ana`, or `extn_ana` and cleared by the export control unit `exporter`.

[0041] When filling in the fields of the cache item, the exception handling module detects in real time whether a read / write request has not ended for a long time, or whether some transactions cannot be matched with cache items, or whether the number of cache array items is insufficient to cache new read / write operations. If so, the exception information is stored in the relevant registers for debugging.

[0042] When 'e' is enabled, the exporter is responsible for exporting the cached data to the classifier, while simultaneously clearing the 'e' and 'v' fields from the cached item.

[0043] Based on the type and prop fields, the Classifier sends all the data in the cached item to different data analysis modules for processing.

[0044] To prevent identified performance defects or shortcomings from interfering with the screening of other performance defects or shortcomings, it may be necessary to exclude the identified ones. Therefore, before performing performance analysis on the data in the cache, an address filter should be set to filter read and write transactions within a specific address range.

[0045] The filtered monitoring data can be processed in real time online or directly output to a server for subsequent offline analysis. For online processing, the online data analysis module first calculates the maximum, minimum, and average values ​​within a set time slice in real time. Then, these maximum, minimum, and average values ​​are printed in real time or stored in a designated storage space and exported uniformly. Alternatively, the maximum, minimum, and average values ​​over the entire time range can be calculated and stored in a register group for easy viewing. For offline processing, due to the massive amount of data, depending on the performance analysis objectives, sometimes only read / write operations exceeding a certain latency threshold or falling below a certain bandwidth threshold need to be monitored. Therefore, the data can be threshold-filtered before being stored in the designated storage space (mem). Once mem is full or the simulation ends, it can be exported for further processing. To avoid frequent simulation pauses for data export, a ping-pang dual-storage approach can be used for data writing and export.

[0046] Figure 3 This is a schematic diagram of the Data Online Analysis unit. First, by extracting the time and read / write data volume information from the cached data, the transaction processing latency of nodes hn and SN, the transmission latency between rn, hn, and sn, and the data bandwidth of nodes rn, hn, sn, or EXT can be calculated.

[0047] The entire lifecycle of a read / write operation definitely begins with the REQ request from the RN node, but the end time can vary. It could be the time when the data arrives at rn, the time when the data arrives at hn, sn, or ext, or the time when the completion message arrives at hn, sn, or ext. In this embodiment of the invention, rn_txREQ represents the time when the RN node issues the REQ request, rn_rxcmp represents the time when the RN node receives the data, hn_rxcmp represents the time when the HN node receives the data or completes the message, sn_rxcmp represents the time when the SN node receives the data or completes the message, and ext_rxcmp represents the time when the EXT node receives the data or completes the message. Therefore, the total delay of the read / write operation, t_total, is equal to rn / hn / sn / ext_rxcmp - rn_txREQ.

[0048] Let rn_txREQ represent the time when a REQ request is sent from the RN node, and hn_rxREQ represent the time when the REQ request arrives at the HN node. Then, the transmission delay from the RN node to the HN node is t_rn2hn = hn_rxREQ - rn_txREQ. Similarly, let hn_txcmp represent the time when a data or completion message is sent from the HN node, and rn_rxcmp represent the time when it arrives at the RN node. Then, the transmission delay from the HN node to the RN node is t_hn2rn = rn_rxcmp - hn_txcmp.

[0049] After receiving a REQ request, the HN node needs to queue and query the directory or on-chip network cache. Based on the query result, it can either send a listening signal to other RN nodes, send a REQ request to the SN node, or return data to the RN node. In this paper, the first case is represented as hn_txcmp, and the latter two are uniformly represented as hn_txREQ. Then, the queuing time for the HN node to process the REQ request is t_hndeal=hn_txcmp / hn_txREQ - hn_rxREQ.

[0050] Let sn_rxREQ represent the time it takes for a REQ request to arrive at the SN node. Then, the transmission delay of the REQ request from hn to the SN node is t_hn2sn = sn_rxREQ - sn_txREQ. Let sn_txcmp represent the time it takes for data or completion messages to be sent from the SN node and hn_rxcmp represent the time it takes to arrive at the HN node. Then, the transmission delay of data or completion messages from the SN node to the HN node is t_sn2hn = hn_rxcmp - hn_txcmp.

[0051] The delay from the SN node receiving the REQ request to returning data or a completion message to the HN node is t_sndeal = sn_cmp - sn_rxREQ, where sn_txcmp represents the time it takes for the SN node to return the data or completion message to the HN node. The t_sndeal delay includes the delay t_sn2exp = exp_rxREQ - sn_txREQ from the REQsn stage to the EXT node, the transmission delay t_exp2sn = sn_rxcmp - exp_txcmp from the data or completion message from the EXT node back to the SN node, and the delay t_extdeal = ext_rxcmp - ext_rxREQ from the EXT node receiving the REQ request to obtaining the data or completion message. In some interface protocols, the SN node directly returns data to the RN node; in this case, the transmission delay of the data or completion message is t_sn2rn = rn_rxcmp - sn_txcmp.

[0052] Data bandwidth is also a very important performance indicator. Based on the size field value in the CHI protocol REQ channel, or the AWLEN and AWSIZE values ​​in the AXI protocol write command channel, or the ARLEN and ARSIZE values ​​in the AXI protocol read command channel, the data volume of a single read / write operation can be calculated. By calculating the sum of the data volume of read / write operations completed between the rn, hn, sn, and EXT nodes per unit time, the data bandwidth on each transmission path can be obtained.

[0053] After processing by the delay / bandwidth extraction unit, the overall delay of read and write operations is decomposed in time, and the system data bandwidth is decomposed in space.

[0054] The minimum latency during the entire test reflects the theoretical minimum latency of the data path, while the maximum latency reflects the performance bottleneck in the data path design. The extracted latency values ​​from each stage are used to obtain the maximum and minimum values ​​using a bubble sort algorithm. To facilitate the identification of multiple bottlenecks, multiple maximum and minimum latency values ​​can be recorded. When new latency data is generated, a comparator checks if it is greater than `max_n`. If it is, the value of `max_n` is replaced with the newly generated value. Then, the values ​​of `max_n` and `max_(n-1)` are compared. If `max_n` is greater than `max_(n-1)`, they are compared again. This process is repeated until `max_0` and `max_1` are compared, thus obtaining the n maximum latency values ​​up to the current moment. A similar method can be used to obtain the n maximum latency values ​​up to the current moment.

[0055] While the maximum and minimum values ​​throughout the testing process can reveal the theoretical minimum latency of the data path and the performance bottleneck in the design, they cannot reflect the impact of program behavior on latency. Therefore, a time-slice performance analysis unit can be used to calculate the maximum, minimum, and average latency within a fixed time slice. This data can then be printed in real-time or exported and printed to generate curves showing the maximum, minimum, and average latency within the fixed time slice, facilitating the analysis of the impact of program behavior on latency.

[0056] Similarly, the data transmission bandwidth on each data channel can also be processed by the time slice processing unit to calculate the maximum, minimum, and average data bandwidth within a fixed time slice. Then, the maximum, minimum, and average bandwidth curves within the fixed time slice can be printed in real time or exported uniformly to facilitate the analysis of the impact of program behavior on bandwidth.

[0057] like Figure 4 As shown, the entire CPU performance analysis method includes the following steps: Step 1: Simulation begins.

[0058] Step 2: Determine if a reset is needed. If a reset is needed, proceed to Step 3; otherwise, proceed to Step 4. When running standard test records, in order to eliminate the influence of previously recorded data in the device, a reset is required to clear the previous data.

[0059] Step 3: The entire device enters a reset state, clears the values ​​in the buffer array and the registers for maximum, minimum, and average delay or bandwidth, as well as the exception register, and then returns to step 1.

[0060] Step 4: Determine if there is a record in the cache array whose read / write operation has timed out before the set time has expired. If so, proceed to step 5 for exception handling; otherwise, proceed to step 6.

[0061] Step 5: Set the corresponding bit of the exception handler according to the different exception types, and then return to the previous step.

[0062] Step 6: Determine whether any of rn_mon, hn_mon, sn_mon, and ext_mon have captured a new transaction.

[0063] Step 7: Determine the type of transaction. If the transaction is the start of a new read / write operation from the perspective of the on-chip network interface protocol, proceed to step 8; if the transaction is the end of a read / write operation from the perspective of the on-chip network interface protocol, proceed to step 12; otherwise, proceed to step 10.

[0064] Step 8: Determine if there are any free entries in the cache array. If not, proceed to step 5; if so, proceed to step 9.

[0065] Step 9: Write the key information into a free cache item, set the v field in that item to valid, and then return to step 1.

[0066] Step 10: Determine whether the detected transaction belongs to a read / write transaction in the cache array. If no match is found, proceed to step 5 for exception handling; if a match is found, proceed to step 11.

[0067] Step 11: Write the key information into the corresponding field of the corresponding cache item, and then return to step 1.

[0068] Step 12: Determine whether the detected transaction belongs to a read / write transaction in the cache array. If no match is found, proceed to step 5 for exception handling; if a match is found, proceed to step 13.

[0069] Step 13: Write the key information into the corresponding field of the corresponding cache item, and then proceed to step 14.

[0070] Step 14: Determine whether the read / write request needs to enter the extended node ext. If so, proceed to step 15; otherwise, directly access step 16.

[0071] In some designs, the extension node and the SN node use different interface protocols. In some protocols, the SN node cannot know whether the write operation of the EXT node has been completed. Therefore, to ensure that the data captured by ext_mon can match a certain item in the cache array, the transaction information recorded in the cache item can only be cleared after the read and write operations of ext are completed.

[0072] Step 15: Determine if the expansion node ext has been completed. If not, wait until it is completed before proceeding to step 16.

[0073] Step 16: Enable the 'e' value in the corresponding cache item, and then proceed to step 17.

[0074] Step 17: The exporter exports the data of the cached item where 'e' is set to valid, then clears the 'e' field, and then proceeds to step 18.

[0075] Step 18: Classify the data according to the type and prop values ​​recorded in the cache item, and then proceed to step 19.

[0076] The monitoring data corresponding to read and write operations at different data hit storage levels, regardless of the operation type, will be sent to different target devices and processed by different modules.

[0077] Step 19: Determine whether to perform online or offline processing. If online analysis and processing is required, proceed to step 20; if offline processing is required, proceed to step 25.

[0078] Step 20: Extract the latency data for each stage based on the time information in the cached data. Extract the data transmission bandwidth on different data transmission paths based on the read and write data volume information in the cached data. If it is necessary to calculate the maximum and minimum values ​​in the entire test process, proceed to step 21. If it is necessary to calculate the maximum, minimum, and average values ​​within each time slice, proceed to step 23.

[0079] Step 21: Use the bubble sort algorithm to determine whether the performance data at the current moment is greater than max_n or less than min_n. If so, proceed to step 22. Step 22: Swap the current performance data with max_n or min_n, and continue to compare the values ​​of max_n / min_n with max_(n-1) / min_(n-1). If max_n / min_n is greater than max_(n-1) / min_(n-1), then the two are swapped. Repeat this process until max_0 / min_0 and max_1 / min_1 are compared. Calculate the maximum and minimum values ​​of the delays and add them to the corresponding register groups for easy viewing.

[0080] Step 23: Divide the test process into many time slices of fixed length, and then proceed to step 24.

[0081] Step 24: Calculate the maximum, minimum, and average values ​​of latency or data bandwidth within each time slice, and then print them out in real time or export the data uniformly to print out the maximum, minimum, and average performance curves within a fixed time slice.

[0082] Step 25: Based on the performance analysis requirements, determine whether it is necessary to filter the data using performance thresholds. If so, proceed to step 26; otherwise, proceed directly to step 27.

[0083] Step 26: Filter the data according to the threshold, and then proceed to step 27.

[0084] Step 27: Specify the threshold-filtered data for storage space. Export the data when the memory is full or the simulation ends for further processing. To avoid frequently pausing the simulation to export stored data, a ping-pang dual-storage approach can be used for data writing and exporting.

[0085] The above inventions are merely a few specific embodiments of the present invention. However, the embodiments of the present invention are not limited thereto, and any variations that can be conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. A CPU performance analysis method, characterized in that, Includes the following steps: Insert transaction monitoring logic into each critical path of the CPU to capture transaction messages on the interface protocol in real time; The protocol analyzer extracts key information from the transaction message, including operation type, address, data size, unique transaction identifier, and timestamp. The extracted key information is temporarily stored in a cache array, and each cache item records all transactions on each data path throughout the entire lifecycle of a read and write operation; When a read / write operation reaches the end of its entire lifecycle, the data recorded in that entry in the cache array is exported, and the number of cycles in the entire lifecycle of each read / write operation is monitored. The data exported from the cache array is categorized according to the transaction type and the target device; The categorized data is processed online or offline to extract latency and bandwidth performance metrics. Decompose latency and bandwidth performance metrics into temporal and spatial dimensions to generate performance analysis results; Output the performance index change curves after decomposition to obtain the impact of each decomposed performance index on the overall performance. The key pathways include: transaction transmission channels between rn nodes and on-chip network, between on-chip network and hn nodes, and between on-chip network and sn nodes; high-speed interconnect protocol interfaces; and ucie or cxl protocol interfaces. The process of processing the classified data online or offline to extract latency and bandwidth performance metrics includes: Extract time and read / write data volume information from the cache array data to obtain the transaction processing latency of hn and sn nodes, the transmission latency between rn, hn, and sn, and the data bandwidth of rn, hn, sn, or ext nodes.

2. The CPU performance analysis method according to claim 1, characterized in that, Each item in the cache array is configured with v and e fields. The v field indicates that the item is valid, and the e field indicates that the item has ended. The monitoring logic is responsible for validating the item, and the export control unit is responsible for clearing it.

3. The CPU performance analysis method according to claim 1, characterized in that, When a read / write operation reaches the end of its entire lifecycle, the data recorded in that entry in the cache array is exported. Simultaneously, the number of cycles in the entire lifecycle of each read / write operation is monitored. Furthermore, if a read / write operation fails to complete for an extended period, an error is reported. This error reporting includes the following steps: The exception handling module detects in real time whether a read / write request has not been completed for a long time, or whether some transactions cannot be matched with cached items, or whether the number of cache array items is insufficient to cache new read / write operations. If so, the exception information is stored in the relevant register and an exception is reported.

4. The CPU performance analysis method according to claim 1, characterized in that, Before exporting the data recorded in the cache array, an address filter is set to filter read and write transactions within a preset address range.

5. The CPU performance analysis method according to claim 1, characterized in that, The latency performance metrics are decomposed after being processed by the latency / bandwidth extraction unit, including the following steps: Calculate the total latency of read and write operations; Decompose the transmission delay of the request from node rn to node hn; Decompose data or complete message transmission delay from node hn to node rn; Decompose the queuing time of node hn; Decomposition of the sn node processing delay.

6. The CPU performance analysis method according to claim 5, characterized in that, The performance analysis results include: Obtain the maximum and minimum values ​​of the delay values ​​extracted by the delay / bandwidth extraction unit for each stage; After processing by the time slice performance analysis unit, the maximum delay, minimum delay, and average delay within a fixed time slice are calculated; Threshold filtering is applied to the calculated maximum, minimum, and average delay values ​​within a fixed time slice to filter out read and write operations that exceed the delay threshold or fall below the bandwidth threshold.

7. The CPU performance analysis method according to claim 1, characterized in that, The bandwidth performance metrics are decomposed after being processed by the latency / bandwidth extraction unit, including the following steps: Calculate the total amount of data completed on each transmission path per unit time; Generate bandwidth curves for different data transmission paths.

8. A CPU performance analysis device, characterized in that, Includes a processor, which, when executed, implements the steps of the CPU performance analysis method as described in any one of claims 1 to 7.

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