Protocol conversion method, device, medium and computer program product

Abstract

The application discloses a protocol conversion method and device, a medium and a computer program product, relates to the technical field of computers, and identifies the instruction type after receiving the request instruction of a host computer; according to the instruction type, a corresponding target function master state is determined and the first subdivided state thereof is jumped to; according to the preset order of each subdivided state in the target function master state, an orderly jump is executed based on a set condition, and the processing of host-side instruction analysis, storage device-side instruction generation, storage device-side instruction execution feedback waiting, host-side response generation is sequentially performed, so as to complete the bidirectional conversion of the host-side protocol and the storage device-side protocol; if an unexpected situation is detected, the jump is made to an unexpected master state, error information is collected, an error response is generated, and the idle state is backed up. In this way, the protocol bidirectional conversion of the host and the storage device can be realized, the instruction mapping and operation granularity adaptation problems can be solved, the abnormal handling mechanism can be unified, and the system cooperation efficiency and the operation stability are improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a protocol conversion method, apparatus, medium, and computer program product. Background Technology

[0002] In traditional architectures where host and storage devices work together, protocol conversion between the two relies heavily on software drivers. Due to the inherent heterogeneity between the memory semantics of host-side instructions and the block storage semantics of storage device-side instructions, and the lack of a bidirectional protocol conversion mechanism, fine-grained and coarse-grained operations cannot be flexibly adapted, making it difficult to meet the collaborative needs of high-performance scenarios. Furthermore, the independent exception handling logic of the host and storage devices makes them highly susceptible to system stability issues due to exception propagation. Summary of the Invention

[0003] This invention provides a protocol conversion method, device, medium, and computer program product to at least solve the problems of mismatched semantic operation granularity between memory and block storage, low protocol conversion efficiency, and inconsistent exception handling mechanisms in related technologies.

[0004] This invention provides a protocol conversion method, comprising: After receiving a request instruction in host-side protocol format sent by the host, identify the type of the request instruction; Based on the type of the request instruction, determine the corresponding target function main state and jump to the first sub-state of the target function main state; each function main state contains multiple sub-states; According to the preset order of each sub-state in the main state of the target function, an orderly jump is performed based on the set conditions, and the host-side instruction parsing, storage device-side instruction generation, storage device-side instruction execution feedback waiting, and host-side response generation are performed in sequence to complete the bidirectional conversion between the host-side protocol and the storage device-side protocol; after the processing is completed, it returns to the idle state. If an unexpected situation is detected during processing, the system jumps to the unexpected main state, collects error information, generates an error response in the host-side protocol format, and then falls back to the idle state.

[0005] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described protocol conversion methods when executing the computer program.

[0006] The present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described protocol conversion methods.

[0007] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described protocol conversion methods.

[0008] This invention enables precise matching of host requirements by receiving request instructions in host-side protocol format and identifying the instruction type, providing a clear direction for subsequent protocol conversion. It determines the corresponding target function main state based on the request instruction type and jumps to the first sub-state, achieving categorized processing of different request types. Combining the multiple sub-states within each function main state allows for targeted adaptation to different instruction processing needs, resolving the operational granularity differences between memory semantics and block storage semantics, supporting fine-grained access, and adapting to both fine-grained and coarse-grained operational differences. Following the preset order of the sub-states within the target function main state, it performs ordered jumps based on set conditions, sequentially completing host-side instruction parsing, storage device-side instruction generation, and storage device-side instruction execution feedback waiting. The processing of host-side response generation effectively solves the problem of accurate mapping between host instructions and storage device instructions, enabling bidirectional conversion between host-side protocols and storage device protocols. This facilitates efficient collaboration between the host and storage devices, while achieving low-latency direct interaction between host and storage device caches. After processing, the system returns to an idle state, ensuring it is ready to receive the next host request, further improving collaboration efficiency and response speed. If an unexpected situation is detected during processing, the system jumps to an unexpected main state, collects error information, generates an error response in the host-side protocol format, and then falls back to the idle state. This effectively solves the compatibility problem between host and storage device exception mechanisms. By uniformly handling various exception scenarios, the system avoids exception propagation and significantly improves the stability of the entire system.

[0009] In addition, the present invention also provides corresponding electronic devices, computer-readable storage media and computer program products for the protocol conversion method, which have the same or corresponding technical features as the protocol conversion method mentioned above, and have the same effect. Attached Figure Description

[0010] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A flowchart of the protocol conversion method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the overall architecture of the protocol conversion device provided in an embodiment of the present invention; Figure 3This is a flowchart illustrating the state machine performing related processes according to an embodiment of the present invention. Figure 4 This is a schematic diagram of different states in a state machine provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the protocol conversion device provided in an embodiment of the present invention. Detailed Implementation

[0012] In practical applications, the host can include a Compute Express Link (CXL) host; storage devices can include solid state drives (SSDs). The CXL protocol, with its low latency and high bandwidth, has become the protocol for interconnecting the CPU and memory / accelerator; while SSDs, as mainstream storage devices, rely on proprietary protocols such as Non-Volatile Memory Express (NVMe) for communication. The CXL protocol focuses on low-latency, high-bandwidth interconnect communication, primarily oriented towards memory semantics and cache consistency design, while the SSD protocol emphasizes fine-grained control of storage operations, such as Logical Block Address (LBA) addressing and Input / Output (IO) queue management. Significant differences exist between the two in instruction format, timing constraints, and functional logic, making direct interoperability impossible. CXL accesses memory on a byte / cache line basis, while NVMe transmits data on LBA blocks (e.g., 4KB), lacking a fine-grained to coarse-grained instruction mapping mechanism; SSDs only support the NVMe protocol and cannot directly parse CXL instructions. This invention can solve this technical problem.

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0014] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0015] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] The specific application environment architecture or specific hardware architecture on which the execution of the protocol conversion method depends is described here.

[0017] The embodiments of the present invention provide a protocol conversion method, and the method is described in detail below in conjunction with the execution flow of the protocol conversion method. Figure 1 A flowchart of the protocol conversion method provided in the embodiments of the present invention is shown below. Figure 1 As shown, the method includes: S101. After receiving the request instruction in host-side protocol format sent by the host, identify the type of the request instruction.

[0018] It should be noted that the execution subject of this invention can be a programmable logic device with integrated state machine logic. That is, the protocol conversion method of this invention is applied to a programmable logic device with integrated state machine logic. All state machine logic and protocol conversion processes are integrated into the hardware carrier of the programmable logic device, forming a protocol conversion device. This programmable logic device can be a Field Programmable Gate Array (FPGA). Based on the hardware carrier of the programmable logic device, this invention can realize a highly integrated, low-latency protocol conversion device, clearly defining the connection methods between the module and the host (such as a CXL host) and storage devices (such as SSDs). This protocol conversion device can be an FPGA-based CXL-SSD protocol conversion device, the core of which is an FPGA hardware carrier, a finite state machine (FSM) with a main state and subdivided state two-level architecture. The module connects to the CXL host through a CXL interface and to the SSD through an NVMe interface.

[0019] In implementation, before receiving the request instruction sent by the host, the process may include: configuring parameters using a debugging interface, and entering an idle state after initialization; the parameter configuration includes address mapping rules, cache size, and setting timeout thresholds. The protocol converter of this invention integrates state machine logic into a programmable logic device, directly connecting the host and storage device through a host interface and a storage device interface to achieve low-latency hardware-level conversion. It allows configuration of internal parameters of the programmable logic device, such as LBA mapping rules, cache size, and exception timeout thresholds, adapting to different models of host and storage devices. Entering an idle state after initialization ensures the hardware is in a ready-to-go state. Upon receiving a request instruction in the host-side protocol format, instruction type identification is prioritized. This step is a crucial prerequisite for subsequent classification and processing according to the preset state machine process, enabling rapid matching of the corresponding functional main state.

[0020] S102. Based on the type of the request instruction, determine the corresponding target function main state and jump to the first sub-state of the target function main state; each function main state contains multiple sub-states.

[0021] In implementation, the main functional state is integrated into the state machine. It comprises functional processing modules for different types of request instructions from the host side, containing several sequentially connected sub-states to complete the entire hardware-level transformation from instruction parsing to response. This invention, through a one-to-one correspondence between instruction types and target main functional states, can match corresponding processing flows to different instruction requirements such as read, write, and cache consistency. Furthermore, the hierarchical design of the sub-states within each main functional state further decomposes complex protocol conversions into sequentially connected sub-steps, ensuring the accuracy of instruction mapping between the host and storage devices while improving the stability and scalability of the state machine.

[0022] S103. According to the preset order of each sub-state in the main state of the target function, perform ordered jumps based on the set conditions, and sequentially perform host-side instruction parsing, storage device-side instruction generation, storage device-side instruction execution feedback waiting, and host-side response generation to complete the bidirectional conversion between the host-side protocol and the storage device-side protocol; after the processing is completed, return to the idle state.

[0023] In implementation, this invention breaks down protocol conversion into four key steps—host-side instruction parsing, storage device-side instruction generation, execution feedback waiting, and host-side response generation—through ordered state transitions according to a preset sequence and set conditions. This achieves precise mapping and bidirectional conversion of instruction semantics between the host and storage devices. The design of returning to an idle state after processing ensures both efficient reuse of hardware resources and rapid response to subsequent host requests, supporting the requirements for low-latency and high-stability protocol conversion at the execution logic level. The set conditions can include three conditions: instruction triggering, timing completion, and device status.

[0024] S104. If an unexpected situation is detected during processing, jump to the unexpected main state, collect error information and generate an error response in the host side protocol format, and then fall back to the idle state.

[0025] In implementation, this invention can uniformly capture unexpected situations such as instruction parsing errors, execution timeouts, and storage device feedback anomalies throughout the entire protocol conversion process by setting an independent unexpected main state. It relies on hardware logic to quickly complete error information collection and host-side protocol format error response generation, avoiding the spread of anomalies that affect subsequent instruction processing. The design of falling back to the idle state after processing ensures that the state machine can quickly recover to the standby state, guaranteeing the continuity and stability of system operation.

[0026] In the protocol conversion method provided in this embodiment of the invention, receiving a request instruction in host-side protocol format sent by the host and identifying the instruction type can accurately match host requirements and provide a clear direction for subsequent protocol conversion; determining the corresponding target function main state according to the request instruction type and jumping to the first sub-state realizes the classification and processing of different types of requests; combining the multiple sub-states contained in each function main state can specifically adapt to the processing requirements of different instructions, solve the difference in operation granularity between memory semantics and block storage semantics, support fine-grained access, and adapt to the difference between fine-grained and coarse-grained operations; according to the preset order of each sub-state in the target function main state, ordered jumps are performed based on set conditions, sequentially completing host-side instruction parsing, storage device-side instruction generation, and storage device-side instruction... The system handles feedback waiting and host-side response generation, effectively resolving the precise mapping issue between host instructions and storage device instructions. It enables bidirectional conversion between host-side and storage device protocols, thereby achieving efficient collaboration between the host and storage devices. Simultaneously, it allows for low-latency direct interaction between host and storage device caches. After processing, it returns to an idle state, ensuring the system is ready to receive the next host request, further improving collaboration efficiency and response speed. If an unexpected situation is detected during processing, it jumps to an unexpected main state, collects error information, generates an error response in the host-side protocol format, and then falls back to the idle state. This effectively solves the compatibility issue between host and storage device anomaly mechanisms. By uniformly handling various anomaly scenarios, it prevents anomaly propagation and significantly improves the overall system stability.

[0027] Figure 2 This is a schematic diagram of the overall architecture of the protocol conversion device provided in an embodiment of the present invention. Figure 2 As shown, the protocol converter can integrate sub-modules such as protocol parsing, address mapping, state machine control, data caching, cache consistency control, and exception handling to achieve hardware-level protocol conversion between CXL and NVMe. The input of the protocol converter connects to the CXL host via the CXL host interface, receiving commands and data sent by the CXL host. The output of the protocol converter connects to the SSD via the NVMe interface, sending NVMe read / write / refresh / management commands to the SSD and receiving data and status returned by the SSD. The protocol converter supports Joint Test Action Group (JTAG) debugging, and module parameters such as LBA mapping rules, cache size, and exception timeout thresholds can be configured through configuration registers. In other words, the programmable logic device integrating state machine logic can complete the hardware logic programming and debugging through the JTAG interface, realizing the functional solidification and operational monitoring of the protocol conversion state machine.

[0028] Taking CXL and SSD as examples, such as Figure 2As shown, the host interface module adapts the CXL protocol's physical and data layers, receiving commands and data from the CXL host and sending converted responses. The command parsing module parses key parameters such as CXL command type, target address, and data length. The state machine core module adopts a two-level architecture of main state and subdivided states, serving as the core logic for protocol conversion. The address mapping module maps fine-grained CXL addresses (bytes / cache lines) to NVMe LBA block addresses. The data caching module temporarily stores data transmitted between CXL and NVMe, adapting to differences in read and write speeds. The cache consistency control module receives CXL cache commands and triggers NVMe refresh commands to ensure data consistency. The exception handling module handles exceptions such as CXL Retry and NVMe errors, generating targeted error responses. The storage device interface module adapts the NVMe protocol, sending commands and data to the SSD and receiving the SSD's execution results.

[0029] Figure 3 This is a schematic diagram illustrating the process of a state machine performing related processing, as provided in an embodiment of the present invention. Figure 3 As shown, after system initialization, it enters the idle state. After receiving a request instruction from the host, it jumps to the first sub-state of the corresponding main state according to the instruction type. After the entire process of parsing, generating, waiting, and responding is completed, it returns to the idle state. If an abnormality is detected in any step, it jumps to the abnormal main state for handling, and then falls back to the idle state after completion.

[0030] Furthermore, in specific implementations, in the protocol conversion method provided in the embodiments of the present invention, the functional master state may include a read operation master state, a write operation master state, and a cache consistency operation master state. Step S102 determines the corresponding target functional master state according to the type of the request instruction, which may specifically include: retrieving a preset mapping relationship between instruction types and functional master states, and matching the corresponding target functional master state according to the mapping relationship and the type of the request instruction; wherein, when the type of the request instruction is a read request instruction, the read operation master state is matched; when the type of the request instruction is a write request instruction, the write operation master state is matched; and when the type of the request instruction is a cache consistency instruction, the cache consistency operation master state is matched.

[0031] In practice, this invention can quickly match the corresponding functional main state for different types of host request instructions, such as read, write, and cache consistency, by invoking a preset instruction type-functional main state mapping relationship, thus ensuring the targeting and efficiency of instruction processing and improving the scalability and maintainability of the state machine logic.

[0032] Figure 4 This is a schematic diagram of different states in a state machine provided in an embodiment of the present invention. For example... Figure 4As shown, the main state for read operations is divided into four sub-states: first, host read instruction parsing; second, storage device read instruction generation; third, storage device read operation waiting; and fourth, host read response generation. Similarly, the main state for write operations is divided into four sub-states: first, host write instruction parsing; second, storage device write instruction generation; third, storage device write operation waiting; and fourth, host write response generation. The main state for cache consistency operations is divided into four sub-states: first, host cache instruction parsing; second, storage device refresh instruction generation; third, storage device refresh waiting; and fourth, host cache response generation. The main state for unexpected events is divided into four sub-states: first, instruction error; second, operation error; and third, abnormal response.

[0033] Furthermore, in specific implementation, in the protocol conversion method provided in the embodiments of the present invention, when jumping to the host read instruction parsing state, an ordered jump is performed based on set conditions to perform host-side instruction parsing processing, which may specifically include: receiving the data frame of the request instruction and the storage device namespace configuration parameters; parsing the data frame to extract key information from the request instruction; the key information includes the target address and data length defined by the host-side protocol; mapping the target address to the target logical block address of the storage device; determining whether the target logical block address is within a preset range according to the storage device namespace configuration parameters; if the target logical block address is within the preset range, jumping to the storage device read instruction generation state; if the target logical block address is not within the preset range, jumping to the instruction error state in the unexpected main state.

[0034] In implementation, the main read operation state handles two types of instructions: memory read and cache read. It completes the entire process from instruction parsing to response feedback through at least four sub-states. Taking CXL and SSD as examples, the CXL read instruction parsing state (CXL_R_PARSE) parses key information about the CXL read request, specifically including the instruction type (e.g., memory read / cached read), the memory target address defined by the CXL protocol, the data length, and the number of bytes read in a single operation. The input signals for this state include the complete CXL instruction frame (containing opcode, address, and length fields) and SSD namespace configuration parameters (used to determine address validity). The output signals are an instruction type flag (distinguishing between memory read and cache read), a valid instruction flag (1 for valid address, 0 for invalid address), and the converted storage device target logical block address (i.e., converting the host-side protocol address to a storage device logical block address using address mapping rules). If a valid instruction is marked as 1, the system jumps to the memory device read instruction generation state; if a valid instruction is marked as 0 (e.g., the converted target logical block address exceeds the memory device namespace range), the system jumps to the instruction error state (EXCEP_CMD_ERR) in the unexpected main state. The read operation main state achieves efficient adaptation of host-side protocol and memory device-side protocol instruction information through precise extraction of key parameters of the host-side read request, standardized address mapping conversion, and hardware-level validity judgment logic. This not only improves the accuracy and timeliness of instruction parsing but also avoids invalid instruction flow by promptly identifying illegal addresses and jumping to the exception handling state, further ensuring the stability and reliability of bidirectional protocol conversion.

[0035] Furthermore, in a specific implementation, in the protocol conversion method provided in the embodiments of the present invention, when jumping to the storage device read instruction generation state, an ordered jump is performed based on set conditions to process the generation of storage device-side instructions. Specifically, this may include: receiving the instruction type flag, target logical block address, data length, and host request priority signal output from the host read instruction parsing state; selecting the corresponding storage device-side read instruction identifier according to the instruction type flag; allocating the corresponding storage device instruction queue identifier according to the host request priority signal and generating a queue selection signal; generating a storage device-side read instruction data frame based on the storage device-side read instruction identifier, queue selection signal, target logical block address, and data length; and jumping to the storage device read operation waiting state after the storage device-side read instruction data frame is generated and the timing parameters are configured.

[0036] In implementation, the storage device read instruction generation state generates the corresponding storage device-side read instruction data frame based on the output of the host read instruction parsing state. Taking CXL and SSD as examples, the SSD read instruction generation state (SSD_R_GEN) functions as follows: selecting the NVMe read instruction opcode (fixed configuration is 0x02) according to the instruction type flag, filling in the LBA address, which comes from the mapping result of CXL_R_PARSE, configuring parameters consistent with the host-side instruction data length, and allocating the storage device instruction queue identifier according to the CXL request priority signal (high priority requests are allocated to queue 0, and low priority requests are allocated to queue 1). The input signals of this state are the instruction type flag, the target logical block address, the data length, and the CXL priority signal, and the output signals are the complete NVMe read instruction data frame and the queue selection signal indicating the target NVMe queue; when the NVMe read instruction data frame is generated and the timing parameters are configured, it jumps to the storage device read operation waiting state. The storage device read instruction generation status achieves efficient conversion from host-side read requests to storage device-side read instructions through precise hardware-level parameter mapping, priority-oriented queue allocation mechanism, and timing configuration verification logic. This ensures the consistency and accuracy of instruction parameters and improves the response efficiency of high-priority requests through priority scheduling.

[0037] Furthermore, in a specific implementation, in the protocol conversion method provided in the embodiments of the present invention, when jumping to the storage device read operation waiting state, an ordered jump is performed based on set conditions to perform storage device-side instruction execution feedback waiting processing, which may specifically include: receiving storage device-side read instruction data frames and sending storage device-side read instruction data frames to the storage device through the storage device interface; monitoring the operation completion signal and latched data fed back by the storage device; when the latched data is detected to be valid, generating a data latch control signal and storing the latched data in the local cache; if the operation completion signal is detected to be valid and the data latch is completed, jumping to the host read response generation state; if no operation completion signal is received and the monitoring time exceeds the preset timeout threshold, or if an error flag is received from the storage device, jumping to the operation error state in the unexpected main state.

[0038] In implementation, the storage device read operation wait state is responsible for sending the storage device-side read instruction data frame to the storage device and waiting for the execution result. Taking CXL and SSD as examples, the functions of the SSD read operation wait state (SSD_R_WAIT) include: sending NVMe read instruction frames through the NVMe interface, monitoring the operation completion signal returned by the SSD in real time, and latching the read data (SSD_DATA) output by the SSD DRAM; the input signals of this state are the NVMe read instruction frame, the SSD Completion signal, and the SSD output data, and the output signal is the data latch control signal, which is used to store the SSD output data into the local cache. The state transition logic is set as follows: when the SSD operation completion signal is detected to be valid and the data latch is completed, it jumps to the CXL read response generation state; if the monitoring time exceeds the preset timeout threshold (such as 100 clock cycles) and no operation completion signal is received, or an error flag is received from the SSD, it jumps to the operation error exception state in the unexpected main state. The read operation waiting state of storage devices achieves precise linkage between instruction transmission and execution feedback through hardware-level timing monitoring mechanism and data latching logic. This not only ensures the integrity of read data and the timeliness of cache storage, but also effectively avoids process blockage caused by instruction execution abnormalities through dual protection of timeout judgment and error capture, significantly improving the stability and efficiency of protocol interaction.

[0039] Furthermore, in a specific implementation, in the protocol conversion method provided in the embodiments of the present invention, when jumping to the host read response generation state, an ordered jump is performed based on set conditions to process the host-side response generation. Specifically, this may include: receiving latched data output from the storage device read operation waiting state and the operation status code fed back by the storage device; extracting key information from the operation status code to determine the execution result of the storage device read operation; when the execution result is successful, converting the latched data into a host-side protocol-compatible data format to generate a host-side read response data frame; when the execution result is unsuccessful, extracting the error status code and jumping to the operation error state in the unexpected main state; sending the host-side read response data frame to the host and detecting the response sending completion status; confirming that the response sending is complete, clearing the status flag bit and jumping back from the host read response generation state to the idle state.

[0040] In implementation, the host read response generation state is responsible for converting the read operation result of the storage device into a host protocol-compatible response format and feeding it back to the host. Taking CXL and SSD as examples, the functions of the CXL read response generation state (CXL_R_RESP) include: receiving the latched SSD_DATA output from the storage device read operation wait status and the status code fed back by the SSD; extracting key information from the status code to determine the execution result of the SSD read operation; when the execution result is successful, converting the latched SSD_DATA into a CXL protocol-compatible data format according to the CXL bus width, and generating a CXL read response frame containing a response opcode, data field, and status field. The input signals of this state are the latched SSD_DATA and the SSD status code, and the output signals are the CXL read response frame and a response transmission completion signal indicating that the response has been successfully sent; when the response transmission is completed and the data valid bit, error flag bit, and other status flag bits are cleared, it jumps back to the idle state. The host read response generation status achieves accurate conversion and reliable feedback of read operation results to the host side response through standardized data format conversion logic and status flag control mechanism. This ensures the consistency and integrity of data transmission, and ensures efficient reuse of hardware resources through status flag clearing operation, significantly improving the closed-loop efficiency and stability of protocol bidirectional conversion.

[0041] Furthermore, in specific implementation, in the protocol conversion method provided in the embodiments of the present invention, when jumping to the host write instruction parsing state, an ordered jump is performed based on set conditions to perform host-side instruction parsing processing, which may specifically include: receiving the data frame of the request instruction, the host-side data to be written, and the storage device write protection configuration parameters; parsing the data frame to extract key information from the request instruction; the key information includes the target address and data length defined by the host-side protocol; mapping the target address to the target logical block address of the storage device, and storing the host-side data to be written into the local cache; determining whether the target logical block address is within a preset range according to the storage device write protection configuration parameters; if the target logical block address is within the preset range, jumping to the storage device write instruction generation state; if the target logical block address is not within the preset range, jumping to the instruction error state in the unexpected main state.

[0042] In implementation, the main write operation state handles memory write and cache write instructions, and also implements the entire process through at least four sub-states. Taking CXL and SSD as examples, the CXL write instruction parsing state (CXL_W_PARSE) includes parsing key information of the CXL write request, including instruction type (MemoryWrite / CacheWrite), target address, write data (i.e., the data to be written on the CXL bus), and data length. The input signals for this state include the CXL instruction frame (containing opcode, address, and length fields), CXL write data (CXL_DATA), and SSD write protection configuration (indicating whether the target area is writable); the output signals are the instruction type flag, the valid instruction flag (1 for valid, 0 for invalid, such as when the target area is write-protected), the converted SSD target LBA address, and the write data caching control signal used to start local cache storage of CXL_DATA. When the valid instruction flag is 1, the process jumps to the storage device write instruction generation state; if the valid instruction flag is 0, the process jumps to the instruction error state. The host write command parsing status achieves accurate extraction and preprocessing of key information of write requests through integrated command parsing, address mapping and data caching control logic. Combined with the legality verification mechanism based on write protection configuration, it effectively intercepts illegal write requests and significantly improves the security and efficiency of the protocol conversion process.

[0043] Furthermore, in a specific implementation, in the protocol conversion method provided in the embodiments of the present invention, when jumping to the storage device write instruction generation state, an ordered jump is performed based on set conditions to process the generation of storage device-side instructions. Specifically, this may include: receiving the instruction type flag, target logical block address, data length, host request priority signal, and host-side data to be written in the local cache from the host write instruction parsing state output; selecting the corresponding storage device-side write instruction identifier according to the instruction type flag; allocating the corresponding storage device instruction queue identifier and generating a queue selection signal according to the host request priority signal; storing the host-side data to be written in the local cache into the data buffer corresponding to the storage device; generating a storage device-side write instruction data frame based on the storage device-side write instruction identifier, queue selection signal, target logical block address, and data length; and jumping to the storage device write operation waiting state after the storage device-side write instruction data frame is generated and the data cache is ready.

[0044] In implementation, the storage device write instruction generation state generates the corresponding storage device write instruction data frame based on the output of the host write instruction parsing state. Taking CXL and SSD as examples, the SSD write instruction generation state (SSD_W_GEN) functions as follows: selecting the NVMe write instruction opcode fixed at 0x01, filling in the parsed SSD target LBA address, configuring the data length consistent with the CXL write request, allocating the NVMe queue ID according to the same priority rules as read operations, and simultaneously storing the CXL_DATA in the local cache into the corresponding data buffer of the SSD. The input signals for this state are the instruction type flag, LBA address, data length, CXL priority, and cached CXL_DATA; the output signals are the NVMe write instruction frame, the queue selection signal, and the write data cache completion signal indicating that CXL_DATA is ready. When the NVMe write instruction frame is generated and the data cache is complete, the state transitions to the storage device write operation waiting state. The storage device write instruction generation status achieves accurate conversion of write requests to instructions on the storage device side and data preprocessing through standardized instruction parameter configuration, priority queue allocation, and data cache linkage logic. This ensures the consistency of instruction parameters and the timeliness of data preparation, and improves the efficiency and stability of the overall protocol conversion.

[0045] Furthermore, in a specific implementation, in the protocol conversion method provided in the embodiments of the present invention, when jumping to the storage device write operation waiting state, an ordered jump is performed based on set conditions to process the storage device-side instruction execution feedback waiting. Specifically, this may include: receiving the storage device-side write instruction data frame, the queue selection signal, and the data to be written in the storage device data buffer; determining the target instruction queue according to the queue selection signal; sending the storage device-side write instruction data frame and the data to be written to the storage device through the storage device interface; tracking the process of the data to be written from the storage device cache to the flash memory and generating a waiting cycle count signal; monitoring the operation completion signal, write confirmation signal, and whether there is an operation error fed back by the storage device; if the operation completion signal is valid, the write confirmation signal is valid, and no operation error occurs, jumping to the host write response generation state; if no operation completion signal is received and the monitoring time exceeds the preset timeout threshold, or if an error flag is received from the storage device, jumping to the operation error state in the unexpected main state.

[0046] In implementation, the storage device write operation wait state is responsible for sending storage device write command data frames and data to be written, and waiting for the storage device to execute. Taking CXL and SSD as examples, the functions of the SSD write operation wait state (SSD_W_WAIT) include: receiving and sending NVMe write command frames and locally cached write data through the storage device interface; tracking the process of data being written from the SSD cache to flash memory and generating refresh monitoring signals and wait cycle count signals; and monitoring the operation completion signal, write confirmation signal, and whether there are operation errors such as write protection from the SSD. The input signals of this state are NVMe write command frames, SSD operation completion signal, and write confirmation signal; the output signals are refresh monitoring signal and wait cycle count signal. The state transition logic is as follows: if the SSD operation completion signal and write confirmation signal are detected to be valid and no operation error occurs, the state transitions to the host write response generation state; if the monitoring time exceeds the preset timeout threshold, or if a write error flag is detected from the SSD (such as write protection in the target area), the state transitions to the operation error state (EXCEP_OP_ERR). The write operation waiting status of storage devices is monitored through the entire process of instruction sending, data refresh tracking, and multi-dimensional anomaly judgment mechanism, which realizes precise control of the write operation execution process. This not only ensures the reliability of data writing to flash memory, but also captures timeout and error issues in a timely manner, improving the closed-loop stability and fault tolerance of protocol conversion.

[0047] Furthermore, in a specific implementation, in the protocol conversion method provided in the embodiments of the present invention, when jumping to the host write response generation state, an ordered jump is performed based on set conditions to process the host-side response generation. Specifically, this may include: receiving the write confirmation signal output from the storage device's write operation waiting state and the operation status code fed back by the storage device; extracting key information from the operation status code to determine the execution result of the storage device's write operation; when the execution result is successful, generating a host-side write response data frame based on the write confirmation signal and the operation status code; when the execution result is unsuccessful, extracting the error status code and jumping to the operation error state in the unexpected main state; sending the host-side write response data frame to the host and detecting the response sending completion status; after confirming that the response sending is completed, clearing the status flag bit and jumping back from the host write response generation state to the idle state.

[0048] In implementation, the host write response generation state is responsible for generating host write response feedback results. Taking CXL and SSD as examples, the functions of the CXL write response generation state (CXL_W_RESP) include: receiving the write acknowledgment signal output from the SSD write operation wait state and the operation status code fed back by the SSD; extracting key information from the SSD status code to determine the execution result of the SSD write operation; when the execution result is successful, generating a CXL write response frame containing a status field (no data field) based on the write acknowledgment signal and the SSD status code. The input signals of this state are the write acknowledgment signal and the SSD status code; the output signals are the CXL write response frame and the response sending completion signal. When the CXL write response is sent and the status flag is cleared, the state transitions from the CXL write response generation state back to the idle state. By accurately extracting operation status information and standardizing the generation of host-side responses, the host write response generation state achieves reliable feedback of write operation results. Combined with the status flag clearing mechanism, it ensures efficient reuse of hardware resources and improves the closed-loop efficiency of protocol conversion and overall operational stability.

[0049] In the above steps, if no operation completion signal is received and the monitoring time exceeds the preset timeout threshold, the system jumps to the operation error state in the unexpected main state. Specifically, this can include: simultaneously sending a storage device write instruction data frame to the storage device and starting a wait cycle counter to count the wait cycles; within each counting cycle, checking whether the operation completion signal fed back by the storage device is valid; if the operation completion signal is valid, stopping the count and jumping to the host write response generation state; or, simultaneously sending a storage device read instruction data frame to the storage device and starting a wait cycle counter to count the wait cycles; within each counting cycle, checking whether the operation completion signal fed back by the storage device is valid; if the operation completion signal is valid, stopping the count and jumping to the host read response generation state. If the operation completion signal is never valid, and the count value of the wait cycle counter reaches the number of cycles corresponding to the preset timeout threshold, it is determined to be a timeout exception, the timeout error flag is set, and the system jumps to the operation error state in the unexpected main state. The preset timeout threshold is pre-written into the configuration register through the debug interface, and the state machine reads the number of cycles corresponding to the timeout threshold from the configuration register.

[0050] In implementation, timeout detection during the read / write operation wait state of the storage device is achieved through a wait cycle counter. Simultaneously with sending the storage device-side instruction data frame, the wait cycle counter is started to count the wait cycles. Within each counting cycle, the validity of the operation completion signal fed back by the storage device is checked: if the operation completion signal is valid, counting stops and the normal jump procedure is executed; if the operation completion signal is never set, and the count value of the wait cycle counter reaches the number of cycles corresponding to the preset timeout threshold (e.g., 100 clock cycles), a timeout exception is determined, the timeout error flag is set, and the system jumps to the operation error state in the unexpected main state. The preset timeout threshold is pre-written into the configuration register through a debug interface (e.g., JTAG interface). The state machine reads the number of cycles corresponding to the timeout threshold from the configuration register before starting the counting process to support flexible adaptation to the response characteristics of different storage devices.

[0051] Furthermore, in specific implementation, in the protocol conversion method provided in the embodiments of the present invention, when jumping to the host cache instruction parsing state, an ordered jump is performed based on set conditions to perform host-side instruction parsing processing, which may specifically include: receiving the data frame of the request instruction and the storage device cache configuration parameters; parsing the instruction identifier in the data frame; if the instruction identifier corresponds to a cache invalidation instruction, parsing the target address and converting it into the target logical block address corresponding to the storage device cache, and extracting the cache consistency level; if the instruction identifier corresponds to a cache write-back instruction, parsing the target address and the data dirty mark, and obtaining the target logical block address to be written back; if the instruction identifier corresponds to a cache snooping instruction, extracting the target logical block address to be queried; judging whether the target logical block address of various cache instructions is within a preset range according to the storage device cache configuration parameters; if the target logical block address is within the preset range, jumping to the storage device refresh instruction generation state; if the target logical block address is not within the preset range, jumping to the instruction error state in the unexpected main state.

[0052] In implementation, the cache consistency master state is used for cache consistency instruction design to ensure the consistency of data between the host cache and storage devices. The host cache instruction parsing state handles the unified parsing of various cache consistency instructions, covering parameter extraction and validity checks for three types of instructions: Cache Invalidate, Cache Writeback, and Cache Snoop. Taking CXL and SSD as examples, the CXL cache instruction parsing state (CXL_CACHE_PARSE) functions as follows: receiving CXL cache instruction frames and SSD DRAM cache configuration parameters; distinguishing instruction types through the opcode field of the CXL instruction (e.g., 0x01 corresponds to Invalidate, 0x02 to Writeback, and 0x03 to Snoop); and extracting corresponding key parameters for different types of instruction branches: for cache invalidate instructions, parsing the target cache address and converting it to the LBA range corresponding to the SSD DRAM, while extracting the consistency level (partial or full cache); for cache writeback instructions, parsing the target address and data dirty flag (1 indicates dirty data needs to be written back); for cache snoop instructions, only extracting the target address of the DRAM cache to be queried. All three types of instructions share the same validity judgment logic. Based on the SSD DRAM cache configuration parameters, it determines whether the target address of each instruction is within the preset range of the SSD DRAM cache, ultimately outputting an instruction type flag, a valid instruction flag, and the corresponding instruction parameters. When the valid instruction flag is valid, it jumps to the SSD_Refresh_GEN state; when the valid instruction flag is invalid, it jumps to the storage device refresh instruction generation state. The host cache instruction parsing state, through a unified instruction parsing framework with different instruction branch adaptation designs, achieves accurate parsing and parameter extraction for various cache consistency instructions. Combined with standardized validity verification logic, this ensures the targeting and accuracy of cache operations, improving the overall efficiency of cache consistency management and the stability of system operation.

[0053] Furthermore, in specific implementation, in the protocol conversion method provided in the embodiments of the present invention, when jumping to the storage device refresh instruction generation state, an ordered jump is performed based on set conditions to process the generation of storage device-side instructions. Specifically, this may include: receiving the instruction type flag and the key parameters of the corresponding instruction output by the host cache instruction parsing state; if the instruction is a cache invalidation instruction, selecting the corresponding storage device refresh instruction flag, configuring the refresh range according to the cache consistency level, and generating a storage device refresh instruction data frame; if the instruction is a cache write-back instruction, selecting the corresponding storage device refresh instruction flag and data verification instruction flag, configuring the refresh range as the logical block address range corresponding to the target address, and generating a storage device refresh instruction data frame and a data verification instruction data frame; if the instruction is a cache snooping instruction, marking the snooping mode as enabled, and extracting the target logical block address to be queried; after the instruction type processing is completed, jumping to the storage device refresh waiting state.

[0054] In implementation, the storage device refresh instruction generation state can be based on the instruction type flag transmitted from the host cache instruction parsing state, using single-state branch processing logic to generate corresponding operation instructions or mark special modes. Taking CXL and SSD as examples, the SSD refresh instruction generation state (SSD_FLUSE_GEN) is based on the instruction type flag transmitted from the CXL cache instruction parsing state, using single-state branch processing logic to generate corresponding operation instructions or mark special modes. If the instruction type is cache invalidation, an NVMe refresh instruction with opcode 0x08 is generated, and the refresh range is configured according to the consistency level, where the local cache corresponds to the target address range, and the full cache corresponds to the entire SSD LBA range; if the instruction type is cache write-back, an NVMe refresh instruction and an NVMe data verification instruction are generated simultaneously. The integrity of the SSD DRAM cache data is first ensured through the data verification instruction, and then the disk flush operation is triggered, while the refresh range is configured to the LBA range corresponding to the target address; if the instruction type is cache snooping, no NVMe instruction needs to be generated (no SSD hardware access is required), only the snooping mode is marked as enabled, and the SSD DRAM cache address to be queried is passed to the next state. The final output signal of the storage device refresh instruction generation state is differentiated according to the instruction type: NVMe instruction frames are output in cache invalidation and cache write-back scenarios, and a snooping mode flag and instruction parameters are output in cache snooping scenarios. After all instruction types have been processed, the state jumps to the storage device refresh waiting state. The storage device refresh instruction generation state, through a single-state branching instruction generation logic, achieves differentiated and precise processing of multiple types of cache instructions. Combined with pre-control of data verification and range configuration, it ensures both the accuracy of instruction execution and data integrity while simplifying the state machine design architecture.

[0055] Furthermore, in specific implementation, in the protocol conversion method provided in the embodiments of the present invention, when jumping to the storage device refresh waiting state, an ordered jump is performed based on set conditions to process the storage device-side instruction execution feedback waiting. Specifically, this may include: receiving the instruction data frame, snooping mode flag, and corresponding instruction key parameters output by the storage device refresh instruction generation state; if the instruction is a cache invalidation instruction, sending a storage device refresh instruction data frame through the storage device interface and monitoring the refresh completion signal fed back by the storage device; if the instruction is a cache write-back instruction, sending a storage device refresh instruction data frame and a data verification instruction data frame through the storage device interface and monitoring the refresh completion signal and verification success signal fed back by the storage device; if the instruction is a cache snooping instruction, calling the internal cache hit detection module, inputting the target address of the storage device cache to be queried, and obtaining the hit status and data validity result; detecting the operation status corresponding to various instructions and determining whether an operation error has occurred; if no operation error has occurred, generating the corresponding operation completion flag and operation result parameters, and jumping to the host cache response generation state; if an operation error has occurred, jumping to the operation error state in the unexpected main state.

[0056] In implementation, the storage device refresh wait state can employ in-state branching logic to handle the operation waiting or direct processing of three types of cache instructions. Taking CXL and SSD as examples, the SSD refresh operation wait state (SSD_FLUSE_WAIT) uses in-state branching logic. For cache invalidation instructions, the NVMe refresh instruction is sent to the SSD, and the refresh completion signal fed back by the SSD is continuously monitored to ensure that the SSD DRAM cache data is successfully flushed to the flash memory. For cache write-back instructions, after sending the NVMe refresh instruction and the data verification instruction, the system simultaneously waits for the refresh completion signal and the verification success signal fed back by the SSD, ensuring the accuracy of the write-back data through a double confirmation mechanism. For cache snooping instructions, no NVMe instruction is sent to the SSD; instead, the DRAM cache hit detection module integrated inside the FPGA is directly called. After inputting the SSD DRAM cache address to be queried, the module quickly returns the address hit / miss status and the data valid / invalid result. All three types of instructions output an operation completion marker (refresh complete or snooping complete) and corresponding operation result parameters (refresh status, verification result, or snooping result) in this state. If no operation error occurs, the system uniformly jumps to the host cache response generation state; if an operation error is detected, the system jumps to the operation error state. The storage device refresh wait state achieves precise control over the cache operation execution process through differentiated monitoring and processing logic based on instruction type. Combined with a dual confirmation and rapid detection mechanism, it ensures both the reliability of data flushing to disk and the timeliness of snooping results, while also promptly capturing operation anomalies, thus improving the closed-loop stability and fault tolerance of cache consistency management.

[0057] Furthermore, in specific implementation, in the protocol conversion method provided in the embodiments of the present invention, when jumping to the host cache response generation state, an orderly jump is performed based on set conditions to process the host-side response generation. Specifically, this may include: receiving the instruction type flag, operation completion flag, and corresponding operation result parameters output by the storage device refresh waiting state; if the instruction is a cache invalidation instruction, filling the response data frame with the cache invalidation completion state and the status information of the storage device cache data being written to flash memory; if the instruction is a cache write-back instruction, filling the response data frame with the cache write-back completion state and attaching the data verification result; if the instruction is a cache snooping instruction, filling the response data frame with the target address hit status and the corresponding data validity information; sending the generated host-side cache response data frame to the host and detecting the response sending completion state; after confirming that the response sending is completed, clearing the status flag bit and orderly jumping back from the host cache response generation state to the idle state.

[0058] In implementation, the host cache response generation status is based on the instruction type flag, operation completion flag, and corresponding operation result parameters output by the storage device refresh wait status. Within a single state, different host responses corresponding to different instructions are generated. Taking CXL and SSD as examples, the CXL cache response generation status (CXL_CACHE_RESP) can generate CXL responses corresponding to three types of cache instructions within a single state. If it is a cache invalidation instruction, the generated CXL response frame will report the cache invalidation completion status and the status code indicating that the SSD DRAM cache data has been flushed to flash memory, clearly indicating the invalidation operation and data persistence result. If it is a cache write-back instruction, the response frame, in addition to reporting the cache write-back completion status, also includes the data verification result (such as a CRC checksum) to ensure the integrity of the write-back data. If it is a cache snooping instruction, the response frame directly reports the hit / miss status of the target address and the valid / invalid status of the corresponding data (e.g., 0x00 indicates a hit and valid, 0x01 indicates a miss, and 0x02 indicates a hit but invalid), satisfying the CXL host's query requirements for the validity of SSD DRAM cache data. This state ultimately outputs a CXL Cache response frame and a response sending completion flag. The generated CXL Cache response data frame is sent to the CXL host. After confirming the response sending is complete, the state flag is cleared, and all instruction types sequentially transition back to the idle state, awaiting the next cache instruction request. The host cache response generation state, through a single-state differentiated response generation logic, achieves accurate feedback of multi-type cache operation results. Combined with the state flag clearing mechanism, it ensures efficient reuse of hardware resources, guarantees the integrity and accuracy of response information, and improves the overall efficiency of cache consistency management and system stability.

[0059] Furthermore, in a specific implementation, in the protocol conversion method provided in the embodiments of the present invention, after step S104 collects error information and generates an error response in the host-side protocol format, it falls back to the idle state. Specifically, this may include: if the collected error information is an instruction-type error, collecting the illegal instruction type, generating the corresponding error code, and jumping to the abnormal response state in the unexpected main state; if the collected error information is an operation-type error, collecting the operation error type, generating the corresponding error code, and jumping to the abnormal response state in the unexpected main state; in the abnormal response state, receiving the error code and the host-side protocol rate parameter, converting the error code into a host-side protocol-compatible error response format, generating a host-side protocol error response data frame, and sending it to the host, and detecting the error response sending completion status; after confirming that the error response has been sent, clearing the unexpected flag bit, and falling back from the unexpected main state to the idle state.

[0060] In implementation, the unexpected main state is used to handle exceptions during all instruction parsing and operation execution phases, and includes three sub-states. The first is the instruction error state (EXCEP_CMD_ERR): When the collected error information is an instruction-related error, this state is responsible for collecting illegal instruction types (such as address out of bounds, opcode undefined, data length error) and generating corresponding error codes (such as 0x01 = address out of bounds, 0x02 = format error); its input is an illegal flag and error type signal, and its output is an error code and error information latch signal. After the error code is generated, it jumps to the exception response state (EXCEP_RESP). The second is the operation error state (EXCEP_OP_ERR): When the collected error information is an operation-related error, this state is responsible for collecting operation error types (such as Media Error, timeout, write protection) and generating corresponding error codes (such as 0x10 = Media Error, 0x11 = timeout); its input is an SSD error signal and error type identifier, and its output is an error code and error details signal. After the information collection is completed, it jumps to EXCEP_RESP. The third is EXCEP_RESP: It receives the error code, error details, and CXL rate parameters from the first two states, converts the error code into the CXL error response format, generates a CXL error response frame, and sends it to the host. Its inputs are the error code, error details, and CXL rate parameters, and its outputs are the CXL error response frame, a response transmission completion signal, and an exception flag clearing signal. After confirming that the error response has been sent, it clears the unexpected flag and jumps back to the idle state, completing the exception handling loop. In this way, through classified error collection, standardized error code generation, and standardized exception response logic, it achieves accurate capture, efficient processing, and reliable feedback of various exceptions. Combined with the exception flag clearing mechanism, it ensures that the system can quickly recover to the normal standby state after exception handling, effectively avoiding exception propagation and process blockage, and improving the system's fault tolerance and operational stability.

[0061] The protocol conversion method provided by this invention is described below using an example. This system consists of three parts: a CXL host, an FPGA-based protocol conversion device, and an SSD device. The protocol conversion device, as the core connection component, is deployed between the CXL host and the SSD device. The CXL host supports the CXL protocol and the cache coherence protocol, and has high-speed data interaction capabilities. The SSD device uses an NVMe interface and has a built-in 1GB DRAM cache (4KB LBA block size) and 2TB flash memory. The protocol conversion device uses an FPGA as its hardware carrier and integrates functional units such as an address mapping module (to convert CXL addresses to SSD LBAs), a data caching module, and a cache coherence control module. This module connects to the CXL host through the CXL interface, receives Memory, Cache, and management commands sent by the CXL host, and connects to the SSD device through the NVMe interface, sending NVMe read, write, refresh, and management commands to the SSD and receiving execution results and data. It also has a debugging interface for module parameter configuration and functional debugging. The following uses a cache write-back command as an example; the specific steps are as follows: Step 1: Initialization. After the FPGA is powered on, configure parameters such as address mapping rules and timeout thresholds via JTAG. If no configuration is performed, the default parameters will be used. After initialization, the protocol conversion device enters an idle state, waiting to receive commands.

[0062] Step 2: Command Reception. The CXL host sends a buffer write-back command (including target address 0x8000_1234 and data length 64B). After receiving the command, the CXL interface module of the protocol converter transmits it to the command parsing module.

[0063] Step 3: Instruction Parsing. The instruction parsing module enters the CXL_CACHE_PARSE state, parses the current instruction type as cache write-back, and determines that the target address is within the SSD DRAM cache range (0x8000_0000~0x8FFF_FFFF) based on the relevant configuration. After parsing is completed, it jumps to the SSD_Refresh_GEN2 state.

[0064] Step 4: NVMe Command Generation. Based on the parsing results, the SSD_Refresh_GEN2 state generates NVMe refresh commands and NVMe data verification commands. Then, through the NVMe interface module of the protocol conversion device, both commands are sent to the SSD device.

[0065] Step 5: Operation Waiting. The protocol conversion device enters the SSD_Refresh_WAIT2 state, continuously monitoring the refresh completion signal and data verification success signal fed back by the SSD device, until it is confirmed that the data in the SSD DRAM cache has been successfully flushed to the flash memory and that the data is error-free.

[0066] Step Six: Response Generation. After confirming that the operation is correct, the protocol conversion device enters the CXL_CACHE_RESP2 state, generates a CXL write-back response frame containing a write-back completion status code, and sends the response back to the CXL host through the CXL interface module.

[0067] Step 7: State Rollback. After confirming that the CXL host has successfully received the response, the protocol converter clears the relevant status flags and rolls back from the CXL_CACHE_RESP2 state to the idle state, waiting to receive the next instruction, thus completing a full instruction processing loop.

[0068] Furthermore, in specific implementations, the protocol conversion method provided in the embodiments of the present invention may further include: after the host read instruction parsing state completes the parsing process, jumping to the cache hit detection state; determining whether the target address has been stored in the local cache built into the state machine; if the target address hits the local cache, reading the corresponding data from the local cache, skipping the steps of generating the storage device-side read instruction and waiting for the storage device-side instruction execution feedback; after reading the local cache data, jumping to the host read response generation state; if the target address does not hit the local cache, jumping to the storage device read instruction generation state.

[0069] In implementation, to optimize read operation performance, this invention designs a DRAM cache hit judgment module and a cache hit detection state after the host read instruction parsing state completes the parsing process. This state's functions include: determining whether the target address of the read request is already stored in the state machine's built-in local cache (capacity can be 1MB); if the target address hits the local cache, the corresponding data is directly read from the local cache, skipping the process of generating and executing read instructions on the storage device side, and after reading, jumping to the host read response generation state (e.g., CXL_R_RESP); if the target address does not hit the local cache, the original process jumps to the storage device read instruction generation state (e.g., SSD_R_GEN). This pre-cached cache hit detection and bypass execution logic significantly shortens the read operation response path in hit scenarios, reduces the time loss from instruction interaction and hardware waiting, significantly improves the overall execution efficiency of read operations, and simultaneously reduces the frequency of storage device access, optimizing the utilization efficiency of system resources.

[0070] It should be noted that this invention can employ an FPGA hardware-level conversion method, enabling low-latency direct interaction between the CXL host and the SSD DRAM cache. This effectively resolves the operational granularity differences between memory semantics and block storage semantics, supporting fine-grained access. Regarding cache consistency, a linkage mechanism between the cache consistency master state and NVMe refresh instructions ensures that CXL cache invalidation instructions can trigger SSD DRAM cache flushing operations, fundamentally avoiding data inconsistency issues. In terms of exception handling, various exception types are finely segmented, compatible with the CXL Retry mechanism and NVMe-specific errors, improving system fault tolerance. Furthermore, the module is reusable, configurable, and scalable. The FPGA hardware carrier supports flexible parameter configuration, offering strong portability and suitability for various application scenarios such as data centers and heterogeneous computing.

[0071] This invention can also be applied to interaction scenarios between other high-speed interconnect protocols and DRAM caches in storage devices. For example, the CXL instruction parsing module in the state machine can be replaced with a PCIe instruction parsing module, while keeping the core logic of other sub-states unchanged. This allows for rapid low-latency access of PCIe hosts to SSD DRAM caches, adapting to the requirements of PCIe protocol scenarios. Adding a network latency compensation module to the NVMe interface, while maintaining other core logic, can effectively offset network transmission latency, enabling stable access of remote CXL hosts to NVM SSD caches. Only the instruction parsing and transmission adaptation modules for the corresponding protocol need to be replaced, while maintaining the sub-state architecture of the state machine, cache consistency coordination logic, and exception handling mechanism, demonstrating strong portability and scalability.

[0072] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0073] Embodiments of the present invention also provide a protocol conversion device. Figure 5 This is a schematic diagram of the protocol conversion device provided in an embodiment of the present invention. This embodiment is based on the perspective of functional modules, such as… Figure 5 As shown, the device includes: The instruction type identification module 10 is used to identify the type of the request instruction after receiving the request instruction in the host-side protocol format sent by the host; The main state determination module 11 is used to determine the corresponding target function main state according to the type of request instruction, and jump to the first sub-state of the target function main state; each function main state contains multiple sub-states. The protocol conversion processing module 12 is used to perform ordered jumps according to the preset order of each sub-state in the main state of the target function, based on set conditions, and sequentially perform host-side instruction parsing, storage device-side instruction generation, storage device-side instruction execution feedback waiting, and host-side response generation to complete the bidirectional conversion between the host-side protocol and the storage device-side protocol; after the processing is completed, it returns to the idle state. The unexpected handling module 13 is used to jump to the unexpected main state if an unexpected situation is detected during the processing, collect error information and generate an error response in the host side protocol format, and then fall back to the idle state.

[0074] Since the embodiments of the protocol conversion device and the protocol conversion method correspond to each other, the descriptions of the features in the embodiments corresponding to the protocol conversion device can be found in the relevant descriptions of the embodiments corresponding to the protocol conversion method, and will not be repeated here. Furthermore, it has the same beneficial effects as the protocol conversion method mentioned above.

[0075] Furthermore, in a specific implementation, in the protocol conversion device provided in the embodiments of the present invention, the main state determination module 11 can be specifically used to retrieve a preset mapping relationship between instruction types and functional main states, and match the corresponding target functional main state according to the mapping relationship and the type of request instruction; wherein, when the type of request instruction is a read request instruction, the read operation main state is matched; when the type of request instruction is a write request instruction, the write operation main state is matched; and when the type of request instruction is a cache consistency instruction, the cache consistency operation main state is matched.

[0076] Furthermore, in a specific implementation, in the protocol conversion device provided in the embodiments of the present invention, the unexpected processing module 13 can be specifically used to: if the collected error information is an instruction-type error, collect the illegal instruction type and generate the corresponding error code; if the collected error information is an operation-type error, collect the operation error type and generate the corresponding error code; after the error information is collected and the error code is generated, jump to the abnormal response state; receive the error code and the host-side protocol rate parameter, convert the error code into a host-side protocol compatible error response format, generate a host-side protocol error response data frame, and send it to the host; detect the error response sending completion status; after confirming that the error response has been sent, clear the unexpected flag bit and return from the unexpected main state to the idle state.

[0077] Furthermore, in a specific implementation, the protocol conversion device provided in the embodiments of the present invention may further include: a cache hit determination module, used to jump to the cache hit detection state after the host read instruction parsing state has completed the parsing process; determine whether the target address has been stored in the local cache built into the state machine; if the target address hits the local cache, read the corresponding data from the local cache, skipping the steps of generating the storage device-side read instruction and waiting for the storage device-side instruction execution feedback; after reading the local cache data, jump to the host read response generation state; if the target address does not hit the local cache, jump to the storage device read instruction generation state.

[0078] Embodiments of the present invention also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described protocol conversion method embodiments.

[0079] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described protocol conversion method embodiments at runtime.

[0080] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0081] Embodiments of the present invention also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described protocol conversion method embodiments.

[0082] Embodiments of the present invention also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described protocol conversion method embodiments.

[0083] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0084] The foregoing has provided a detailed description of the protocol conversion method, apparatus, medium, and computer program product provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only intended to aid in understanding the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A protocol conversion method, characterized in that, Programmable logic devices used in integrated state machine logic include: After receiving a request instruction in host-side protocol format sent by the host, identify the type of the request instruction; Based on the type of the request instruction, the corresponding target function main state is determined, and the user jumps to the first sub-state of the target function main state. Each function main state contains multiple sub-states. The function main states include a read operation main state, a write operation main state, and a cache consistency operation main state. The first sub-state of the read operation main state is the host read instruction parsing state, and the second sub-state is the storage device read instruction generation state. A preset mapping relationship between instruction types and function main states is retrieved, and the corresponding target function main state is obtained based on the mapping relationship and the type of the request instruction. When the type of the request instruction is a read request instruction, the read operation main state is obtained; when the type of the request instruction is a write request instruction, the write operation main state is obtained; and when the type of the request instruction is a cache consistency instruction, the cache consistency operation main state is obtained. According to the preset order of each sub-state in the main state of the target function, an orderly jump is performed based on the set conditions, and the host-side instruction parsing, storage device-side instruction generation, storage device-side instruction execution feedback waiting, and host-side response generation are performed in sequence to complete the bidirectional conversion between the host-side protocol and the storage device-side protocol; after the processing is completed, it returns to the idle state. When the system jumps to the host read instruction parsing state, an ordered jump is performed based on set conditions to process host-side instruction parsing, including: receiving the data frame of the request instruction and storage device namespace configuration parameters; parsing the received data frame to extract key information from the request instruction; the key information includes the target address and data length defined by the host-side protocol; mapping the target address to the target logical block address of the storage device; determining whether the target logical block address is within a preset range based on the received storage device namespace configuration parameters; if the target logical block address is within the preset range, the system jumps to the storage device read instruction generation state; if the target logical block address is not within the preset range, the system jumps to the instruction error state in the unexpected main state. If an unexpected situation is detected during processing, the system jumps to the unexpected main state, collects error information, generates an error response in the host-side protocol format, and then falls back to the idle state.

2. The protocol conversion method according to claim 1, characterized in that, The third sub-state of the main read operation state is the storage device read operation waiting state; When the jump reaches the storage device read instruction generation state, an ordered jump is performed based on set conditions to process the storage device-side instruction generation, including: Receive the instruction type flag, target logical block address, data length, and host request priority signal output by the host read instruction parsing status; Select the corresponding storage device read instruction identifier based on the instruction type flag; Based on the host request priority signal, allocate the corresponding storage device instruction queue identifier and generate a queue selection signal; Based on the storage device read instruction identifier, queue selection signal, target logic block address and data length, a storage device read instruction data frame is generated. Once the data frame for the read instruction on the storage device side is generated and the timing parameters are configured, the process jumps to the waiting state for the read operation of the storage device.

3. The protocol conversion method according to claim 2, characterized in that, The fourth sub-state of the main read operation state is the host read response generation state; When the process jumps to the storage device read operation wait state, an ordered jump is performed based on set conditions to handle the storage device-side instruction execution feedback wait, including: Receive the storage device side read instruction data frame, and send the storage device side read instruction data frame to the storage device through the storage device interface; The system monitors the operation completion signal and latched data from the storage device; when the latched data is detected to be valid, it generates a data latch control signal and stores the latched data in the local cache. If the operation completion signal is detected as valid and the data latching is completed, the process jumps to the host read response generation state. If no operation completion signal is received and the monitoring time exceeds the preset timeout threshold, or if an error flag is received from the storage device, the system will jump to the operation error state in the unexpected main state.

4. The protocol conversion method according to claim 3, characterized in that, When the system jumps to the host read response generation state, an ordered jump is performed based on set conditions to process the host-side response generation, including: Receive latched data output from the read operation wait state of the storage device and the operation status code fed back by the storage device; Extract key information from the operation status code to determine the execution result of the storage device read operation; When the execution result is successful, the latched data is converted into a host-side protocol-compatible data format, and a host-side read response data frame is generated. The host-side read response data frame is sent to the host, and the response sending completion status is detected; After confirming that the response has been sent, the status flag is cleared, and the response generation status is read from the host to jump back to the idle state.

5. The protocol conversion method according to claim 1, characterized in that, The first sub-state of the main state of the write operation is the host write instruction parsing state, and the second sub-state is the storage device write instruction generation state. When the system jumps to the host write instruction parsing state, an ordered jump is performed based on set conditions to process the host-side instruction parsing, including: The data frame receiving the request instruction, the host-side data to be written, and the write protection configuration parameters of the storage device are received. The received data frame is parsed to extract key information from the request instruction; the key information includes the target address and data length defined by the host-side protocol. The target address is mapped to the target logical block address of the storage device, and the received host-side data to be written is stored in the local cache. Based on the received write protection configuration parameters of the storage device, determine whether the address of the target logic block is within the preset range; If the target logical block address is within a preset range, the process jumps to the memory device write instruction generation state; if the target logical block address is not within a preset range, the process jumps to the instruction error state in the unexpected main state.

6. The protocol conversion method according to claim 5, characterized in that, The third sub-state of the main state of the write operation is the storage device write operation wait state; When the jump reaches the storage device write instruction generation state, an ordered jump is performed based on set conditions to process the generation of storage device-side instructions, including: Receive the instruction type flag, target logical block address, data length, host request priority signal, and host-side data to be written in the local cache output by the host write instruction parsing status; Select the corresponding storage device write instruction identifier based on the instruction type flag; Based on the host request priority signal, allocate the corresponding storage device instruction queue identifier and generate a queue selection signal; Store the host-side data to be written in the local cache into the data buffer corresponding to the storage device; Based on the storage device sidewrite instruction identifier, queue selection signal, target logic block address and data length, a storage device sidewrite instruction data frame is generated. Once the storage device write instruction data frame is generated and the data cache is ready, the process jumps to the storage device write operation waiting state.

7. The protocol conversion method according to claim 6, characterized in that, The fourth sub-state of the main state of the write operation is the host write response generation state; When the process jumps to the memory device write operation wait state, an ordered jump is performed based on set conditions to handle the memory device-side instruction execution feedback wait, including: Receive the storage device write instruction data frame, queue selection signal and data to be written in the storage device data buffer, and send the storage device write instruction data frame and data to be written to the storage device through the storage device interface; Track the process of writing data from the storage device cache to the flash memory and generate a wait cycle count signal; Monitor the operation completion signal and write confirmation signal fed back by the monitoring storage device, and check for any operation errors; If the operation completion signal is valid, the write confirmation signal is valid, and no operation error occurs, the process jumps to the host write response generation state. If no operation completion signal is received and the monitoring time exceeds the preset timeout threshold, or if an error flag is received from the storage device, the system will jump to the operation error state in the unexpected main state.

8. The protocol conversion method according to claim 7, characterized in that, When the system jumps to the host write response generation state, an ordered jump is performed based on set conditions to process the host-side response generation, including: Receive the write confirmation signal output by the write operation waiting state of the storage device and the operation status code fed back by the storage device; Extract key information from the operation status code to determine the execution result of the write operation on the storage device; When the execution result is successful, a host-side write response data frame is generated based on the write confirmation signal and the operation status code; Send the host side-writing response data frame to the host and check the response sending completion status; After confirming that the response has been sent, the status flag is cleared, and the host transitions from the response generation state back to the idle state.

9. The protocol conversion method according to claim 7, characterized in that, If no operation completion signal is received and the monitoring time exceeds the preset timeout threshold, the system will jump to the operation error state in the unexpected main state, including: While sending the memory device write instruction data frame to the memory device, a wait cycle counter is started to count the wait cycles; Within each counting cycle, check whether the operation completion signal fed back by the storage device is valid; If the operation completion signal is valid, the counting stops and the process jumps to the host write response generation state. If the operation completion signal is not valid and the count value of the waiting period counter reaches the number of periods corresponding to the preset timeout threshold, it is determined to be a timeout abnormality, the timeout error flag is set, and the process jumps to the operation error state in the unexpected main state. The preset timeout threshold is pre-written into the configuration register through the debugging interface, and the state machine reads the number of cycles corresponding to the timeout threshold from the configuration register.

10. The protocol conversion method according to claim 1, characterized in that, The first sub-state of the main state of the cache consistency operation is the host cache instruction parsing state, and the second sub-state is the storage device refresh instruction generation state. When the process jumps to the host cache instruction parsing state, an ordered jump is performed based on set conditions to process host-side instruction parsing, including: The data frame and storage device cache configuration parameters received from the request instruction; Parse the instruction identifier in the received data frame; if the instruction identifier corresponds to a cache invalidation instruction, parse the target address and convert it into the target logical block address corresponding to the storage device cache, and extract the cache consistency level; if the instruction identifier corresponds to a cache write-back instruction, parse the target address and data dirty flag, and obtain the target logical block address to be written back; if the instruction identifier corresponds to a cache snooping instruction, extract the target logical block address to be queried. Based on the received storage device cache configuration parameters, determine whether the target logical block address of various cache instructions is within the preset range; If the target logical block address is within the preset range, the process jumps to the storage device refresh instruction generation state; if the target logical block address is not within the preset range, the process jumps to the instruction error state in the unexpected main state.

11. The protocol conversion method according to claim 10, characterized in that, The third sub-state of the main state of the cache consistency operation is the storage device refresh wait state; When the jump reaches the storage device refresh instruction generation state, an ordered jump is performed based on set conditions to process the generation of instructions on the storage device side, including: Receive the instruction type flag and the key parameters of the corresponding instruction output by the host cache instruction parsing status; If the instruction is a cache invalidation instruction, select the corresponding storage device refresh instruction identifier, configure the refresh range according to the cache consistency level, and generate a storage device refresh instruction data frame; If the instruction is a cache write-back instruction, select the corresponding storage device refresh instruction identifier and data verification instruction identifier, configure the refresh range to the logical block address range corresponding to the target address, and generate a storage device refresh instruction data frame and a data verification instruction data frame. If the instruction is a cache snooping instruction, mark the snooping mode as enabled and extract the address of the target logical block to be queried; After the instruction type is processed, the process jumps to the storage device refresh waiting state.

12. The protocol conversion method according to claim 11, characterized in that, The fourth sub-state of the main state of the cache consistency operation is the host cache response generation state; When the process jumps to the storage device refresh waiting state, an ordered jump is performed based on set conditions to handle the storage device-side instruction execution feedback waiting process, including: The system receives the storage device refresh instruction and generates a status output instruction data frame, a snooping mode flag, and corresponding instruction key parameters. If the instruction is a cache invalidation instruction, a storage device refresh instruction data frame is sent through the storage device interface, and the refresh completion signal fed back by the storage device is monitored; If the instruction is a cache write-back instruction, send the storage device refresh instruction data frame and the data verification instruction data frame through the storage device interface, and monitor the refresh completion signal and verification success signal fed back by the storage device; If the instruction is a cache snooping instruction, input the target address of the storage device cache to be queried, and obtain the hit status and data validity results; Detect the operation status corresponding to various commands and determine whether an operation error has occurred; If no operation error occurs, the corresponding operation completion flag and operation result parameters are generated, and the system jumps to the host cache response generation status. If an operation error occurs, the system will jump to the operation error state in the unexpected main state.

13. The protocol conversion method according to claim 12, characterized in that, When navigating to the host cache response generation state, an ordered jump is performed based on set conditions to process the host-side response generation, including: Receive the instruction type flag, operation completion flag, and corresponding operation result parameters output by the storage device in the refresh waiting state; If the instruction is a cache invalidation instruction, the cache invalidation completion status and the status information of the storage device cache data being written to flash memory are filled into the response data frame; If the instruction is a cache write-back instruction, fill in the cache write-back completion status in the response data frame and attach the data verification result; If the instruction is a cache snooping instruction, the hit status of the target address and the validity information of the corresponding data are filled into the response data frame; Send the generated host-side cached response data frame to the host and check the response sending completion status; After confirming that the response has been sent, the status flag is cleared, and the system transitions back to the idle state from the response generation status in the host cache in an orderly manner.

14. The protocol conversion method according to claim 1, characterized in that, After collecting error information and generating an error response in the host-side protocol format, the system falls back to an idle state, including: If the collected error information is a command-related error, collect the illegal command type and generate the corresponding error code; If the collected error information is an operation-related error, collect the operation error type and generate the corresponding error code; After error information is collected and error codes are generated, the system transitions to an abnormal response state. Receive error codes and host-side protocol rate parameters, convert error codes into host-side protocol-compatible error response formats, generate host-side protocol error response data frames, send them to the host, and check the error response sending completion status; After confirming that the error response has been sent, clear the unexpected flag and return from the unexpected main state to the idle state.

15. The protocol conversion method according to claim 3, characterized in that, Also includes: After the host read instruction parsing process is completed, the process jumps to the cache hit detection state. Determine whether the target address has been stored in the local cache built into the state machine; If the target address hits the local cache, the corresponding data is read from the local cache, skipping the steps of generating the storage device-side read instruction and waiting for the storage device-side instruction execution feedback; After reading the local cached data, the process jumps to the host read response generation status; If the target address does not hit the local cache, the process jumps to the storage device read instruction generation state.

16. An electronic device, characterized in that, include: A host computer, a storage device, and a protocol converter connected to the interfaces of the host computer and the storage device, respectively; wherein the protocol converter includes a memory for storing computer programs; A processor, configured to implement the steps of the protocol conversion method as described in any one of claims 1 to 15 when executing the computer program.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the protocol conversion method as described in any one of claims 1 to 15.

18. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the protocol conversion method as described in any one of claims 1 to 15.

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