Conversion circuit and control method, control device, computing and storage system and electronic equipment

Abstract

The application discloses a conversion circuit and a control method, a control device, a storage-computing system and electronic equipment, relates to the technical field of semiconductors, and is used for a storage-computing system to convert and output an output signal of a storage circuit of the storage-computing system. The conversion circuit comprises a first conversion branch, a second conversion branch and a feedback control circuit. The first conversion branch is used for generating a first voltage signal under the action of a first current signal and a first bias current. The second conversion branch is used for generating a second voltage signal under the action of a second current signal and a second bias current. The feedback control circuit is used for controlling the first bias current and the second bias current. A difference between the first voltage signal and the second voltage signal is used for generating a difference result of the storage-computing system. In this way, the feedback control circuit controls the effective current on the conversion branch, reduces the common-mode part on the basis that the difference-mode part is unchanged, improves the proportion of the difference-mode part, and thus improves the calculation accuracy of the storage-computing system.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a conversion circuit and control method, control device, memory computing system and electronic device. Background Technology

[0002] In traditional computing paradigms, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this paradigm, data is frequently transferred between storage devices and computing devices, resulting in data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing paradigms unable to meet the demands of processing power.

[0003] In-memory computing (IMC) architecture physically merges storage and computation. This physical fusion includes, for example, integrating storage and computation components close together through packaging processes; integrating processing circuitry within memory to achieve in-memory processing integration; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. IMC architecture can reduce data transfer requirements, lower transmission latency and energy consumption, and greatly improve data processing efficiency. However, IMC architecture still faces challenges; for example, the computational accuracy of IMC architecture still needs improvement. Summary of the Invention

[0004] This application provides a conversion circuit and control method, control device, in-memory computing system and electronic device, which can reduce the common-mode part and improve the computing accuracy of the in-memory array without affecting the output differential result.

[0005] In a first aspect, a conversion circuit is provided for a memory computing system, the memory computing system including a storage circuit, the conversion circuit being used to convert and output an output signal of the storage circuit, the output signal of the storage circuit including a first current signal and a second current signal, comprising: a first conversion branch including a first input terminal and a first output terminal, the first input terminal being used to couple the first current signal, the first output terminal being used to output a first voltage signal; a second conversion branch including a second input terminal and a second output terminal, the second input terminal being used to couple the second current signal, the second output terminal being used to output a second voltage signal; a feedback control circuit connected to the first conversion branch and the second conversion branch, used to control a first bias current acting on the first conversion branch and a second bias current acting on the second conversion branch according to the first signal of the first conversion branch and the second signal of the second conversion branch; the first conversion branch being used to generate the first voltage signal at the first output terminal when the first current signal and the first bias current act for a first time, and the second conversion branch being used to generate the second voltage signal at the second output terminal when the second current signal and the second bias current act for the first time.

[0006] Optionally, the first and second conversion branches can include symmetrical structures. Identical suppression of the common-mode portion of both outputs can be achieved through a simple symmetrical circuit structure.

[0007] Based on the above scheme, by setting a feedback control circuit in the conversion circuit, the signal on the conversion branch of the conversion circuit is detected and the effective current on the conversion branch is controlled by the signal, so that the common-mode part of the effective current is reduced, thereby increasing the proportion of the differential-mode part, and thus increasing the proportion of the differential voltage corresponding to the differential-mode part in the output voltage of the conversion circuit, thereby improving the conversion accuracy of the subsequent conversion circuit, and thus improving the calculation accuracy of the in-memory computing system.

[0008] In some implementations of the first aspect, the first signal includes a third current signal flowing through the first conversion branch during a second time period or a third voltage signal at the first output terminal when the second time period expires; the second signal includes a fourth current signal flowing through the second conversion branch during the second time period or a fourth voltage signal at the second output terminal when the second time period expires.

[0009] In some implementations of the first aspect, the second time includes part or all of the first time, or the second time is independent of the first time.

[0010] For example, when the second time includes part or all of the first time, the conversion circuit can use a closed-loop feedback method for calculation; when the second time is independent of the first time, the conversion circuit can also use an open-loop feedback method for calculation.

[0011] In some implementations of the first aspect, the feedback control circuit includes a comparator circuit, a gating circuit, and an analog-to-digital converter circuit; the comparator circuit is used to receive the first signal and the second signal, and output a first control signal based on the comparison result of the first signal and the second signal; the gating circuit, connected to the comparator circuit, is used to receive the first control signal, and according to the first control signal, to connect the first signal or the second signal to the analog-to-digital converter circuit; the analog-to-digital converter circuit is used to convert the first signal or the second signal into a second control signal, the second control signal being used to control the first bias current and the second bias current.

[0012] In this way, by setting the feedback control circuit as described above, while reducing power consumption and simplifying the circuit structure, it is possible to achieve low-latency and real-time adjustments, thereby improving output accuracy.

[0013] In some implementations of the first aspect, the first signal and the second signal include current signals, and the first control signal is used to control the gating circuit to select the signal with smaller current among the first signal and the second signal; or, the first signal and the second signal include voltage signals, and the first control signal is used to control the gating circuit to select the signal with smaller voltage difference relative to the reference voltage among the first signal and the second signal.

[0014] In this way, the common-mode component can be reduced or eliminated as much as possible with zero difference.

[0015] In some implementations of the first aspect, the feedback control circuit includes a comparator circuit, a first analog-to-digital converter (ADC) circuit, and a second ADC circuit; the first ADC circuit receives a first signal and converts the first signal into a third signal; the second ADC circuit receives a second signal and converts the second signal into a fourth signal; the comparator circuit is connected to the first and second ADC circuits, and is used to compare the third signal and the fourth signal, and outputs a third control signal based on the comparison result of the third signal and the fourth signal, the third control signal being used to control the first bias current and the second bias current.

[0016] In this way, signal characteristics can be sampled as accurately as possible, further improving control accuracy and computational precision.

[0017] In some implementations of the first aspect, the first bias current and the second bias current are equal in magnitude and less than or equal to the smaller of the first current signal and the second current signal.

[0018] In this way, the common-mode component can be reduced or eliminated as much as possible with zero difference, thereby improving the calculation accuracy.

[0019] In some implementations of the first aspect, the first conversion branch includes a first control circuit, a first energy storage element, a first reset circuit, and a first bias circuit. One end of the first energy storage element is used to couple to a supply voltage or a reference voltage, and the other end is used for the first output terminal. The first control circuit is connected between the first input terminal and the first output terminal. The first reset circuit is connected to the other end of the first energy storage element and is used to reset the voltage at the first output terminal. The first bias circuit is connected to the feedback control circuit and the first input terminal and is used to provide the voltage to the first input terminal under the control of the feedback control circuit. The first bias current; the second conversion branch includes a second control circuit, a second energy storage element, a second reset circuit, and a second bias circuit, wherein one end of the second energy storage element is used to couple to the supply voltage or reference voltage, and the other end is used to the second output terminal; the second control circuit is connected between the second input terminal and the second output terminal; the second reset circuit is connected to the other end of the second energy storage element and is used to reset the voltage of the second output terminal; the second bias circuit is connected to the feedback control circuit and the second input terminal and is used to provide the second bias current to the second input terminal under the control of the feedback control circuit.

[0020] Thus, by setting a reset circuit, residual charge from the previous calculation can be eliminated before the next calculation, ensuring the consistency of the initial state, reducing interference, and improving the output accuracy of the conversion circuit.

[0021] In some implementations of the first aspect, the feedback control circuit samples the first signal and the second signal via an analog-to-digital converter; the first bias circuit generates the first bias current via a first digital-to-analog converter; and the second bias circuit generates the second bias current via a second digital-to-analog converter.

[0022] In some implementations of the first aspect, the first conversion branch further includes a first clamping circuit for stabilizing the voltage at the first input terminal; the second conversion branch further includes a second clamping circuit for stabilizing the voltage at the second input terminal.

[0023] In this way, the clamping circuit can stabilize the voltage at the input terminals of the first and second conversion branches, ensuring the voltage margin of the conversion circuit and guaranteeing the stability of the calculation voltage of the memory array.

[0024] In a second aspect, a control method is provided for controlling a switching circuit as described in the first aspect and any possible implementation thereof. The control method includes: controlling a feedback control circuit to turn on, the feedback circuit being used to control a first bias current acting on the first switching branch and a second bias current acting on the second switching branch based on a first signal of the first switching branch and a second signal of the second switching branch; controlling the feedback circuit to turn off when a first time expires, outputting a first voltage signal at a first output terminal of the first switching branch, and outputting a second voltage signal at a second output terminal of the second switching branch.

[0025] For a description of the beneficial effects of the second aspect, please refer to the description of the beneficial effects of the first aspect, which will not be repeated here.

[0026] Thirdly, a control device is provided, including at least one processor and an interface circuit, the interface circuit being electrically connected to a conversion circuit in the first aspect and any possible implementation thereof, and the at least one processor being used to execute a control method of any of the second aspects.

[0027] For a description of the beneficial effects of the third aspect, please refer to the descriptions of the first and second aspects, and will not be repeated here.

[0028] Fourthly, a storage computing system is provided, including a storage circuit for receiving an input signal and converting the input signal into an output signal based on stored weight data; as in the first aspect and any possible implementation thereof, the conversion circuit is connected to the storage circuit to convert the output signal and output it.

[0029] Fifthly, an electronic device is provided, including the in-memory computing system described in the fourth aspect. Attached Figure Description

[0030] Figure 1 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown.

[0031] Figure 2 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown.

[0032] Figure 3 A schematic diagram of yet another in-memory computing system according to an exemplary embodiment of this application is shown.

[0033] Figure 4 A schematic diagram of the circuit structure of a conversion circuit according to an exemplary embodiment of this application is shown.

[0034] Figure 5 A schematic diagram of the output current of a storage circuit according to an exemplary embodiment of this application is shown.

[0035] Figure 6A schematic diagram of a conversion circuit according to an exemplary embodiment of this application is shown.

[0036] Figure 7 A schematic diagram of another conversion circuit according to an exemplary embodiment of this application is shown.

[0037] Figure 8 A schematic diagram of another conversion circuit according to an exemplary embodiment of this application is shown.

[0038] Figure 9 A schematic diagram of another conversion circuit according to an exemplary embodiment of this application is shown.

[0039] Figure 10 A schematic diagram of a feedback control circuit according to an exemplary embodiment of this application is shown.

[0040] Figure 11 A schematic diagram of another feedback control circuit according to an exemplary embodiment of this application is shown.

[0041] Figure 12 Schematic diagrams of several clamping circuits according to exemplary embodiments of this application are shown.

[0042] Figure 13 Schematic diagrams of several control circuits according to exemplary embodiments of this application are shown.

[0043] Figure 14 Schematic diagrams of several control circuits according to exemplary embodiments of this application are shown.

[0044] Figure 15 Schematic diagrams of several reset circuits according to exemplary embodiments of this application are shown.

[0045] Figure 16 A schematic diagram of a conversion circuit in a first preparation stage according to an exemplary embodiment of this application is shown.

[0046] Figure 17 A schematic diagram of a conversion circuit for a second preparation stage according to an exemplary embodiment of this application is shown.

[0047] Figure 18 A schematic diagram of a conversion circuit for a computing stage according to an exemplary embodiment of this application is shown.

[0048] Figure 19 A schematic diagram of a conversion circuit for another computing stage according to an exemplary embodiment of this application is shown.

[0049] Figure 20 A schematic diagram of a conversion circuit for an output stage according to an exemplary embodiment of this application is shown.

[0050] Figure 21 A schematic diagram of a control method according to an exemplary embodiment of this application is shown.

[0051] Figure 22 A schematic diagram of a control device according to an exemplary embodiment of this application is shown.

[0052] Figure 23 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Detailed Implementation

[0053] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0054] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0055] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0056] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0057] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0058] In in-memory computing technology, storage and computation (or arithmetic) are physically integrated. This physical integration includes, for example, integrating storage and computation components close together through processes such as packaging; integrating processing circuits with processing capabilities within the memory to achieve integrated processing functions within the memory; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. According to some embodiments, an in-memory computing system may include a storage circuit and a processing circuit (or control circuit); the storage circuit is used to store data; the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computation, or sensing of computation results. For example, the processing circuit can call up data stored in the storage circuit and perform computation based on the called data; or the processing circuit can control the computation of the storage circuit; or the processing circuit can be used to read or sense the computation results of the storage circuit and process the computation results. This application does not limit the type of memory, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM) or dynamic random access memory (DRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric memory (FeRAM), or phase change memory (PCM).

[0059] For ease of understanding, Figure 1 A schematic diagram of an in-memory computing system according to an exemplary embodiment of this application is shown. This in-memory computing system is described as an example of implementing in-memory computation using memory as a carrier.

[0060] like Figure 1 As shown, the in-memory computing system 100 may include a storage circuit 110 and a control circuit 120. The storage circuit 110 can be used to store weight data (also called weights); the control circuit 120 can be used to control the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit 110. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 includes a storage cell array, which includes multiple storage cells arranged in an array.

[0061] The storage unit may include a semiconductor device and utilize the conductivity of the semiconductor device, such as electrical conductance or transconductance, to store weight data. For example, the storage unit may include a resistive storage device or a transistor storage device. For example, weight data can be stored by controlling the conductivity of the resistive storage device, or by controlling the transconductance of the transistor storage device. Alternatively, the storage unit may utilize the energy stored in an energy storage element to store weight data, such as the charge stored in a capacitor; this energy storage element may be connected to the semiconductor device, and the stored energy may act on the semiconductor device, causing the semiconductor device to generate a corresponding conductivity.

[0062] The storage circuit 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group and outputting them can achieve an equivalent multiplication operation. The storage cell array can include a one-dimensional array, a two-dimensional array, or a three-dimensional array, etc., and the storage cell group includes multiple storage cells located in the same row or column of the storage cell array, or multiple storage cells located in multiple rows or columns, etc., and these multiple storage cells can be output collinearly.

[0063] In some possible embodiments, the in-memory computing system 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 can convert input data D1 into at least one input signal Sin and provide it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on weight data; the output circuit 140 can convert the output signal Sout into output data D2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0064] As an example, Figure 2 A schematic diagram of yet another in-memory computing system according to an exemplary embodiment of this application is shown.

[0065] like Figure 2 As shown, the in-memory computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes multiple memory cells S. ij Where i∈[1,m], j∈[1,n], m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array. Storage cell S ij It can store weight data W ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula:

[0066]

[0067] In some possible embodiments, the input data includes digital input signals, such as the input signal V of the storage cell array 210. iThe input signal may include an analog signal. The input circuit 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal and provide it to the memory cell array 210. In some possible embodiments, the input signal to the memory cell array 210 may include a digital signal, which is represented by the signal's waveform characteristics, such as pulse width, amplitude, or area. The input circuit 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array 210.

[0068] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. This conversion may include one or more signal type conversions, signal magnitude conversions, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For instance, if the output signal of the memory cell array 210 includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Alternatively, the output circuit 240 may include a second conversion circuit 242 for performing a second conversion on the output signal of the memory cell array 210. The second conversion may be implemented, for example, through a sampling circuit. Optionally, the signal converted by the first conversion circuit 241 may be further provided to the second conversion circuit 242 for a second conversion. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert a current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal for subsequent circuitry. Alternatively, the output circuit may include a sense amplifier (SA) that can sense, amplify, or process the signal obtained from the memory cell array 210 or the first conversion circuit 241. Furthermore, in Figure 2 In the example, the in-memory computing system 200 may further include a control circuit 220, which can be used to control the memory cells S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.

[0069] Figure 2 This is merely an example illustrating a connection method of storage cells in a storage cell array 210, except... Figure 2Besides the connection method shown, other connection methods can also be used. For example, the input terminals of the memory cells can be connected in columns along a common line, and the output terminals of the memory cells can be connected in rows along a common line. Furthermore, the input terminals of the memory cells can include the gate of a transistor memory device, or the input terminals of the memory cells can include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, the memory cell can include, but is not limited to, transistors, memristors, magnetic tunnel junctions (MTJs), or phase-change structures. This application also does not limit the type of transistor, including, for example, metal oxide semiconductor field-effect transistors (MOSFETs), floating gate transistors (FGTs), ferroelectric field-effect transistors (FeFETs), and thin-film transistors (TFTs). A memory cell may include multiple transistors; for example, a memory cell may include a first transistor and a second transistor, wherein the gate of the first transistor (which may be referred to as a "read transistor" or "read tube") and the source or drain of the second transistor (which may be referred to as a "write transistor" or "write tube") are connected, and the charge stored at the gate of the first transistor can be used to characterize weight data. Optionally, the gate of the first transistor may also be connected to a capacitor to increase the stability and duration of the stored charge.

[0070] The output circuit 140 / 240 conversion circuit can adopt a differential structure, utilizing the two outputs of the storage circuit to obtain differential results, thereby reducing the impact of common-mode noise and improving the accuracy of the calculation results of the in-memory computing system. For example, Figure 3 A schematic diagram of yet another in-memory computing system according to an exemplary embodiment of this application is shown. For example... Figure 3 As shown, the in-memory computing system 300 includes a storage circuit 310 and a conversion circuit 320. The storage circuit 310 may include multiple outputs, and the conversion circuit 320 may couple two of the outputs. The difference between the two outputs is used to represent the calculation result of the in-memory computing system. For example, the storage circuit can be used to calculate vector W*I, where W can be realized using the weight data stored in the storage unit group of the storage circuit, and I can be realized using the input of the storage circuit. In the difference structure, vector W can be split into the difference of two vectors, i.e., W = Wp - Wn; where vector Wp represents the minuend vector and can be stored in the first storage unit group; Wn represents the subtrahend vector and can be stored in the second storage unit group; the output of the first storage unit group ( Figure 3(represented by "+") and the output of the second memory cell group ( Figure 3 The difference result (represented by "-") represents the calculation result. The output of the first memory cell group and the output of the second memory cell group may include a common-mode part and a differential-mode part. The common-mode part can be eliminated when the difference is calculated, thereby reducing the influence of common-mode noise. The differential-mode part can be used to characterize the calculation result, thereby improving the calculation accuracy of the memory circuit. The memory cell group is described as in the above embodiment. For example, the memory cells in the memory cell group may be located in the same column or the same row and share the same output line. Figure 3 The direction of the middle arrow does not indicate the direction of current flow, but only the input or output direction.

[0071] This description uses a conversion circuit to convert a current signal into a voltage signal as an example. Please refer to [link / reference]. Figure 4 This diagram illustrates a circuit structure of a conversion circuit according to an exemplary embodiment of this application. The conversion circuit 400 includes a first branch 410 and a second branch 420. The first branch 410 may include an input terminal INp and an output terminal OUTp, and the second branch 420 may include an input terminal INn and an output terminal OUTn; wherein the input terminals INp and INn are respectively used to couple two outputs of a storage circuit (e.g., ...). Figure 3 (The "+" and "-" symbols indicate the two outputs). For example, the first branch 410 includes a capacitor Cp, switches Sp1 and Sp2, and a clamping circuit 411. One end of capacitor Cp, Cp1, serves as the output terminal OUTp of the first branch 410, and the other end is coupled to a voltage V. Switch Sp1 is connected in parallel across capacitor Cp. Switch Sp2 is connected between capacitor Cp and the input terminal INp. The clamping circuit 411 is used to clamp the voltage at the input terminal INp, stabilizing the voltage at INp. The second branch 420 includes a capacitor Cn, switches Sn1 and Sn2, and a clamping circuit 421. One end of capacitor Cn, Cn1, serves as the output terminal OUTn of the second branch 420, and the other end is coupled to a voltage V. Switch Sn1 is connected in parallel across capacitor Cn. Switch Sn2 is connected between capacitor Cn and the input terminal INn. The clamping circuit 421 is used to clamp the voltage at the input terminal INn, stabilizing the voltage at INn. This application does not limit the magnitude of the voltage V, which may include the supply voltage or reference voltage of the circuit. For example, the voltage V may include a positive supply voltage (VDD) or a negative supply voltage / ground voltage (VSS).

[0072] During in-memory computing, control switches Sp1 and Sn1 are turned on or off, resetting one end (Cp1) and one end (Cn1) of capacitors Cp and Cn to voltage V. Control switches Sp2 and Sn2 are turned on or off, allowing one output current from the storage circuit to flow from one end (Cp1) of capacitor Cp to the storage circuit, discharging capacitor Cp, and the other output current from one end (Cn1) of capacitor Cn to the storage circuit, discharging capacitor Cn; or, allowing one output current from the storage circuit to flow from the storage circuit to one end (Cp1) of capacitor Cp, charging capacitor Cp, and the other output current from the storage circuit to flow from the storage circuit to one end (Cn1) of capacitor Cn, charging capacitor Cn. After time t, the voltage across one end (Cp1) and one end (Cn1) of capacitors Cp and Cn changes, and the magnitudes of the two output currents of the storage circuit can be converted into changes in the voltage across capacitors Cp and Cn, respectively. By using the difference in voltage output at the output terminals of capacitors Cp and Cn as the calculation result of the memory system, common-mode noise can be reduced using analog circuit design, thereby improving the calculation accuracy of the memory circuit.

[0073] As an example, the voltage difference can be expressed by the following formula (1):

[0074] ΔV out =ΔV p -ΔV n Formula (1)

[0075] Where, ΔV out The voltage difference, ΔV p ΔV represents the voltage change across capacitor Cp. n This represents the change in voltage across capacitor Cn.

[0076] The voltage change across capacitor Cp and the voltage change across capacitor Cn can be expressed by the following formulas (2) and (3), respectively:

[0077]

[0078] Among them, C p C represents the capacitance value of capacitor Cp. n I represents the capacitance value of capacitor Cn. p I represents the output current of the storage circuit flowing through the first branch 410. n t represents the output current of the storage circuit flowing through the second branch 420, and t represents the charging or discharging time.

[0079] Substituting formulas (2) and (3) into formula (1) yields formula (4):

[0080]

[0081] Taking the example where the capacitance values ​​of capacitors Cp and Cn are both C, the voltage difference ΔV can be obtained. out It is related to the difference in current ΔI, time t, and capacitance C.

[0082] The output current of a storage circuit includes a common-mode component (common-mode current) and a differential-mode component (differential-mode current). Differential calculation using these two outputs eliminates the common-mode component, and the calculation result of the in-memory computing system is primarily affected by the differential-mode component. Although the common-mode component theoretically should not affect the calculation result according to the above formula, in practical circuits, it can still affect the calculation accuracy, especially as the size of the storage circuit increases. For example, an increase in the common-mode component reduces the proportion of the differential-mode component, which is equivalent to a decrease in the proportion of the useful part of the signal output to the subsequent circuit. This leads to a decrease in the conversion accuracy of the subsequent circuit during conversion, thus reducing the calculation accuracy of the in-memory computing system. For instance, if the subsequent circuit includes an analog-to-digital converter (ADC), a decrease in the proportion of the differential voltage corresponding to the differential-mode component in the voltage supplied to the ADC reduces the quantization accuracy of the differential-mode component by the ADC, resulting in a decrease in the calculation accuracy of the in-memory computing system.

[0083] For ease of understanding, Figure 5 The following is a description of an example. Figure 5 A schematic diagram of the output current of a storage circuit according to an exemplary embodiment of this application is shown. Figure 5 As shown, one output of the storage circuit includes a current signal Ip01 or Ip02, and the other output includes a current signal In01 or In02. Both outputs include common-mode and differential-mode components. When the common-mode component increases, the proportion of the differential-mode component decreases. Consequently, the proportion of the differential voltage corresponding to the differential-mode component in the output voltage of the conversion circuit decreases, thus affecting the conversion accuracy of subsequent conversion circuits. For example, if the common-mode components of current signals Ip02 and In02 are larger than those of current signals Ip01 and In01, the proportion of the differential-mode component in current signals Ip02 and In02 is smaller compared to Ip01 and In01. When using the above conversion circuit, for output currents with larger common-mode components, the proportion of the differential voltage corresponding to the differential-mode component in the output voltage of the conversion circuit becomes smaller, leading to a decrease in the quantization accuracy of subsequent conversion circuits and consequently a decrease in the computational accuracy of the memory computing system.

[0084] Based on this, embodiments of this application provide a conversion circuit and control method, control device, memory computing device, and electronic device. By setting a feedback control circuit in the conversion circuit, the signal on the conversion branch in the conversion circuit is detected, and the effective current on the conversion branch is controlled by the signal, so that the common-mode part in the effective current is reduced, thereby increasing the proportion of the differential-mode part, and thus increasing the proportion of the differential voltage corresponding to the differential-mode part in the output voltage of the conversion circuit, thereby improving the conversion accuracy of the subsequent conversion circuit, and thus improving the calculation accuracy of the memory computing system.

[0085] The following description is in conjunction with the accompanying drawings.

[0086] Figure 6 A schematic diagram of a conversion circuit according to an exemplary embodiment of this application is shown. The conversion circuit 600 can be used in a memory computing system, which may include a storage circuit. The conversion circuit 600 is used to convert and output the output signal of the storage circuit. The output signal of the storage circuit includes a first current signal Ip1 and a second current signal In1. The conversion circuit 600 includes a first conversion branch 610, a second conversion branch 620, and a feedback control circuit 630. The first conversion branch 610 includes a first input terminal INp and a first output terminal OUTp. The first input terminal INp can be connected to the storage circuit to couple the first current signal Ip1 of the storage circuit, and the first output terminal OUTp is used to output a first voltage signal. The second conversion branch 620 includes a second input terminal INn and a second output terminal OUTn. The second input terminal INn can be connected to the storage circuit to couple the second current signal In1 of the storage circuit, and the second output terminal OUTn is used to output a second voltage signal. Feedback control circuit 630 is connected to the first conversion branch 610 and the second conversion branch 620, and is used to control the first bias current acting on the first conversion branch 610 and the second bias current acting on the second conversion branch 620 according to the first signal of the first conversion branch 610 and the second signal of the second conversion branch 620. The first conversion branch 610 is used to generate a first voltage signal at the first output terminal OUTp when the first current signal Ip1 and the first bias current act for a first time, and the second conversion branch 620 is used to generate a second voltage signal at the second output terminal OUTn when the second current signal In1 and the second bias current act for a first time.

[0087] In the above conversion circuit, a feedback control circuit is used to detect the signal on the conversion branch and use the signal to control the bias current supplied to the conversion branch. This bias current can change the effective current of the conversion branch, thereby reducing the common-mode portion of the effective current and increasing the proportion of the differential-mode portion. This, in turn, increases the proportion of the differential voltage corresponding to the differential-mode portion in the output voltage of the conversion circuit, thereby improving the conversion accuracy of the subsequent conversion circuit and thus improving the calculation accuracy of the in-memory computing system.

[0088] The feedback control circuit can control the bias current based on a voltage or current signal on the switching branch. According to some embodiments, the first signal includes a third current signal flowing through the first switching branch 610 during a second time period; the second signal includes a fourth current signal flowing through the second switching branch 620 during the second time period. According to some embodiments, the first signal includes a third voltage signal at the first output terminal OUTp when the second time period expires, and the second signal includes a fourth voltage signal at the second output terminal OUTn when the second time period expires.

[0089] This application does not limit the magnitude of the first time period, which can be a preset time. The first time period may include, for example, the time from when the bias current acts on the switching branch until the switching branch stabilizes. This application does not limit the magnitude of the second time period, which may include the calculation time of the switching branch. During this calculation time, the switching branch can use the charging or discharging control of the energy storage element to realize the calculation of converting the current signal into a voltage signal.

[0090] The feedback control circuit 630 can control the bias current (first bias current or second bias current) using a closed-loop feedback method. In this case, the second time may include part or all of the first time. Alternatively, the feedback control circuit 630 can control the bias current using an open-loop feedback method. In this case, the second time can be independent of the first time.

[0091] The first conversion branch 610 can be coupled to a first current signal Ip1 and a first bias current during the calculation phase. When the first current signal Ip1 and the first bias current act for a first time, a first voltage signal is generated at the first output terminal OUTp; and during the output phase, the first voltage signal is output. The second conversion branch 620 can be coupled to a second current signal In1 and a second bias current during the calculation phase. When the second current signal In1 and the second bias current act for a first time, a second voltage signal is generated at the second output terminal OUTn; and during the output phase, the second voltage signal is output. The difference between the first voltage signal and the second voltage signal is used to generate the differential result of the memory computing system.

[0092] According to some embodiments of this application, the operation stages of the conversion circuit may include a preparation stage 1, a preparation stage 2, a calculation stage, and an output stage. In the calculation stage, the conversion circuit 600 converts the output current of the storage circuit into a voltage change that reflects the magnitude of the output current. In the output stage, the conversion circuit 600 outputs an output voltage that reflects this voltage change to the subsequent circuit.

[0093] According to some embodiments of this application, the first bias current and the second bias current can be the same, or differ within a tolerance range. In this way, the debiasing current can not affect the differential-mode portion of the two outputs, thereby reducing the common-mode portion while keeping the differential-mode portion of the two output currents unchanged, thus increasing the proportion of the differential-mode portion.

[0094] According to some implementations of this application, the first conversion branch 610 and the second conversion branch 620 may include symmetrical structures. Thus, the same suppression of the common-mode portion of the two outputs can be achieved through a simple symmetrical circuit structure.

[0095] The conversion circuit provided in this application embodiment can be applied to, for example... Figure 2 The first conversion circuit 241 is shown. The outputs of the two memory cell groups of the memory cell array 210 can be used as the first current signal Ip1 and the second current signal In1 of the conversion circuit. The conversion circuit 241 can convert the current signal output by the memory cell array 210 into a voltage signal.

[0096] The conversion circuit provided in this application embodiment can support differential input and differential output. For details regarding differential input and differential output, please refer to the above. Figure 3 As described in the illustrated embodiment, this input and output method can effectively suppress common-mode noise and improve the signal's anti-interference capability. Differential output can include two output signals, which can be subtracted in a conversion circuit or subsequent circuit to obtain the differential result calculated by the in-memory computing system. Differential output can eliminate common-mode noise, thereby improving calculation accuracy, which is of great significance for in-memory computing systems.

[0097] According to some embodiments of this application, the conversion circuit may include a differential amplifier circuit. In the differential amplifier circuit, the differential signal between the two input terminals (i.e., the two outputs of the storage circuit) can be amplified while suppressing the common-mode signal. This provides a wider range of useful signals for subsequent circuits, which can obtain a differential signal corresponding to the differential output of the storage circuit by subtracting the output signal of the conversion circuit.

[0098] According to some implementations of this application, the switching branch may include a control circuit, an energy storage element, a reset circuit, and a bias circuit. The control circuit can be used to control the charging / discharging of the energy storage element, such as controlling whether the energy storage element is discharging / charging, or controlling one or more parameters such as the discharging / charging time or discharging / charging ratio of the energy storage element. The reset circuit is used to reset the voltage of the energy storage element. The bias circuit is used to provide a bias current (a first bias current or a second bias current).

[0099] The switching branch is described below with reference to the attached diagram. Please refer to it. Figure 7This illustrates a schematic diagram of another conversion circuit according to an exemplary embodiment of this application. Figure 7 As shown, the conversion circuit 700 includes a first conversion branch 710, a second conversion branch 720, and a feedback control circuit 730. The first conversion branch 710 may include a first control circuit 713, a first energy storage element 711, and a first reset circuit 712. One end of the first energy storage element 711 is used to couple a voltage V, which may include a supply voltage or a reference voltage; the other end is used for the first output terminal OUTp. The first control circuit 713 is connected between the first input terminal INp and the first output terminal OUTp. The first reset circuit 712 is connected to the other end of the first energy storage element 711 and is used to reset the voltage at the first output terminal OUTp; for example, it may be connected in parallel with the first energy storage element 711. The second conversion branch 720 may include a second control circuit 723, a second energy storage element 721, and a second reset circuit 722. In this circuit, one end of the second energy storage element 721 is used to couple a voltage V, which may include a supply voltage or a reference voltage, and the other end is used for the second output terminal OUTn. A second control circuit 723 is connected between the second input terminal INn and the second output terminal OUTn. A second reset circuit 722 is connected to the other end of the second energy storage element 721 and is used to reset the voltage at the second output terminal OUTn, for example, it can be connected in parallel with the second energy storage element 721. The first conversion branch 710 may further include a first bias circuit 714, connected to the feedback control circuit 730 and the first input terminal INp, for providing a first bias current Ip2 to the first input terminal INp under the control of the feedback control circuit 730. The second conversion branch 720 may further include a second bias circuit 724, connected to the feedback control circuit 730 and the second input terminal INn, for providing a second bias current In2 to the second input terminal INn under the control of the feedback control circuit 730.

[0100] The first reset circuit 712 can reset the voltage of the first energy storage element 711 to a preset voltage, and the second reset circuit 722 can reset the voltage of the second energy storage element 712 to a preset voltage, which may include, for example, voltage V. That is, the first reset circuit 712 and the second reset circuit 722 can be coupled to voltage V, thereby reducing the number of signal sources coupled to the conversion circuit and reducing signal interference. In some other embodiments, the preset voltage may also include other voltages independent of voltage V. For example, the first energy storage element 711 and the second energy storage element 721 may include capacitors. The control circuit can be used to control parameters related to the charging or discharging of the capacitors. For example, the first control circuit 713 can be used to control parameters related to the charging or discharging of capacitor Cp, and the second control circuit 723 can be used to control parameters related to the charging or discharging of capacitor Cn. For example, the parameters may include one or more of the following: the discharge state of the capacitor (e.g., whether the capacitor is discharging), the discharge time of the capacitor, or the discharge ratio of the capacitor.

[0101] This application does not limit the type of capacitor. For example, the energy storage element may include one or more capacitors, which may include, but are not limited to: metal-oxide-metal (MOM) capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-poly (PIP) capacitors, metal-oxide-semiconductor (MOS) capacitors, or diode capacitors, etc.

[0102] In one implementation, the conversion branch may further include a clamping circuit. The clamping circuit can be used to stabilize the voltage at the output terminal of the storage circuit. For example, the first conversion branch 710 may also include a first clamping circuit 715, which is used to stabilize the voltage at the first input terminal INp. The second conversion branch 720 may further include a second clamping circuit 725, which is used to stabilize the voltage at the second input terminal INn. In this way, the voltage at the output terminal of the storage cell group of the storage circuit remains stable during calculations, thereby further improving the calculation accuracy of the in-memory computing system.

[0103] According to some embodiments of this application, the feedback control circuit may employ an analog-to-digital converter (ADC) to sample the first signal and the second signal, and the bias circuit may employ a digital-to-analog converter (DAC) to generate a bias current. For example, the first bias circuit 714 includes a first DAC and generates a first bias current Ip2 through the first DAC; the second bias circuit 724 includes a second DAC and generates a second bias current In2 through the second DAC.

[0104] Thus, the above conversion circuit can detect the current of the conversion branch of the conversion circuit through the AD (analog-to-digital) to DA (digital-to-analog) feedback circuit and its control method, and subtract part or all of the common-mode current in a zero-differential manner. Without affecting the differential result, the common-mode part of the output current is reduced, thereby increasing the proportion of the differential part.

[0105] According to some embodiments of this application, the control circuit (e.g., the first control circuit or the second control circuit) may include a discharge control circuit for controlling the discharge of the energy storage element (e.g., the first energy storage element or the second energy storage element), at which time the current flows from the first output terminal OUTp or the energy storage element 711 to the first input terminal INp, and the current flows from the second output terminal OUTn or the energy storage element 721 to the second input terminal INn.

[0106] According to some embodiments of this application, the control circuit (e.g., the first control circuit or the second control circuit) may include a charging control circuit for controlling the charging of the energy storage element (e.g., the first energy storage element or the second energy storage element), in which current flows from the first input terminal INp to the first output terminal OUTp or the energy storage element 711, and current flows from the second input terminal INn to the second output terminal OUTn or the energy storage element 721.

[0107] The following description is in conjunction with the accompanying drawings. For example, please refer to... Figure 8 This illustrates a schematic diagram of another conversion circuit according to an embodiment of this application. Figure 8 As shown, the control circuit (e.g., the first control circuit or the second control circuit) may include a discharge control circuit as an example. The conversion circuit 800 includes a first conversion branch 810, a second conversion branch 820, and a feedback control circuit 830. The first conversion branch 810 may include: a first energy storage element 811, a first reset circuit 812, a first control circuit 813, and a first bias circuit 814. The second conversion branch 820 may include: a second energy storage element 821, a second reset circuit 822, a second control circuit 823, and a second bias circuit 824. The descriptions of each circuit are the same as above. Figure 7 In the embodiment shown, the voltage V includes, for example, the voltage VDD.

[0108] In one implementation, the conversion branch may further include a clamping circuit, which can be used to stabilize the voltage at the output terminal of the storage circuit. For example, the first conversion branch 810 may further include a first clamping circuit 815 for stabilizing the voltage at the first input terminal INp. The second conversion branch 820 may further include a second clamping circuit 825 for stabilizing the voltage at the second input terminal INn. In this way, the voltage at the output terminal of the storage cell group of the storage circuit remains stable during calculations, thereby further improving the calculation accuracy of the in-memory computing system.

[0109] exist Figure 8 In the illustrated embodiment, the control circuit may include a discharge control circuit for controlling parameters related to the discharge of the capacitor. For example, the first control circuit 813 may be a first discharge control circuit for controlling parameters related to the discharge of capacitor Cp, and the second control circuit 823 may be a second discharge control circuit for controlling parameters related to the discharge of capacitor Cn. At this time, current flows from the first output terminal OUTp or the energy storage element 811 to the first input terminal INp, and current flows from the second output terminal OUTn or the energy storage element 821 to the second input terminal INn.

[0110] For example, please refer to Figure 9 This illustrates a schematic diagram of another conversion circuit according to an exemplary embodiment of this application. Figure 9 As shown, the control circuit (e.g., the first control circuit or the second control circuit) may include a charging control circuit as an example. The conversion circuit 900 includes a first conversion branch 910, a second conversion branch 920, and a feedback control circuit 930. The first conversion branch 910 may include: a first energy storage element 911, a first reset circuit 912, a first control circuit 913, and a first bias circuit 914. The second conversion branch 920 may include: a second energy storage element 921, a second reset circuit 922, a second control circuit 923, and a first bias circuit 924. The descriptions of each circuit are the same as above. Figure 7 In the embodiment shown, the voltage V includes, for example, the voltage VSS.

[0111] In one implementation, the conversion branch may further include a clamping circuit, which can be used to stabilize the voltage at the output terminal of the storage circuit. For example, the first conversion branch 910 may further include a first clamping circuit 915 for stabilizing the voltage at the first input terminal INp. The second conversion branch 920 may further include a second clamping circuit 925 for stabilizing the voltage at the second input terminal INn. In this way, the voltage at the output terminal of the storage cell group of the storage circuit remains stable during calculations, thereby further improving the calculation accuracy of the in-memory computing system.

[0112] exist Figure 9 In the example shown, the control circuit may include a charging control circuit for controlling charging-related parameters of the capacitor. For example, the first control circuit 913 may be a first charging control circuit for controlling charging-related parameters of capacitor Cp, and the second control circuit 923 may be a second charging control circuit for controlling charging-related parameters of capacitor Cn. At this time, current flows from the first input terminal INp to the first output terminal OUTp or energy storage element 911, and current flows from the second input terminal INn to the second output terminal OUTn or energy storage element 921.

[0113] This application does not limit the implementation of the feedback control circuit, as long as the feedback control circuit can control the bias current acting on the switching branch according to the signal on the switching branch. This application also does not limit the implementation of the control circuit (first control circuit or second control circuit), as long as the control circuit can control the charging or discharging of the energy storage element in the corresponding switching branch. This application also does not limit the implementation of the reset circuit (first reset circuit or second reset circuit), as long as the reset circuit can reset the voltage of the corresponding input terminal or energy storage element. This application also does not limit the implementation of the clamping circuit (first clamping circuit and second clamping circuit), as long as the clamping circuit can stabilize the voltage of the corresponding input terminal.

[0114] The following, with reference to the accompanying drawings, presents several implementation methods for the feedback control circuit, control circuit, reset circuit, and clamping circuit, which are not limited to these methods in this application.

[0115] The feedback control circuit can control the generation of bias current by comparing the current of the first conversion branch; this current comparison can obtain the common-mode portion of the two outputs of the storage circuit, and use the common-mode portion to control the bias current, thereby reducing the common-mode portion in the output current. According to some embodiments, the feedback control circuit can directly compare the current magnitudes of the first and second conversion branches, or it can indirectly compare the currents by comparing the voltages of the first and second conversion branches.

[0116] This application does not limit the connection position of the feedback control circuit and the switching branch. For example, when the feedback control circuit compares currents, the current used for comparison (i.e., the first signal and the second signal) can be provided by the control circuit; when the feedback control circuit compares voltages (i.e., the first signal and the second signal), the voltage used for comparison can be provided by the control circuit; or the voltage for comparison can be obtained by sampling the voltage between the control circuit and the energy storage element or the voltage between the control circuit and the clamping circuit.

[0117] For example, Figure 10 A schematic diagram of a feedback control circuit according to an exemplary embodiment of this application is shown.

[0118] like Figure 10As shown, the feedback control circuit 1000 includes a comparator circuit 1010, a gating circuit 1020, and an analog-to-digital converter circuit 1030. The comparator circuit 1010 receives a first signal and a second signal, and outputs a first control signal based on the comparison result of the first and second signals. The gating circuit 1020 is connected to the comparator circuit 1010 and receives the first control signal, and according to the first control signal, connects either the first signal or the second signal to the analog-to-digital converter circuit 1030. The analog-to-digital converter circuit 1030 converts the first signal or the second signal into a second control signal, which controls a first bias current and a second bias current. According to some embodiments of this application, the feedback control circuit can compare the magnitudes of currents and generate a control signal using a smaller current. Alternatively, the feedback control circuit can compare the magnitudes of voltages and generate a control signal using a voltage with a smaller voltage difference relative to a reference voltage.

[0119] For example, the first and second signals include current signals, and the first control signal is used to control the gating circuit 1020 to select the signal with the smaller current among the first and second signals. For instance, the feedback control circuit can compare the magnitudes of the currents in the first and second switching branches, select the smaller one, and quantize it through an analog-to-digital converter to obtain a second control signal, which then controls the discharge of the digital-to-analog converter. As another example, the first and second signals include voltage signals, and the first control signal is used to control the gating circuit 1020 to select the signal with the smaller voltage difference relative to the reference voltage among the first and second signals.

[0120] In one implementation, the first bias circuit and the second bias circuit each include a first digital-to-analog converter (DAC) circuit and a second DAC circuit, respectively. The analog-to-digital converter (ADC) circuit 1030 outputs the generated second control signal to both the first ADC circuit and the second ADC circuit. The first ADC circuit and the second ADC circuit are, for example, current-mode ADC circuits, which output bias currents of the same magnitude.

[0121] In one implementation, the bias current is less than or equal to the smaller of the first and second current signals.

[0122] According to some embodiments of this application, when the first signal and the second signal are current signals, the comparison circuit 1010 can be a current-type comparison circuit, and the analog-to-digital conversion circuit 1030 can be a current-type analog-to-digital conversion circuit.

[0123] According to some embodiments of this application, when the first signal and the second signal are voltage signals, the comparison circuit 1010 can be a voltage-type comparison circuit, and the analog-to-digital conversion circuit 1030 can be a voltage-type analog-to-digital conversion circuit.

[0124] According to some embodiments of this application, when the feedback control circuit 1000 operates as a closed-loop feedback during the calculation phase, the comparison circuit 1010 can be a static comparator. When the feedback control circuit 1000 operates as an open-loop feedback during the calculation phase, the comparison circuit 1010 is a dynamic comparator. The static comparator can operate continuously for a period of time; the dynamic comparator operates only once under the action of an enable signal.

[0125] For example, Figure 11 A schematic diagram of another feedback control circuit according to an exemplary embodiment of this application is shown. Figure 11 As shown, the feedback circuit 1100 includes a comparator circuit 1110, a first analog-to-digital converter (ADC) circuit 1120, and a second ADC circuit 1130. The first ADC circuit 1120 receives a first signal and converts it into a third signal. The second ADC circuit 1130 receives a second signal and converts it into a fourth signal. The comparator circuit 1110 is connected to the first ADC circuit 1120 and the second ADC circuit 1130, and compares the third signal and the fourth signal. Based on the comparison result, it outputs a third control signal, which controls the first bias current and the second bias current.

[0126] According to some embodiments of this application, the feedback control circuit can compare the quantized signals and generate a control signal based on the comparison result. For example, the first and second signals include current signals. The first and second signals are quantized into a third and a fourth signal respectively through analog-to-digital conversion. The comparison circuit 1110 receives the third and fourth signals, and by comparing the magnitudes of the third and fourth signals, selects the smaller signal to generate a third control signal, which is then output to the first and second bias circuits. As another example, the first and second signals include voltage signals. The first and second signals are quantized into a third and a fourth signal respectively through analog-to-digital conversion. The comparison circuit 1110 receives the third and fourth signals, and by comparing the magnitudes of the third and fourth signals, selects either the smaller or larger signal to generate a third control signal, which is then output to the first and second bias circuits. This smaller or larger signal corresponds to the signal among the first and second signals that has a smaller voltage difference relative to the reference voltage.

[0127] In one implementation, the first bias circuit and the second bias circuit each include a first digital-to-analog converter (DAC) circuit and a second DAC circuit, respectively. The comparator circuit 1110 outputs the generated third control signal to both the first DAC circuit and the second DAC circuit. The first DAC circuit and the second DAC circuit are, for example, current-mode DAC circuits, which output bias currents of the same magnitude.

[0128] In one implementation, the bias current is less than or equal to the smaller of the first and second current signals.

[0129] According to some embodiments of this application, when the feedback control circuit 1110 is a closed-loop feedback during the calculation phase, the comparison circuit 1110 can be a static comparator. When the feedback control circuit 1110 is an open-loop feedback during the calculation phase, the comparison circuit 1110 is a dynamic comparator.

[0130] When the input signal to the feedback control circuit 1100 is a current signal, the first analog-to-digital converter (ADC) 1120 and the second ADC 1130 can be current-type ADCs; when the input signal to the feedback control circuit 1100 is a voltage signal, the first ADC 1120 and the second ADC 1130 can be voltage-type ADCs. The comparator circuit 1110 may include a digital logic comparator.

[0131] For example, Figure 12 Schematic diagrams of several clamping circuits according to exemplary embodiments of this application are shown. Exemplarily, the clamping circuits may be implemented using transistors, or a combination of operational amplifiers and transistors, or other circuit structures capable of stabilizing input node voltages. For example, such as... Figure 12 As shown in (a), the clamping circuit can have a single-stage transistor structure, such as including transistor M21. Alternatively, the clamping circuit can have a multi-stage transistor structure, such as... Figure 12 As shown in (b), the clamping circuit may include transistors M21 and M22 connected in series, or as shown in (b). Figure 12 As shown in (c), the clamping circuit may include transistors M21-M2Y connected in series, where Y is a positive integer greater than or equal to 3. For example, as... Figure 12 As shown in (d), the clamping circuit may include a transistor M20 and an operational amplifier O20, wherein the output terminal of the operational amplifier O20 is connected to the gate of the transistor M20, the inverting input terminal is connected to the source or drain of the transistor, and the non-inverting input terminal is coupled to the clamping voltage VCLAMP. The clamping circuit may also be other circuit structures that can stabilize the input node voltage, and this application embodiment does not limit this.

[0132] Figure 12 In this example, the transistor includes an N-channel transistor, such as an NMOS transistor. In other embodiments, the transistor may include a P-channel transistor, such as a PMOS transistor. Figure 12In the structure of a single-stage transistor, the drain and source can serve as the first terminal T1 and the second terminal T2, respectively. The first terminal T1 is used to connect to the energy storage element, and the second terminal T2 is used to connect to the storage circuit. In other embodiments, the source and drain can serve as the first terminal T1 and the second terminal T2, respectively. The first terminal T1 is used to connect to the energy storage element, and the second terminal T2 is used to connect to the storage circuit. The gate of the transistor is coupled to a clamping voltage VCLAMP1. Figure 12 In a multi-stage transistor structure, the sources and drains of different transistors are connected in series. In one transistor, the drain of one transistor can serve as the first terminal T1, and the source of the other transistor can serve as the second terminal T2. The first terminal T1 is used to connect to an energy storage element, and the second terminal T2 is used to connect to a storage circuit. In other embodiments, the source of one transistor can serve as the first terminal T1, and the drain of the other transistor can serve as the second terminal T2. The first terminal T1 is used to connect to an energy storage element, and the second terminal T2 is used to connect to a storage circuit. The gate coupling clamping voltage VCLAMPy of transistor M2y is given by y∈[1,Y]. When the current generation circuit has a multi-stage transistor structure, the clamping voltages of different transistors can be the same or different. For example, VCLAMP1 to VCLAMPY can be all the same, all different, or partially the same.

[0133] For example, Figure 13 and Figure 14 Schematic diagrams of several control circuits according to exemplary embodiments of this application are shown. Exemplarily, the control circuit can be implemented using transmission gates. This application does not limit the structure of the transmission gates; for example, they may include, but are not limited to, p-type transmission gates, n-type transmission gates, or CMOS transmission gates. Alternatively, they can be implemented using transmission gates combined with current mirrors. The transmission gates can include any of the above types and can be placed on any branch of the current mirror. This application does not limit the circuit structure of the current mirror, as long as the circuit structure of the current mirror can realize the proportional current mirroring function. This application also does not limit the current mirroring ratio, which can be set as needed. For example, the control circuit can have a transmission gate structure. Figure 13 As shown in (a), the control circuit can have a p-type transmission gate structure. Figure 13 As shown in (b) above, the control circuit can have an n-type transmission gate structure. Figure 13 As shown in (c), the control circuit can have a CMOS transmission gate structure. In the figure, Ctrl_N represents a control signal used to drive a p-type transmission gate, and Ctrl represents a control signal used to drive an n-type transmission gate. Furthermore, the control circuit can have a transmission gate structure combined with a current mirror. The transmission gate G30 can be placed on any branch of the current mirror structure, such as... Figure 13 (d) Figure 13 (e) and Figure 13On any branch shown in (f) in the diagram.

[0134] When the input signal to the feedback control circuit is a voltage signal, the control circuit can adopt any of the above structures. When the input signal to the feedback control circuit is a current signal, the control circuit can be implemented using a transmission gate combined with a current mirror, and the current signal is output on one branch of the current mirror, such as... Figure 14 (a) or Figure 14 On any branch shown in (b) in the diagram.

[0135] One end of the current mirror is coupled to voltage V31, and the other end is coupled to voltage V32, where there is a voltage difference between voltages V31 and V32 to drive the current mirror. For example, voltage V31 may include voltage VDD, and voltage V32 may include voltage VSS. A control circuit can be connected between the energy storage element and the input terminal of the corresponding conversion branch. One end of the control circuit, T31, is used to connect to the energy storage element, and the other end, T32, is used to connect to the input terminal of the corresponding conversion branch. One end of the control circuit, I31, is used to connect to the feedback control circuit.

[0136] For example, Figure 15 Schematic diagrams of several reset circuits according to exemplary embodiments of this application are shown. Exemplarily, the reset circuit may include a transmission gate, or a parallel structure between a transmission gate and a transmission gate-sampling resistor, wherein the sampling resistor is used to convert the difference between the current in the first conversion branch and the current in the second conversion branch into a voltage difference; the transmission gate or transmission gate branch is used to reset the voltages of the first energy storage element and the second energy storage element to a preset voltage Vpre. Exemplarily, when the input signal of the feedback control circuit is a voltage signal, the reset circuit may include a parallel structure between a transmission gate and a transmission gate-sampling resistor structure. Figure 15 As shown in (a), the sampling resistor R4 can be used to convert the current difference between the first and second conversion branches into a voltage difference. The transmission gate branch, such as transmission gate G41, is used to reset the voltage of the energy storage element to a preset voltage Vpre. For example, when the input signal to the feedback control circuit is a current signal, the reset circuit may include a transmission gate structure. Figure 15 As shown in (b), the transmission gate G40 is used to reset the voltage of the energy storage element to a preset voltage Vpre. The preset voltage Vpre may include, for example, the voltage V mentioned above, such as voltage VDD or VSS, or may be other voltages different from voltage V.

[0137] The switches (or transmission gates) illustrated in the accompanying drawings of the embodiments of this application may include p-type transmission gates, n-type transmission gates, or CMOS transmission gates. As long as they can satisfy the function of controllable voltage transmission, they can be understood as switches.

[0138] In any of the conversion circuits provided in the above embodiments, by setting a feedback control circuit in the conversion circuit, the signal on the conversion branch in the conversion circuit is detected, and the effective current on the conversion branch is controlled by the signal, so that the common-mode part in the effective current is reduced, thereby increasing the proportion of the differential-mode part, and thus increasing the proportion of the differential voltage corresponding to the differential-mode part in the output voltage of the conversion circuit, thereby improving the conversion accuracy of the subsequent conversion circuit, and thus improving the calculation accuracy of the in-memory computing system.

[0139] According to some embodiments of this application, the operation of the conversion circuit may include a first preparation stage, a second preparation stage, a calculation stage, and an output stage. In the first preparation stage, the voltages at the first output terminal of the first conversion branch and the second output terminal of the second conversion branch are reset, and the initial currents at the first input terminal of the first conversion branch and the second input terminal of the second conversion branch are established. In the second preparation stage, the feedback control circuit is activated, controlling the first bias current acting on the first conversion branch and the second bias current acting on the second conversion branch. When the currents in each part of the conversion circuit stabilize under the influence of the first and second bias currents, the calculation stage can begin; this stabilization time can be referred to as the first time, which may be, for example, a preset time. In the calculation stage, the feedback control circuit can be activated to form a closed-loop feedback, or deactivated to form an open-loop feedback; the conversion branch converts the current signal into a voltage signal at the output terminal; in the output stage, the conversion branch outputs a voltage signal at the output terminal.

[0140] by Figure 7 Taking the conversion circuit shown as an example, in the first preparation stage, the feedback control circuit 730, the first bias circuit 714 and the second bias circuit 724 are turned off, while the first reset circuit 712, the second reset circuit 722, the first control circuit 713 and the second control circuit 723 are turned on; the connection between voltage V and the first input terminal INp is turned on, the connection between voltage V and the second input terminal INn is turned on, the initial current at the output terminal of the storage circuit is established, that is, the current at the first input terminal INp and the second input terminal INn is initially established; and the voltages at the first output terminal OUTp and the second output terminal OUTn are reset.

[0141] According to some embodiments of this application, the voltages of the first output terminal OUTp and the second output terminal OUTn can be reset to voltage V, which simplifies the requirement for signal sources in the circuit and reduces signal interference.

[0142] In the second preparation phase, the feedback control circuit 730, the first bias circuit 714, the second bias circuit 724, the first reset circuit 712, the second reset circuit 722, the first control circuit 713, and the second control circuit 723 are activated. The first bias circuit outputs a first bias current Ip2, and the second bias circuit outputs a second bias current In2. The first bias current Ip2 and the second bias current In2 act on the first conversion branch and the second conversion branch, respectively, to reduce the common-mode portion of the effective current in the first conversion branch and the second conversion branch.

[0143] During the calculation phase, the first reset circuit 712 and the second reset circuit 722 are turned off, the feedback control circuit 730 is turned on or off, the first bias circuit 714, the second bias circuit 724, the first control circuit 713 and the second control circuit 723 are turned on, the first energy storage element 711 and the second energy storage element 721 begin to charge or discharge, and when the first time expires, the first output terminal OUTp or the second output terminal OUTn generates a voltage, realizing the conversion from current to voltage.

[0144] During the output phase, the feedback control circuit 730, the first bias circuit 714, the second bias circuit 724, the first control circuit 713, the second control circuit 723, the first reset circuit 712, and the second reset circuit 722 are turned off. The connection between the first energy storage element 711 in the first conversion branch 710 and the first input terminal INp is disconnected, and the connection between the second energy storage element 721 in the second conversion branch 720 and the second input terminal INn is disconnected. A first voltage signal is output at the first output terminal OUTp, and a second voltage signal is output at the second output terminal OUTn. The difference between the first voltage signal and the second voltage signal can be used as the differential result of the conversion circuit output, i.e., the differential result of the memory computing system.

[0145] The following description, in conjunction with the accompanying drawings, will illustrate the workflow of the conversion circuit. This workflow may include, for example, a first preparation stage, a second preparation stage, a calculation stage, and an output stage.

[0146] The following is based on Figure 8 The conversion circuit shown is used as an example to describe the working process of the conversion circuit. Other structures are similar and will not be described in detail. For example, Figure 16 A schematic diagram of a conversion circuit in a first preparation stage according to an exemplary embodiment of this application is shown.

[0147] In the first preparation phase, the feedback control circuit 830, the first bias circuit 814, and the second bias circuit 824 are turned off. The first reset circuit 812, the second reset circuit 822, the first control circuit 813, and the second control circuit 823 are turned on. The connection between voltage VDD and the first input terminal INp is turned on, and the connection between voltage VDD and the second input terminal INn is turned on. The initial current at the output terminal of the storage circuit is established, that is, the current at the first input terminal INp and the second input terminal INn is initially established; and the voltages at the first output terminal OUTp and the second output terminal OUTn are reset. The voltages at the first output terminal OUTp and the second output terminal OUTn can be reset to a preset voltage, which may include, for example, voltage VDD.

[0148] Figure 17 A schematic diagram of a conversion circuit for a second preparation stage according to an exemplary embodiment of this application is shown.

[0149] In the second preparation phase, the feedback control circuit 830, the first bias circuit 814, the second bias circuit 824, the first reset circuit 812, the second reset circuit 822, the first control circuit 813, and the second control circuit 823 are activated. The feedback control circuit 830 compares and quantizes the first signal of the first conversion branch 810 and the second signal of the second conversion branch 820. For example, the smaller current signal between the first and second signals is quantized into a voltage control signal and sent to the first bias circuit 814 and the second bias circuit 824. The first bias circuit 814 includes a first digital-to-analog converter circuit, and the second bias circuit 824 includes a second digital-to-analog converter circuit. The voltage control signal controls the first and second digital-to-analog converter circuits to generate a first bias current Ip2 and a second bias current In2, respectively, wherein the first bias current Ip2 and the second bias current In2 are of the same magnitude. The first and second digital-to-analog converters can be current-mode digital-to-analog converters. Based on the voltage control signal from the feedback control circuit, they adjust the output current so that it is less than or equal to the common-mode current in the first and second conversion branches. After the currents in each part of the conversion circuit 800 stabilize, the next stage begins.

[0150] Figure 18 A schematic diagram of a conversion circuit for a computing stage according to an exemplary embodiment of this application is shown.

[0151] In one implementation, during the calculation phase, the feedback control circuit can employ closed-loop feedback. During this phase, the first reset circuit 812 and the second reset circuit 822 are turned off, while the feedback control circuit 830, the first bias circuit 814, the second bias circuit 824, the first control circuit 813, and the second control circuit 823 are turned on. The first energy storage element 811 and the second energy storage element 821 begin discharging. The feedback control circuit 830 samples the first signal in the first conversion branch 810 and the second signal in the second conversion branch 820, dynamically compares and quantizes them, and adjusts the control of the first bias circuit 814 and the second bias circuit 824 in real time. For example, the feedback control circuit 830 quantizes the smaller current signal from the first and second signals into a control signal and sends it to the first bias circuit 814 and the second bias circuit 824. Based on this control signal, the first bias circuit 814 and the second bias circuit 824 adjust in real time and output a first bias current Ip2 and a second bias current In2 of the same magnitude. After the preset calculation time is reached, the calculation phase ends and the next phase, the output phase, begins.

[0152] Figure 19 A schematic diagram of a conversion circuit for another computing stage according to an exemplary embodiment of this application is shown.

[0153] In another implementation, during the calculation phase, the feedback control circuit can employ open-loop feedback. In this open-loop feedback phase, the first reset circuit 812, the second reset circuit 822, and the feedback control circuit 830 are turned off, while the first bias circuit 814, the second bias circuit 824, the first control circuit 813, and the second control circuit 823 are turned on. The feedback control circuit 830 does not sample the first signal in the first conversion branch 810 or the second signal in the second conversion branch 820. The control signal provided by the feedback control circuit 830 to the first bias circuit 814 and the second bias circuit 824 is the control signal obtained in the second preparation phase. The first energy storage element 811 and the second energy storage element 821 begin discharging. The feedback control circuit 830 sends the control signal obtained in the second preparation phase to the first bias circuit 814 and the second bias circuit 824. Based on this control signal, the first bias circuit 814 and the second bias circuit 824 adjust and output the same first bias current Ip2 and second bias current In2. After reaching the preset calculation time, the calculation phase ends, and the next phase, the output phase, begins.

[0154] In the above embodiments, the control circuit (e.g., the first control circuit 813 or the second control circuit 823) includes a discharge control circuit for controlling the discharge of the energy storage element (e.g., the first energy storage element 811 or the second energy storage element 821). At this time, the current flows from the first output terminal OUTp or the energy storage element 811 to the first input terminal INp, and the current flows from the second output terminal OUTn or the energy storage element 821 to the second input terminal INn.

[0155] Figure 20 A schematic diagram of an output stage conversion circuit according to an exemplary embodiment of this application is shown.

[0156] During the output phase, the feedback control circuit 830, the first reset circuit 812, the second reset circuit 822, the first control circuit 813, the second control circuit 823, the first bias circuit 814, and the second bias circuit 824 are turned off. The voltage VDD in the first conversion branch 810 and the connection between the first energy storage element 811 and the first input terminal INp are disconnected. The voltage VDD in the second conversion branch 820 and the connection between the second energy storage element 821 and the second input terminal INn are disconnected. The energy storage element no longer discharges. The first voltage signal Vp is output at the first output terminal OUTp, and the second voltage signal Vn is output at the second output terminal OUTn. The difference between the first voltage signal and the second voltage signal (Vp-Vn) is the differential voltage output of the conversion circuit 800, which can be used for differential result calculation of the storage system.

[0157] This application also provides an in-memory computing system, which may include a storage circuit and any of the above-described conversion circuits. The storage circuit receives an input signal and converts the input signal into an output signal based on stored weight data. The storage circuit may include a storage cell array. The conversion circuit is connected to the storage circuit and is used to convert the output signal before outputting it.

[0158] This application also provides a control method for controlling a conversion circuit to convert and output the output signal of a storage circuit.

[0159] Figure 21 A schematic diagram of a control method provided according to an exemplary embodiment of this application is shown. The control method may include the following steps:

[0160] S211, the control feedback control circuit is turned on. The feedback control circuit controls the first bias current acting on the first conversion branch and the second bias current acting on the second conversion branch according to the first signal of the first conversion branch and the second signal of the second conversion branch.

[0161] S212, the control feedback control circuit shuts down when the first time expires, outputs a first voltage signal at the first output terminal of the first conversion branch, and outputs a second voltage signal at the second output terminal of the second conversion branch.

[0162] The above control method can be executed by a control device that can control each circuit part of the conversion circuit to be in an on or off state, so that the conversion circuit operates in the first preparation stage, the second preparation stage, the calculation stage, and the output stage. The description of the state of the conversion circuit in each working stage is as described in the above embodiments and will not be repeated here.

[0163] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0164] Based on the above control method, the signal on the conversion branch of the conversion circuit is detected by the feedback control circuit in the conversion circuit, and the effective current on the conversion branch is controlled by the signal, so that the common mode part in the effective current is reduced, thereby increasing the proportion of the differential mode part, and thus increasing the proportion of the differential voltage corresponding to the differential mode part in the output voltage of the conversion circuit, thereby improving the conversion accuracy of the subsequent conversion circuit, and thus improving the calculation accuracy of the in-memory computing system.

[0165] This application embodiment also provides a control device, which may be located at or include the above. Figure 1 or Figure 2 The control circuit 120 / 220 shown, or independent of the control circuit 120 / 220, is used to execute the control method described above, controlling the conversion circuit described above to convert and output the signal from the storage circuit.

[0166] The control device may include a unit or means for performing any of the above control methods.

[0167] This application also provides a control device, which can be found in the embodiments of this application. Figure 22 , Figure 22 A schematic block diagram of a control device according to an exemplary embodiment of this application is shown. Figure 22 As shown, the control device 2200 includes at least one processor 2210 and an interface circuit 2220. The interface circuit 2220 is used to connect to the storage circuit via signals, and the at least one processor 2210 is used to execute any of the control methods provided in the above embodiments.

[0168] This application also provides a computer program product, which includes instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0169] This application also provides a computer-readable medium storing instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0170] This application also provides an electronic device, which can be found in [reference 1]. Figure 23 . Figure 23 A schematic diagram of an electronic device according to an exemplary embodiment of this application is shown. Figure 23 As shown, the electronic device 2300 may include any of the above-mentioned in-memory computing systems 2310 for processing data from the electronic device. The electronic device may also include an input / output device 2320 for receiving user input or outputting processing results. This application does not limit the input and output types; for example, input may include voice input, text input, image input, or video input. Output may include text output, voice output, image output, or video output. The electronic device may also include a processor 2330, which can process data provided to the in-memory computing system 2310 or process the output data of the in-memory computing system 2310. The output of the input / output device 2320 may be based on the output of the processor 2330 or the output of the in-memory computing system 2310.

[0171] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0172] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A conversion circuit, characterized in that, For use in a memory computing system, the memory computing system includes a storage circuit, and the conversion circuit is used to convert and output the output signal of the storage circuit. The output signal of the storage circuit includes a first current signal and a second current signal, including: The first conversion branch includes a first input terminal and a first output terminal. The first input terminal is used to couple the first current signal, and the first output terminal is used to output the first voltage signal. The second conversion branch includes a second input terminal and a second output terminal. The second input terminal is used to couple the second current signal, and the second output terminal is used to output the second voltage signal. A feedback control circuit, connected to the first conversion branch and the second conversion branch, is used to control the first bias current acting on the first conversion branch and the second bias current acting on the second conversion branch according to the first signal of the first conversion branch and the second signal of the second conversion branch. The first conversion branch is used to generate the first voltage signal at the first output terminal when the first current signal and the first bias current act at the first time, and the second conversion branch is used to generate the second voltage signal at the second output terminal when the second current signal and the second bias current act at the first time.

2. The conversion circuit according to claim 1, characterized in that, The first signal includes a third current signal flowing through the first conversion branch during the second time period or a third voltage signal at the first output terminal when the second time period expires. The second signal includes a fourth current signal flowing through the second conversion branch during the second time period or a fourth voltage signal at the second output terminal when the second time period expires.

3. The conversion circuit according to claim 2, characterized in that, The second time includes part or all of the first time, or the second time is independent of the first time.

4. The conversion circuit according to claim 2 or 3, characterized in that, The feedback control circuit includes a comparator circuit, a gating circuit, and an analog-to-digital converter circuit. The comparison circuit is used to receive the first signal and the second signal, and output a first control signal based on the comparison result of the first signal and the second signal; The gating circuit is connected to the comparator circuit and is used to receive the first control signal and, according to the first control signal, to connect the first signal or the second signal to the analog-to-digital conversion circuit. The analog-to-digital converter circuit is used to convert the first signal or the second signal into a second control signal, and the second control signal is used to control the first bias current and the second bias current.

5. The conversion circuit according to claim 4, characterized in that, The first signal and the second signal both include current signals. The first control signal is used to control the gating circuit to select the signal with the smaller current between the first signal and the second signal; or, The first signal and the second signal include voltage signals, and the first control signal is used to control the gating circuit to select the signal with a smaller voltage difference relative to the reference voltage between the first signal and the second signal.

6. The conversion circuit according to claim 2 or 3, characterized in that, The feedback control circuit includes a comparator circuit, a first analog-to-digital converter circuit, and a second analog-to-digital converter circuit. The first analog-to-digital converter circuit is used to receive the first signal and convert the first signal into a third signal; The second analog-to-digital converter circuit is used to receive the second signal and convert the second signal into a fourth signal; The comparison circuit is connected to the first analog-to-digital converter circuit and the second analog-to-digital converter circuit, and is used to compare the third signal and the fourth signal. Based on the comparison result of the third signal and the fourth signal, a third control signal is output, which is used to control the first bias current and the second bias current.

7. The conversion circuit according to any one of claims 1-6, characterized in that, The first bias current and the second bias current are equal in magnitude and less than or equal to the smaller of the first current signal and the second current signal.

8. The conversion circuit according to any one of claims 1-7, characterized in that, The first conversion branch includes a first control circuit, a first energy storage element, a first reset circuit, and a first bias circuit. One end of the first energy storage element is used to couple to the supply voltage or reference voltage, and the other end is used to the first output terminal. The first control circuit is connected between the first input terminal and the first output terminal. The first reset circuit is connected to the other end of the first energy storage element and is used to reset the voltage of the first output terminal. The first bias circuit is connected to the feedback control circuit and the first input terminal and is used to provide the first bias current to the first input terminal under the control of the feedback control circuit. The second conversion branch includes a second control circuit, a second energy storage element, a second reset circuit, and a second bias circuit. One end of the second energy storage element is used to couple to the supply voltage or reference voltage, and the other end is used as the second output terminal. The second control circuit is connected between the second input terminal and the second output terminal. The second reset circuit is connected to the other end of the second energy storage element and is used to reset the voltage of the second output terminal. The second bias circuit is connected to the feedback control circuit and the second input terminal and is used to provide the second bias current to the second input terminal under the control of the feedback control circuit.

9. The conversion circuit according to claim 8, characterized in that, The feedback control circuit samples the first signal and the second signal through an analog-to-digital converter circuit; The first bias circuit generates the first bias current through the first digital-to-analog converter circuit; The second bias circuit generates the second bias current through the second digital-to-analog converter circuit.

10. The conversion circuit according to claim 8 or 9, characterized in that, The first conversion branch also includes a first clamping circuit for stabilizing the voltage at the first input terminal; The second conversion branch also includes a second clamping circuit for stabilizing the voltage at the second input terminal.

11. A control method, characterized in that, The control method for controlling the conversion circuit as described in any one of claims 1 to 10 includes: The feedback control circuit is turned on, and the feedback control circuit is used to control the first bias current acting on the first conversion branch and the second bias current acting on the second conversion branch according to the first signal of the first conversion branch and the second signal of the second conversion branch. The feedback control circuit is shut down when the first time expires, outputting a first voltage signal at the first output terminal of the first conversion branch and a second voltage signal at the second output terminal of the second conversion branch.

12. A control device, characterized in that, It includes at least one processor and an interface circuit, the interface circuit being electrically connected to a conversion circuit as described in any one of claims 1 to 10, and the at least one processor being used to execute the control method as described in claim 11.

13. An in-memory computing system, characterized in that, include: A storage circuit is used to receive an input signal and convert the input signal into an output signal based on stored weight data; The conversion circuit as described in any one of claims 1 to 10, connected to the storage circuit, is used to convert and output the output signal.

14. An electronic device, characterized in that, Including the in-memory computing system as described in claim 13.

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