An asynchronous control structure compatible with scan chains and its design-for-test method

Abstract

The application discloses an asynchronous control structure compatible with a scan chain and a design method thereof, and is composed of a plurality of asynchronous control units connected in a head-to-tail mode. Each asynchronous control unit is based on a "sending-relaying-receiving" structure to form an asynchronous control chain. Each asynchronous control chain internally comprises a control register unit, a scan clock selection circuit, a control combination logic circuit, a data path register unit and a handshake freezing and isolation circuit. A handshake freezing circuit is introduced on a generation path of a fire event pulse in the relaying structure, and a scan clock selection logic is introduced on a clock path of the control register and the data path register. In a test mode, the control path and the data path are completely decoupled, a high-coverage test on structural faults such as a stuck fault is realized, meanwhile, the existing DFT or scan chain insertion tool can automatically identify the standard scannable register, and the testability is significantly improved while the circuit performance and energy consumption are ensured.

Description

Technical Field

[0001] This invention belongs to the field of circuit testing technology, specifically relating to an asynchronous control structure compatible with scan chains and its testability design method. Background Technology

[0002] Asynchronous control structures based on handshake protocols typically consist of several control registers, combinational logic, and data registers that work in conjunction with the data path. Events are transmitted between different functional units through handshake signals such as request / response (Req / Ack) to achieve pipeline control, flow regulation, and power optimization.

[0003] In the chip design process, the testability of a chip can be improved by incorporating specific testability logic. Existing research has introduced test_mode selection logic into the clock domain of the data register, enabling the synchronous scan chain to identify and drive the data register in the bundled data (BD) circuit. This allows existing synchronous DFT or ATPG tools to be used at the data path level to scan and test the data path of Click-type bundled data asynchronous circuits, achieving high fault coverage and low area and power consumption overhead on RISC-V five-stage asynchronous pipelined processors.

[0004] However, the aforementioned technology mainly focuses on enabling scanning tools to identify and drive data registers. It does not structurally reconstruct the timing model, state preservation mechanism, and handshake behavior in test mode of the asynchronous control structure itself, resulting in the following shortcomings in asynchronous control scenarios: 1. The control path and data path are not structurally isolated, making it difficult to completely suppress handshake behavior. During the scan shift process, the contents of the control register will change continuously with the scan data, and the handshake combination logic connected to it will also continuously flip, which can easily generate additional request / response pulses locally, and even violate the original "single token, one direction" protocol constraints. The asynchronous control network is still in a certain "pseudo-active" state in the test mode, and cannot guarantee strict silence. 2. Control register shifting still has an adverse effect on the behavior of data registers. Since the control path itself is not frozen and isolated, its contents are constantly shifted when the scan chain passes through the control register. The corresponding write enable, reset, and select signals change in an unpredictable way in test mode. For example, in test mode, the data register may be written to incorrectly, cleared prematurely, or switched to the wrong data path. This weakens the controllability of the test vector, the determinism of the fault stimulus, and the observability of the fault effect. 3. Existing EDA tools have difficulty automatically identifying asynchronous registers and generating adaptation structures. Existing EDA tools have difficulty automatically identifying asynchronous registers and lack the ability to automatically replace these registers with dedicated units that allow "freezing of control paths and scanning of data paths". When promoting this in general asynchronous control networks containing a large number of heterogeneous handshaking units and complex branch / merge topologies, the insertion of Design for Testability (DFT) will rely heavily on manual constraints and local modifications, resulting in high design costs and a high risk of omissions, making it difficult to form a reusable general design paradigm. 4. Purely asynchronous handshake control structure that is difficult to cover The above technique inserts test_mode selection logic on the premise that a clear fire interface already exists. For more general pure asynchronous handshake control structures, such as pipeline units that implement control based on C element states, FULL or EMPTY lines or GasP state lines, their control states are usually implicit in the local feedback loop in the form of levels. There is no explicit fire port that is easy to insert a multiplexer externally. If such structures are not specially frozen and templated in scan mode, it is difficult to ensure protocol security and difficult for EDA tools to treat them as scannable registers. Summary of the Invention

[0005] To address the problems existing in the aforementioned background technology, the purpose of this invention is to provide an asynchronous control structure compatible with scan chains and its testability design method. Within the control path, a handshake control register and a data register are explicitly distinguished, and a dedicated scanable unit with a freeze function is introduced for the former. This structurally decouples the control path and the data path, ensuring that the registers on the control path do not functionally affect the data path during scan shifts. This achieves structural independence between the control path and the data path, significantly improving the controllability and observability of the asynchronous control circuit in test mode.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: An asynchronous control structure compatible with scan chains is provided, consisting of several levels of asynchronous control units connected end-to-end. Each level of asynchronous control unit forms an asynchronous control chain based on a "transmit-relay-receive" structure, which includes: The sender structure is used to receive the preceding drive pulses and generate a forward handshake signal; The receiver structure is used to receive feedback pulses from the subsequent stage and generate backward handshake signals. At least one relay structure is connected between the transmitting structure and the receiving structure; Each asynchronous control chain includes: The control register unit stores the control status or handshake phase information of this level. It embeds a serial scan multiplexer controlled by the scan enable signal and is uniformly packaged as a scannable register unit. The data input of the control register unit is connected to the function data input and the serial scan input respectively through the serial scan multiplexer. The data output of the control register unit is divided into two paths: one path is sent as a status signal to the control combinational logic circuit of this level; the other path is connected as a serial scan output to the serial scan input of the next-level control register unit, forming a control path scan chain. The scan enable signal selects one input from the serial scan multiplexer to enter the data input of the control register unit. In function mode, the function data input is selected; in scan mode, the serial scan input is selected. The control combinational logic circuit uses the status signal of the control register unit at this level as the status input, and combines it with the handshake signals of the preceding and following levels to generate the fire event pulse at this level, the external handshake signal, and the data path control signal, such as write enable, reset, and multiplexing control. The handshake freeze and isolation circuit introduces freeze logic controlled by the scan enable signal into the fire event pulse generation path within the relay, forming a three-input AND gate. Therefore, the logic value of the scan enable signal can be used to control whether to allow or block the generation of fire event pulses. The data path register unit stores the actual data signal and constitutes the pipeline registers at each stage in the data path. An embedded data scan multiplexer controlled by the scan enable signal is included. The input terminals of the data path register unit are connected to the functional data input terminal and the data scan input terminal respectively through the data scan multiplexer. The output terminals of the data path register unit are divided into two paths: one as the functional data output terminal and the other as the data scan output terminal. The input terminal of the data path register unit is selected by the scan enable signal. In functional mode, the data path register unit is driven by the fire event pulse processed by the handshake freeze and isolation circuit to complete data updates. In scan test mode, the data path register unit is driven by the global scan clock to complete scan shifting. The scan clock selection circuit includes a control register clock selection branch and a data path register clock selection branch, both controlled by a scan enable signal. The input of the control register clock selection branch receives a control write pulse generated by a local asynchronous event and a global scan clock, and its output is connected to the clock terminal of the control register unit. The input of the data path register clock selection branch receives a fire event pulse processed by a handshake freeze and isolation circuit and a global scan clock, and its output is connected to the clock terminal of the data path register unit.

[0007] Furthermore, the relay also includes an enable control input terminal, which receives an enable control signal. The enable control signal and a logic signal used to detect the phase relationship between the handshake signals of the preceding and following stages jointly participate in the generation of the fire event pulse, so that the relay generates the fire event pulse only when the enable control signal is at the enable level and the preset handshake phase condition is met.

[0008] Furthermore, in the asynchronous control unit, the serial scan output and serial scan input of the preceding and following control register units are connected in series to form a control path scan chain, and the data scan output and data scan input of the preceding and following data path register units are connected in series to form a data path scan chain.

[0009] Furthermore, in the control register unit and the data path register unit, when the scan enable signal is high, the serial scan multiplexer selects the serial scan input terminal, and the data scan multiplexer selects the data scan input terminal; when the scan enable signal is low, both the serial scan multiplexer and the data scan multiplexer select the functional data input terminal.

[0010] Furthermore, the control register unit is a D flip-flop with an embedded serial scan multiplexer; the data path register unit is a D flip-flop or latch with an embedded data scan multiplexer.

[0011] Furthermore, the control combinational logic circuit includes a Click controller composed of XOR gates, NAND gates, and inverters.

[0012] Furthermore, the handshake freeze and isolation circuit includes a three-input AND gate. The first and second inputs of the three-input AND gate respectively receive two handshake logic signals used to generate a fire event pulse, and the third input receives the inverted signal of the scan enable signal. When the scan enable signal is low, the inverted signal is high, and the three-input AND gate allows the generation of a fire event pulse. When the scan enable signal is high, the inverted signal is low, and the output of the three-input AND gate remains low to block the fire event pulse.

[0013] Furthermore, the control register clock selection branch and the data path register clock selection branch are each equipped with a clock multiplexer; when the scan enable signal is high, both clock multiplexers select the global scan clock; when the scan enable signal is low, the control register clock selection branch selects the control write pulse, and the data path register clock selection branch selects the fire event pulse processed by the handshake freeze and isolation circuit.

[0014] Based on the above-mentioned asynchronous control structure compatible with scan chains, this invention provides a design-for-testability method, comprising: Mode switching: Set the scan enable signal to an invalid level to enter the function mode, release the handshake freeze and isolation circuit blocking the fire event pulse, and the asynchronous control unit performs handshake communication based on the local asynchronous event; set the scan enable signal to an active level to enter the scan test mode; In scan test mode, the clock source for both the control register unit and the data register unit is switched from a local asynchronous event to a global scan clock via the scan clock selection circuit. A serial scan multiplexer switches the data source of the control register unit to the serial scan input, and a data scan multiplexer switches the data source of the data path register unit to the data scan input. A handshake freeze and isolation circuit blocks the fire event pulse generated within the relay structure, isolating the data path from the control path. Test vectors are shifted into the control path scan chain and the data path scan chain via the serial scan input and the data scan input, respectively, and response results are shifted out via the serial scan output and the data scan output, respectively, thus completing the fault detection of the asynchronous control logic and data path.

[0015] Circuit working principle: The asynchronous control circuit of this invention has different operating processes in different working modes, mainly including a functional mode and a scan test mode. By switching the handshake interface and the register data / clock source, the asynchronous control structure and the synchronous scan chain are decoupled in behavior.

[0016] (1) Functional mode In functional mode, the scan enable signal `scan_enable` has a logical value of 0, i.e., `scan_enable=0`. The test control module disables the scan chain function, the global scan clock `scan_clk` is not used as the register clock, the handshake freeze logic is transparent, and the entire "send-relay-receive" link operates normally according to the original asynchronous handshake protocol. The handshake freeze and isolation circuit selects real handshake signals from adjacent units. The control combinational logic takes the state of the control register at this level and the handshake signals from the preceding and following levels as inputs, and generates or receives asynchronous handshake signals at different positions in the link accordingly, generating internal fire event pulses when the phase relationship meets the conditions. For asynchronous control chains with multi-level relay structures, a single drive event sequentially triggers multiple fire event pulses within the chain, which are transmitted from the sender through each relay level to the receiver. The data input of the control register unit selects the signal function path in functional mode, and its write timing is provided by the local fire pulse. The serial scan inputs `scan_in` and `scan_clk` do not participate in the operation in this mode, but are only reserved as physical interfaces. The data input to the data path register unit also follows the strobe signal function path. Its update is triggered by the corresponding level's fire event pulse and controlled by the write enable, reset, and multiplexing signals generated by the control combinational logic. This allows the data to advance step by step in the "register-(sequential or combinational logic)-register" link along with the fire event pulse sequence. Since the scan_enable on the AND gate in the handshake freeze circuit is equivalent to a logic value "1" after inversion, it does not block the generation of the fire event pulse. Therefore, the behavior of the entire control chain and data path remains consistent with that without the introduction of a testability structure.

[0017] (2) Scan test mode In scan test mode, scan_enable=1. The test control module enables the scan chain function and blocks the generation of functional fire event pulses through the handshake freeze circuit, thus logically freezing the asynchronous control chain and retaining only the scan shift behavior. Specifically, the final-stage AND gate used to generate fire event pulses inside the relay is a two-input structure in functional mode. After connecting scan_enable in scan test mode, it becomes a three-input AND gate, and scan_enable is first inverted: in functional mode scan_enable=0, after inversion it is a logic value "1", which does not affect the combinational logic to generate fire event pulses; in scan test mode scan_enable=1, after inversion it is a logic value "0". Regardless of the phase change of the handshake signal between the preceding and following stages, the output logic value of the AND gate is always "0". No new fire event pulses are generated inside the relay structure, the functional write of the control register and data path register no longer occurs, the handshake signal driven by the register on the link remains at the current level, and the state of the entire "transmit-relay-receive" control chain is frozen.

[0018] Based on this, the data inputs of the control registers and data path registers are switched to the serial scan path. The serial scan input `scan_in` and serial scan output `scan_out` are connected to the serial scan path, and the clock input is switched to `scan_clk`. The write pulses and related function control signals, originally triggered by the `fire` event pulse, are no longer effective in scan test mode. The register contents are shifted only along the serial scan path `scan_in→…→scan_out` with the pulse edge of `scan_clk`. External test equipment can inject test vectors and read responses through `scan_in` and `scan_out` respectively, thus enabling bit-by-bit observation and control of the control and data states. Since the `fire` function is disabled by `scan_enable`, `scan_clk` becomes the sole clock source for these registers. Therefore, the test process does not introduce new asynchronous events into the handshake path or data path, thereby constructing a controllable and observable test environment consistent with the traditional synchronous scan chain.

[0019] Compared with the shortcomings and deficiencies of existing technologies, the present invention has the following beneficial effects: 1. This invention abstracts the target asynchronous control structure into several control links formed by the series connection of a transmitting structure, several levels of relay structures and a receiving structure. Through this abstraction, asynchronous control links constructed by various structures can be uniformly mapped to the same type of circuit template, which facilitates standardized description and automated transformation at the RTL level and provides a clear structural boundary for subsequent tool-based processing. 2. This invention introduces a handshake freezing circuit on the generation path of the fire event pulse inside the relay structure, and introduces scan clock selection logic on the clock path of the control register and the data path register. In the scan test mode, the control path and the data path are completely decoupled, ensuring that the register scan in the scan test mode will not have an adverse effect on the data path function, and achieving high coverage testing of structural faults such as jamming faults. 3. This invention adopts a register design scheme that is compatible with the logic interface of "with scan enable trigger" in traditional synchronous testability design. This enables all control registers and data path registers to have interface features such as normal data input terminal, serial scan input or output terminal, and clock selection capability of function trigger signal and scan_clk. Existing scan chain insertion tools can directly identify these registers as standard scan units for wiring and optimization without modifying the EDA tool itself. 4. Since this invention only adds a small amount of logic around the fire event pulse generation path and the register clock path without changing the original data path and the asynchronous protocol itself, the area and power consumption overhead are small, and the testability is significantly improved while ensuring circuit performance and energy consumption. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of an asynchronous control structure with measurability provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of a testable cFifon circuit structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a relay structure with permission and testability mechanisms provided in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0022] This invention, based on a "transmit-relay-receive" structure, designs an asynchronous control structure compatible with scan chains. This structurally decouples the control and data paths, ensuring that registers on the control path do not functionally affect the data path during scan shifts. Simultaneously, it can be automatically recognized as standard scanable registers by existing DFT / scan chain insertion tools, thus achieving structural compatibility and automated support between asynchronous control circuits and synchronous DFT processes. This solution is applicable to various asynchronous controllers containing internal registers, such as Click / GASP control units, two-phase / four-phase handshake controllers, asynchronous micropipeline units based on a "transmit-relay-receive" structure, and asynchronous control chains represented by cFifo.

[0023] The scan-chain compatible asynchronous control structure consists of several levels of asynchronous control units connected end-to-end. Each level of asynchronous control unit forms an asynchronous control chain based on a "transmit-relay-receive" structure, which includes: The sender structure is used to receive the preceding drive pulses and generate a forward handshake signal; The receiver structure is used to receive feedback pulses from the subsequent stage and generate backward handshake signals. At least one relay structure connects the transmitting structure and the receiving structure; By explicitly distinguishing between the control path and the data path in the "send-relay-receive" structure, all registers are uniformly incorporated into the scannable test framework while ensuring that the event-driven behavior remains unchanged.

[0024] Each asynchronous control chain includes a control register unit, a scan clock selection circuit, a control combinational logic circuit, a data path register unit, and a handshake freeze and isolation circuit.

[0025] 1. Control Register Unit Used to store the control state or handshake phase information of this level, reflecting the current event state of this level in the "transmit-relay-receive" control chain. An embedded serial scan multiplexer controlled by a scan enable signal is uniformly encapsulated as a scannable register unit, such as a D flip-flop with an embedded serial scan multiplexer. The data input of the control register unit is connected to the function data input and the serial scan input respectively through the serial scan multiplexer, with the scan enable signal selecting one of the inputs. The data output of the control register unit is divided into two paths: one path is sent as a status signal to the control combinational logic circuit of this level, which generates a handshake signal and sends it to the handshake signal input of the next level; the other path serves as a serial scan output and is connected to the serial scan input of the next level control register unit, forming a control path scan chain.

[0026] In the control register unit, the serial scan multiplexer is controlled by the scan enable signal; when the scan enable signal is high, the serial scan multiplexer selects the serial scan input terminal; when the scan enable signal is low, the serial scan multiplexer selects the function data input terminal.

[0027] In each asynchronous control unit, the serial scan output and serial scan input of the preceding and following control register units are connected in series to form a control path scan chain.

[0028] 2. Control combinational logic circuits Using the status signal of the control register unit at this level as the status input, and combining it with the handshake signals from the preceding and following stages, the system generates the fire event pulse for this level, external handshake signals, and data path control signals, such as write enable, reset, and multiplexing control. The control combinational logic circuit includes a Click controller composed of XOR gates, NAND gates, and inverters.

[0029] 3. Handshake Freeze and Isolation Circuit In an asynchronous control chain consisting of a "transmit-relay-receive" structure, the fire event pulse used within the relay to drive the updates of the control register and data path register of this stage is generated through combinational logic (e.g., a phase detection circuit composed of XOR gates, XNOR gates, and AND gates) based on the phase relationship between the handshake signals of the preceding and following stages. The fire event pulse is a key trigger signal for the normal operation of this stage. This invention introduces a freeze logic controlled by a scan enable signal into the fire generation path within the relay structure, forming a three-input AND gate. Specifically, the first and second inputs of the three-input AND gate receive two handshake logic signals used to generate the fire event pulse, respectively, while the third input receives the inverted signal of the scan enable signal. When the scan enable signal is low, the inverted signal is high, and the three-input AND gate allows the generation of the fire event pulse. When the scan enable signal is high, the inverted signal is low, and the output of the three-input AND gate remains low to block the fire event pulse.

[0030] 4. Data Path Register Unit Used to store actual data signals, forming the pipeline registers at each stage of the data path. An embedded data scan multiplexer, controlled by a scan enable signal, such as a D flip-flop or latch with an embedded data scan multiplexer, is used. The inputs of the data path register unit are connected to the functional data input and the data scan input respectively through the data scan multiplexer; the output of the data path register unit is divided into two paths, one as the functional data output and the other as the data scan output. The data scan outputs and data scan inputs of the preceding and following data path register units are connected in series to form a data path scan chain.

[0031] In the data path register unit, the data scan multiplexer is controlled by the scan enable signal; when the scan enable signal is high, the data scan multiplexer selects the data scan input terminal; when the scan enable signal is low, the data scan multiplexer selects the function data input terminal.

[0032] In functional mode, the data path register unit is updated by fire event pulses processed by handshake freezing and isolation circuits. In scan test mode, the data path register unit is shifted by the global scan clock. For a certain level of data path register, after the previous relevant fire event pulse is activated, the data passes through a processing path composed of sequential logic and combinational logic of this level. When the next fire event pulse corresponding to this level is generated, the calculation result is latched into the data path register, so that the multi-step operation unfolds in time according to the sequence of fire event pulses. After implementing "handshake freezing", since the fire event pulses of the control section are masked in scan test mode, the data path register is shifted only by the scan clock. EDA tools can identify these data path registers driven by the scan clock as scan register units, and the data will not be interfered with by fire event pulses during the scan.

[0033] 5. Scan clock selection circuit The scan clock selection circuit includes a control register clock selection branch and a data path register clock selection branch, both controlled by the scan enable signal. The input of the control register clock selection branch receives the control write pulse generated by a local asynchronous event and the global scan clock; its output is connected to the clock terminal of the control register unit. The input of the data path register clock selection branch receives the fire event pulse processed by the handshake-freeze and isolation circuit and the global scan clock; its output is connected to the clock terminal of the data path register unit. The control terminals of both clock selection branches receive the scan enable signal, which selects the signal received at the input. Both the control register clock selection branch and the data path register clock selection branch have clock multiplexers. When the scan enable signal is high, both clock multiplexers select the global scan clock; when the scan enable signal is low, the control register clock selection branch selects the control write pulse, and the data path register clock selection branch selects the fire event pulse processed by the handshake-freeze and isolation circuit.

[0034] The testability design method based on the above-mentioned compatible scan chain asynchronous control structure is as follows: Mode switching: Set the scan enable signal to an invalid level to enter the function mode, release the handshake freeze and isolation circuit blocking the fire event pulse, and the asynchronous control unit performs handshake communication based on the local asynchronous event; set the scan enable signal to an active level to enter the scan test mode; In scan test mode, the clock source of both the control register unit and the data register unit is switched from the local asynchronous event to the global scan clock through the scan clock selection circuit. The data source of the control register unit is switched to the serial scan input terminal through the serial scan multiplexer, and the data source of the data path register unit is switched to the data scan input terminal through the data scan multiplexer. The handshake freeze and isolation circuit is used to block the fire event pulse generated inside the relay structure, thus isolating the data path and the control path. The test vector is moved into the control path scan chain and the data path scan chain through the serial scan input terminal and the data scan input terminal, respectively, and the response result is moved out through the serial scan output terminal and the data scan output terminal, respectively, to complete the fault detection of the asynchronous control logic and the data path. After the test is completed, set the scan enable signal to an invalid level to restore the function mode.

[0035] Example 1: An asynchronous control chain with a "transmit-relay-receive" structure containing one relay. like Figure 1As shown, the asynchronous control chain starts with the sender and ends with the receiver, with a relay inserted in between, such as in a cFifo controller. Internally, the asynchronous control chain includes a control register unit, a scan clock selection circuit, a control combinational logic circuit, a data path register unit, and a handshake, freeze, and isolation circuit. The sender receives the event-driven signal i_drive from the previous level's control combinational logic. When the control combinational logic circuit detects a valid drive signal, it triggers the current level's control register to flip, causing the handshake signal outR requesting the next level to flip. This converts the single-pulse event into a level phase change and sends it to the relay. Simultaneously, it receives the event pulse signal from the next level, inverts it, and outputs the feedback signal o_free to the previous level. The relay receives the request level handshake signal *inR* from the previous stage and the feedback level handshake signal *outA* from the next stage. It controls the combinational logic circuit to compare the phase of *inR* with the phase recorded in the current stage's control register. When a flip of *inR* is detected, a short *fire* event pulse is generated to drive the current stage's control register and data path register to complete one operation. Subsequently, the control register and data path register are updated, and *outR* is flipped. Simultaneously, based on *outA*, the feedback level handshake signal *inA* from the previous stage is generated, restoring the relay to a stable state capable of receiving the next event after the handshake is complete, thus completing a combination of level handshake and pulse handshake. The receiver receives *inR* from the relay and the event pulse signal *i_freeNext* from the next control chain or subsequent modules. When the control combinational logic circuit detects *i_freeNext*, it updates the current stage's control register and generates *inA* to return a stable state feedback signal to the previous stage. It then releases the current control chain and, in conjunction with the final stage's data path register, completes data synchronization, outputting *o_drive* to drive the next stage module.

[0036] In functional mode, the logic value of the scan enable signal is 0, i.e., scan_enable=0. The final AND gate in the fire event pulse generation path receives the signal from the phase detection combinational logic and the inverted scan_enable. Since scan_enable=0, the inverted signal is equivalent to the logic value "1", which does not affect the normal behavior of generating fire event pulses by XOR / XNOR. The relay can generate fire event pulses normally according to the Click protocol, driving handshake signals such as outR and inA to complete one event transmission in sender, relay and receiver.

[0037] In scan test mode, scan_enable=1. After introducing scan_enable, the final AND gate in the fire event pulse generation path becomes a three-input structure. scan_enable is inverted and then fed into the AND gate. After inversion, it becomes a logic value of "0", directly blocking the generation of fire event pulses. This prevents the relay from generating new fire event pulses. The control register and the data path register directly triggered by the fire event pulse no longer respond to asynchronous events. The handshake state on the link remains static, achieving control path freezing. This avoids control register state flipping and handshake signal switching again. The entire asynchronous control chain remains in an idle level state at the protocol level. Simultaneously, the data input terminals of the control register and data path register are switched to the serial scan input and data scan input terminals, respectively. That is, both input terminals are switched to the serial scan path. Test vectors are shifted into the control path scan chain and data path scan chain via the serial scan input `scan_in`, and the response results are shifted out via the serial scan output `scan_out`. The clock input is switched to `scan_clk`. The function write path, originally driven by the `fire` event pulse, is no longer effective in scan test mode. The register contents are driven only by `scan_clk`, shifting sequentially along the serial scan path (`scan_path`) from `scan_in` to `scan_out` with each pulse edge of `scan_clk`. External test equipment injects test vectors via `scan_in` and reads the response via `scan_out`, allowing for bit-by-bit loading and observation of the control and data states. EDA tools can thus identify registers driven by `scan_clk` as scan register units, achieving test behavior consistent with traditional synchronous scan chains.

[0038] Example 2: Asynchronous control chain with multiple relays in a "transmit-relay-receive" structure like Figure 2 As shown, taking the cFifon controller as an example, cFifon is constructed using a "send-relay-receive" structure. Through several relay levels, it sequentially generates several fire event pulses under a single driving event, which are used to trigger different levels of data path registers or combinational / timing logic to complete multi-step pipelined operations. Its asynchronous control chain starts with the sender and ends with the receiver, with multiple sequentially connected relays inserted in between. The asynchronous control chain internally includes control register units, scan clock selection circuits, control combinational logic circuits, data path register units, and handshake, freeze, and isolation circuits.

[0039] In functional mode, scan_enable=0, and the fire event pulses are generated by the cFifon's internal phase detection combinational logic and the final-stage AND gate. After the event-driven signal i_drive is triggered by the sender, multiple fire event pulses are generated sequentially within cFifon. These fire event pulses drive the connected "register-(sequential or combinational logic)-register" segments to complete corresponding operations in a predefined order: for a certain level of data path register, after the previous related fire event pulse is activated, the data is processed by the sequential and combinational logic of this level, and the calculation is completed and the result is saved before the next logically corresponding fire event pulse of this level is generated, realizing the temporal expansion of multi-step operations. After all fire event pulses are completed, cFifon sends inA to the next level through the receiver, allowing the reception of the next event-driven signal.

[0040] In scan test mode, with scan_enable=1, all final-stage AND gates within cFifon used to generate fire event pulses are pulled to a constant logic value of "0" by scan_enable. No new fire event pulses are generated, and multiple fire event pulse sequences are completely disabled. At this time, the data inputs of all control registers and data path registers are switched to the scan input path, the clock input is switched to scan_clk, and registers are shifted only according to the scan chain order under the drive of scan_clk.

[0041] Since the multi-fire event pulse links within cFifon are all frozen in scan test mode, data no longer propagates through multiple steps along the functional path. The test process only needs to consider the shifting behavior on the scan path. This avoids interference from the uncertainty of the timing of multi-fire event pulses and maintains the same scan link interface format as in Embodiment 1, making it easy for existing DFT / scan chain tools to identify and process. Therefore, the freezing and scanning mechanism proposed in this invention is applicable to complex asynchronous controllers containing multi-fire event pulse sequences and is not limited to simple links with single-fire event pulses.

[0042] Example 3: Relay with an enable mechanism in a "transmit-relay-receive" structure Introducing an enable control signal pmt into the relay creates a relay with an enable mechanism (PmtRelay), such as... Figure 3As shown, the Relay also includes an enable control input, which receives the PMT signal. The PMT signal, along with a logic signal used to detect the phase relationship between the handshake signals of the preceding and following stages, participates in the generation of the fire event pulse. This ensures that the relay generates the fire event pulse only when the PMT signal is at the enable level and the preset handshake phase condition is met. The PmtRelay structure still follows the basic framework of "control register + control combinational logic + fire event pulse generation path + data path register". The difference is that when the control combinational logic generates the fire event pulse, it not only depends on the phase relationship between inR and the control register of this stage, but also on the condition of the enable signal PMT. That is, the fire event pulse is generated and outR is flipped only when the PMT signal is at the enable level and the phase flip of inR is detected, thus providing finer gating of the event pulse transmission.

[0043] In functional mode, with scan_enable=0, PmtRelay conditionally generates and transmits the fire event pulse and outR according to the logic described above. In scan test mode, with scan_enable=1, PmtRelay behaves the same as relay; the final AND gate in its fire event pulse generation path is also controlled by scan_enable and pulled to a constant logic value of "0". No new fire event pulses are generated, and the control register and the data path register directly triggered by the fire event pulse remain frozen. The register scanning process is the same as in Example 1, both driven by scan_clk.

[0044] Therefore, the fire event pulse freezing logic and scan register structure based on scan_enable proposed in this invention are not only applicable to relay, but also to relay variants such as PmtRelay, indicating that this invention has good adaptability within the "transmit-relay-receive" structure.

[0045] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An asynchronous control structure compatible with scan chains, characterized in that, The asynchronous control structure consists of several levels of asynchronous control units connected end-to-end. Each level of asynchronous control unit forms an asynchronous control chain based on a "transmit-relay-receive" structure, which includes: The sender is used to receive the previous drive pulse and generate a forward handshake signal. The receiver is used to receive feedback pulses from the subsequent stage and generate a backward handshake signal. At least one relay is connected between the sender and the receiver; Each asynchronous control chain includes: The control register unit stores the control status or handshake phase information of this level. It is embedded with a serial scan multiplexer controlled by the scan enable signal and is uniformly packaged into a scannable register unit. The data input of the control register unit is connected to the function data input and the serial scan input through the serial scan multiplexer. The data output of the control register unit is divided into two paths: one path is sent as a status signal to the control combinational logic circuit of this level; the other path is connected as a serial scan output to the serial scan input of the next level control register unit, forming a control path scan chain. The control combinational logic circuit uses the status signal of the control register unit at this level as the status input, and combines it with the handshake signals of the preceding and following levels to generate the fire event pulse, the external handshake signal, and the data path control signal at this level. The handshake freeze and isolation circuit introduces freeze logic controlled by the scan enable signal into the fire event pulse generation path within the relay, forming a three-input AND gate. The handshake freeze and isolation circuit includes a three-input AND gate. The first and second inputs of the three-input AND gate respectively receive two handshake logic signals used to generate the fire event pulse, and the third input receives the inverted signal of the scan enable signal. When the scan enable signal is low, the inverted signal is high, and the three-input AND gate allows the generation of the fire event pulse. When the scan enable signal is high, the inverted signal is low, and the output of the three-input AND gate remains low to block the fire event pulse. The data path register unit is used to store actual data signals and constitutes the pipeline registers at each stage in the data path; it embeds a data scan multiplexer controlled by a scan enable signal, and the input of the data path register unit is connected to the functional data input and the data scan input respectively through the data scan multiplexer; the output of the data path register unit is divided into two paths, one as the functional data output and the other as the data scan output. The scan clock selection circuit includes a control register clock selection branch and a data path register clock selection branch, both controlled by the scan enable signal. The input of the control register clock selection branch receives a control write pulse generated by a local asynchronous event and the global scan clock, and its output is connected to the clock terminal of the control register unit. The input of the data path register clock selection branch receives a fire event pulse processed by the handshake freeze and isolation circuit and the global scan clock, and its output is connected to the clock terminal of the data path register unit. The control register clock selection branch and the data path register clock selection branch are each equipped with a clock multiplexer. When the scan enable signal is high, both clock multiplexers select the global scan clock. When the scan enable signal is low, the control register clock selection branch selects the control write pulse, and the data path register clock selection branch selects the fire event pulse processed by the handshake freeze and isolation circuit.

2. The asynchronous control structure as described in claim 1, characterized in that, The relay also includes an enable control input terminal, which receives an enable control signal. The enable control signal and a logic signal used to detect the phase relationship between the handshake signals of the preceding and following stages jointly participate in the generation of the fire event pulse, so that the relay generates the fire event pulse only when the enable control signal is at the enable level and the preset handshake phase condition is met.

3. The asynchronous control structure as described in claim 1, characterized in that, In the asynchronous control unit, the serial scan output and serial scan input of the preceding and following control register units are connected in series to form a control path scan chain; the data scan output and data scan input of the preceding and following data path register units are connected in series to form a data path scan chain.

4. The asynchronous control structure as described in claim 3, characterized in that, In the control register unit and data path register unit, when the scan enable signal is high, the serial scan multiplexer selects the serial scan input terminal and the data scan multiplexer selects the data scan input terminal; when the scan enable signal is low, both the serial scan multiplexer and the data scan multiplexer select the functional data input terminal.

5. The asynchronous control structure as described in claim 1, 3, or 4, characterized in that, The control register unit is a D flip-flop with an embedded serial scan multiplexer; the data path register unit is a D flip-flop or latch with an embedded data scan multiplexer.

6. The asynchronous control structure as described in claim 1, characterized in that, The control combinational logic circuit includes a Click controller composed of XOR gates, NAND gates, and inverters.

7. A testability design method for an asynchronous control structure as described in any one of claims 1-6, comprising: Mode switching: Set the scan enable signal to an invalid level to enter the function mode, release the handshake freeze and the isolation circuit from blocking the fire event pulse, and the asynchronous control unit performs handshake communication based on the local asynchronous event; Set the scan enable signal to an active level to enter scan test mode; In scan test mode, the clock source for both the control register unit and the data register unit is switched from a local asynchronous event to a global scan clock via the scan clock selection circuit. A serial scan multiplexer switches the data source of the control register unit to the serial scan input, and a data scan multiplexer switches the data source of the data path register unit to the data scan input. A handshake freeze and isolation circuit blocks the fire event pulse generated within the relay, isolating the data path from the control path. Test vectors are shifted into the control path scan chain and the data path scan chain via the serial scan input and the data scan input, respectively, and response results are shifted out via the serial scan output and the data scan output, respectively, thus completing the fault detection of the asynchronous control logic and data path.

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